Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/phase_shifter.vhd
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/phase_shifter.vhd	(revision 10149)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/phase_shifter.vhd	(revision 10154)
@@ -35,6 +35,6 @@
 		shifting : OUT std_logic := '0';
 		ready : OUT std_logic := '0';
-		offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
-		DCM_locked : OUT std_logic
+		offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0')
+		
 		
 	);
@@ -71,9 +71,9 @@
 
 architecture first_behave of phase_shifter is
-  constant OFFS_MIN : integer := -51;
-  constant OFFS_MAX : integer := 51;
-    
+	constant OFFS_MIN : integer := -51;
+	constant OFFS_MAX : integer := 51;
+		
 	type states is (INIT, READY_STATE, PRE_SHIFTING_STATE, SHIFTING_STATE, WAITINGFORDONE, RESET_STATE); 
-	signal state,next_state : states := INIT;
+	signal state : states := INIT;
 	
 	signal local_direction : std_logic;
@@ -88,28 +88,17 @@
 
 -- concurrent statements:
-DCM_locked <= LOCKED;
 ready <= ready_int;
 PSCLK <= CLK;
 offset <= LOCKED & ready_int & std_logic_vector(to_signed(offset_int,6));
 
-  -- MAIN FSM: go to next state if rising edge, or to INIT if LOCKED not high.
-  -- is this really coorect?
-  
-  FSM_Registers: process(CLK, LOCKED, rst)
-  begin
-    if LOCKED = '0' then
-      state <= INIT;
-    elsif Rising_edge(CLK) then
-      state <= next_state;
-    end if;
-  end process;
-
-  -- MAIN FSM
-  FSM_logic: process(state, PSDONE, LOCKED, shift_phase, direction, local_direction)
-  begin
-    next_state <= state;
+	-- MAIN FSM
+	FSM: process(state, PSDONE, LOCKED, shift_phase, direction, local_direction)
+	begin
+	
+	if rising_edge(CLK) then
 	reset_dcm_sr <= reset_dcm_sr(1) & reset_DCM;  --synch in
 	shift_phase_sr <= shift_phase_sr(1) & shift_phase; --synch in
-    case state is
+	
+		case state is
 		-- INIT state: here the FSM is idling, when LOCKED is not HIGH.
 		when INIT =>
@@ -120,8 +109,9 @@
 			offset_int <= 0;
 			if (LOCKED = '1') then
-				next_state <= READY_STATE;
+				state <= READY_STATE;
 			else 
-				next_state <= INIT;
+				state <= INIT;
 			end if;
+			
 		-- RESET state: when ordered to do so: DCM is reseted and FSM send back to INIT. 
 		when RESET_STATE =>
@@ -130,5 +120,5 @@
 			shifting <= '0';
 			PSEN <= '0';
-			next_state <= INIT;
+			state <= INIT;
 			
 		-- READY_STATE state: here FSM is waiting for the 'shift_phase' to go high, or
@@ -149,11 +139,11 @@
 			if (shift_phase_sr = "01") then
 				local_direction <= direction; -- direction is sampled, once 'shift_phase' goes high
-				next_state <= PRE_SHIFTING_STATE;
+				state <= PRE_SHIFTING_STATE;
 			else
-				next_state <= READY_STATE;
+				state <= READY_STATE;
 			end if;
 			
 			if (reset_dcm_sr = "01") then
-				next_state <= RESET_STATE;
+				state <= RESET_STATE;
 			end if;
 		
@@ -163,7 +153,7 @@
 			if (local_direction = '1' and upper_limit_reached = '1') or
 				(local_direction = '0' and lower_limit_reached = '1') then
-				next_state <= READY_STATE;
+				state <= READY_STATE;
 			else
-				next_state <= SHIFTING_STATE;
+				state <= SHIFTING_STATE;
 			end if;
 		
@@ -175,5 +165,5 @@
 			PSEN <= '1';
 			PSINCDEC <= local_direction; -- this is the value of 'direction', when 'shift_phase' went up.
-			next_state <= WAITINGFORDONE;
+			state <= WAITINGFORDONE;
 		
 		-- WAITINGFORDONE state: PSENC is set LOW, ensuring that is was high only one clock cycle.
@@ -183,5 +173,5 @@
 			PSEN <= '0';
 			if (PSDONE = '1') then
-				next_state <= READY_STATE;
+				state <= READY_STATE;
 				if (local_direction = '1') then
 					offset_int <= offset_int + 1;
@@ -190,13 +180,14 @@
 				end if;
 			else
-				next_state <= WAITINGFORDONE;
+				state <= WAITINGFORDONE;
 			end if;
 			
 		-- does this work????
 		when others =>
-			next_state <= RESET_STATE;
+			state <= RESET_STATE;
 		
-    end case;
-  end process;
+		end case;
+		end if;
+	end process;
 
 end first_behave;