Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD.hdp =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD.hdp (revision 10154) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD.hdp (revision 10155) @@ -5,17 +5,17 @@ FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/work secureip = D:/unisim/secureip -simprim = D:/unisim/simprim -unimacro = D:/unisim/unimacro -unisim = D:/unisim/unisim -XilinxCoreLib = D:/unisim/xilinxcorelib +simprim = C:/FPGAdv82PS/Xilinx_Lib/simprim +unimacro = C:/FPGAdv82PS/Xilinx_Lib/unimacro +unisim = C:/FPGAdv82PS/Xilinx_Lib/unisim +XilinxCoreLib = C:/FPGAdv82PS/Xilinx_Lib/XilinxCoreLib [QuestaSim] secureip = D:/unisim/secureip -simprim = D:/unisim/simprim -unimacro = D:/unisim/unimacro -unisim = D:/unisim/unisim -XilinxCoreLib = D:/unisim/xilinxcorelib +simprim = C:/FPGAdv82PS/Xilinx_Lib/simprim +unimacro = C:/FPGAdv82PS/Xilinx_Lib/unimacro +unisim = C:/FPGAdv82PS/Xilinx_Lib/unisim +XilinxCoreLib = C:/FPGAdv82PS/Xilinx_Lib/XilinxCoreLib [XilinxISE] FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/ise -FACT_FAD_TB_lib = $HDS_PROJECT_DIR\FACT_FAD_TB_lib\ise +FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise [hdl] FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/hdl Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd (revision 10154) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd (revision 10155) @@ -3,5 +3,5 @@ -- Created: -- by - dneise.UNKNOWN (E5B-LABOR6) --- at - 15:27:49 04.02.2011 +-- at - 13:26:27 14.02.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) @@ -32,5 +32,5 @@ -- Created: -- by - dneise.UNKNOWN (E5B-LABOR6) --- at - 15:27:49 04.02.2011 +-- at - 13:26:27 14.02.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) @@ -42,4 +42,6 @@ LIBRARY UNISIM; --USE UNISIM.Vcomponents.all; +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all; LIBRARY FACT_FAD_lib; @@ -56,4 +58,5 @@ SIGNAL PSEN_IN : std_logic; SIGNAL PSINCDEC_IN : std_logic; + SIGNAL rst : std_logic := '0'; --asynch in of DCM -- Implicit buffer signal declarations @@ -91,19 +94,19 @@ PORT ( CLK : IN std_logic ; - rst : IN std_logic ; --asynch in of DCM + rst : OUT std_logic := '0'; --asynch in of DCM -- interface to: clock_generator_variable_PS_struct.vhd PSCLK : OUT std_logic ; PSEN : OUT std_logic := '0'; - PSINCDEC : OUT std_logic := '1'; -- default is 'incrementing' - PSDONE : IN std_logic ; -- will pulse once, if phase shifting was done. - LOCKED : IN std_logic ; + PSINCDEC : OUT std_logic := '1'; -- default is 'incrementing' + PSDONE : IN std_logic ; -- will pulse once, if phase shifting was done. + LOCKED : IN std_logic ; -- when is this going high? -- interface to: w5300_modul.vhd shift_phase : IN std_logic ; - direction : IN std_logic ; -- corresponds TO 'PSINCDEC' + direction : IN std_logic ; -- corresponds TO 'PSINCDEC' + reset_DCM : IN std_logic ; -- asynch in: orders us, TO reset the DCM -- status: shifting : OUT std_logic := '0'; ready : OUT std_logic := '0'; - offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); - DCM_locked : OUT std_logic + offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ); END COMPONENT; @@ -139,5 +142,5 @@ PSEN_IN => PSEN_IN, PSINCDEC_IN => PSINCDEC_IN, - RST_IN => RST_IN, + RST_IN => rst, CLK0_OUT => CLK_25_PS, LOCKED_OUT => LOCKED_OUT, @@ -147,5 +150,5 @@ PORT MAP ( CLK => CLK0_OUT, - rst => RST_IN, + rst => rst, PSCLK => PSCLK_IN, PSEN => PSEN_IN, @@ -155,8 +158,8 @@ shift_phase => do_shift, direction => direction, + reset_DCM => RST_IN, shifting => OPEN, ready => OPEN, - offset => offset, - DCM_locked => OPEN + offset => offset ); Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_unit_struct.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_unit_struct.vhd (revision 10154) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_unit_struct.vhd (revision 10155) @@ -3,5 +3,5 @@ -- Created: -- by - dneise.UNKNOWN (E5B-LABOR6) --- at - 11:39:13 04.02.2011 +-- at - 13:10:37 12.02.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) @@ -42,5 +42,5 @@ -- Created: -- by - dneise.UNKNOWN (E5B-LABOR6) --- at - 11:39:13 04.02.2011 +-- at - 13:10:37 12.02.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd (revision 10154) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd (revision 10155) @@ -45,8 +45,40 @@ sensor_ready : in std_logic; dac_array : in dac_array_type; + + -- EVT HEADER - part 1 package_length : in std_logic_vector (15 downto 0); + pll_lock : in std_logic_vector ( 3 downto 0); + -- + + -- EVT HEADER - part 2 --> FTM trigger informaton, comes in late ... + -- during EVT header wrinting, this field is left out ... and only written into event header, + -- when the DRS chip were read out already. + FTM_RS485_ready : in std_logic; + FTM_trigger_info : in std_logic_vector (55 downto 0); --7 byte + -- + + -- EVT HEADER - part 3 + fad_event_counter : in std_logic_vector (31 downto 0); + refclk_counter : in std_logic_vector (11 downto 0); + refclk_too_high: in std_logic; + refclk_too_low : in std_logic; + -- + + -- EVT HEADER - part 4 board_id : in std_logic_vector (3 downto 0); crate_id : in std_logic_vector (1 downto 0); - trigger_id : in std_logic_vector (47 downto 0); + DCM_PS_status : in std_logic_vector (7 downto 0); + TRG_GEN_no : in std_logic_vector (15 downto 0); + TRG_GEN_div : in std_logic_vector (15 downto 0); + -- + + -- EVT HEADER - part 5 + dna : in std_logic_vector (63 downto 0); + -- + + -- EVT HEADER - part 6 + timer_value : in std_logic_vector (31 downto 0); -- time in units of 100us + -- + trigger : in std_logic; -- s_trigger : in std_logic; @@ -79,8 +111,17 @@ architecture Behavioral of data_generator is -type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, CONFIG7, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES, - WRITE_DAC1, WRITE_DAC2, WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_ADC_DATA, WRITE_DATA_END, WRITE_DATA_END_WAIT, - WRITE_END_FLAG, WRITE_DATA_STOP, WRITE_DATA_STOP1, - WRITE_DATA_IDLE, WAIT_FOR_ADC, WAIT_FOR_STOP_CELL, START_DRS_READING); +type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, CONFIG5, CONFIG6, CONFIG7, + WRITE_DATA_IDLE, + WRITE_HEADER, WRITE_FTM_INFO, WRITE_EVENTCOUNTER_AND_REFCLK_COUNTER, WRITE_BOARD_ID, + WRITE_DNA, WRITE_TIMER, WRITE_TEMPERATURES, + WRITE_DAC1, WRITE_DAC2, + WAIT_FOR_STOP_CELL, + START_DRS_READING, + WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_FILLING, + WAIT_FOR_ADC, WRITE_ADC_DATA, + WRITE_EXTERNAL_TRIGGER, + WRITE_END_FLAG, + WRITE_DATA_END, WRITE_DATA_END_WAIT, + WRITE_DATA_STOP, WRITE_DATA_STOP1); signal state_generate : state_generate_type := INIT; @@ -199,11 +240,39 @@ when WRITE_HEADER => write_ea <= "1"; - data_out <= X"0000" & PACKAGE_VERSION & PACKAGE_SUB_VERSION & package_length & X"FB01"; - addr_cntr <= addr_cntr + 3; - state_generate <= WRITE_BOARD_ID; - when WRITE_BOARD_ID => -- crate ID & board ID - data_out <= (63 downto 10 => '0') & crate_id & "1000" & board_id; - addr_cntr <= addr_cntr + 1; - state_generate <= WRITE_TEMPERATURES; + data_out <= X"000" & pll_lock & PACKAGE_VERSION & PACKAGE_SUB_VERSION & package_length & X"FB01"; + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_FTM_INFO; + + when WRITE_FTM_INFO => + -- here we do not write the FTM info ... just jump over it. + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_EVENTCOUNTER_AND_REFCLK_COUNTER; + + when WRITE_EVENTCOUNTER_AND_REFCLK_COUNTER => + data_out <= X"0000" & + refclk_too_high & refclk_too_low & "00" & refclk_counter & + fad_event_counter(15 downto 0) & + fad_event_counter(31 downto 16) ; + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_BOARD_ID; + -- crate ID & board ID + -- and a lot more... + -- info about the phase shifter + -- status of the trigger generator + when WRITE_BOARD_ID => + data_out <= TRG_GEN_div & TRG_GEN_no & X"00" & DCM_PS_status & "000000" & crate_id & "1000" & board_id; + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_DNA; + + when WRITE_DNA => + data_out <= X"00" & dna(55 downto 0); + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_TIMER; + + when WRITE_TIMER => + data_out <= X"0000" & X"0000" & timer_value; -- 2times 16bit reserved for additional status info + addr_cntr <= addr_cntr + 1; + state_generate <= WRITE_TEMPERATURES; + when WRITE_TEMPERATURES => -- temperatures if (sensor_ready = '1') then @@ -248,8 +317,8 @@ when WRITE_CHANNEL_ID => -- write DRS and Channel IDs - data_out <= conv_std_logic_vector(0,10) & conv_std_logic_vector(3,2) & conv_std_logic_vector(channel_id,4) - & conv_std_logic_vector(0,10) & conv_std_logic_vector(2,2) & conv_std_logic_vector(channel_id,4) - & conv_std_logic_vector(0,10) & conv_std_logic_vector(1,2) & conv_std_logic_vector(channel_id,4) - & conv_std_logic_vector(0,10) & conv_std_logic_vector(0,2) & conv_std_logic_vector(channel_id,4); + data_out <= conv_std_logic_vector(3,12) & conv_std_logic_vector(channel_id,4) + & conv_std_logic_vector(2,12) & conv_std_logic_vector(channel_id,4) + & conv_std_logic_vector(1,12) & conv_std_logic_vector(channel_id,4) + & conv_std_logic_vector(0,12) & conv_std_logic_vector(channel_id,4); addr_cntr <= addr_cntr + 1; state_generate <= WRITE_START_CELL; @@ -267,5 +336,11 @@ & "00000" & conv_std_logic_vector (roi_array((0) * 9 + channel_id), 11); addr_cntr <= addr_cntr + 1; - state_generate <= WAIT_FOR_ADC; + state_generate <= WRITE_FILLING; + + when WRITE_FILLING => -- write FILLING + data_out <= conv_std_logic_vector(0,64); -- filling + addr_cntr <= addr_cntr + 1; + state_generate <= WAIT_FOR_ADC; + when WAIT_FOR_ADC => -- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! @@ -281,5 +356,5 @@ & "000" & adc_otr(1) & adc_data_array(1) & "000" & adc_otr(0) & adc_data_array(0); - -- data_out <= "00000" & conv_std_logic_vector (data_cntr, 11) +-- data_out <= "00000" & conv_std_logic_vector (data_cntr, 11) -- & "00010" & conv_std_logic_vector (data_cntr, 11) -- & "00100" & conv_std_logic_vector (data_cntr, 11) @@ -303,14 +378,12 @@ end if; - when WRITE_EXTERNAL_TRIGGER => -- external trigger ID addr_out <= start_addr + conv_std_logic_vector(1, RAM_ADDR_WIDTH); --- data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & trigger_id(15 downto 0) & trigger_id(31 downto 16); - data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & evnt_cntr(15 downto 0) & evnt_cntr(31 downto 16); - state_generate <= WRITE_INTERNAL_TRIGGER; - when WRITE_INTERNAL_TRIGGER => -- internal trigger ID - addr_out <= start_addr + conv_std_logic_vector(2, RAM_ADDR_WIDTH); - data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & evnt_cntr(15 downto 0) & evnt_cntr(31 downto 16); + data_out <= FTM_trigger_info(15 downto 0) + & FTM_trigger_info(31 downto 16) + & FTM_trigger_info(47 downto 32) + & X"00" & FTM_trigger_info(55 downto 48); state_generate <= WRITE_END_FLAG; + when WRITE_END_FLAG => data_out <= (63 downto 32 => '0') & X"04FE" & X"4242"; Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/dna_gen.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/dna_gen.vhd (revision 10155) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/dna_gen.vhd (revision 10155) @@ -0,0 +1,109 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: Q. Weitzel +-- +-- Create Date: 10/06/2010 +-- Design Name: +-- Module Name: FTU_dna_gen - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: entity to read out the FPGA DNA identifier +-- +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +entity dna_gen is + Port ( + clk : IN STD_LOGIC; + start : IN STD_LOGIC; + dna : OUT STD_LOGIC_VECTOR(63 downto 0) := (others => '0'); + ready : OUT STD_LOGIC := '0' + ); +end dna_gen; + +architecture Behavioral of dna_gen is + constant DNA_FOR_SIM : bit_vector := X"01710000E000FAD2"; -- for simulation only + signal dout_sig : STD_LOGIC := '0'; + signal read_sig : STD_LOGIC := '0'; + signal shift_sig : STD_LOGIC := '0'; + signal dna_sig : STD_LOGIC_VECTOR(63 downto 0) := (others => '0'); + + type FTU_dna_gen_StateType is (IDLE, READ_DNA, SHIFT_DNA, DNA_READY); + signal FTU_dna_gen_State : FTU_dna_gen_StateType; + + signal shift_cntr : INTEGER range 0 to 64 := 0; + +begin + + DNA_PORT_inst : DNA_PORT + generic map ( + SIM_DNA_VALUE => DNA_FOR_SIM) -- Specifies the Pre-programmed factory ID value + port map ( + DOUT => dout_sig, -- 1-bit DNA output data + CLK => clk, -- 1-bit clock input + DIN => '0', -- 1-bit user data input pin + READ => read_sig, -- 1-bit input, active high load DNA, active low read + SHIFT => shift_sig -- 1-bit input, active high shift enable + ); + + FTU_dna_gen_FSM : process(clk) + begin + if Falling_edge(clk) then + case FTU_dna_gen_State is + when IDLE => + ready <= '0'; + read_sig <= '0'; + shift_sig <= '0'; + if (start = '1') then + FTU_dna_gen_State <= READ_DNA; + else + FTU_dna_gen_State <= IDLE; + end if; + when READ_DNA => + ready <= '0'; + read_sig <= '1'; + shift_sig <= '0'; + FTU_dna_gen_State <= SHIFT_DNA; + when SHIFT_DNA => + shift_cntr <= shift_cntr + 1; + ready <= '0'; + read_sig <= '0'; + if (shift_cntr < 57) then + dna_sig <= dna_sig(62 downto 0) & dout_sig; -- put in from right + shift_sig <= '1'; + FTU_dna_gen_State <= SHIFT_DNA; + --elsif (shift_cntr = 56) then + --dna_sig <= dna_sig(62 downto 0) & dout_sig; -- put in from right + --shift_sig <= '0'; + --FTU_dna_gen_State <= SHIFT_DNA; + else + shift_sig <= '1'; + FTU_dna_gen_State <= DNA_READY; + end if; + when DNA_READY => + ready <= '1'; + read_sig <= '0'; + shift_sig <= '0'; + end case; + end if; + end process FTU_dna_gen_FSM; + + dna <= dna_sig; + +end Behavioral; Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd (revision 10154) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd (revision 10155) @@ -3,5 +3,5 @@ -- Created: -- by - dneise.UNKNOWN (E5B-LABOR6) --- at - 15:27:51 04.02.2011 +-- at - 13:26:28 14.02.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) @@ -76,5 +76,5 @@ -- Created: -- by - dneise.UNKNOWN (E5B-LABOR6) --- at - 15:27:51 04.02.2011 +-- at - 13:26:28 14.02.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd (revision 10154) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd (revision 10155) @@ -56,4 +56,5 @@ constant PACKAGE_HEADER_LENGTH : integer := 22; constant PACKAGE_END_LENGTH : integer := 2; -- CRC and END-Flag + constant CHANNEL_HEADER_SIZE : integer := 3; constant W5300_S_INC : std_logic_vector(6 downto 0) := "1000000"; -- socket address offset Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd (revision 10154) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd (revision 10155) @@ -3,5 +3,5 @@ -- Created: -- by - dneise.UNKNOWN (E5B-LABOR6) --- at - 15:27:49 04.02.2011 +-- at - 13:26:27 14.02.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) @@ -72,5 +72,5 @@ -- Created: -- by - dneise.UNKNOWN (E5B-LABOR6) --- at - 15:27:50 04.02.2011 +-- at - 13:26:28 14.02.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) @@ -171,5 +171,5 @@ SIGNAL trigger_enable : std_logic; SIGNAL trigger_id : std_logic_vector(47 DOWNTO 0); - SIGNAL trigger_out : std_logic; + SIGNAL trigger_out : std_logic := '0'; SIGNAL wiz_ack : std_logic; SIGNAL wiz_busy : std_logic; @@ -451,30 +451,49 @@ c_trigger_enable : OUT std_logic := '0'; c_trigger_mult : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '1'); --subject TO changes - -- + -- FAD configuration signals: + ------------------------------------------------------------------------------ + -- start entire configuration chain new_config : OUT std_logic := '0'; config_started : IN std_logic ; + -- read/write configRAM config_addr : OUT std_logic_vector (7 DOWNTO 0); config_data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); config_wr_en : OUT std_logic := '0'; config_rd_en : OUT std_logic := '0'; - -- -- config_rw_ack : IN std_logic ; - -- -- config_rw_ready : IN std_logic ; - -- -- config_busy : IN std_logic ; + ------------------------------------------------------------------------------ + + -- MAC/IP calculation signals: + ------------------------------------------------------------------------------ MAC_jumper : IN std_logic_vector (1 DOWNTO 0); BoardID : IN std_logic_vector (3 DOWNTO 0); CrateID : IN std_logic_vector (1 DOWNTO 0); + ------------------------------------------------------------------------------ + + -- user controllable enable signals + ------------------------------------------------------------------------------ + trigger_enable : OUT std_logic := '0'; -- default triggers are NOT accepted denable : OUT std_logic := '0'; -- default domino wave off dwrite_enable : OUT std_logic := '0'; -- default DWRITE low. sclk_enable : OUT std_logic := '1'; -- default DWRITE HIGH. + srclk_enable : OUT std_logic := '1'; -- default SRCLK on. + ------------------------------------------------------------------------------ + + -- ADC CLK generator, is able to shift phase with respect to X_50M + -- these signals control the behavior of the digital clock manager (DCM) + ------------------------------------------------------------------------------ ps_direction : OUT std_logic := '1'; -- default phase shift upwards ps_do_phase_shift : OUT std_logic := '0'; --pulse this TO phase shift once ps_reset : OUT std_logic := '0'; -- pulse this TO reset the variable phase shift - srclk_enable : OUT std_logic := '1'; -- default SRCLK on. - trigger_enable : OUT std_logic := '0'; -- default triggers are NOT accepted + ------------------------------------------------------------------------------ + + -- signals used to control FAD LED bahavior: + -- one of the three LEDs is used for com-status info + ------------------------------------------------------------------------------ socks_waiting : OUT std_logic ; socks_connected : OUT std_logic + ------------------------------------------------------------------------------ ); END COMPONENT; Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd (revision 10154) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd (revision 10155) @@ -51,5 +51,5 @@ wiz_write_end : OUT std_logic := '0'; wiz_busy : IN std_logic; - wiz_ack : IN std_logic; + wiz_ack : IN std_logic; ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0') ); @@ -134,5 +134,5 @@ roi_max_array (channel_id) <= temp_roi; end if; - channel_size (channel_id) <= channel_size (channel_id) + temp_roi + 3; + channel_size (channel_id) <= channel_size (channel_id) + temp_roi + CHANNEL_HEADER_SIZE; drs_id <= drs_id + 1; state_mm <= MAX_ROI; Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/phase_shifter.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/phase_shifter.vhd (revision 10154) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/phase_shifter.vhd (revision 10155) @@ -35,4 +35,5 @@ shifting : OUT std_logic := '0'; ready : OUT std_logic := '0'; + offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') @@ -93,5 +94,5 @@ -- MAIN FSM - FSM: process(state, PSDONE, LOCKED, shift_phase, direction, local_direction) + FSM: process(CLK) begin @@ -144,5 +145,5 @@ end if; - if (reset_dcm_sr = "01") then + if (reset_dcm_sr = "01") then state <= RESET_STATE; end if; Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_interface_struct.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_interface_struct.vhd (revision 10154) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_interface_struct.vhd (revision 10155) @@ -3,5 +3,5 @@ -- Created: -- by - dneise.UNKNOWN (E5B-LABOR6) --- at - 16:13:08 03.02.2011 +-- at - 13:10:37 12.02.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) @@ -38,5 +38,5 @@ -- Created: -- by - dneise.UNKNOWN (E5B-LABOR6) --- at - 16:13:08 03.02.2011 +-- at - 13:10:37 12.02.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/trigger_counter_beha.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/trigger_counter_beha.vhd (revision 10154) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/trigger_counter_beha.vhd (revision 10155) @@ -16,5 +16,5 @@ entity trigger_counter is port( - trigger_id : out std_logic_vector(47 downto 0); + trigger_id : out std_logic_vector(31 downto 0); trigger : in std_logic; clk : in std_logic @@ -29,5 +29,5 @@ begin - trigger_id <= X"AA55" & conv_std_logic_vector(temp_id, 32); + trigger_id <= conv_std_logic_vector(temp_id, 32); trigger_incr_proc: process(clk) Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/clock_generator_var_ps_struct.xrf =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/clock_generator_var_ps_struct.xrf (revision 10154) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/clock_generator_var_ps_struct.xrf (revision 10155) @@ -43,203 +43,209 @@ DESIGN clock_generator_var_ps VIEW struct.bd -NO_GRAPHIC 43 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 0,0 46 2 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 524,0 51 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 600,0 52 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 530,0 53 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 586,0 54 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 544,0 55 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 558,0 56 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -NO_GRAPHIC 57 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 229,0 59 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -NO_GRAPHIC 61 +NO_GRAPHIC 45 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 0,0 48 2 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 524,0 53 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 600,0 54 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 530,0 55 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 586,0 56 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 544,0 57 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 558,0 58 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 1979,0 59 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +NO_GRAPHIC 60 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 229,0 62 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +NO_GRAPHIC 64 LIBRARY FACT_FAD_lib DESIGN dcm_50_to_25 VIEW @b@e@h@a@v@i@o@r@a@l -GRAPHIC 403,0 63 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -NO_GRAPHIC 69 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 354,0 71 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -NO_GRAPHIC 75 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 514,0 77 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -NO_GRAPHIC 87 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 826,0 89 0 -DESIGN phase_shifter -VIEW first_behave -GRAPHIC 48,0 91 0 -DESIGN phase_shifter -VIEW first_behave -GRAPHIC 281,0 92 0 -DESIGN phase_shifter -VIEW first_behave -GRAPHIC 53,0 93 0 -DESIGN phase_shifter -VIEW first_behave -GRAPHIC 58,0 95 0 -DESIGN phase_shifter -VIEW first_behave -GRAPHIC 63,0 96 0 -DESIGN phase_shifter -VIEW first_behave -GRAPHIC 68,0 97 0 -DESIGN phase_shifter -VIEW first_behave -GRAPHIC 73,0 98 0 -DESIGN phase_shifter -VIEW first_behave -GRAPHIC 83,0 99 0 -DESIGN phase_shifter -VIEW first_behave -GRAPHIC 88,0 101 0 -DESIGN phase_shifter -VIEW first_behave -GRAPHIC 93,0 102 0 -DESIGN phase_shifter -VIEW first_behave -GRAPHIC 98,0 104 0 -DESIGN phase_shifter -VIEW first_behave -GRAPHIC 103,0 105 0 -DESIGN phase_shifter -VIEW first_behave -GRAPHIC 108,0 106 0 +GRAPHIC 403,0 66 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +NO_GRAPHIC 72 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 354,0 74 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +NO_GRAPHIC 78 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 514,0 80 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +NO_GRAPHIC 90 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 826,0 92 0 +DESIGN phase_shifter +VIEW first_behave +GRAPHIC 48,0 94 0 +DESIGN phase_shifter +VIEW first_behave +GRAPHIC 281,0 95 0 +DESIGN phase_shifter +VIEW first_behave +GRAPHIC 53,0 96 0 +DESIGN phase_shifter +VIEW first_behave +GRAPHIC 58,0 98 0 +DESIGN phase_shifter +VIEW first_behave +GRAPHIC 63,0 99 0 +DESIGN phase_shifter +VIEW first_behave +GRAPHIC 68,0 100 0 +DESIGN phase_shifter +VIEW first_behave +GRAPHIC 73,0 101 0 +DESIGN phase_shifter +VIEW first_behave +GRAPHIC 83,0 102 0 +DESIGN phase_shifter +VIEW first_behave +GRAPHIC 88,0 104 0 +DESIGN phase_shifter +VIEW first_behave +GRAPHIC 362,0 105 0 +DESIGN phase_shifter +VIEW first_behave +GRAPHIC 93,0 106 0 +DESIGN phase_shifter +VIEW first_behave +GRAPHIC 98,0 108 0 +DESIGN phase_shifter +VIEW first_behave +GRAPHIC 103,0 109 0 LIBRARY FACT_FAD_lib DESIGN clock_generator_var_ps VIEW struct.bd -NO_GRAPHIC 109 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 403,0 112 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 354,0 113 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 514,0 114 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 826,0 115 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -NO_GRAPHIC 118 -DESIGN clock_generator_var_ps -VIEW struct.bd -NO_GRAPHIC 120 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 403,0 122 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 163,0 124 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 209,0 125 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 191,0 127 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 354,0 129 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 229,0 131 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 526,0 132 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 514,0 134 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 526,0 136 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 532,0 137 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 546,0 138 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 841,0 139 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 1493,0 140 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 1254,0 141 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 602,0 142 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 588,0 143 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 826,0 145 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 1458,0 147 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 1625,0 148 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 532,0 149 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 546,0 150 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 841,0 151 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 588,0 152 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 602,0 153 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 1272,0 154 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 1286,0 155 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 1609,0 158 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -GRAPHIC 229,0 163 0 -DESIGN clock_generator_var_ps -VIEW struct.bd -NO_GRAPHIC 165 +NO_GRAPHIC 112 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 403,0 115 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 354,0 116 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 514,0 117 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 826,0 118 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +NO_GRAPHIC 121 +DESIGN clock_generator_var_ps +VIEW struct.bd +NO_GRAPHIC 123 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 403,0 125 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 163,0 127 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 209,0 128 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 191,0 130 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 354,0 132 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 229,0 134 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 526,0 135 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 514,0 137 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 526,0 139 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 532,0 140 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 546,0 141 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 841,0 142 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 1981,0 143 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 1254,0 144 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 602,0 145 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 588,0 146 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 826,0 148 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 1458,0 150 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 1981,0 151 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 532,0 152 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 546,0 153 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 841,0 154 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 588,0 155 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 602,0 156 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 1272,0 157 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 1286,0 158 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 1493,0 159 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 1609,0 162 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +GRAPHIC 229,0 166 0 +DESIGN clock_generator_var_ps +VIEW struct.bd +NO_GRAPHIC 168 Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_main_struct.xrf =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_main_struct.xrf (revision 10154) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_main_struct.xrf (revision 10155) @@ -367,5 +367,5 @@ DESIGN @f@a@d_main VIEW struct.bd -GRAPHIC 10449,0 172 0 +GRAPHIC 15492,0 172 0 DESIGN @f@a@d_main VIEW struct.bd @@ -884,26 +884,26 @@ DESIGN w5300_modul VIEW @behavioral -GRAPHIC 566,0 454 0 -DESIGN w5300_modul -VIEW @behavioral -GRAPHIC 551,0 455 0 -DESIGN w5300_modul -VIEW @behavioral -GRAPHIC 561,0 456 0 -DESIGN w5300_modul -VIEW @behavioral -GRAPHIC 571,0 457 0 -DESIGN w5300_modul -VIEW @behavioral -GRAPHIC 640,0 458 0 -DESIGN w5300_modul -VIEW @behavioral -GRAPHIC 1052,0 459 0 -DESIGN w5300_modul -VIEW @behavioral -GRAPHIC 1057,0 461 0 -DESIGN w5300_modul -VIEW @behavioral -GRAPHIC 556,0 463 0 +GRAPHIC 566,0 456 0 +DESIGN w5300_modul +VIEW @behavioral +GRAPHIC 551,0 457 0 +DESIGN w5300_modul +VIEW @behavioral +GRAPHIC 561,0 459 0 +DESIGN w5300_modul +VIEW @behavioral +GRAPHIC 571,0 460 0 +DESIGN w5300_modul +VIEW @behavioral +GRAPHIC 640,0 461 0 +DESIGN w5300_modul +VIEW @behavioral +GRAPHIC 1052,0 462 0 +DESIGN w5300_modul +VIEW @behavioral +GRAPHIC 1057,0 463 0 +DESIGN w5300_modul +VIEW @behavioral +GRAPHIC 556,0 464 0 DESIGN w5300_modul VIEW @behavioral @@ -911,435 +911,384 @@ DESIGN w5300_modul VIEW @behavioral -GRAPHIC 1315,0 466 0 -DESIGN w5300_modul -VIEW @behavioral -GRAPHIC 1320,0 467 0 -DESIGN w5300_modul -VIEW @behavioral -GRAPHIC 670,0 468 0 -DESIGN w5300_modul -VIEW @behavioral -GRAPHIC 723,0 469 0 -DESIGN w5300_modul -VIEW @behavioral -GRAPHIC 917,0 470 0 -DESIGN w5300_modul -VIEW @behavioral -GRAPHIC 949,0 471 0 -DESIGN w5300_modul -VIEW @behavioral -GRAPHIC 954,0 472 0 -DESIGN w5300_modul -VIEW @behavioral -GRAPHIC 988,0 473 0 -DESIGN w5300_modul -VIEW @behavioral -GRAPHIC 1020,0 474 0 -DESIGN w5300_modul -VIEW @behavioral -GRAPHIC 1130,0 475 0 -DESIGN w5300_modul -VIEW @behavioral -GRAPHIC 1096,0 476 0 -DESIGN w5300_modul -VIEW @behavioral -GRAPHIC 1091,0 477 0 +GRAPHIC 1315,0 470 0 +DESIGN w5300_modul +VIEW @behavioral +GRAPHIC 1320,0 471 0 +DESIGN w5300_modul +VIEW @behavioral +GRAPHIC 1130,0 472 0 +DESIGN w5300_modul +VIEW @behavioral +GRAPHIC 670,0 477 0 +DESIGN w5300_modul +VIEW @behavioral +GRAPHIC 723,0 478 0 +DESIGN w5300_modul +VIEW @behavioral +GRAPHIC 917,0 479 0 +DESIGN w5300_modul +VIEW @behavioral +GRAPHIC 1020,0 480 0 +DESIGN w5300_modul +VIEW @behavioral +GRAPHIC 949,0 481 0 +DESIGN w5300_modul +VIEW @behavioral +GRAPHIC 954,0 487 0 +DESIGN w5300_modul +VIEW @behavioral +GRAPHIC 988,0 488 0 +DESIGN w5300_modul +VIEW @behavioral +GRAPHIC 1096,0 489 0 +DESIGN w5300_modul +VIEW @behavioral +GRAPHIC 1091,0 495 0 LIBRARY FACT_FAD_lib DESIGN @f@a@d_main VIEW struct.bd -NO_GRAPHIC 480 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 14417,0 483 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 5678,0 484 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 9175,0 485 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 13117,0 486 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 5072,0 487 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 8277,0 488 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 1399,0 489 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 4903,0 490 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 11209,0 491 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 2311,0 492 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 5793,0 493 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 1768,0 494 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 12625,0 495 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 1606,0 496 0 -DESIGN @f@a@d_main -VIEW struct.bd NO_GRAPHIC 499 DESIGN @f@a@d_main VIEW struct.bd -GRAPHIC 6529,0 501 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 9957,0 504 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 8721,0 507 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 14991,0 510 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 12295,0 513 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 15058,0 516 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 15036,0 519 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 10380,0 523 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 13266,0 526 0 -DESIGN @f@a@d_main -VIEW struct.bd -NO_GRAPHIC 529 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 14417,0 531 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 14427,0 533 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 14048,0 534 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 14622,0 535 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 14479,0 536 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 14493,0 537 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 5678,0 539 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 5646,0 541 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 4272,0 542 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 2786,0 543 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 5626,0 544 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 5634,0 545 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 9175,0 547 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 4042,0 549 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 10036,0 550 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 9253,0 551 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 9261,0 552 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 6072,0 553 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 3984,0 554 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 3888,0 555 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 13117,0 558 0 -DESIGN @f@a@d_main -VIEW struct.bd -GRAPHIC 13124,0 559 1 -DESIGN @f@a@d_main -VIEW struct.bd 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9943,0 800 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 9951,0 801 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 11858,0 802 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 10637,0 803 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 10629,0 804 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 6276,0 808 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 3888,0 809 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 15138,0 810 0 +DESIGN @f@a@d_main +VIEW struct.bd +GRAPHIC 15130,0 811 0 +DESIGN @f@a@d_main +VIEW struct.bd +NO_GRAPHIC 813 Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd (revision 10154) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd (revision 10155) @@ -26,4 +26,8 @@ library "IEEE" unitName "std_logic_signed" +) +(DmPackageRef +library "UNISIM" +unitName "VComponents" ) ] @@ -278,4 +282,13 @@ uid 15058,0 ) +(Instance +name "U_0" +duLibraryName "FACT_FAD_lib" +duName "dna_gen" +elements [ +] +mwi 0 +uid 15728,0 +) ] libraryRefs [ @@ -333,5 +346,5 @@ (vvPair variable "date" -value "08.02.2011" +value "15.02.2011" ) (vvPair @@ -345,5 +358,5 @@ (vvPair variable "dd" -value "08" +value "15" ) (vvPair @@ -485,5 +498,5 @@ (vvPair variable "time" -value "11:06:22" +value "09:27:14" ) (vvPair @@ -1363,5 +1376,5 @@ preAdd 0 posAdd 0 -o 24 +o 25 suid 9,0 ) @@ -1369,41 +1382,4 @@ ) *29 (CptPort -uid 1388,0 -ps "OnEdgeStrategy" -shape (Triangle -uid 1389,0 -ro 90 -va (VaSet -vasetType 1 -fg "0,65535,0" -) -xt "-21750,69625,-21000,70375" -) -tg (CPTG -uid 1390,0 -ps "CptPortTextPlaceStrategy" -stg "VerticalLayoutStrategy" -f (Text -uid 1391,0 -va (VaSet -) -xt "-20000,69500,-13200,70500" -st "trigger_id : (47:0)" -blo "-20000,70300" -) -) -thePort (LogicalPort -decl (Decl -n "trigger_id" -t "std_logic_vector" -b "(47 downto 0)" -preAdd 0 -posAdd 0 -o 26 -suid 10,0 -) -) -) -*30 (CptPort uid 1392,0 ps "OnEdgeStrategy" @@ -1436,10 +1412,10 @@ preAdd 0 posAdd 0 -o 27 +o 28 suid 11,0 ) ) ) -*31 (CptPort +*30 (CptPort uid 1676,0 ps "OnEdgeStrategy" @@ -1471,10 +1447,10 @@ t "std_logic_vector" b "(1 downto 0)" -o 25 +o 26 suid 12,0 ) ) ) -*32 (CptPort +*31 (CptPort uid 2562,0 ps "OnEdgeStrategy" @@ -1511,5 +1487,5 @@ ) ) -*33 (CptPort +*32 (CptPort uid 2566,0 ps "OnEdgeStrategy" @@ -1549,5 +1525,5 @@ ) ) -*34 (CptPort +*33 (CptPort uid 2570,0 ps "OnEdgeStrategy" @@ -1584,5 +1560,5 @@ ) ) -*35 (CptPort +*34 (CptPort uid 2614,0 ps "OnEdgeStrategy" @@ -1619,5 +1595,5 @@ ) ) -*36 (CptPort +*35 (CptPort uid 2624,0 ps "OnEdgeStrategy" @@ -1655,5 +1631,5 @@ ) ) -*37 (CptPort +*36 (CptPort uid 2760,0 ps "OnEdgeStrategy" @@ -1685,5 +1661,5 @@ n "adc_oeb" t "std_logic" -o 31 +o 32 suid 23,0 i "'1'" @@ -1691,5 +1667,5 @@ ) ) -*38 (CptPort +*37 (CptPort uid 2764,0 ps "OnEdgeStrategy" @@ -1721,10 +1697,10 @@ t "std_logic_vector" b "(3 downto 0)" -o 33 +o 34 suid 24,0 ) ) ) -*39 (CptPort +*38 (CptPort uid 3918,0 ps "OnEdgeStrategy" @@ -1758,5 +1734,5 @@ b "(3 downto 0)" posAdd 0 -o 34 +o 35 suid 25,0 i "(others => '0')" @@ -1764,5 +1740,5 @@ ) ) -*40 (CptPort +*39 (CptPort uid 3922,0 ps "OnEdgeStrategy" @@ -1797,5 +1773,5 @@ preAdd 0 posAdd 0 -o 37 +o 38 suid 26,0 i "'0'" @@ -1803,5 +1779,5 @@ ) ) -*41 (CptPort +*40 (CptPort uid 3930,0 ps "OnEdgeStrategy" @@ -1835,5 +1811,5 @@ prec "-- --" preAdd 0 -o 38 +o 39 suid 33,0 i "'0'" @@ -1841,5 +1817,5 @@ ) ) -*42 (CptPort +*41 (CptPort uid 3934,0 ps "OnEdgeStrategy" @@ -1870,10 +1846,10 @@ n "drs_read_s_cell_ready" t "std_logic" -o 43 +o 44 suid 34,0 ) ) ) -*43 (CptPort +*42 (CptPort uid 3938,0 ps "OnEdgeStrategy" @@ -1904,10 +1880,10 @@ n "drs_s_cell_array" t "drs_s_cell_array_type" -o 44 +o 45 suid 35,0 ) ) ) -*44 (CptPort +*43 (CptPort uid 4246,0 ps "OnEdgeStrategy" @@ -1938,10 +1914,10 @@ n "adc_data_array" t "adc_data_array_type" -o 30 +o 31 suid 37,0 ) ) ) -*45 (CptPort +*44 (CptPort uid 5174,0 ps "OnEdgeStrategy" @@ -1978,5 +1954,5 @@ ) ) -*46 (CptPort +*45 (CptPort uid 5178,0 ps "OnEdgeStrategy" @@ -2018,5 +1994,5 @@ ) ) -*47 (CptPort +*46 (CptPort uid 5392,0 ps "OnEdgeStrategy" @@ -2053,5 +2029,5 @@ ) ) -*48 (CptPort +*47 (CptPort uid 5396,0 ps "OnEdgeStrategy" @@ -2088,5 +2064,5 @@ ) ) -*49 (CptPort +*48 (CptPort uid 5464,0 ps "OnEdgeStrategy" @@ -2123,5 +2099,5 @@ ) ) -*50 (CptPort +*49 (CptPort uid 5468,0 ps "OnEdgeStrategy" @@ -2158,5 +2134,5 @@ ) ) -*51 (CptPort +*50 (CptPort uid 5735,0 ps "OnEdgeStrategy" @@ -2198,5 +2174,5 @@ ) ) -*52 (CptPort +*51 (CptPort uid 5739,0 ps "OnEdgeStrategy" @@ -2237,5 +2213,5 @@ ) ) -*53 (CptPort +*52 (CptPort uid 5916,0 ps "OnEdgeStrategy" @@ -2268,5 +2244,5 @@ n "config_started" t "std_logic" -o 29 +o 30 suid 48,0 i "'0'" @@ -2274,5 +2250,5 @@ ) ) -*54 (CptPort +*53 (CptPort uid 5920,0 ps "OnEdgeStrategy" @@ -2306,10 +2282,10 @@ prec "-- s_trigger : in std_logic;" preAdd 0 -o 28 +o 29 suid 49,0 ) ) ) -*55 (CptPort +*54 (CptPort uid 5974,0 ps "OnEdgeStrategy" @@ -2346,5 +2322,5 @@ ) ) -*56 (CptPort +*55 (CptPort uid 5978,0 ps "OnEdgeStrategy" @@ -2381,5 +2357,5 @@ ) ) -*57 (CptPort +*56 (CptPort uid 5982,0 ps "OnEdgeStrategy" @@ -2416,5 +2392,5 @@ ) ) -*58 (CptPort +*57 (CptPort uid 6060,0 ps "OnEdgeStrategy" @@ -2451,5 +2427,5 @@ ) ) -*59 (CptPort +*58 (CptPort uid 9000,0 ps "OnEdgeStrategy" @@ -2481,5 +2457,5 @@ n "adc_clk_en" t "std_logic" -o 32 +o 33 suid 54,0 i "'0'" @@ -2487,5 +2463,5 @@ ) ) -*60 (CptPort +*59 (CptPort uid 10244,0 ps "OnEdgeStrategy" @@ -2518,5 +2494,5 @@ t "std_logic_vector" b "(7 downto 0)" -o 41 +o 42 suid 56,0 i "(others => '0')" @@ -2524,5 +2500,5 @@ ) ) -*61 (CptPort +*60 (CptPort uid 10248,0 ps "OnEdgeStrategy" @@ -2554,5 +2530,5 @@ n "drs_srin_write_8b" t "std_logic" -o 39 +o 40 suid 57,0 i "'0'" @@ -2560,5 +2536,5 @@ ) ) -*62 (CptPort +*61 (CptPort uid 10252,0 ps "OnEdgeStrategy" @@ -2589,10 +2565,10 @@ n "drs_srin_write_ack" t "std_logic" -o 40 +o 41 suid 58,0 ) ) ) -*63 (CptPort +*62 (CptPort uid 10256,0 ps "OnEdgeStrategy" @@ -2623,10 +2599,10 @@ n "drs_srin_write_ready" t "std_logic" -o 42 +o 43 suid 59,0 ) ) ) -*64 (CptPort +*63 (CptPort uid 10260,0 ps "OnEdgeStrategy" @@ -2666,5 +2642,5 @@ ) ) -*65 (CptPort +*64 (CptPort uid 11385,0 ps "OnEdgeStrategy" @@ -2697,5 +2673,5 @@ n "drs_readout_started" t "std_logic" -o 45 +o 46 suid 61,0 i "'0'" @@ -2703,5 +2679,5 @@ ) ) -*66 (CptPort +*65 (CptPort uid 12597,0 ps "OnEdgeStrategy" @@ -2737,5 +2713,5 @@ preAdd 0 posAdd 0 -o 35 +o 36 suid 62,0 i "'0'" @@ -2743,5 +2719,5 @@ ) ) -*67 (CptPort +*66 (CptPort uid 12601,0 ps "OnEdgeStrategy" @@ -2772,6 +2748,76 @@ n "drs_readout_ready_ack" t "std_logic" -o 36 +o 37 suid 63,0 +) +) +) +*67 (CptPort +uid 15740,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 15741,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "-21750,69625,-21000,70375" +) +tg (CPTG +uid 15742,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 15743,0 +va (VaSet +) +xt "-20000,69500,-10200,70500" +st "fad_event_counter : (31:0)" +blo "-20000,70300" +) +) +thePort (LogicalPort +decl (Decl +n "fad_event_counter" +t "std_logic_vector" +b "(31 downto 0)" +o 27 +suid 65,0 +) +) +) +*68 (CptPort +uid 15744,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 15745,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "-21750,95625,-21000,96375" +) +tg (CPTG +uid 15746,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 15747,0 +va (VaSet +) +xt "-20000,95500,-14500,96500" +st "pll_lock : (3:0)" +blo "-20000,96300" +) +) +thePort (LogicalPort +decl (Decl +n "pll_lock" +t "std_logic_vector" +b "( 3 downto 0)" +o 24 +suid 64,0 ) ) @@ -2794,5 +2840,5 @@ stg "VerticalLayoutStrategy" textVec [ -*68 (Text +*69 (Text uid 1402,0 va (VaSet @@ -2804,5 +2850,5 @@ tm "BdLibraryNameMgr" ) -*69 (Text +*70 (Text uid 1403,0 va (VaSet @@ -2814,5 +2860,5 @@ tm "CptNameMgr" ) -*70 (Text +*71 (Text uid 1404,0 va (VaSet @@ -2867,5 +2913,5 @@ archFileType "UNKNOWN" ) -*71 (Net +*72 (Net uid 1409,0 decl (Decl @@ -2886,5 +2932,5 @@ ) ) -*72 (Net +*73 (Net uid 1423,0 decl (Decl @@ -2906,5 +2952,5 @@ ) ) -*73 (PortIoIn +*74 (PortIoIn uid 1443,0 shape (CompositeShape @@ -2951,8 +2997,8 @@ ) ) -*74 (SaComponent +*75 (SaComponent uid 1606,0 optionalChildren [ -*75 (CptPort +*76 (CptPort uid 1542,0 ps "OnEdgeStrategy" @@ -2990,5 +3036,5 @@ ) ) -*76 (CptPort +*77 (CptPort uid 1546,0 ps "OnEdgeStrategy" @@ -3029,5 +3075,5 @@ ) ) -*77 (CptPort +*78 (CptPort uid 1550,0 ps "OnEdgeStrategy" @@ -3068,5 +3114,5 @@ ) ) -*78 (CptPort +*79 (CptPort uid 1554,0 ps "OnEdgeStrategy" @@ -3107,5 +3153,5 @@ ) ) -*79 (CptPort +*80 (CptPort uid 1558,0 ps "OnEdgeStrategy" @@ -3146,5 +3192,5 @@ ) ) -*80 (CptPort +*81 (CptPort uid 1562,0 ps "OnEdgeStrategy" @@ -3185,5 +3231,5 @@ ) ) -*81 (CptPort +*82 (CptPort uid 1570,0 ps "OnEdgeStrategy" @@ -3224,5 +3270,5 @@ ) ) -*82 (CptPort +*83 (CptPort uid 1574,0 ps "OnEdgeStrategy" @@ -3261,5 +3307,5 @@ ) ) -*83 (CptPort +*84 (CptPort uid 1578,0 ps "OnEdgeStrategy" @@ -3298,5 +3344,5 @@ ) ) -*84 (CptPort +*85 (CptPort uid 1582,0 ps "OnEdgeStrategy" @@ -3335,5 +3381,5 @@ ) ) -*85 (CptPort +*86 (CptPort uid 1586,0 ps "OnEdgeStrategy" @@ -3372,5 +3418,5 @@ ) ) -*86 (CptPort +*87 (CptPort uid 1590,0 ps "OnEdgeStrategy" @@ -3410,5 +3456,5 @@ ) ) -*87 (CptPort +*88 (CptPort uid 1594,0 ps "OnEdgeStrategy" @@ -3446,5 +3492,5 @@ ) ) -*88 (CptPort +*89 (CptPort uid 1598,0 ps "OnEdgeStrategy" @@ -3484,5 +3530,5 @@ ) ) -*89 (CptPort +*90 (CptPort uid 2218,0 ps "OnEdgeStrategy" @@ -3520,5 +3566,5 @@ ) ) -*90 (CptPort +*91 (CptPort uid 2222,0 ps "OnEdgeStrategy" @@ -3554,5 +3600,5 @@ ) ) -*91 (CptPort +*92 (CptPort uid 2226,0 ps "OnEdgeStrategy" @@ -3588,5 +3634,5 @@ ) ) -*92 (CptPort +*93 (CptPort uid 5216,0 ps "OnEdgeStrategy" @@ -3627,5 +3673,5 @@ ) ) -*93 (CptPort +*94 (CptPort uid 5275,0 ps "OnEdgeStrategy" @@ -3665,5 +3711,5 @@ ) ) -*94 (CptPort +*95 (CptPort uid 5924,0 ps "OnEdgeStrategy" @@ -3701,5 +3747,5 @@ ) ) -*95 (CptPort +*96 (CptPort uid 5928,0 ps "OnEdgeStrategy" @@ -3737,5 +3783,5 @@ ) ) -*96 (CptPort +*97 (CptPort uid 5932,0 ps "OnEdgeStrategy" @@ -3774,5 +3820,5 @@ ) ) -*97 (CptPort +*98 (CptPort uid 5936,0 ps "OnEdgeStrategy" @@ -3808,5 +3854,5 @@ ) ) -*98 (CptPort +*99 (CptPort uid 5940,0 ps "OnEdgeStrategy" @@ -3844,5 +3890,5 @@ ) ) -*99 (CptPort +*100 (CptPort uid 5944,0 ps "OnEdgeStrategy" @@ -3882,5 +3928,5 @@ ) ) -*100 (CptPort +*101 (CptPort uid 5970,0 ps "OnEdgeStrategy" @@ -3919,5 +3965,5 @@ ) ) -*101 (CptPort +*102 (CptPort uid 6356,0 ps "OnEdgeStrategy" @@ -3958,5 +4004,5 @@ ) ) -*102 (CptPort +*103 (CptPort uid 6446,0 ps "OnEdgeStrategy" @@ -3998,5 +4044,5 @@ ) ) -*103 (CptPort +*104 (CptPort uid 8406,0 ps "OnEdgeStrategy" @@ -4034,5 +4080,5 @@ ) ) -*104 (CptPort +*105 (CptPort uid 8748,0 ps "OnEdgeStrategy" @@ -4073,5 +4119,5 @@ ) ) -*105 (CptPort +*106 (CptPort uid 9223,0 ps "OnEdgeStrategy" @@ -4112,5 +4158,5 @@ ) ) -*106 (CptPort +*107 (CptPort uid 9227,0 ps "OnEdgeStrategy" @@ -4152,5 +4198,5 @@ ) ) -*107 (CptPort +*108 (CptPort uid 9933,0 ps "OnEdgeStrategy" @@ -4191,5 +4237,5 @@ ) ) -*108 (CptPort +*109 (CptPort uid 9937,0 ps "OnEdgeStrategy" @@ -4230,5 +4276,5 @@ ) ) -*109 (CptPort +*110 (CptPort uid 10212,0 ps "OnEdgeStrategy" @@ -4267,5 +4313,5 @@ ) ) -*110 (CptPort +*111 (CptPort uid 10216,0 ps "OnEdgeStrategy" @@ -4304,5 +4350,5 @@ ) ) -*111 (CptPort +*112 (CptPort uid 10619,0 ps "OnEdgeStrategy" @@ -4340,5 +4386,5 @@ ) ) -*112 (CptPort +*113 (CptPort uid 10623,0 ps "OnEdgeStrategy" @@ -4377,5 +4423,5 @@ ) ) -*113 (CptPort +*114 (CptPort uid 11838,0 ps "OnEdgeStrategy" @@ -4416,5 +4462,5 @@ ) ) -*114 (CptPort +*115 (CptPort uid 13149,0 ps "OnEdgeStrategy" @@ -4452,5 +4498,5 @@ ) ) -*115 (CptPort +*116 (CptPort uid 13153,0 ps "OnEdgeStrategy" @@ -4491,5 +4537,5 @@ ) ) -*116 (CptPort +*117 (CptPort uid 13806,0 ps "OnEdgeStrategy" @@ -4526,5 +4572,5 @@ ) ) -*117 (CptPort +*118 (CptPort uid 13911,0 ps "OnEdgeStrategy" @@ -4561,5 +4607,5 @@ ) ) -*118 (CptPort +*119 (CptPort uid 13915,0 ps "OnEdgeStrategy" @@ -4613,5 +4659,5 @@ stg "VerticalLayoutStrategy" textVec [ -*119 (Text +*120 (Text uid 1609,0 va (VaSet @@ -4623,5 +4669,5 @@ tm "BdLibraryNameMgr" ) -*120 (Text +*121 (Text uid 1610,0 va (VaSet @@ -4633,5 +4679,5 @@ tm "CptNameMgr" ) -*121 (Text +*122 (Text uid 1611,0 va (VaSet @@ -4686,5 +4732,5 @@ archFileType "UNKNOWN" ) -*122 (Net +*123 (Net uid 1680,0 decl (Decl @@ -4705,8 +4751,8 @@ ) ) -*123 (SaComponent +*124 (SaComponent uid 1768,0 optionalChildren [ -*124 (CptPort +*125 (CptPort uid 1760,0 ps "OnEdgeStrategy" @@ -4729,5 +4775,5 @@ ) xt "-48800,68500,-42000,69500" -st "trigger_id : (47:0)" +st "trigger_id : (31:0)" ju 2 blo "-42000,69300" @@ -4740,5 +4786,5 @@ n "trigger_id" t "std_logic_vector" -b "(47 downto 0)" +b "(31 downto 0)" preAdd 0 posAdd 0 @@ -4748,5 +4794,5 @@ ) ) -*125 (CptPort +*126 (CptPort uid 1764,0 ps "OnEdgeStrategy" @@ -4785,5 +4831,5 @@ ) ) -*126 (CptPort +*127 (CptPort uid 6207,0 ps "OnEdgeStrategy" @@ -4837,5 +4883,5 @@ stg "VerticalLayoutStrategy" textVec [ -*127 (Text +*128 (Text uid 1771,0 va (VaSet @@ -4848,5 +4894,5 @@ tm "BdLibraryNameMgr" ) -*128 (Text +*129 (Text uid 1772,0 va (VaSet @@ -4859,5 +4905,5 @@ tm "CptNameMgr" ) -*129 (Text +*130 (Text uid 1773,0 va (VaSet @@ -4907,26 +4953,4 @@ ) archFileType "UNKNOWN" -) -*130 (Net -uid 1981,0 -lang 2 -decl (Decl -n "trigger_id" -t "std_logic_vector" -b "(47 downto 0)" -preAdd 0 -posAdd 0 -o 119 -suid 34,0 -) -declText (MLText -uid 1982,0 -va (VaSet -font "Courier New,8,0" -) -xt "-172000,98800,-139500,99600" -st "SIGNAL trigger_id : std_logic_vector(47 downto 0) -" -) ) *131 (Net @@ -17011,5 +17035,284 @@ ) ) -*599 (Wire +*599 (SaComponent +uid 15728,0 +optionalChildren [ +*600 (CptPort +uid 15712,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 15713,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "-83750,113625,-83000,114375" +) +tg (CPTG +uid 15714,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 15715,0 +va (VaSet +) +xt "-82000,113500,-80700,114500" +st "clk" +blo "-82000,114300" +) +) +thePort (LogicalPort +decl (Decl +n "clk" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 1 +suid 1,0 +) +) +) +*601 (CptPort +uid 15716,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 15717,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "-83750,115625,-83000,116375" +) +tg (CPTG +uid 15718,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 15719,0 +va (VaSet +) +xt "-82000,115500,-80100,116500" +st "start" +blo "-82000,116300" +) +) +thePort (LogicalPort +decl (Decl +n "start" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 2 +suid 2,0 +) +) +) +*602 (CptPort +uid 15720,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 15721,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "-73000,113625,-72250,114375" +) +tg (CPTG +uid 15722,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 15723,0 +va (VaSet +) +xt "-78600,113500,-74000,114500" +st "dna : (63:0)" +ju 2 +blo "-74000,114300" +) +t (Text +uid 15738,0 +va (VaSet +) +xt "-79700,114500,-74000,115500" +st "(others => '0')" +ju 2 +blo "-74000,115300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "dna" +t "STD_LOGIC_VECTOR" +b "(63 downto 0)" +preAdd 0 +posAdd 0 +o 3 +suid 3,0 +i "(others => '0')" +) +) +) +*603 (CptPort +uid 15724,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 15725,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "-73000,115625,-72250,116375" +) +tg (CPTG +uid 15726,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 15727,0 +va (VaSet +) +xt "-76200,115500,-74000,116500" +st "ready" +ju 2 +blo "-74000,116300" +) +t (Text +uid 15739,0 +va (VaSet +) +xt "-75200,116500,-74000,117500" +st "'0'" +ju 2 +blo "-74000,117300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "ready" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 4 +suid 4,0 +i "'0'" +) +) +) +] +shape (Rectangle +uid 15729,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "-83000,112000,-73000,118000" +) +oxt "39000,2000,49000,12000" +ttg (MlTextGroup +uid 15730,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*604 (Text +uid 15731,0 +va (VaSet +font "Arial,8,1" +) +xt "-80800,118000,-74600,119000" +st "FACT_FAD_lib" +blo "-80800,118800" +tm "BdLibraryNameMgr" +) +*605 (Text +uid 15732,0 +va (VaSet +font "Arial,8,1" +) +xt "-80800,119000,-77200,120000" +st "dna_gen" +blo "-80800,119800" +tm "CptNameMgr" +) +*606 (Text +uid 15733,0 +va (VaSet +font "Arial,8,1" +) +xt "-80800,120000,-79000,121000" +st "U_0" +blo "-80800,120800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 15734,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 15735,0 +text (MLText +uid 15736,0 +va (VaSet +font "Courier New,8,0" +) +xt "-83000,111000,-83000,111000" +) +header "" +) +elements [ +] +) +viewicon (ZoomableIcon +uid 15737,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "-82750,116250,-81250,117750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +ordering 1 +viewiconposition 0 +portVis (PortSigDisplay +sIVOD 1 +) +archFileType "UNKNOWN" +) +*607 (Net +uid 15748,0 +lang 2 +decl (Decl +n "trigger_id" +t "std_logic_vector" +b "(31 downto 0)" +preAdd 0 +posAdd 0 +o 123 +suid 302,0 +) +declText (MLText +uid 15749,0 +va (VaSet +font "Courier New,8,0" +) +xt "-172000,98800,-139500,99600" +st "SIGNAL trigger_id : std_logic_vector(31 downto 0) +" +) +) +*608 (Wire uid 322,0 shape (OrthoPolyLine @@ -17050,5 +17353,5 @@ on &2 ) -*600 (Wire +*609 (Wire uid 328,0 shape (OrthoPolyLine @@ -17089,5 +17392,5 @@ on &3 ) -*601 (Wire +*610 (Wire uid 334,0 shape (OrthoPolyLine @@ -17128,5 +17431,5 @@ on &4 ) -*602 (Wire +*611 (Wire uid 364,0 shape (OrthoPolyLine @@ -17144,5 +17447,5 @@ ] ) -start &86 +start &87 end &336 sat 32 @@ -17168,5 +17471,5 @@ on &5 ) -*603 (Wire +*612 (Wire uid 370,0 shape (OrthoPolyLine @@ -17184,5 +17487,5 @@ ] ) -start &85 +start &86 end &337 sat 32 @@ -17208,5 +17511,5 @@ on &6 ) -*604 (Wire +*613 (Wire uid 376,0 shape (OrthoPolyLine @@ -17221,5 +17524,5 @@ ] ) -start &76 +start &77 end &14 sat 32 @@ -17246,5 +17549,5 @@ on &7 ) -*605 (Wire +*614 (Wire uid 384,0 shape (OrthoPolyLine @@ -17260,5 +17563,5 @@ ] ) -start &77 +start &78 end &15 sat 32 @@ -17286,5 +17589,5 @@ on &8 ) -*606 (Wire +*615 (Wire uid 392,0 shape (OrthoPolyLine @@ -17300,5 +17603,5 @@ ] ) -start &78 +start &79 end &16 sat 32 @@ -17326,5 +17629,5 @@ on &9 ) -*607 (Wire +*616 (Wire uid 400,0 shape (OrthoPolyLine @@ -17339,5 +17642,5 @@ ] ) -start &79 +start &80 end &17 sat 32 @@ -17364,5 +17667,5 @@ on &10 ) -*608 (Wire +*617 (Wire uid 408,0 shape (OrthoPolyLine @@ -17377,5 +17680,5 @@ ] ) -start &80 +start &81 end &18 sat 32 @@ -17402,5 +17705,5 @@ on &11 ) -*609 (Wire +*618 (Wire uid 424,0 shape (OrthoPolyLine @@ -17415,5 +17718,5 @@ ] ) -start &81 +start &82 end &20 sat 32 @@ -17440,5 +17743,5 @@ on &12 ) -*610 (Wire +*619 (Wire uid 432,0 shape (OrthoPolyLine @@ -17454,5 +17757,5 @@ ) start &21 -end &82 +end &83 sat 32 eat 32 @@ -17478,5 +17781,5 @@ on &13 ) -*611 (Wire +*620 (Wire uid 1411,0 shape (OrthoPolyLine @@ -17515,7 +17818,7 @@ ) ) -on &71 -) -*612 (Wire +on &72 +) +*621 (Wire uid 1425,0 shape (OrthoPolyLine @@ -17530,5 +17833,5 @@ ] ) -start &73 +start &74 end &409 es 0 @@ -17554,7 +17857,7 @@ ) ) -on &72 -) -*613 (Wire +on &73 +) +*622 (Wire uid 1682,0 shape (OrthoPolyLine @@ -17571,5 +17874,5 @@ ) start &173 -end &31 +end &30 sat 32 eat 32 @@ -17593,46 +17896,7 @@ ) ) -on &122 -) -*614 (Wire -uid 1983,0 -shape (OrthoPolyLine -uid 1984,0 -va (VaSet -vasetType 3 -lineWidth 2 -) -xt "-40250,69000,-21750,70000" -pts [ -"-40250,69000" -"-36000,69000" -"-36000,70000" -"-21750,70000" -] -) -start &124 -end &29 -sat 32 -eat 32 -sty 1 -st 0 -sf 1 -tg (WTG -uid 1985,0 -ps "ConnStartEndStrategy" -stg "STSignalDisplayStrategy" -f (Text -uid 1986,0 -va (VaSet -) -xt "-29000,70000,-22200,71000" -st "trigger_id : (47:0)" -blo "-29000,70800" -tm "WireNameMgr" -) -) -on &130 -) -*615 (Wire +on &123 +) +*623 (Wire uid 2299,0 shape (OrthoPolyLine @@ -17672,5 +17936,5 @@ on &131 ) -*616 (Wire +*624 (Wire uid 2470,0 shape (OrthoPolyLine @@ -17686,5 +17950,5 @@ ) start &140 -end &88 +end &89 sat 32 eat 32 @@ -17708,5 +17972,5 @@ on &155 ) -*617 (Wire +*625 (Wire uid 2476,0 shape (OrthoPolyLine @@ -17722,5 +17986,5 @@ ) start &143 -end &87 +end &88 sat 32 eat 32 @@ -17744,5 +18008,5 @@ on &156 ) -*618 (Wire +*626 (Wire uid 2482,0 shape (OrthoPolyLine @@ -17759,5 +18023,5 @@ ) start &146 -end &83 +end &84 sat 32 eat 32 @@ -17782,5 +18046,5 @@ on &157 ) -*619 (Wire +*627 (Wire uid 2488,0 shape (OrthoPolyLine @@ -17797,5 +18061,5 @@ ) start &142 -end &84 +end &85 sat 32 eat 32 @@ -17820,5 +18084,5 @@ on &158 ) -*620 (Wire +*628 (Wire uid 2494,0 shape (OrthoPolyLine @@ -17835,5 +18099,5 @@ ) start &141 -end &89 +end &90 sat 32 eat 32 @@ -17858,5 +18122,5 @@ on &159 ) -*621 (Wire +*629 (Wire uid 2500,0 shape (OrthoPolyLine @@ -17872,5 +18136,5 @@ ) start &144 -end &90 +end &91 sat 32 eat 32 @@ -17894,5 +18158,5 @@ on &160 ) -*622 (Wire +*630 (Wire uid 2506,0 shape (OrthoPolyLine @@ -17908,5 +18172,5 @@ ) start &145 -end &91 +end &92 sat 32 eat 32 @@ -17930,5 +18194,5 @@ on &161 ) -*623 (Wire +*631 (Wire uid 2576,0 shape (OrthoPolyLine @@ -17943,5 +18207,5 @@ ] ) -start &32 +start &31 end &137 sat 32 @@ -17966,5 +18230,5 @@ on &162 ) -*624 (Wire +*632 (Wire uid 2582,0 shape (OrthoPolyLine @@ -17979,5 +18243,5 @@ ] ) -start &33 +start &32 end &138 sat 32 @@ -18002,5 +18266,5 @@ on &163 ) -*625 (Wire +*633 (Wire uid 2588,0 shape (OrthoPolyLine @@ -18015,5 +18279,5 @@ ] ) -start &51 +start &50 end &136 ss 0 @@ -18039,5 +18303,5 @@ on &164 ) -*626 (Wire +*634 (Wire uid 2594,0 shape (OrthoPolyLine @@ -18052,5 +18316,5 @@ ] ) -start &47 +start &46 end &135 sat 32 @@ -18075,5 +18339,5 @@ on &165 ) -*627 (Wire +*635 (Wire uid 2600,0 shape (OrthoPolyLine @@ -18088,5 +18352,5 @@ ] ) -start &34 +start &33 end &139 sat 32 @@ -18111,5 +18375,5 @@ on &166 ) -*628 (Wire +*636 (Wire uid 2642,0 shape (OrthoPolyLine @@ -18125,5 +18389,5 @@ ] ) -start &36 +start &35 end &148 sat 32 @@ -18149,5 +18413,5 @@ on &167 ) -*629 (Wire +*637 (Wire uid 2778,0 shape (OrthoPolyLine @@ -18162,5 +18426,5 @@ ] ) -start &37 +start &36 end &169 sat 32 @@ -18187,5 +18451,5 @@ on &168 ) -*630 (Wire +*638 (Wire uid 2786,0 shape (OrthoPolyLine @@ -18227,8 +18491,8 @@ on &191 ) -*631 (Wire +*639 (Wire uid 3888,0 optionalChildren [ -*632 (BdJunction +*640 (BdJunction uid 4230,0 ps "OnConnectorStrategy" @@ -18242,5 +18506,5 @@ ) ) -*633 (BdJunction +*641 (BdJunction uid 4244,0 ps "OnConnectorStrategy" @@ -18270,5 +18534,5 @@ ) start &365 -end &75 +end &76 sat 32 eat 32 @@ -18293,5 +18557,5 @@ on &187 ) -*634 (Wire +*642 (Wire uid 3984,0 shape (OrthoPolyLine @@ -18334,5 +18598,5 @@ on &185 ) -*635 (Wire +*643 (Wire uid 4042,0 shape (OrthoPolyLine @@ -18372,5 +18636,5 @@ on &190 ) -*636 (Wire +*644 (Wire uid 4226,0 shape (OrthoPolyLine @@ -18388,5 +18652,5 @@ ) start &189 -end &632 +end &640 sat 32 eat 32 @@ -18412,5 +18676,5 @@ on &187 ) -*637 (Wire +*645 (Wire uid 4240,0 shape (OrthoPolyLine @@ -18428,5 +18692,5 @@ ) start &335 -end &633 +end &641 sat 32 eat 32 @@ -18451,5 +18715,5 @@ on &187 ) -*638 (Wire +*646 (Wire uid 4272,0 shape (OrthoPolyLine @@ -18489,5 +18753,5 @@ on &192 ) -*639 (Wire +*647 (Wire uid 4401,0 shape (OrthoPolyLine @@ -18504,5 +18768,5 @@ ] ) -start &40 +start &39 end &212 sat 32 @@ -18527,5 +18791,5 @@ on &194 ) -*640 (Wire +*648 (Wire uid 4407,0 shape (OrthoPolyLine @@ -18542,5 +18806,5 @@ ] ) -start &43 +start &42 end &218 sat 32 @@ -18565,5 +18829,5 @@ on &195 ) -*641 (Wire +*649 (Wire uid 4419,0 shape (OrthoPolyLine @@ -18580,5 +18844,5 @@ ] ) -start &41 +start &40 end &213 sat 32 @@ -18603,5 +18867,5 @@ on &196 ) -*642 (Wire +*650 (Wire uid 4537,0 shape (OrthoPolyLine @@ -18617,5 +18881,5 @@ ] ) -start &39 +start &38 end &199 sat 32 @@ -18643,5 +18907,5 @@ on &197 ) -*643 (Wire +*651 (Wire uid 4545,0 shape (OrthoPolyLine @@ -18680,5 +18944,5 @@ on &198 ) -*644 (Wire +*652 (Wire uid 4671,0 shape (OrthoPolyLine @@ -18718,5 +18982,5 @@ on &201 ) -*645 (Wire +*653 (Wire uid 4679,0 shape (OrthoPolyLine @@ -18756,5 +19020,5 @@ on &202 ) -*646 (Wire +*654 (Wire uid 4687,0 shape (OrthoPolyLine @@ -18794,5 +19058,5 @@ on &203 ) -*647 (Wire +*655 (Wire uid 4695,0 shape (OrthoPolyLine @@ -18832,5 +19096,5 @@ on &204 ) -*648 (Wire +*656 (Wire uid 4743,0 shape (OrthoPolyLine @@ -18848,5 +19112,5 @@ ) start &219 -end &42 +end &41 sat 32 eat 32 @@ -18870,8 +19134,8 @@ on &209 ) -*649 (Wire +*657 (Wire uid 4757,0 optionalChildren [ -*650 (BdJunction +*658 (BdJunction uid 6076,0 ps "OnConnectorStrategy" @@ -18881,5 +19145,5 @@ vasetType 1 ) -xt "-25400,40600,-24600,41400" +xt "-26400,40600,-25600,41400" radius 400 ) @@ -18892,14 +19156,14 @@ lineColor "0,32896,0" ) -xt "-62000,41000,-25000,48000" +xt "-64000,41000,-26000,48000" pts [ "-58750,48000" -"-62000,48000" -"-62000,41000" -"-25000,41000" +"-64000,48000" +"-64000,41000" +"-26000,41000" ] ) start &211 -end *651 (BdJunction +end *659 (BdJunction uid 6080,0 ps "OnConnectorStrategy" @@ -18909,5 +19173,5 @@ vasetType 1 ) -xt "-25400,40600,-24600,41400" +xt "-26400,40600,-25600,41400" radius 400 ) @@ -18935,5 +19199,5 @@ on &188 ) -*652 (Wire +*660 (Wire uid 4948,0 shape (OrthoPolyLine @@ -18973,5 +19237,5 @@ on &230 ) -*653 (Wire +*661 (Wire uid 4962,0 shape (OrthoPolyLine @@ -19011,5 +19275,5 @@ on &232 ) -*654 (Wire +*662 (Wire uid 5090,0 shape (OrthoPolyLine @@ -19027,5 +19291,5 @@ ] ) -start &94 +start &95 end &236 sat 32 @@ -19050,5 +19314,5 @@ on &252 ) -*655 (Wire +*663 (Wire uid 5098,0 shape (OrthoPolyLine @@ -19084,5 +19348,5 @@ on &253 ) -*656 (Wire +*664 (Wire uid 5106,0 shape (OrthoPolyLine @@ -19100,5 +19364,5 @@ ) start &238 -end &95 +end &96 sat 32 eat 32 @@ -19121,5 +19385,5 @@ on &254 ) -*657 (Wire +*665 (Wire uid 5114,0 shape (OrthoPolyLine @@ -19138,5 +19402,5 @@ ) start &239 -end &96 +end &97 sat 32 eat 32 @@ -19160,5 +19424,5 @@ on &255 ) -*658 (Wire +*666 (Wire uid 5122,0 shape (OrthoPolyLine @@ -19175,5 +19439,5 @@ ] ) -start &98 +start &99 end &241 sat 32 @@ -19197,5 +19461,5 @@ on &256 ) -*659 (Wire +*667 (Wire uid 5130,0 shape (OrthoPolyLine @@ -19212,5 +19476,5 @@ ] ) -start &100 +start &101 end &243 sat 32 @@ -19234,8 +19498,8 @@ on &257 ) -*660 (Wire +*668 (Wire uid 5138,0 optionalChildren [ -*661 (BdJunction +*669 (BdJunction uid 5400,0 ps "OnConnectorStrategy" @@ -19264,5 +19528,5 @@ ) start &240 -end &35 +end &34 ss 0 es 0 @@ -19287,5 +19551,5 @@ on &171 ) -*662 (Wire +*670 (Wire uid 5146,0 shape (OrthoPolyLine @@ -19323,5 +19587,5 @@ on &258 ) -*663 (Wire +*671 (Wire uid 5168,0 shape (OrthoPolyLine @@ -19338,5 +19602,5 @@ ] ) -start &661 +start &669 end &147 sat 32 @@ -19361,5 +19625,5 @@ on &171 ) -*664 (Wire +*672 (Wire uid 5184,0 shape (OrthoPolyLine @@ -19377,5 +19641,5 @@ ) start &244 -end &46 +end &45 sat 32 eat 32 @@ -19398,5 +19662,5 @@ on &259 ) -*665 (Wire +*673 (Wire uid 5190,0 shape (OrthoPolyLine @@ -19414,5 +19678,5 @@ ) start &245 -end &45 +end &44 sat 32 eat 32 @@ -19435,5 +19699,5 @@ on &260 ) -*666 (Wire +*674 (Wire uid 5222,0 shape (OrthoPolyLine @@ -19449,5 +19713,5 @@ ] ) -start &92 +start &93 end &19 sat 32 @@ -19475,5 +19739,5 @@ on &261 ) -*667 (Wire +*675 (Wire uid 5404,0 shape (OrthoPolyLine @@ -19491,5 +19755,5 @@ ) start &280 -end &48 +end &47 sat 32 eat 32 @@ -19512,5 +19776,5 @@ on &264 ) -*668 (Wire +*676 (Wire uid 5474,0 shape (OrthoPolyLine @@ -19528,5 +19792,5 @@ ) start &283 -end &50 +end &49 sat 32 eat 32 @@ -19549,5 +19813,5 @@ on &262 ) -*669 (Wire +*677 (Wire uid 5480,0 shape (OrthoPolyLine @@ -19565,5 +19829,5 @@ ) start &282 -end &49 +end &48 sat 32 eat 32 @@ -19586,5 +19850,5 @@ on &263 ) -*670 (Wire +*678 (Wire uid 5582,0 shape (OrthoPolyLine @@ -19621,8 +19885,8 @@ on &187 ) -*671 (Wire +*679 (Wire uid 5602,0 optionalChildren [ -&651 +&659 ] shape (OrthoPolyLine @@ -19632,9 +19896,9 @@ lineColor "0,32896,0" ) -xt "-25000,41000,36250,51000" +xt "-26000,41000,36250,51000" pts [ "-21750,51000" -"-25000,51000" -"-25000,41000" +"-26000,51000" +"-26000,41000" "28000,41000" "28000,47000" @@ -19666,5 +19930,5 @@ on &188 ) -*672 (Wire +*680 (Wire uid 5626,0 shape (OrthoPolyLine @@ -19679,5 +19943,5 @@ ] ) -start &44 +start &43 end &269 sat 32 @@ -19702,5 +19966,5 @@ on &266 ) -*673 (Wire +*681 (Wire uid 5634,0 shape (OrthoPolyLine @@ -19716,5 +19980,5 @@ ] ) -start &38 +start &37 end &270 sat 32 @@ -19740,5 +20004,5 @@ on &265 ) -*674 (Wire +*682 (Wire uid 5646,0 shape (OrthoPolyLine @@ -19776,5 +20040,5 @@ on &185 ) -*675 (Wire +*683 (Wire uid 5745,0 shape (OrthoPolyLine @@ -19791,5 +20055,5 @@ ] ) -start &52 +start &51 end &281 sat 32 @@ -19814,5 +20078,5 @@ on &276 ) -*676 (Wire +*684 (Wire uid 5805,0 shape (OrthoPolyLine @@ -19848,5 +20112,5 @@ on &187 ) -*677 (Wire +*685 (Wire uid 5813,0 shape (OrthoPolyLine @@ -19886,5 +20150,5 @@ on &293 ) -*678 (Wire +*686 (Wire uid 5821,0 shape (OrthoPolyLine @@ -19924,5 +20188,5 @@ on &294 ) -*679 (Wire +*687 (Wire uid 5829,0 shape (OrthoPolyLine @@ -19962,5 +20226,5 @@ on &295 ) -*680 (Wire +*688 (Wire uid 5837,0 shape (OrthoPolyLine @@ -20002,5 +20266,5 @@ on &296 ) -*681 (Wire +*689 (Wire uid 5950,0 shape (OrthoPolyLine @@ -20017,6 +20281,6 @@ ] ) -start &99 -end &54 +start &100 +end &53 sat 32 eat 32 @@ -20040,5 +20304,5 @@ on &301 ) -*682 (Wire +*690 (Wire uid 5962,0 shape (OrthoPolyLine @@ -20055,6 +20319,6 @@ ] ) -start &97 -end &53 +start &98 +end &52 sat 32 eat 32 @@ -20078,5 +20342,5 @@ on &302 ) -*683 (Wire +*691 (Wire uid 6002,0 shape (OrthoPolyLine @@ -20094,5 +20358,5 @@ ) start &246 -end &55 +end &54 sat 32 eat 32 @@ -20116,5 +20380,5 @@ on &304 ) -*684 (Wire +*692 (Wire uid 6008,0 shape (OrthoPolyLine @@ -20132,5 +20396,5 @@ ) start &287 -end &57 +end &56 sat 32 eat 32 @@ -20154,5 +20418,5 @@ on &303 ) -*685 (Wire +*693 (Wire uid 6018,0 shape (OrthoPolyLine @@ -20167,5 +20431,5 @@ ] ) -start &56 +start &55 end &149 sat 32 @@ -20190,5 +20454,5 @@ on &305 ) -*686 (Wire +*694 (Wire uid 6064,0 shape (OrthoPolyLine @@ -20203,5 +20467,5 @@ ] ) -end &58 +end &57 sat 16 eat 32 @@ -20225,5 +20489,5 @@ on &258 ) -*687 (Wire +*695 (Wire uid 6072,0 shape (OrthoPolyLine @@ -20233,13 +20497,13 @@ lineColor "0,32896,0" ) -xt "-41250,23000,-25000,41000" +xt "-41250,23000,-26000,41000" pts [ "-41250,23000" -"-25000,23000" -"-25000,41000" +"-26000,23000" +"-26000,41000" ] ) start &366 -end &650 +end &658 sat 32 eat 32 @@ -20264,5 +20528,5 @@ on &188 ) -*688 (Wire +*696 (Wire uid 6160,0 shape (OrthoPolyLine @@ -20302,5 +20566,5 @@ on &306 ) -*689 (Wire +*697 (Wire uid 6276,0 shape (OrthoPolyLine @@ -20315,5 +20579,5 @@ ] ) -end &126 +end &127 sat 16 eat 32 @@ -20336,5 +20600,5 @@ on &185 ) -*690 (Wire +*698 (Wire uid 6362,0 shape (OrthoPolyLine @@ -20375,5 +20639,5 @@ on &308 ) -*691 (Wire +*699 (Wire uid 6452,0 shape (OrthoPolyLine @@ -20388,5 +20652,5 @@ ] ) -start &102 +start &103 sat 32 eat 16 @@ -20411,5 +20675,5 @@ on &310 ) -*692 (Wire +*700 (Wire uid 6540,0 shape (OrthoPolyLine @@ -20448,5 +20712,5 @@ on &329 ) -*693 (Wire +*701 (Wire uid 6548,0 shape (OrthoPolyLine @@ -20485,5 +20749,5 @@ on &310 ) -*694 (Wire +*702 (Wire uid 8416,0 shape (OrthoPolyLine @@ -20499,5 +20763,5 @@ ) start &150 -end &103 +end &104 sat 32 eat 32 @@ -20521,5 +20785,5 @@ on &341 ) -*695 (Wire +*703 (Wire uid 8732,0 shape (OrthoPolyLine @@ -20559,5 +20823,5 @@ on &360 ) -*696 (Wire +*704 (Wire uid 8738,0 shape (OrthoPolyLine @@ -20595,5 +20859,5 @@ on &361 ) -*697 (Wire +*705 (Wire uid 8752,0 shape (OrthoPolyLine @@ -20608,5 +20872,5 @@ ] ) -start &104 +start &105 sat 32 eat 16 @@ -20630,5 +20894,5 @@ on &361 ) -*698 (Wire +*706 (Wire uid 9006,0 shape (OrthoPolyLine @@ -20643,5 +20907,5 @@ ] ) -start &59 +start &58 end &363 sat 32 @@ -20668,5 +20932,5 @@ on &362 ) -*699 (Wire +*707 (Wire uid 9233,0 shape (OrthoPolyLine @@ -20681,5 +20945,5 @@ ] ) -start &105 +start &106 sat 32 eat 16 @@ -20703,5 +20967,5 @@ on &376 ) -*700 (Wire +*708 (Wire uid 9241,0 shape (OrthoPolyLine @@ -20716,5 +20980,5 @@ ] ) -start &106 +start &107 sat 32 eat 16 @@ -20738,5 +21002,5 @@ on &377 ) -*701 (Wire +*709 (Wire uid 9253,0 shape (OrthoPolyLine @@ -20772,5 +21036,5 @@ on &376 ) -*702 (Wire +*710 (Wire uid 9261,0 shape (OrthoPolyLine @@ -20806,5 +21070,5 @@ on &377 ) -*703 (Wire +*711 (Wire uid 9943,0 shape (OrthoPolyLine @@ -20819,5 +21083,5 @@ ] ) -start &107 +start &108 sat 32 eat 16 @@ -20841,5 +21105,5 @@ on &378 ) -*704 (Wire +*712 (Wire uid 9951,0 shape (OrthoPolyLine @@ -20854,5 +21118,5 @@ ] ) -start &108 +start &109 sat 32 eat 16 @@ -20876,5 +21140,5 @@ on &379 ) -*705 (Wire +*713 (Wire uid 10010,0 shape (OrthoPolyLine @@ -20914,5 +21178,5 @@ on &398 ) -*706 (Wire +*714 (Wire uid 10018,0 shape (OrthoPolyLine @@ -20950,5 +21214,5 @@ on &379 ) -*707 (Wire +*715 (Wire uid 10036,0 shape (OrthoPolyLine @@ -20984,5 +21248,5 @@ on &378 ) -*708 (Wire +*716 (Wire uid 10194,0 shape (OrthoPolyLine @@ -21000,5 +21264,5 @@ ) start &247 -end &109 +end &110 ss 0 es 0 @@ -21024,5 +21288,5 @@ on &399 ) -*709 (Wire +*717 (Wire uid 10202,0 shape (OrthoPolyLine @@ -21040,5 +21304,5 @@ ) start &248 -end &110 +end &111 sat 32 eat 32 @@ -21062,5 +21326,5 @@ on &400 ) -*710 (Wire +*718 (Wire uid 10266,0 shape (OrthoPolyLine @@ -21075,5 +21339,5 @@ ] ) -start &93 +start &94 sat 32 eat 16 @@ -21097,5 +21361,5 @@ on &498 ) -*711 (Wire +*719 (Wire uid 10298,0 shape (OrthoPolyLine @@ -21111,5 +21375,5 @@ ) start &226 -end &61 +end &60 sat 32 eat 32 @@ -21133,5 +21397,5 @@ on &402 ) -*712 (Wire +*720 (Wire uid 10304,0 shape (OrthoPolyLine @@ -21147,5 +21411,5 @@ ) start &224 -end &62 +end &61 sat 32 eat 32 @@ -21169,5 +21433,5 @@ on &403 ) -*713 (Wire +*721 (Wire uid 10310,0 shape (OrthoPolyLine @@ -21183,5 +21447,5 @@ ) start &225 -end &63 +end &62 sat 32 eat 32 @@ -21205,5 +21469,5 @@ on &404 ) -*714 (Wire +*722 (Wire uid 10316,0 shape (OrthoPolyLine @@ -21219,5 +21483,5 @@ ] ) -start &60 +start &59 end &222 sat 32 @@ -21243,5 +21507,5 @@ on &405 ) -*715 (Wire +*723 (Wire uid 10322,0 shape (OrthoPolyLine @@ -21281,5 +21545,5 @@ on &406 ) -*716 (Wire +*724 (Wire uid 10431,0 shape (OrthoPolyLine @@ -21318,5 +21582,5 @@ on &401 ) -*717 (Wire +*725 (Wire uid 10467,0 shape (OrthoPolyLine @@ -21332,5 +21596,5 @@ ) start &151 -end &64 +end &63 es 0 sat 32 @@ -21355,5 +21619,5 @@ on &431 ) -*718 (Wire +*726 (Wire uid 10629,0 shape (OrthoPolyLine @@ -21368,5 +21632,5 @@ ] ) -start &111 +start &112 sat 32 eat 16 @@ -21390,5 +21654,5 @@ on &432 ) -*719 (Wire +*727 (Wire uid 10637,0 shape (OrthoPolyLine @@ -21403,5 +21667,5 @@ ] ) -start &112 +start &113 sat 32 eat 16 @@ -21425,5 +21689,5 @@ on &433 ) -*720 (Wire +*728 (Wire uid 10685,0 shape (OrthoPolyLine @@ -21460,5 +21724,5 @@ on &433 ) -*721 (Wire +*729 (Wire uid 10691,0 shape (OrthoPolyLine @@ -21495,5 +21759,5 @@ on &432 ) -*722 (Wire +*730 (Wire uid 10699,0 shape (OrthoPolyLine @@ -21531,5 +21795,5 @@ on &187 ) -*723 (Wire +*731 (Wire uid 10707,0 shape (OrthoPolyLine @@ -21566,5 +21830,5 @@ on &452 ) -*724 (Wire +*732 (Wire uid 10723,0 shape (OrthoPolyLine @@ -21604,5 +21868,5 @@ on &434 ) -*725 (Wire +*733 (Wire uid 10737,0 shape (OrthoPolyLine @@ -21642,5 +21906,5 @@ on &436 ) -*726 (Wire +*734 (Wire uid 10751,0 shape (OrthoPolyLine @@ -21680,5 +21944,5 @@ on &438 ) -*727 (Wire +*735 (Wire uid 11405,0 shape (OrthoPolyLine @@ -21694,5 +21958,5 @@ ] ) -start &65 +start &64 sat 32 eat 16 @@ -21716,5 +21980,5 @@ on &452 ) -*728 (Wire +*736 (Wire uid 11858,0 shape (OrthoPolyLine @@ -21729,5 +21993,5 @@ ] ) -start &113 +start &114 sat 32 eat 16 @@ -21751,5 +22015,5 @@ on &453 ) -*729 (Wire +*737 (Wire uid 11952,0 shape (OrthoPolyLine @@ -21787,5 +22051,5 @@ on &453 ) -*730 (Wire +*738 (Wire uid 12306,0 shape (OrthoPolyLine @@ -21825,5 +22089,5 @@ on &472 ) -*731 (Wire +*739 (Wire uid 12643,0 shape (OrthoPolyLine @@ -21865,5 +22129,5 @@ on &483 ) -*732 (Wire +*740 (Wire uid 12649,0 shape (OrthoPolyLine @@ -21878,5 +22142,5 @@ ] ) -start &66 +start &65 end &477 sat 32 @@ -21901,5 +22165,5 @@ on &484 ) -*733 (Wire +*741 (Wire uid 12655,0 shape (OrthoPolyLine @@ -21915,5 +22179,5 @@ ] ) -start &67 +start &66 end &478 sat 32 @@ -21938,5 +22202,5 @@ on &485 ) -*734 (Wire +*742 (Wire uid 12687,0 shape (OrthoPolyLine @@ -21976,5 +22240,5 @@ on &188 ) -*735 (Wire +*743 (Wire uid 12707,0 shape (OrthoPolyLine @@ -22014,5 +22278,5 @@ on &486 ) -*736 (Wire +*744 (Wire uid 13143,0 shape (OrthoPolyLine @@ -22049,5 +22313,5 @@ on &188 ) -*737 (Wire +*745 (Wire uid 13159,0 shape (OrthoPolyLine @@ -22064,5 +22328,5 @@ ] ) -start &114 +start &115 end &490 sat 32 @@ -22087,5 +22351,5 @@ on &496 ) -*738 (Wire +*746 (Wire uid 13165,0 shape (OrthoPolyLine @@ -22103,5 +22367,5 @@ ] ) -start &115 +start &116 end &491 sat 32 @@ -22127,5 +22391,5 @@ on &497 ) -*739 (Wire +*747 (Wire uid 13210,0 shape (OrthoPolyLine @@ -22163,5 +22427,5 @@ on &499 ) -*740 (Wire +*748 (Wire uid 13216,0 shape (OrthoPolyLine @@ -22199,5 +22463,5 @@ on &498 ) -*741 (Wire +*749 (Wire uid 13224,0 shape (OrthoPolyLine @@ -22235,5 +22499,5 @@ on &401 ) -*742 (Wire +*750 (Wire uid 13695,0 shape (OrthoPolyLine @@ -22250,5 +22514,5 @@ ) start &523 -end &116 +end &117 sat 32 eat 32 @@ -22274,5 +22538,5 @@ on &524 ) -*743 (Wire +*751 (Wire uid 13921,0 shape (OrthoPolyLine @@ -22288,5 +22552,5 @@ ] ) -end &117 +end &118 sat 16 eat 32 @@ -22309,7 +22573,7 @@ ) ) -on &71 -) -*744 (Wire +on &72 +) +*752 (Wire uid 13929,0 shape (OrthoPolyLine @@ -22325,5 +22589,5 @@ ] ) -end &118 +end &119 sat 16 eat 32 @@ -22346,7 +22610,7 @@ ) ) -on &122 -) -*745 (Wire +on &123 +) +*753 (Wire uid 14048,0 shape (OrthoPolyLine @@ -22385,5 +22649,5 @@ on &526 ) -*746 (Wire +*754 (Wire uid 14171,0 shape (OrthoPolyLine @@ -22423,5 +22687,5 @@ on &528 ) -*747 (Wire +*755 (Wire uid 14427,0 shape (OrthoPolyLine @@ -22458,5 +22722,5 @@ on &187 ) -*748 (Wire +*756 (Wire uid 14479,0 shape (OrthoPolyLine @@ -22496,5 +22760,5 @@ on &538 ) -*749 (Wire +*757 (Wire uid 14493,0 shape (OrthoPolyLine @@ -22534,5 +22798,5 @@ on &540 ) -*750 (Wire +*758 (Wire uid 14622,0 shape (OrthoPolyLine @@ -22574,5 +22838,5 @@ on &542 ) -*751 (Wire +*759 (Wire uid 15071,0 shape (OrthoPolyLine @@ -22587,5 +22851,5 @@ ] ) -start &101 +start &102 end &548 sat 32 @@ -22610,5 +22874,5 @@ on &595 ) -*752 (Wire +*760 (Wire uid 15081,0 shape (OrthoPolyLine @@ -22648,5 +22912,5 @@ on &596 ) -*753 (Wire +*761 (Wire uid 15122,0 shape (OrthoPolyLine @@ -22686,5 +22950,5 @@ on &597 ) -*754 (Wire +*762 (Wire uid 15130,0 shape (OrthoPolyLine @@ -22724,5 +22988,5 @@ on &540 ) -*755 (Wire +*763 (Wire uid 15138,0 shape (OrthoPolyLine @@ -22762,5 +23026,5 @@ on &538 ) -*756 (Wire +*764 (Wire uid 15379,0 shape (OrthoPolyLine @@ -22797,8 +23061,8 @@ on &188 ) -*757 (Wire +*765 (Wire uid 15494,0 optionalChildren [ -*758 (BdJunction +*766 (BdJunction uid 15502,0 ps "OnConnectorStrategy" @@ -22825,5 +23089,5 @@ ) start &475 -end &30 +end &29 sat 32 eat 32 @@ -22847,5 +23111,5 @@ on &598 ) -*759 (Wire +*767 (Wire uid 15498,0 shape (OrthoPolyLine @@ -22861,6 +23125,6 @@ ] ) -start &125 -end &758 +start &126 +end &766 sat 32 eat 32 @@ -22885,4 +23149,43 @@ on &598 ) +*768 (Wire +uid 15750,0 +shape (OrthoPolyLine +uid 15751,0 +va (VaSet +vasetType 3 +lineWidth 2 +) +xt "-40250,69000,-21750,70000" +pts [ +"-40250,69000" +"-28000,69000" +"-28000,70000" +"-21750,70000" +] +) +start &125 +end &67 +sat 32 +eat 32 +sty 1 +st 0 +sf 1 +tg (WTG +uid 15752,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 15753,0 +va (VaSet +) +xt "-38250,68000,-31450,69000" +st "trigger_id : (31:0)" +blo "-38250,68800" +tm "WireNameMgr" +) +) +on &607 +) ] bg "65535,65535,65535" @@ -22897,9 +23200,9 @@ color "26368,26368,26368" ) -packageList *760 (PackageList +packageList *769 (PackageList uid 41,0 stg "VerticalLayoutStrategy" textVec [ -*761 (Text +*770 (Text uid 42,0 va (VaSet @@ -22910,9 +23213,9 @@ blo "-163000,-15200" ) -*762 (MLText +*771 (MLText uid 43,0 va (VaSet ) -xt "-163000,-15000,-148600,-3000" +xt "-163000,-15000,-148600,-2000" st "library ieee; use ieee.std_logic_1164.all; @@ -22926,5 +23229,6 @@ --use UNISIM.VComponents.all; USE IEEE.NUMERIC_STD.all; -USE IEEE.std_logic_signed.all;" +USE IEEE.std_logic_signed.all; +USE UNISIM.VComponents.all;" tm "PackageList" ) @@ -22935,5 +23239,5 @@ stg "VerticalLayoutStrategy" textVec [ -*763 (Text +*772 (Text uid 45,0 va (VaSet @@ -22945,5 +23249,5 @@ blo "20000,800" ) -*764 (Text +*773 (Text uid 46,0 va (VaSet @@ -22955,5 +23259,5 @@ blo "20000,1800" ) -*765 (MLText +*774 (MLText uid 47,0 va (VaSet @@ -22965,5 +23269,5 @@ tm "BdCompilerDirectivesTextMgr" ) -*766 (Text +*775 (Text uid 48,0 va (VaSet @@ -22975,5 +23279,5 @@ blo "20000,4800" ) -*767 (MLText +*776 (MLText uid 49,0 va (VaSet @@ -22983,5 +23287,5 @@ tm "BdCompilerDirectivesTextMgr" ) -*768 (Text +*777 (Text uid 50,0 va (VaSet @@ -22993,5 +23297,5 @@ blo "20000,5800" ) -*769 (MLText +*778 (MLText uid 51,0 va (VaSet @@ -23005,5 +23309,5 @@ ) windowSize "0,0,1281,1024" -viewArea "-65700,47500,1143,102625" +viewArea "-70475,46416,-3930,101296" cachedDiagramExtent "-174000,-25425,428157,346294" pageSetupInfo (PageSetupInfo @@ -23031,5 +23335,5 @@ hasePageBreakOrigin 1 pageBreakOrigin "-73000,0" -lastUid 15505,0 +lastUid 15755,0 defaultCommentText (CommentText shape (Rectangle @@ -23093,5 +23397,5 @@ stg "VerticalLayoutStrategy" textVec [ -*770 (Text +*779 (Text va (VaSet font "Arial,8,1" @@ -23102,5 +23406,5 @@ tm "BdLibraryNameMgr" ) -*771 (Text +*780 (Text va (VaSet font "Arial,8,1" @@ -23111,5 +23415,5 @@ tm "BlkNameMgr" ) -*772 (Text +*781 (Text va (VaSet font "Arial,8,1" @@ -23157,202 +23461,4 @@ ) xt "0,0,8000,10000" -) -ttg (MlTextGroup -ps "CenterOffsetStrategy" -stg "VerticalLayoutStrategy" -textVec [ -*773 (Text -va (VaSet -font "Arial,8,1" -) -xt "550,3500,3450,4500" -st "Library" -blo "550,4300" -) -*774 (Text -va (VaSet -font "Arial,8,1" -) -xt "550,4500,7450,5500" -st "MWComponent" -blo "550,5300" -) -*775 (Text -va (VaSet -font "Arial,8,1" -) -xt "550,5500,2350,6500" -st "U_0" -blo "550,6300" -tm "InstanceNameMgr" -) -] -) -ga (GenericAssociation -ps "EdgeToEdgeStrategy" -matrix (Matrix -text (MLText -va (VaSet -font "Courier New,8,0" -) -xt "-6450,1500,-6450,1500" -) -header "" -) -elements [ -] -) -portVis (PortSigDisplay -) -prms (Property -pclass "params" -pname "params" -ptn "String" -) -visOptions (mwParamsVisibilityOptions -) -) -defaultSaComponent (SaComponent -shape (Rectangle -va (VaSet -vasetType 1 -fg "0,65535,0" -lineColor "0,32896,0" -lineWidth 2 -) -xt "0,0,8000,10000" -) -ttg (MlTextGroup -ps "CenterOffsetStrategy" -stg "VerticalLayoutStrategy" -textVec [ -*776 (Text -va (VaSet -font "Arial,8,1" -) -xt "900,3500,3800,4500" -st "Library" -blo "900,4300" -tm "BdLibraryNameMgr" -) -*777 (Text -va (VaSet -font "Arial,8,1" -) -xt "900,4500,7100,5500" -st "SaComponent" -blo "900,5300" -tm "CptNameMgr" -) -*778 (Text -va (VaSet -font "Arial,8,1" -) -xt "900,5500,2700,6500" -st "U_0" -blo "900,6300" -tm "InstanceNameMgr" -) -] -) -ga (GenericAssociation -ps "EdgeToEdgeStrategy" -matrix (Matrix -text (MLText -va (VaSet -font "Courier New,8,0" -) -xt "-6100,1500,-6100,1500" -) -header "" -) -elements [ -] -) -viewicon (ZoomableIcon -sl 0 -va (VaSet -vasetType 1 -fg "49152,49152,49152" -) -xt "0,0,1500,1500" -iconName "UnknownFile.png" -iconMaskName "UnknownFile.msk" -) -viewiconposition 0 -portVis (PortSigDisplay -) -archFileType "UNKNOWN" -) -defaultVhdlComponent (VhdlComponent -shape (Rectangle -va (VaSet -vasetType 1 -fg "0,65535,0" -lineColor "0,32896,0" -lineWidth 2 -) -xt "0,0,8000,10000" -) -ttg (MlTextGroup -ps "CenterOffsetStrategy" -stg "VerticalLayoutStrategy" -textVec [ -*779 (Text -va (VaSet -font "Arial,8,1" -) -xt "500,3500,3400,4500" -st "Library" -blo "500,4300" -) -*780 (Text -va (VaSet -font "Arial,8,1" -) -xt "500,4500,7500,5500" -st "VhdlComponent" -blo "500,5300" -) -*781 (Text -va (VaSet -font "Arial,8,1" -) -xt "500,5500,2300,6500" -st "U_0" -blo "500,6300" -tm "InstanceNameMgr" -) -] -) -ga (GenericAssociation -ps "EdgeToEdgeStrategy" -matrix (Matrix -text (MLText -va (VaSet -font "Courier New,8,0" -) -xt "-6500,1500,-6500,1500" -) -header "" -) -elements [ -] -) -portVis (PortSigDisplay -) -entityPath "" -archName "" -archPath "" -) -defaultVerilogComponent (VerilogComponent -shape (Rectangle -va (VaSet -vasetType 1 -fg "0,65535,0" -lineColor "0,32896,0" -lineWidth 2 -) -xt "-450,0,8450,10000" ) ttg (MlTextGroup @@ -23364,7 +23470,7 @@ font "Arial,8,1" ) -xt "50,3500,2950,4500" +xt "550,3500,3450,4500" st "Library" -blo "50,4300" +blo "550,4300" ) *783 (Text @@ -23372,7 +23478,7 @@ font "Arial,8,1" ) -xt "50,4500,7950,5500" -st "VerilogComponent" -blo "50,5300" +xt "550,4500,7450,5500" +st "MWComponent" +blo "550,5300" ) *784 (Text @@ -23380,7 +23486,7 @@ font "Arial,8,1" ) -xt "50,5500,1850,6500" +xt "550,5500,2350,6500" st "U_0" -blo "50,6300" +blo "550,6300" tm "InstanceNameMgr" ) @@ -23394,5 +23500,5 @@ font "Courier New,8,0" ) -xt "-6950,1500,-6950,1500" +xt "-6450,1500,-6450,1500" ) header "" @@ -23401,12 +23507,20 @@ ] ) -entityPath "" -) -defaultHdlText (HdlText +portVis (PortSigDisplay +) +prms (Property +pclass "params" +pname "params" +ptn "String" +) +visOptions (mwParamsVisibilityOptions +) +) +defaultSaComponent (SaComponent shape (Rectangle va (VaSet vasetType 1 -fg "65535,65535,37120" -lineColor "0,0,32768" +fg "0,65535,0" +lineColor "0,32896,0" lineWidth 2 ) @@ -23421,4 +23535,194 @@ font "Arial,8,1" ) +xt "900,3500,3800,4500" +st "Library" +blo "900,4300" +tm "BdLibraryNameMgr" +) +*786 (Text +va (VaSet +font "Arial,8,1" +) +xt "900,4500,7100,5500" +st "SaComponent" +blo "900,5300" +tm "CptNameMgr" +) +*787 (Text +va (VaSet +font "Arial,8,1" +) +xt "900,5500,2700,6500" +st "U_0" +blo "900,6300" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +ps "EdgeToEdgeStrategy" +matrix (Matrix +text (MLText +va (VaSet +font "Courier New,8,0" +) +xt "-6100,1500,-6100,1500" +) +header "" +) +elements [ +] +) +viewicon (ZoomableIcon +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "0,0,1500,1500" +iconName "UnknownFile.png" +iconMaskName "UnknownFile.msk" +) +viewiconposition 0 +portVis (PortSigDisplay +) +archFileType "UNKNOWN" +) +defaultVhdlComponent (VhdlComponent +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "0,0,8000,10000" +) +ttg (MlTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*788 (Text +va (VaSet +font "Arial,8,1" +) +xt "500,3500,3400,4500" +st "Library" +blo "500,4300" +) +*789 (Text +va (VaSet +font "Arial,8,1" +) +xt "500,4500,7500,5500" +st "VhdlComponent" +blo "500,5300" +) +*790 (Text +va (VaSet +font "Arial,8,1" +) +xt "500,5500,2300,6500" +st "U_0" +blo "500,6300" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +ps "EdgeToEdgeStrategy" +matrix (Matrix +text (MLText +va (VaSet +font "Courier New,8,0" +) +xt "-6500,1500,-6500,1500" +) +header "" +) +elements [ +] +) +portVis (PortSigDisplay +) +entityPath "" +archName "" +archPath "" +) +defaultVerilogComponent (VerilogComponent +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "-450,0,8450,10000" +) +ttg (MlTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*791 (Text +va (VaSet +font "Arial,8,1" +) +xt "50,3500,2950,4500" +st "Library" +blo "50,4300" +) +*792 (Text +va (VaSet +font "Arial,8,1" +) +xt "50,4500,7950,5500" +st "VerilogComponent" +blo "50,5300" +) +*793 (Text +va (VaSet +font "Arial,8,1" +) +xt "50,5500,1850,6500" +st "U_0" +blo "50,6300" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +ps "EdgeToEdgeStrategy" +matrix (Matrix +text (MLText +va (VaSet +font "Courier New,8,0" +) +xt "-6950,1500,-6950,1500" +) +header "" +) +elements [ +] +) +entityPath "" +) +defaultHdlText (HdlText +shape (Rectangle +va (VaSet +vasetType 1 +fg "65535,65535,37120" +lineColor "0,0,32768" +lineWidth 2 +) +xt "0,0,8000,10000" +) +ttg (MlTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*794 (Text +va (VaSet +font "Arial,8,1" +) xt "3150,4000,4850,5000" st "eb1" @@ -23426,5 +23730,5 @@ tm "HdlTextNameMgr" ) -*786 (Text +*795 (Text va (VaSet font "Arial,8,1" @@ -23829,5 +24133,5 @@ stg "VerticalLayoutStrategy" textVec [ -*787 (Text +*796 (Text va (VaSet font "Arial,8,1" @@ -23837,5 +24141,5 @@ blo "14100,20800" ) -*788 (MLText +*797 (MLText va (VaSet ) @@ -23889,5 +24193,5 @@ stg "VerticalLayoutStrategy" textVec [ -*789 (Text +*798 (Text va (VaSet font "Arial,8,1" @@ -23897,5 +24201,5 @@ blo "14100,20800" ) -*790 (MLText +*799 (MLText va (VaSet ) @@ -24037,44 +24341,44 @@ commonDM (CommonDM ldm (LogicalDM -suid 301,0 +suid 302,0 usingSuid 1 -emptyRow *791 (LEmptyRow +emptyRow *800 (LEmptyRow ) uid 54,0 optionalChildren [ -*792 (RefLabelRowHdr -) -*793 (TitleRowHdr -) -*794 (FilterRowHdr -) -*795 (RefLabelColHdr +*801 (RefLabelRowHdr +) +*802 (TitleRowHdr +) +*803 (FilterRowHdr +) +*804 (RefLabelColHdr tm "RefLabelColHdrMgr" ) -*796 (RowExpandColHdr +*805 (RowExpandColHdr tm "RowExpandColHdrMgr" ) -*797 (GroupColHdr +*806 (GroupColHdr tm "GroupColHdrMgr" ) -*798 (NameColHdr +*807 (NameColHdr tm "BlockDiagramNameColHdrMgr" ) -*799 (ModeColHdr +*808 (ModeColHdr tm "BlockDiagramModeColHdrMgr" ) -*800 (TypeColHdr +*809 (TypeColHdr tm "BlockDiagramTypeColHdrMgr" ) -*801 (BoundsColHdr +*810 (BoundsColHdr tm "BlockDiagramBoundsColHdrMgr" ) -*802 (InitColHdr +*811 (InitColHdr tm "BlockDiagramInitColHdrMgr" ) -*803 (EolColHdr +*812 (EolColHdr tm "BlockDiagramEolColHdrMgr" ) -*804 (LeafLogPort +*813 (LeafLogPort port (LogicalPort m 4 @@ -24090,5 +24394,5 @@ uid 516,0 ) -*805 (LeafLogPort +*814 (LeafLogPort port (LogicalPort m 4 @@ -24103,5 +24407,5 @@ uid 518,0 ) -*806 (LeafLogPort +*815 (LeafLogPort port (LogicalPort m 4 @@ -24116,5 +24420,5 @@ uid 520,0 ) -*807 (LeafLogPort +*816 (LeafLogPort port (LogicalPort m 4 @@ -24129,5 +24433,5 @@ uid 530,0 ) -*808 (LeafLogPort +*817 (LeafLogPort port (LogicalPort m 4 @@ -24142,5 +24446,5 @@ uid 532,0 ) -*809 (LeafLogPort +*818 (LeafLogPort port (LogicalPort m 1 @@ -24155,5 +24459,5 @@ uid 534,0 ) -*810 (LeafLogPort +*819 (LeafLogPort port (LogicalPort m 1 @@ -24168,5 +24472,5 @@ uid 536,0 ) -*811 (LeafLogPort +*820 (LeafLogPort port (LogicalPort m 2 @@ -24181,5 +24485,5 @@ uid 538,0 ) -*812 (LeafLogPort +*821 (LeafLogPort port (LogicalPort m 1 @@ -24194,5 +24498,5 @@ uid 540,0 ) -*813 (LeafLogPort +*822 (LeafLogPort port (LogicalPort m 1 @@ -24207,5 +24511,5 @@ uid 542,0 ) -*814 (LeafLogPort +*823 (LeafLogPort port (LogicalPort m 1 @@ -24220,5 +24524,5 @@ uid 546,0 ) -*815 (LeafLogPort +*824 (LeafLogPort port (LogicalPort decl (Decl @@ -24231,5 +24535,5 @@ uid 548,0 ) -*816 (LeafLogPort +*825 (LeafLogPort port (LogicalPort decl (Decl @@ -24243,5 +24547,5 @@ uid 1455,0 ) -*817 (LeafLogPort +*826 (LeafLogPort port (LogicalPort decl (Decl @@ -24256,5 +24560,5 @@ uid 1457,0 ) -*818 (LeafLogPort +*827 (LeafLogPort port (LogicalPort decl (Decl @@ -24268,21 +24572,5 @@ uid 1694,0 ) -*819 (LeafLogPort -port (LogicalPort -lang 2 -m 4 -decl (Decl -n "trigger_id" -t "std_logic_vector" -b "(47 downto 0)" -preAdd 0 -posAdd 0 -o 119 -suid 34,0 -) -) -uid 1993,0 -) -*820 (LeafLogPort +*828 (LeafLogPort port (LogicalPort m 4 @@ -24299,5 +24587,5 @@ uid 2305,0 ) -*821 (LeafLogPort +*829 (LeafLogPort port (LogicalPort lang 2 @@ -24312,5 +24600,5 @@ uid 2510,0 ) -*822 (LeafLogPort +*830 (LeafLogPort port (LogicalPort lang 2 @@ -24326,5 +24614,5 @@ uid 2512,0 ) -*823 (LeafLogPort +*831 (LeafLogPort port (LogicalPort lang 2 @@ -24341,5 +24629,5 @@ uid 2514,0 ) -*824 (LeafLogPort +*832 (LeafLogPort port (LogicalPort lang 2 @@ -24357,5 +24645,5 @@ uid 2516,0 ) -*825 (LeafLogPort +*833 (LeafLogPort port (LogicalPort lang 2 @@ -24372,5 +24660,5 @@ uid 2518,0 ) -*826 (LeafLogPort +*834 (LeafLogPort port (LogicalPort lang 2 @@ -24386,5 +24674,5 @@ uid 2520,0 ) -*827 (LeafLogPort +*835 (LeafLogPort port (LogicalPort lang 2 @@ -24400,5 +24688,5 @@ uid 2522,0 ) -*828 (LeafLogPort +*836 (LeafLogPort port (LogicalPort m 4 @@ -24412,5 +24700,5 @@ uid 2604,0 ) -*829 (LeafLogPort +*837 (LeafLogPort port (LogicalPort m 4 @@ -24425,5 +24713,5 @@ uid 2606,0 ) -*830 (LeafLogPort +*838 (LeafLogPort port (LogicalPort m 4 @@ -24438,5 +24726,5 @@ uid 2608,0 ) -*831 (LeafLogPort +*839 (LeafLogPort port (LogicalPort m 4 @@ -24450,5 +24738,5 @@ uid 2610,0 ) -*832 (LeafLogPort +*840 (LeafLogPort port (LogicalPort m 4 @@ -24462,5 +24750,5 @@ uid 2612,0 ) -*833 (LeafLogPort +*841 (LeafLogPort port (LogicalPort m 4 @@ -24475,5 +24763,5 @@ uid 2646,0 ) -*834 (LeafLogPort +*842 (LeafLogPort port (LogicalPort m 1 @@ -24488,5 +24776,5 @@ uid 2812,0 ) -*835 (LeafLogPort +*843 (LeafLogPort port (LogicalPort m 4 @@ -24500,5 +24788,5 @@ uid 2962,0 ) -*836 (LeafLogPort +*844 (LeafLogPort port (LogicalPort m 1 @@ -24512,5 +24800,5 @@ uid 3902,0 ) -*837 (LeafLogPort +*845 (LeafLogPort port (LogicalPort m 1 @@ -24524,5 +24812,5 @@ uid 4070,0 ) -*838 (LeafLogPort +*846 (LeafLogPort port (LogicalPort m 4 @@ -24536,5 +24824,5 @@ uid 4212,0 ) -*839 (LeafLogPort +*847 (LeafLogPort port (LogicalPort decl (Decl @@ -24547,5 +24835,5 @@ uid 4234,0 ) -*840 (LeafLogPort +*848 (LeafLogPort port (LogicalPort decl (Decl @@ -24559,5 +24847,5 @@ uid 4262,0 ) -*841 (LeafLogPort +*849 (LeafLogPort port (LogicalPort decl (Decl @@ -24570,5 +24858,5 @@ uid 4276,0 ) -*842 (LeafLogPort +*850 (LeafLogPort port (LogicalPort m 4 @@ -24583,5 +24871,5 @@ uid 4563,0 ) -*843 (LeafLogPort +*851 (LeafLogPort port (LogicalPort m 4 @@ -24595,5 +24883,5 @@ uid 4565,0 ) -*844 (LeafLogPort +*852 (LeafLogPort port (LogicalPort m 4 @@ -24608,5 +24896,5 @@ uid 4569,0 ) -*845 (LeafLogPort +*853 (LeafLogPort port (LogicalPort m 1 @@ -24622,5 +24910,5 @@ uid 4585,0 ) -*846 (LeafLogPort +*854 (LeafLogPort port (LogicalPort m 1 @@ -24635,5 +24923,5 @@ uid 4587,0 ) -*847 (LeafLogPort +*855 (LeafLogPort port (LogicalPort decl (Decl @@ -24646,5 +24934,5 @@ uid 4733,0 ) -*848 (LeafLogPort +*856 (LeafLogPort port (LogicalPort decl (Decl @@ -24657,5 +24945,5 @@ uid 4735,0 ) -*849 (LeafLogPort +*857 (LeafLogPort port (LogicalPort decl (Decl @@ -24668,5 +24956,5 @@ uid 4737,0 ) -*850 (LeafLogPort +*858 (LeafLogPort port (LogicalPort decl (Decl @@ -24679,5 +24967,5 @@ uid 4739,0 ) -*851 (LeafLogPort +*859 (LeafLogPort port (LogicalPort m 4 @@ -24691,5 +24979,5 @@ uid 4749,0 ) -*852 (LeafLogPort +*860 (LeafLogPort port (LogicalPort m 1 @@ -24704,5 +24992,5 @@ uid 4974,0 ) -*853 (LeafLogPort +*861 (LeafLogPort port (LogicalPort m 1 @@ -24717,5 +25005,5 @@ uid 4976,0 ) -*854 (LeafLogPort +*862 (LeafLogPort port (LogicalPort m 4 @@ -24730,5 +25018,5 @@ uid 5198,0 ) -*855 (LeafLogPort +*863 (LeafLogPort port (LogicalPort m 4 @@ -24742,5 +25030,5 @@ uid 5200,0 ) -*856 (LeafLogPort +*864 (LeafLogPort port (LogicalPort m 4 @@ -24754,5 +25042,5 @@ uid 5202,0 ) -*857 (LeafLogPort +*865 (LeafLogPort port (LogicalPort m 4 @@ -24767,5 +25055,5 @@ uid 5204,0 ) -*858 (LeafLogPort +*866 (LeafLogPort port (LogicalPort m 4 @@ -24779,5 +25067,5 @@ uid 5206,0 ) -*859 (LeafLogPort +*867 (LeafLogPort port (LogicalPort m 4 @@ -24791,5 +25079,5 @@ uid 5208,0 ) -*860 (LeafLogPort +*868 (LeafLogPort port (LogicalPort m 4 @@ -24803,5 +25091,5 @@ uid 5210,0 ) -*861 (LeafLogPort +*869 (LeafLogPort port (LogicalPort m 4 @@ -24815,5 +25103,5 @@ uid 5212,0 ) -*862 (LeafLogPort +*870 (LeafLogPort port (LogicalPort m 4 @@ -24827,5 +25115,5 @@ uid 5214,0 ) -*863 (LeafLogPort +*871 (LeafLogPort port (LogicalPort m 1 @@ -24842,5 +25130,5 @@ uid 5226,0 ) -*864 (LeafLogPort +*872 (LeafLogPort port (LogicalPort m 4 @@ -24854,5 +25142,5 @@ uid 5502,0 ) -*865 (LeafLogPort +*873 (LeafLogPort port (LogicalPort m 4 @@ -24866,5 +25154,5 @@ uid 5504,0 ) -*866 (LeafLogPort +*874 (LeafLogPort port (LogicalPort m 4 @@ -24878,5 +25166,5 @@ uid 5600,0 ) -*867 (LeafLogPort +*875 (LeafLogPort port (LogicalPort lang 10 @@ -24892,5 +25180,5 @@ uid 5642,0 ) -*868 (LeafLogPort +*876 (LeafLogPort port (LogicalPort m 4 @@ -24904,5 +25192,5 @@ uid 5644,0 ) -*869 (LeafLogPort +*877 (LeafLogPort port (LogicalPort m 4 @@ -24917,5 +25205,5 @@ uid 5751,0 ) -*870 (LeafLogPort +*878 (LeafLogPort port (LogicalPort m 1 @@ -24929,5 +25217,5 @@ uid 5867,0 ) -*871 (LeafLogPort +*879 (LeafLogPort port (LogicalPort m 2 @@ -24943,5 +25231,5 @@ uid 5869,0 ) -*872 (LeafLogPort +*880 (LeafLogPort port (LogicalPort m 1 @@ -24955,5 +25243,5 @@ uid 5871,0 ) -*873 (LeafLogPort +*881 (LeafLogPort port (LogicalPort m 1 @@ -24968,5 +25256,5 @@ uid 5873,0 ) -*874 (LeafLogPort +*882 (LeafLogPort port (LogicalPort m 4 @@ -24981,5 +25269,5 @@ uid 5966,0 ) -*875 (LeafLogPort +*883 (LeafLogPort port (LogicalPort m 4 @@ -24993,5 +25281,5 @@ uid 5968,0 ) -*876 (LeafLogPort +*884 (LeafLogPort port (LogicalPort m 4 @@ -25006,5 +25294,5 @@ uid 6022,0 ) -*877 (LeafLogPort +*885 (LeafLogPort port (LogicalPort m 4 @@ -25019,5 +25307,5 @@ uid 6024,0 ) -*878 (LeafLogPort +*886 (LeafLogPort port (LogicalPort m 4 @@ -25031,5 +25319,5 @@ uid 6026,0 ) -*879 (LeafLogPort +*887 (LeafLogPort port (LogicalPort m 1 @@ -25044,5 +25332,5 @@ uid 6172,0 ) -*880 (LeafLogPort +*888 (LeafLogPort port (LogicalPort m 1 @@ -25059,5 +25347,5 @@ uid 6374,0 ) -*881 (LeafLogPort +*889 (LeafLogPort port (LogicalPort m 4 @@ -25072,5 +25360,5 @@ uid 6464,0 ) -*882 (LeafLogPort +*890 (LeafLogPort port (LogicalPort m 4 @@ -25085,5 +25373,5 @@ uid 6554,0 ) -*883 (LeafLogPort +*891 (LeafLogPort port (LogicalPort lang 2 @@ -25098,5 +25386,5 @@ uid 8420,0 ) -*884 (LeafLogPort +*892 (LeafLogPort port (LogicalPort m 4 @@ -25110,5 +25398,5 @@ uid 8758,0 ) -*885 (LeafLogPort +*893 (LeafLogPort port (LogicalPort m 4 @@ -25122,5 +25410,5 @@ uid 8760,0 ) -*886 (LeafLogPort +*894 (LeafLogPort port (LogicalPort m 1 @@ -25135,5 +25423,5 @@ uid 9018,0 ) -*887 (LeafLogPort +*895 (LeafLogPort port (LogicalPort m 4 @@ -25150,5 +25438,5 @@ uid 9247,0 ) -*888 (LeafLogPort +*896 (LeafLogPort port (LogicalPort m 4 @@ -25166,5 +25454,5 @@ uid 9249,0 ) -*889 (LeafLogPort +*897 (LeafLogPort port (LogicalPort m 4 @@ -25181,5 +25469,5 @@ uid 10024,0 ) -*890 (LeafLogPort +*898 (LeafLogPort port (LogicalPort m 4 @@ -25194,5 +25482,5 @@ uid 10026,0 ) -*891 (LeafLogPort +*899 (LeafLogPort port (LogicalPort m 4 @@ -25207,5 +25495,5 @@ uid 10028,0 ) -*892 (LeafLogPort +*900 (LeafLogPort port (LogicalPort m 4 @@ -25223,5 +25511,5 @@ uid 10208,0 ) -*893 (LeafLogPort +*901 (LeafLogPort port (LogicalPort m 4 @@ -25239,5 +25527,5 @@ uid 10210,0 ) -*894 (LeafLogPort +*902 (LeafLogPort port (LogicalPort m 4 @@ -25251,5 +25539,5 @@ uid 10294,0 ) -*895 (LeafLogPort +*903 (LeafLogPort port (LogicalPort m 4 @@ -25263,5 +25551,5 @@ uid 10334,0 ) -*896 (LeafLogPort +*904 (LeafLogPort port (LogicalPort m 4 @@ -25276,5 +25564,5 @@ uid 10336,0 ) -*897 (LeafLogPort +*905 (LeafLogPort port (LogicalPort m 4 @@ -25289,5 +25577,5 @@ uid 10338,0 ) -*898 (LeafLogPort +*906 (LeafLogPort port (LogicalPort m 4 @@ -25303,5 +25591,5 @@ uid 10340,0 ) -*899 (LeafLogPort +*907 (LeafLogPort port (LogicalPort m 1 @@ -25316,5 +25604,5 @@ uid 10342,0 ) -*900 (LeafLogPort +*908 (LeafLogPort port (LogicalPort lang 2 @@ -25333,5 +25621,5 @@ uid 10475,0 ) -*901 (LeafLogPort +*909 (LeafLogPort port (LogicalPort m 4 @@ -25345,5 +25633,5 @@ uid 10763,0 ) -*902 (LeafLogPort +*910 (LeafLogPort port (LogicalPort m 4 @@ -25357,5 +25645,5 @@ uid 10765,0 ) -*903 (LeafLogPort +*911 (LeafLogPort port (LogicalPort m 1 @@ -25369,5 +25657,5 @@ uid 10767,0 ) -*904 (LeafLogPort +*912 (LeafLogPort port (LogicalPort m 1 @@ -25381,5 +25669,5 @@ uid 10769,0 ) -*905 (LeafLogPort +*913 (LeafLogPort port (LogicalPort m 1 @@ -25393,5 +25681,5 @@ uid 10771,0 ) -*906 (LeafLogPort +*914 (LeafLogPort port (LogicalPort m 4 @@ -25405,5 +25693,5 @@ uid 11411,0 ) -*907 (LeafLogPort +*915 (LeafLogPort port (LogicalPort m 4 @@ -25417,5 +25705,5 @@ uid 11966,0 ) -*908 (LeafLogPort +*916 (LeafLogPort port (LogicalPort m 4 @@ -25431,5 +25719,5 @@ uid 12310,0 ) -*909 (LeafLogPort +*917 (LeafLogPort port (LogicalPort m 4 @@ -25445,5 +25733,5 @@ uid 12659,0 ) -*910 (LeafLogPort +*918 (LeafLogPort port (LogicalPort m 4 @@ -25462,5 +25750,5 @@ uid 12661,0 ) -*911 (LeafLogPort +*919 (LeafLogPort port (LogicalPort m 4 @@ -25474,5 +25762,5 @@ uid 12663,0 ) -*912 (LeafLogPort +*920 (LeafLogPort port (LogicalPort m 1 @@ -25486,5 +25774,5 @@ uid 12719,0 ) -*913 (LeafLogPort +*921 (LeafLogPort port (LogicalPort m 4 @@ -25499,5 +25787,5 @@ uid 13275,0 ) -*914 (LeafLogPort +*922 (LeafLogPort port (LogicalPort m 4 @@ -25515,5 +25803,5 @@ uid 13277,0 ) -*915 (LeafLogPort +*923 (LeafLogPort port (LogicalPort m 4 @@ -25527,5 +25815,5 @@ uid 13279,0 ) -*916 (LeafLogPort +*924 (LeafLogPort port (LogicalPort m 4 @@ -25539,5 +25827,5 @@ uid 13281,0 ) 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+*935 (LeafLogPort +port (LogicalPort +lang 2 +m 4 +decl (Decl +n "trigger_id" +t "std_logic_vector" +b "(31 downto 0)" +preAdd 0 +posAdd 0 +o 123 +suid 302,0 +) +) +uid 15754,0 ) ] @@ -25688,5 +25992,5 @@ uid 67,0 optionalChildren [ -*927 (Sheet +*936 (Sheet sheetRow (SheetRow headerVa (MVa @@ -25705,6 +26009,6 @@ font "Tahoma,10,0" ) -emptyMRCItem *928 (MRCItem -litem &791 +emptyMRCItem *937 (MRCItem +litem &800 pos 123 dimension 20 @@ -25712,18 +26016,18 @@ uid 69,0 optionalChildren [ -*929 (MRCItem -litem &792 +*938 (MRCItem +litem &801 pos 0 dimension 20 uid 70,0 ) -*930 (MRCItem -litem &793 +*939 (MRCItem +litem &802 pos 1 dimension 23 uid 71,0 ) -*931 (MRCItem -litem &794 +*940 (MRCItem +litem &803 pos 2 hidden 1 @@ -25731,741 +26035,741 @@ uid 72,0 ) -*932 (MRCItem -litem &804 +*941 (MRCItem +litem &813 pos 37 dimension 20 uid 517,0 ) -*933 (MRCItem -litem &805 +*942 (MRCItem +litem &814 pos 38 dimension 20 uid 519,0 ) -*934 (MRCItem -litem &806 +*943 (MRCItem +litem &815 pos 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(MRCItem -litem &898 -pos 99 -dimension 20 uid 10341,0 ) -*1027 (MRCItem -litem &899 +*1035 (MRCItem +litem &907 pos 32 dimension 20 uid 10343,0 ) -*1028 (MRCItem -litem &900 +*1036 (MRCItem +litem &908 +pos 99 +dimension 20 +uid 10476,0 +) +*1037 (MRCItem +litem &909 pos 100 dimension 20 -uid 10476,0 -) -*1029 (MRCItem -litem &901 +uid 10764,0 +) +*1038 (MRCItem +litem &910 pos 101 dimension 20 -uid 10764,0 -) -*1030 (MRCItem -litem &902 -pos 102 -dimension 20 uid 10766,0 ) -*1031 (MRCItem -litem &903 +*1039 (MRCItem +litem &911 pos 33 dimension 20 uid 10768,0 ) -*1032 (MRCItem -litem &904 +*1040 (MRCItem +litem &912 pos 34 dimension 20 uid 10770,0 ) -*1033 (MRCItem -litem &905 +*1041 (MRCItem +litem &913 pos 35 dimension 20 uid 10772,0 ) -*1034 (MRCItem -litem &906 +*1042 (MRCItem +litem &914 +pos 102 +dimension 20 +uid 11412,0 +) +*1043 (MRCItem +litem &915 pos 103 dimension 20 -uid 11412,0 -) -*1035 (MRCItem -litem &907 +uid 11967,0 +) +*1044 (MRCItem +litem &916 pos 104 dimension 20 -uid 11967,0 -) -*1036 (MRCItem -litem &908 +uid 12311,0 +) +*1045 (MRCItem +litem &917 pos 105 dimension 20 -uid 12311,0 -) -*1037 (MRCItem -litem &909 +uid 12660,0 +) +*1046 (MRCItem +litem &918 pos 106 dimension 20 -uid 12660,0 -) -*1038 (MRCItem -litem &910 +uid 12662,0 +) +*1047 (MRCItem +litem &919 pos 107 dimension 20 -uid 12662,0 -) -*1039 (MRCItem -litem &911 -pos 108 -dimension 20 uid 12664,0 ) -*1040 (MRCItem -litem &912 +*1048 (MRCItem +litem &920 pos 36 dimension 20 uid 12720,0 ) -*1041 (MRCItem -litem &913 +*1049 (MRCItem +litem &921 +pos 108 +dimension 20 +uid 13276,0 +) +*1050 (MRCItem +litem &922 pos 109 dimension 20 -uid 13276,0 -) -*1042 (MRCItem -litem &914 +uid 13278,0 +) +*1051 (MRCItem +litem &923 pos 110 dimension 20 -uid 13278,0 -) -*1043 (MRCItem -litem &915 +uid 13280,0 +) +*1052 (MRCItem +litem &924 pos 111 dimension 20 -uid 13280,0 -) -*1044 (MRCItem -litem &916 +uid 13282,0 +) +*1053 (MRCItem +litem &925 pos 112 dimension 20 -uid 13282,0 -) -*1045 (MRCItem -litem &917 +uid 13688,0 +) +*1054 (MRCItem +litem &926 pos 113 dimension 20 -uid 13688,0 -) -*1046 (MRCItem -litem &918 +uid 14041,0 +) +*1055 (MRCItem +litem &927 pos 114 dimension 20 -uid 14041,0 -) -*1047 (MRCItem -litem &919 +uid 14164,0 +) +*1056 (MRCItem +litem &928 pos 115 dimension 20 -uid 14164,0 -) -*1048 (MRCItem -litem &920 +uid 14508,0 +) +*1057 (MRCItem +litem &929 pos 116 dimension 20 -uid 14508,0 -) -*1049 (MRCItem -litem &921 +uid 14510,0 +) +*1058 (MRCItem +litem &930 pos 117 dimension 20 -uid 14510,0 -) -*1050 (MRCItem -litem &922 +uid 14635,0 +) +*1059 (MRCItem +litem &931 pos 118 dimension 20 -uid 14635,0 -) -*1051 (MRCItem -litem &923 +uid 15145,0 +) +*1060 (MRCItem +litem &932 pos 119 dimension 20 -uid 15145,0 -) -*1052 (MRCItem -litem &924 +uid 15147,0 +) +*1061 (MRCItem +litem &933 pos 120 dimension 20 -uid 15147,0 -) -*1053 (MRCItem -litem &925 +uid 15149,0 +) +*1062 (MRCItem +litem &934 pos 121 dimension 20 -uid 15149,0 -) -*1054 (MRCItem -litem &926 +uid 15505,0 +) +*1063 (MRCItem +litem &935 pos 122 dimension 20 -uid 15505,0 +uid 15755,0 ) ] @@ -26480,48 +26784,48 @@ uid 73,0 optionalChildren [ -*1055 (MRCItem -litem &795 +*1064 (MRCItem +litem &804 pos 0 dimension 20 uid 74,0 ) -*1056 (MRCItem -litem &797 +*1065 (MRCItem +litem &806 pos 1 dimension 50 uid 75,0 ) -*1057 (MRCItem -litem &798 +*1066 (MRCItem +litem &807 pos 2 dimension 100 uid 76,0 ) -*1058 (MRCItem -litem &799 +*1067 (MRCItem +litem &808 pos 3 dimension 50 uid 77,0 ) -*1059 (MRCItem -litem &800 +*1068 (MRCItem +litem &809 pos 4 dimension 100 uid 78,0 ) -*1060 (MRCItem -litem &801 +*1069 (MRCItem +litem &810 pos 5 dimension 100 uid 79,0 ) -*1061 (MRCItem -litem &802 +*1070 (MRCItem +litem &811 pos 6 dimension 50 uid 80,0 ) -*1062 (MRCItem -litem &803 +*1071 (MRCItem +litem &812 pos 7 dimension 290 @@ -26543,39 +26847,39 @@ genericsCommonDM (CommonDM ldm (LogicalDM -emptyRow *1063 (LEmptyRow +emptyRow *1072 (LEmptyRow ) uid 83,0 optionalChildren [ -*1064 (RefLabelRowHdr -) -*1065 (TitleRowHdr -) -*1066 (FilterRowHdr -) -*1067 (RefLabelColHdr +*1073 (RefLabelRowHdr +) +*1074 (TitleRowHdr +) +*1075 (FilterRowHdr +) +*1076 (RefLabelColHdr tm "RefLabelColHdrMgr" ) -*1068 (RowExpandColHdr +*1077 (RowExpandColHdr tm "RowExpandColHdrMgr" ) -*1069 (GroupColHdr +*1078 (GroupColHdr tm "GroupColHdrMgr" ) -*1070 (NameColHdr +*1079 (NameColHdr tm "GenericNameColHdrMgr" ) -*1071 (TypeColHdr +*1080 (TypeColHdr tm "GenericTypeColHdrMgr" ) -*1072 (InitColHdr +*1081 (InitColHdr tm "GenericValueColHdrMgr" ) -*1073 (PragmaColHdr +*1082 (PragmaColHdr tm "GenericPragmaColHdrMgr" ) -*1074 (EolColHdr +*1083 (EolColHdr tm "GenericEolColHdrMgr" ) -*1075 (LogGeneric +*1084 (LogGeneric generic (GiElement name "RAMADDRWIDTH64b" @@ -26592,5 +26896,5 @@ uid 95,0 optionalChildren [ -*1076 (Sheet +*1085 (Sheet sheetRow (SheetRow headerVa (MVa @@ -26609,6 +26913,6 @@ font "Tahoma,10,0" ) -emptyMRCItem *1077 (MRCItem -litem &1063 +emptyMRCItem *1086 (MRCItem +litem &1072 pos 1 dimension 20 @@ -26616,18 +26920,18 @@ uid 97,0 optionalChildren [ -*1078 (MRCItem -litem &1064 +*1087 (MRCItem +litem &1073 pos 0 dimension 20 uid 98,0 ) -*1079 (MRCItem -litem &1065 +*1088 (MRCItem +litem &1074 pos 1 dimension 23 uid 99,0 ) -*1080 (MRCItem -litem &1066 +*1089 (MRCItem +litem &1075 pos 2 hidden 1 @@ -26635,6 +26939,6 @@ uid 100,0 ) -*1081 (MRCItem -litem &1075 +*1090 (MRCItem +litem &1084 pos 0 dimension 20 @@ -26652,42 +26956,42 @@ uid 101,0 optionalChildren [ -*1082 (MRCItem -litem &1067 +*1091 (MRCItem +litem &1076 pos 0 dimension 20 uid 102,0 ) -*1083 (MRCItem -litem &1069 +*1092 (MRCItem +litem &1078 pos 1 dimension 50 uid 103,0 ) -*1084 (MRCItem -litem &1070 +*1093 (MRCItem +litem &1079 pos 2 dimension 186 uid 104,0 ) -*1085 (MRCItem -litem &1071 +*1094 (MRCItem +litem &1080 pos 3 dimension 96 uid 105,0 ) -*1086 (MRCItem -litem &1072 +*1095 (MRCItem +litem &1081 pos 4 dimension 50 uid 106,0 ) -*1087 (MRCItem -litem &1073 +*1096 (MRCItem +litem &1082 pos 5 dimension 50 uid 107,0 ) -*1088 (MRCItem -litem &1074 +*1097 (MRCItem +litem &1083 pos 6 dimension 80 Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.bak =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.bak (revision 10154) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/struct.bd.bak (revision 10155) @@ -333,17 +333,17 @@ (vvPair variable "date" -value "08.02.2011" +value "14.02.2011" ) (vvPair variable "day" -value "Di" +value "Mo" ) (vvPair variable "day_long" -value "Dienstag" +value "Montag" ) (vvPair variable "dd" -value "08" +value "14" ) (vvPair @@ -485,5 +485,5 @@ (vvPair variable "time" -value "11:05:26" +value "17:05:04" ) (vvPair @@ -576,7 +576,6 @@ font "Courier New,8,0" ) -xt "-172000,106000,-128500,106800" -st "SIGNAL write_ea : std_logic_vector(0 downto 0) := \"0\" -" +xt "-172000,106800,-128500,107600" +st "SIGNAL write_ea : std_logic_vector(0 downto 0) := \"0\"" ) ) @@ -596,6 +595,5 @@ ) xt "-172000,42800,-132000,43600" -st "SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0) -" +st "SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)" ) ) @@ -615,6 +613,5 @@ ) xt "-172000,62000,-139500,62800" -st "SIGNAL data_out : std_logic_vector(63 DOWNTO 0) -" +st "SIGNAL data_out : std_logic_vector(63 DOWNTO 0)" ) ) @@ -634,6 +631,5 @@ ) xt "-172000,80400,-132000,81200" -st "SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) -" +st "SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0)" ) ) @@ -653,6 +649,5 @@ ) xt "-172000,81200,-139500,82000" -st "SIGNAL ram_data : std_logic_vector(15 downto 0) -" +st "SIGNAL ram_data : std_logic_vector(15 downto 0)" ) ) @@ -672,6 +667,5 @@ ) xt "-172000,34400,-132000,35200" -st "wiz_reset : std_logic := '1' -" +st "wiz_reset : std_logic := '1'" ) ) @@ -691,6 +685,5 @@ ) xt "-172000,32000,-143500,32800" -st "wiz_addr : std_logic_vector(9 DOWNTO 0) -" +st "wiz_addr : std_logic_vector(9 DOWNTO 0)" ) ) @@ -710,6 +703,5 @@ ) xt "-172000,36800,-143000,37600" -st "wiz_data : std_logic_vector(15 DOWNTO 0) -" +st "wiz_data : std_logic_vector(15 DOWNTO 0)" ) ) @@ -729,6 +721,5 @@ ) xt "-172000,32800,-132000,33600" -st "wiz_cs : std_logic := '1' -" +st "wiz_cs : std_logic := '1'" ) ) @@ -748,6 +739,5 @@ ) xt "-172000,35200,-132000,36000" -st "wiz_wr : std_logic := '1' -" +st "wiz_wr : std_logic := '1'" ) ) @@ -767,6 +757,5 @@ ) xt "-172000,33600,-132000,34400" -st "wiz_rd : std_logic := '1' -" +st "wiz_rd : std_logic := '1'" ) ) @@ -785,6 +774,5 @@ ) xt "-172000,13600,-153500,14400" -st "wiz_int : std_logic -" +st "wiz_int : std_logic" ) ) @@ -2882,6 +2870,5 @@ ) xt "-172000,9600,-143500,10400" -st "board_id : std_logic_vector(3 DOWNTO 0) -" +st "board_id : std_logic_vector(3 DOWNTO 0)" ) ) @@ -2902,6 +2889,5 @@ ) xt "-172000,12800,-153500,13600" -st "trigger : std_logic -" +st "trigger : std_logic" ) ) @@ -4701,6 +4687,5 @@ ) xt "-172000,10400,-143500,11200" -st "crate_id : std_logic_vector(1 DOWNTO 0) -" +st "crate_id : std_logic_vector(1 DOWNTO 0)" ) ) @@ -4926,6 +4911,5 @@ ) xt "-172000,98800,-139500,99600" -st "SIGNAL trigger_id : std_logic_vector(47 downto 0) -" +st "SIGNAL trigger_id : std_logic_vector(47 downto 0)" ) ) @@ -4947,6 +4931,5 @@ ) xt "-172000,82000,-132000,82800" -st "SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0) -" +st "SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)" ) ) @@ -5799,7 +5782,6 @@ font "Courier New,8,0" ) -xt "-172000,100400,-149500,101200" -st "SIGNAL wiz_busy : std_logic -" +xt "-172000,101200,-149500,102000" +st "SIGNAL wiz_busy : std_logic" ) ) @@ -5819,7 +5801,6 @@ font "Courier New,8,0" ) -xt "-172000,102800,-128500,103600" -st "SIGNAL wiz_write_ea : std_logic := '0' -" +xt "-172000,103600,-128500,104400" +st "SIGNAL wiz_write_ea : std_logic := '0'" ) ) @@ -5840,7 +5821,6 @@ font "Courier New,8,0" ) -xt "-172000,105200,-122500,106000" -st "SIGNAL wiz_write_length : std_logic_vector(16 downto 0) := (others => '0') -" +xt "-172000,106000,-122500,106800" +st "SIGNAL wiz_write_length : std_logic_vector(16 downto 0) := (others => '0')" ) ) @@ -5862,7 +5842,6 @@ font "Courier New,8,0" ) -xt "-172000,102000,-122500,102800" -st "SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0') -" +xt "-172000,102800,-122500,103600" +st "SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')" ) ) @@ -5883,7 +5862,6 @@ font "Courier New,8,0" ) -xt "-172000,101200,-122500,102000" -st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0) := (others => '0') -" +xt "-172000,102000,-122500,102800" +st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0) := (others => '0')" ) ) @@ -5903,7 +5881,6 @@ font "Courier New,8,0" ) -xt "-172000,103600,-128500,104400" -st "SIGNAL wiz_write_end : std_logic := '0' -" +xt "-172000,104400,-128500,105200" +st "SIGNAL wiz_write_end : std_logic := '0'" ) ) @@ -5923,7 +5900,6 @@ font "Courier New,8,0" ) -xt "-172000,104400,-128500,105200" -st "SIGNAL wiz_write_header : std_logic := '0' -" +xt "-172000,105200,-128500,106000" +st "SIGNAL wiz_write_header : std_logic := '0'" ) ) @@ -5942,6 +5918,5 @@ ) xt "-172000,82800,-149500,83600" -st "SIGNAL ram_write_ea : std_logic -" +st "SIGNAL ram_write_ea : std_logic" ) ) @@ -5961,6 +5936,5 @@ ) xt "-172000,83600,-128500,84400" -st "SIGNAL ram_write_ready : std_logic := '0' -" +st "SIGNAL ram_write_ready : std_logic := '0'" ) ) @@ -5980,6 +5954,5 @@ ) xt "-172000,54800,-128500,55600" -st "SIGNAL config_start : std_logic := '0' -" +st "SIGNAL config_start : std_logic := '0'" ) ) @@ -5998,6 +5971,5 @@ ) xt "-172000,49200,-149500,50000" -st "SIGNAL config_ready : std_logic -" +st "SIGNAL config_ready : std_logic" ) ) @@ -6016,6 +5988,5 @@ ) xt "-172000,86800,-148000,87600" -st "SIGNAL roi_max : roi_max_type -" +st "SIGNAL roi_max : roi_max_type" ) ) @@ -6035,6 +6006,5 @@ ) xt "-172000,77200,-139500,78000" -st "SIGNAL package_length : std_logic_vector(15 downto 0) -" +st "SIGNAL package_length : std_logic_vector(15 downto 0)" ) ) @@ -6054,6 +6024,5 @@ ) xt "-172000,19200,-132000,20000" -st "adc_oeb : std_logic := '1' -" +st "adc_oeb : std_logic := '1'" ) ) @@ -6162,6 +6131,5 @@ ) xt "-172000,86000,-147000,86800" -st "SIGNAL roi_array : roi_array_type -" +st "SIGNAL roi_array : roi_array_type" ) ) @@ -6596,6 +6564,5 @@ ) xt "-172000,14400,-153500,15200" -st "CLK_25_PS : std_logic -" +st "CLK_25_PS : std_logic" ) ) @@ -6659,6 +6626,5 @@ ) xt "-172000,15200,-153500,16000" -st "CLK_50 : std_logic -" +st "CLK_50 : std_logic" ) ) @@ -6677,6 +6643,5 @@ ) xt "-172000,39600,-149500,40400" -st "SIGNAL CLK_25 : std_logic -" +st "SIGNAL CLK_25 : std_logic" ) ) @@ -6740,6 +6705,5 @@ ) xt "-172000,3200,-153500,4000" -st "CLK : std_logic -" +st "CLK : std_logic" ) ) @@ -6759,6 +6723,5 @@ ) xt "-172000,8800,-143500,9600" -st "adc_otr_array : std_logic_vector(3 DOWNTO 0) -" +st "adc_otr_array : std_logic_vector(3 DOWNTO 0)" ) ) @@ -6777,6 +6740,5 @@ ) xt "-172000,8000,-148000,8800" -st "adc_data_array : adc_data_array_type -" +st "adc_data_array : adc_data_array_type" ) ) @@ -6841,6 +6803,5 @@ ) xt "-172000,66800,-128500,67600" -st "SIGNAL drs_clk_en : std_logic := '0' -" +st "SIGNAL drs_clk_en : std_logic := '0'" ) ) @@ -6859,6 +6820,5 @@ ) xt "-172000,73200,-143500,74000" -st "SIGNAL drs_s_cell_array : drs_s_cell_array_type -" +st "SIGNAL drs_s_cell_array : drs_s_cell_array_type" ) ) @@ -6878,6 +6838,5 @@ ) xt "-172000,67600,-128500,68400" -st "SIGNAL drs_read_s_cell : std_logic := '0' -" +st "SIGNAL drs_read_s_cell : std_logic := '0'" ) ) @@ -6898,6 +6857,5 @@ ) xt "-172000,25600,-126000,26400" -st "drs_channel_id : std_logic_vector(3 downto 0) := (others => '0') -" +st "drs_channel_id : std_logic_vector(3 downto 0) := (others => '0')" ) ) @@ -6917,6 +6875,5 @@ ) xt "-172000,26400,-132000,27200" -st "drs_dwrite : std_logic := '1' -" +st "drs_dwrite : std_logic := '1'" ) ) @@ -7025,6 +6982,5 @@ ) xt "-172000,4800,-153500,5600" -st "SROUT_in_0 : std_logic -" +st "SROUT_in_0 : std_logic" ) ) @@ -7043,6 +6999,5 @@ ) xt "-172000,5600,-153500,6400" -st "SROUT_in_1 : std_logic -" +st "SROUT_in_1 : std_logic" ) ) @@ -7061,6 +7016,5 @@ ) xt "-172000,6400,-153500,7200" -st "SROUT_in_2 : std_logic -" +st "SROUT_in_2 : std_logic" ) ) @@ -7079,6 +7033,5 @@ ) xt "-172000,7200,-153500,8000" -st "SROUT_in_3 : std_logic -" +st "SROUT_in_3 : std_logic" ) ) @@ -7277,6 +7230,5 @@ ) xt "-172000,68400,-149500,69200" -st "SIGNAL drs_read_s_cell_ready : std_logic -" +st "SIGNAL drs_read_s_cell_ready : std_logic" ) ) @@ -7933,6 +7885,5 @@ ) xt "-172000,16000,-132000,16800" -st "RSRLOAD : std_logic := '0' -" +st "RSRLOAD : std_logic := '0'" ) ) @@ -7997,6 +7948,5 @@ ) xt "-172000,16800,-132000,17600" -st "SRCLK : std_logic := '0' -" +st "SRCLK : std_logic := '0'" ) ) @@ -8651,6 +8601,5 @@ ) xt "-172000,45200,-140000,46000" -st "SIGNAL config_addr : std_logic_vector(7 DOWNTO 0) -" +st "SIGNAL config_addr : std_logic_vector(7 DOWNTO 0)" ) ) @@ -8669,6 +8618,5 @@ ) xt "-172000,47600,-149500,48400" -st "SIGNAL config_data_valid : std_logic -" +st "SIGNAL config_data_valid : std_logic" ) ) @@ -8687,6 +8635,5 @@ ) xt "-172000,46000,-149500,46800" -st "SIGNAL config_busy : std_logic -" +st "SIGNAL config_busy : std_logic" ) ) @@ -8706,6 +8653,5 @@ ) xt "-172000,46800,-139500,47600" -st "SIGNAL config_data : std_logic_vector(15 DOWNTO 0) -" +st "SIGNAL config_data : std_logic_vector(15 DOWNTO 0)" ) ) @@ -8724,6 +8670,5 @@ ) xt "-172000,60400,-149500,61200" -st "SIGNAL config_wr_en : std_logic -" +st "SIGNAL config_wr_en : std_logic" ) ) @@ -8742,6 +8687,5 @@ ) xt "-172000,48400,-149500,49200" -st "SIGNAL config_rd_en : std_logic -" +st "SIGNAL config_rd_en : std_logic" ) ) @@ -8760,6 +8704,5 @@ ) xt "-172000,61200,-147000,62000" -st "SIGNAL dac_array : dac_array_type -" +st "SIGNAL dac_array : dac_array_type" ) ) @@ -8778,6 +8721,5 @@ ) xt "-172000,55600,-149500,56400" -st "SIGNAL config_start_cm : std_logic -" +st "SIGNAL config_start_cm : std_logic" ) ) @@ -8796,6 +8738,5 @@ ) xt "-172000,50000,-149500,50800" -st "SIGNAL config_ready_cm : std_logic -" +st "SIGNAL config_ready_cm : std_logic" ) ) @@ -8817,6 +8758,5 @@ ) xt "-172000,28000,-126000,28800" -st "led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') -" +st "led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" ) ) @@ -8835,6 +8775,5 @@ ) xt "-172000,91600,-149500,92400" -st "SIGNAL sensor_ready : std_logic -" +st "SIGNAL sensor_ready : std_logic" ) ) @@ -8853,6 +8792,5 @@ ) xt "-172000,90800,-145500,91600" -st "SIGNAL sensor_array : sensor_array_type -" +st "SIGNAL sensor_array : sensor_array_type" ) ) @@ -8871,6 +8809,5 @@ ) xt "-172000,50800,-149500,51600" -st "SIGNAL config_ready_spi : std_logic -" +st "SIGNAL config_ready_spi : std_logic" ) ) @@ -8891,6 +8828,5 @@ ) xt "-172000,42000,-140000,42800" -st "SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0) -" +st "SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0)" ) ) @@ -8909,6 +8845,5 @@ ) xt "-172000,41200,-144500,42000" -st "SIGNAL adc_data_array_int : adc_data_array_type -" +st "SIGNAL adc_data_array_int : adc_data_array_type" ) ) @@ -9200,6 +9135,5 @@ ) xt "-172000,56400,-128500,57200" -st "SIGNAL config_start_spi : std_logic := '0' -" +st "SIGNAL config_start_spi : std_logic := '0'" ) ) @@ -9734,6 +9668,5 @@ ) xt "-172000,30400,-153500,31200" -st "sclk : std_logic -" +st "sclk : std_logic" ) ) @@ -9754,6 +9687,5 @@ ) xt "-172000,36000,-153500,36800" -st "sio : std_logic -" +st "sio : std_logic" ) ) @@ -9772,6 +9704,5 @@ ) xt "-172000,24000,-153500,24800" -st "dac_cs : std_logic -" +st "dac_cs : std_logic" ) ) @@ -9791,6 +9722,5 @@ ) xt "-172000,31200,-143500,32000" -st "sensor_cs : std_logic_vector(3 DOWNTO 0) -" +st "sensor_cs : std_logic_vector(3 DOWNTO 0)" ) ) @@ -9990,6 +9920,5 @@ ) xt "-172000,76400,-128500,77200" -st "SIGNAL new_config : std_logic := '0' -" +st "SIGNAL new_config : std_logic := '0'" ) ) @@ -10008,6 +9937,5 @@ ) xt "-172000,57200,-149500,58000" -st "SIGNAL config_started : std_logic -" +st "SIGNAL config_started : std_logic" ) ) @@ -10027,6 +9955,5 @@ ) xt "-172000,59600,-128500,60400" -st "SIGNAL config_started_spi : std_logic := '0' -" +st "SIGNAL config_started_spi : std_logic := '0'" ) ) @@ -10046,6 +9973,5 @@ ) xt "-172000,58000,-128500,58800" -st "SIGNAL config_started_cu : std_logic := '0' -" +st "SIGNAL config_started_cu : std_logic := '0'" ) ) @@ -10064,6 +9990,5 @@ ) xt "-172000,58800,-149500,59600" -st "SIGNAL config_started_mm : std_logic -" +st "SIGNAL config_started_mm : std_logic" ) ) @@ -10083,6 +10008,5 @@ ) xt "-172000,28800,-132000,29600" -st "mosi : std_logic := '0' -" +st "mosi : std_logic := '0'" ) ) @@ -10149,6 +10073,5 @@ ) xt "-172000,24800,-118500,25600" -st "denable : std_logic := '0' -- default domino wave off -" +st "denable : std_logic := '0' -- default domino wave off" ) ) @@ -10212,6 +10135,5 @@ ) xt "-172000,75600,-128500,76400" -st "SIGNAL dwrite_enable : std_logic := '1' -" +st "SIGNAL dwrite_enable : std_logic := '1'" ) ) @@ -10600,6 +10522,5 @@ ) xt "-172000,74800,-128500,75600" -st "SIGNAL dwrite : std_logic := '1' -" +st "SIGNAL dwrite : std_logic := '1'" ) ) @@ -10974,7 +10895,6 @@ font "Courier New,8,0" ) -xt "-172000,99600,-149500,100400" -st "SIGNAL wiz_ack : std_logic -" +xt "-172000,100400,-149500,101200" +st "SIGNAL wiz_ack : std_logic" ) ) @@ -11359,6 +11279,5 @@ ) xt "-172000,89200,-149500,90000" -st "SIGNAL sclk1 : std_logic -" +st "SIGNAL sclk1 : std_logic" ) ) @@ -11377,6 +11296,5 @@ ) xt "-172000,90000,-149500,90800" -st "SIGNAL sclk_enable : std_logic -" +st "SIGNAL sclk_enable : std_logic" ) ) @@ -11396,6 +11314,5 @@ ) xt "-172000,18400,-132000,19200" -st "adc_clk_en : std_logic := '0' -" +st "adc_clk_en : std_logic := '0'" ) ) @@ -11851,6 +11768,5 @@ ) xt "-172000,78000,-113000,78800" -st "SIGNAL ps_direction : std_logic := '1' -- default phase shift upwards -" +st "SIGNAL ps_direction : std_logic := '1' -- default phase shift upwards" ) ) @@ -11873,6 +11789,5 @@ ) xt "-172000,78800,-112000,79600" -st "SIGNAL ps_do_phase_shift : std_logic := '0' --pulse this to phase shift once -" +st "SIGNAL ps_do_phase_shift : std_logic := '0' --pulse this to phase shift once" ) ) @@ -11894,6 +11809,5 @@ ) xt "-172000,79600,-104500,80400" -st "SIGNAL ps_reset : std_logic := '0' -- pulse this to reset the variable phase shift -" +st "SIGNAL ps_reset : std_logic := '0' -- pulse this to reset the variable phase shift" ) ) @@ -11913,6 +11827,5 @@ ) xt "-172000,94000,-128500,94800" -st "SIGNAL srclk_enable : std_logic := '0' -" +st "SIGNAL srclk_enable : std_logic := '0'" ) ) @@ -12298,6 +12211,5 @@ ) xt "-172000,40400,-128500,41200" -st "SIGNAL SRCLK1 : std_logic := '0' -" +st "SIGNAL SRCLK1 : std_logic := '0'" ) ) @@ -12321,6 +12233,5 @@ xt "-172000,51600,-128500,53200" st "-- -- -SIGNAL config_rw_ack : std_logic := '0' -" +SIGNAL config_rw_ack : std_logic := '0'" ) ) @@ -12344,6 +12255,5 @@ xt "-172000,53200,-128500,54800" st "-- -- -SIGNAL config_rw_ready : std_logic := '0' -" +SIGNAL config_rw_ready : std_logic := '0'" ) ) @@ -12362,6 +12272,5 @@ ) xt "-172000,87600,-149500,88400" -st "SIGNAL s_trigger : std_logic -" +st "SIGNAL s_trigger : std_logic" ) ) @@ -12380,6 +12289,5 @@ ) xt "-172000,96400,-149500,97200" -st "SIGNAL start_srin_write_8b : std_logic -" +st "SIGNAL start_srin_write_8b : std_logic" ) ) @@ -12399,6 +12307,5 @@ ) xt "-172000,94800,-128500,95600" -st "SIGNAL srin_write_ack : std_logic := '0' -" +st "SIGNAL srin_write_ack : std_logic := '0'" ) ) @@ -12418,6 +12325,5 @@ ) xt "-172000,95600,-128500,96400" -st "SIGNAL srin_write_ready : std_logic := '0' -" +st "SIGNAL srin_write_ready : std_logic := '0'" ) ) @@ -12438,6 +12344,5 @@ ) xt "-172000,74000,-122500,74800" -st "SIGNAL drs_srin_data : std_logic_vector(7 downto 0) := (others => '0') -" +st "SIGNAL drs_srin_data : std_logic_vector(7 downto 0) := (others => '0')" ) ) @@ -12457,6 +12362,5 @@ ) xt "-172000,17600,-132000,18400" -st "SRIN_out : std_logic := '0' -" +st "SRIN_out : std_logic := '0'" ) ) @@ -12980,6 +12884,5 @@ xt "-172000,84400,-128500,86000" st "-- -- -SIGNAL ram_write_ready_ack : std_logic := '0' -" +SIGNAL ram_write_ready_ack : std_logic := '0'" ) ) @@ -12998,6 +12901,5 @@ ) xt "-172000,92400,-149500,93200" -st "SIGNAL socks_connected : std_logic -" +st "SIGNAL socks_connected : std_logic" ) ) @@ -13016,6 +12918,5 @@ ) xt "-172000,93200,-149500,94000" -st "SIGNAL socks_waiting : std_logic -" +st "SIGNAL socks_waiting : std_logic" ) ) @@ -13034,6 +12935,5 @@ ) xt "-172000,27200,-153500,28000" -st "green : std_logic -" +st "green : std_logic" ) ) @@ -13096,6 +12996,5 @@ ) xt "-172000,22400,-153500,23200" -st "amber : std_logic -" +st "amber : std_logic" ) ) @@ -13158,6 +13057,5 @@ ) xt "-172000,29600,-153500,30400" -st "red : std_logic -" +st "red : std_logic" ) ) @@ -13599,6 +13497,5 @@ ) xt "-172000,72400,-149500,73200" -st "SIGNAL drs_readout_started : std_logic -" +st "SIGNAL drs_readout_started : std_logic" ) ) @@ -13617,6 +13514,5 @@ ) xt "-172000,98000,-149500,98800" -st "SIGNAL trigger_enable : std_logic -" +st "SIGNAL trigger_enable : std_logic" ) ) @@ -14006,6 +13902,5 @@ ) xt "-172000,65200,-149500,66000" -st "SIGNAL dout : std_logic -" +st "SIGNAL dout : std_logic" ) ) @@ -14320,6 +14215,5 @@ ) xt "-172000,66000,-149500,66800" -st "SIGNAL dout1 : std_logic -" +st "SIGNAL dout1 : std_logic" ) ) @@ -14345,6 +14239,5 @@ st "-- -- -- drs_dwrite : out std_logic := '1'; -SIGNAL drs_readout_ready : std_logic := '0' -" +SIGNAL drs_readout_ready : std_logic := '0'" ) ) @@ -14363,6 +14256,5 @@ ) xt "-172000,71600,-149500,72400" -st "SIGNAL drs_readout_ready_ack : std_logic -" +st "SIGNAL drs_readout_ready_ack : std_logic" ) ) @@ -14381,6 +14273,5 @@ ) xt "-172000,20000,-153500,20800" -st "additional_flasher_out : std_logic -" +st "additional_flasher_out : std_logic" ) ) @@ -14674,6 +14565,5 @@ ) xt "-172000,43600,-128500,44400" -st "SIGNAL c_trigger_enable : std_logic := '0' -" +st "SIGNAL c_trigger_enable : std_logic := '0'" ) ) @@ -14696,6 +14586,5 @@ ) xt "-172000,44400,-112000,45200" -st "SIGNAL c_trigger_mult : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1') --subject to changes -" +st "SIGNAL c_trigger_mult : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1') --subject to changes" ) ) @@ -14714,6 +14603,5 @@ ) xt "-172000,88400,-149500,89200" -st "SIGNAL s_trigger_0 : std_logic -" +st "SIGNAL s_trigger_0 : std_logic" ) ) @@ -14732,6 +14620,5 @@ ) xt "-172000,97200,-149500,98000" -st "SIGNAL trigger1 : std_logic -" +st "SIGNAL trigger1 : std_logic" ) ) @@ -15247,6 +15134,5 @@ ) xt "-172000,4000,-143500,4800" -st "D_T_in : std_logic_vector(1 DOWNTO 0) -" +st "D_T_in : std_logic_vector(1 DOWNTO 0)" ) ) @@ -15311,6 +15197,5 @@ ) xt "-172000,11200,-121500,12000" -st "drs_refclk_in : std_logic -- used to check if DRS REFCLK exsists, if not DENABLE inhibit -" +st "drs_refclk_in : std_logic -- used to check if DRS REFCLK exsists, if not DENABLE inhibit" ) ) @@ -15376,6 +15261,5 @@ ) xt "-172000,12000,-114000,12800" -st "plllock_in : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked -" +st "plllock_in : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked" ) ) @@ -15660,6 +15544,5 @@ ) xt "-172000,20800,-118500,21600" -st "alarm_refclk_too_high : std_logic := '0' -- default domino wave off -" +st "alarm_refclk_too_high : std_logic := '0' -- default domino wave off" ) ) @@ -15725,6 +15608,5 @@ ) xt "-172000,21600,-118500,22400" -st "alarm_refclk_too_low : std_logic := '0' -- default domino wave off -" +st "alarm_refclk_too_low : std_logic := '0' -- default domino wave off" ) ) @@ -15789,6 +15671,5 @@ ) xt "-172000,23200,-126000,24000" -st "counter_result : std_logic_vector(11 downto 0) := (others => '0') -" +st "counter_result : std_logic_vector(11 downto 0) := (others => '0')" ) ) @@ -16946,6 +16827,5 @@ ) xt "-172000,63600,-115000,64400" -st "SIGNAL denable_prim : std_logic := '0' -- default domino wave off -" +st "SIGNAL denable_prim : std_logic := '0' -- default domino wave off" ) ) @@ -16967,6 +16847,5 @@ ) xt "-172000,64400,-115000,65200" -st "SIGNAL din1 : std_logic := '0' -- default domino wave off -" +st "SIGNAL din1 : std_logic := '0' -- default domino wave off" ) ) @@ -16988,9 +16867,26 @@ ) xt "-172000,62800,-115000,63600" -st "SIGNAL denable_inhibit : std_logic := '0' -- default domino wave off -" -) -) -*598 (Wire +st "SIGNAL denable_inhibit : std_logic := '0' -- default domino wave off" +) +) +*598 (Net +uid 15492,0 +decl (Decl +n "trigger_out" +t "std_logic" +o 123 +suid 301,0 +i "'0'" +) +declText (MLText +uid 15493,0 +va (VaSet +font "Courier New,8,0" +) +xt "-172000,99600,-128500,100400" +st "SIGNAL trigger_out : std_logic := '0'" +) +) +*599 (Wire uid 322,0 shape (OrthoPolyLine @@ -17031,5 +16927,5 @@ on &2 ) -*599 (Wire +*600 (Wire uid 328,0 shape (OrthoPolyLine @@ -17070,5 +16966,5 @@ on &3 ) -*600 (Wire +*601 (Wire uid 334,0 shape (OrthoPolyLine @@ -17109,5 +17005,5 @@ on &4 ) -*601 (Wire +*602 (Wire uid 364,0 shape (OrthoPolyLine @@ -17149,5 +17045,5 @@ on &5 ) -*602 (Wire +*603 (Wire uid 370,0 shape (OrthoPolyLine @@ -17189,5 +17085,5 @@ on &6 ) -*603 (Wire +*604 (Wire uid 376,0 shape (OrthoPolyLine @@ -17227,5 +17123,5 @@ on &7 ) -*604 (Wire +*605 (Wire uid 384,0 shape (OrthoPolyLine @@ -17267,5 +17163,5 @@ on &8 ) -*605 (Wire +*606 (Wire uid 392,0 shape (OrthoPolyLine @@ -17307,5 +17203,5 @@ on &9 ) -*606 (Wire +*607 (Wire uid 400,0 shape (OrthoPolyLine @@ -17345,5 +17241,5 @@ on &10 ) -*607 (Wire +*608 (Wire uid 408,0 shape (OrthoPolyLine @@ -17383,5 +17279,5 @@ on &11 ) -*608 (Wire +*609 (Wire uid 424,0 shape (OrthoPolyLine @@ -17421,5 +17317,5 @@ on &12 ) -*609 (Wire +*610 (Wire uid 432,0 shape (OrthoPolyLine @@ -17459,5 +17355,5 @@ on &13 ) -*610 (Wire +*611 (Wire uid 1411,0 shape (OrthoPolyLine @@ -17498,5 +17394,5 @@ on &71 ) -*611 (Wire +*612 (Wire uid 1425,0 shape (OrthoPolyLine @@ -17537,5 +17433,5 @@ on &72 ) -*612 (Wire +*613 (Wire uid 1682,0 shape (OrthoPolyLine @@ -17576,5 +17472,5 @@ on &122 ) -*613 (Wire +*614 (Wire uid 1983,0 shape (OrthoPolyLine @@ -17615,5 +17511,5 @@ on &130 ) -*614 (Wire +*615 (Wire uid 2299,0 shape (OrthoPolyLine @@ -17653,5 +17549,5 @@ on &131 ) -*615 (Wire +*616 (Wire uid 2470,0 shape (OrthoPolyLine @@ -17689,5 +17585,5 @@ on &155 ) -*616 (Wire +*617 (Wire uid 2476,0 shape (OrthoPolyLine @@ -17725,5 +17621,5 @@ on &156 ) -*617 (Wire +*618 (Wire uid 2482,0 shape (OrthoPolyLine @@ -17763,5 +17659,5 @@ on &157 ) -*618 (Wire +*619 (Wire uid 2488,0 shape (OrthoPolyLine @@ -17801,5 +17697,5 @@ on &158 ) -*619 (Wire +*620 (Wire uid 2494,0 shape (OrthoPolyLine @@ -17839,5 +17735,5 @@ on &159 ) -*620 (Wire +*621 (Wire uid 2500,0 shape (OrthoPolyLine @@ -17875,5 +17771,5 @@ on &160 ) -*621 (Wire +*622 (Wire uid 2506,0 shape (OrthoPolyLine @@ -17911,5 +17807,5 @@ on &161 ) -*622 (Wire +*623 (Wire uid 2576,0 shape (OrthoPolyLine @@ -17947,5 +17843,5 @@ on &162 ) -*623 (Wire +*624 (Wire uid 2582,0 shape (OrthoPolyLine @@ -17983,5 +17879,5 @@ on &163 ) -*624 (Wire +*625 (Wire uid 2588,0 shape (OrthoPolyLine @@ -18020,5 +17916,5 @@ on &164 ) -*625 (Wire +*626 (Wire uid 2594,0 shape (OrthoPolyLine @@ -18056,5 +17952,5 @@ on &165 ) -*626 (Wire +*627 (Wire uid 2600,0 shape (OrthoPolyLine @@ -18092,5 +17988,5 @@ on &166 ) -*627 (Wire +*628 (Wire uid 2642,0 shape (OrthoPolyLine @@ -18130,5 +18026,5 @@ on &167 ) -*628 (Wire +*629 (Wire uid 2778,0 shape (OrthoPolyLine @@ -18168,5 +18064,5 @@ on &168 ) -*629 (Wire +*630 (Wire uid 2786,0 shape (OrthoPolyLine @@ -18208,8 +18104,8 @@ on &191 ) -*630 (Wire +*631 (Wire uid 3888,0 optionalChildren [ -*631 (BdJunction +*632 (BdJunction uid 4230,0 ps "OnConnectorStrategy" @@ -18223,5 +18119,5 @@ ) ) -*632 (BdJunction +*633 (BdJunction uid 4244,0 ps "OnConnectorStrategy" @@ -18274,5 +18170,5 @@ on &187 ) -*633 (Wire +*634 (Wire uid 3984,0 shape (OrthoPolyLine @@ -18315,5 +18211,5 @@ on &185 ) -*634 (Wire +*635 (Wire uid 4042,0 shape (OrthoPolyLine @@ -18353,5 +18249,5 @@ on &190 ) -*635 (Wire +*636 (Wire uid 4226,0 shape (OrthoPolyLine @@ -18369,5 +18265,5 @@ ) start &189 -end &631 +end &632 sat 32 eat 32 @@ -18393,5 +18289,5 @@ on &187 ) -*636 (Wire +*637 (Wire uid 4240,0 shape (OrthoPolyLine @@ -18409,5 +18305,5 @@ ) start &335 -end &632 +end &633 sat 32 eat 32 @@ -18432,5 +18328,5 @@ on &187 ) -*637 (Wire +*638 (Wire uid 4272,0 shape (OrthoPolyLine @@ -18470,5 +18366,5 @@ on &192 ) -*638 (Wire +*639 (Wire uid 4401,0 shape (OrthoPolyLine @@ -18508,5 +18404,5 @@ on &194 ) -*639 (Wire +*640 (Wire uid 4407,0 shape (OrthoPolyLine @@ -18546,5 +18442,5 @@ on &195 ) -*640 (Wire +*641 (Wire uid 4419,0 shape (OrthoPolyLine @@ -18584,5 +18480,5 @@ on &196 ) -*641 (Wire +*642 (Wire uid 4537,0 shape (OrthoPolyLine @@ -18624,5 +18520,5 @@ on &197 ) -*642 (Wire +*643 (Wire uid 4545,0 shape (OrthoPolyLine @@ -18661,5 +18557,5 @@ on &198 ) -*643 (Wire +*644 (Wire uid 4671,0 shape (OrthoPolyLine @@ -18699,5 +18595,5 @@ on &201 ) -*644 (Wire +*645 (Wire uid 4679,0 shape (OrthoPolyLine @@ -18737,5 +18633,5 @@ on &202 ) -*645 (Wire +*646 (Wire uid 4687,0 shape (OrthoPolyLine @@ -18775,5 +18671,5 @@ on &203 ) -*646 (Wire +*647 (Wire uid 4695,0 shape (OrthoPolyLine @@ -18813,5 +18709,5 @@ on &204 ) -*647 (Wire +*648 (Wire uid 4743,0 shape (OrthoPolyLine @@ -18851,8 +18747,8 @@ on &209 ) -*648 (Wire +*649 (Wire uid 4757,0 optionalChildren [ -*649 (BdJunction +*650 (BdJunction uid 6076,0 ps "OnConnectorStrategy" @@ -18862,5 +18758,5 @@ vasetType 1 ) -xt "-25400,40600,-24600,41400" +xt "-26400,40600,-25600,41400" radius 400 ) @@ -18873,14 +18769,14 @@ lineColor "0,32896,0" ) -xt "-62000,41000,-25000,48000" +xt "-64000,41000,-26000,48000" pts [ "-58750,48000" -"-62000,48000" -"-62000,41000" -"-25000,41000" +"-64000,48000" +"-64000,41000" +"-26000,41000" ] ) start &211 -end *650 (BdJunction +end *651 (BdJunction uid 6080,0 ps "OnConnectorStrategy" @@ -18890,5 +18786,5 @@ vasetType 1 ) -xt "-25400,40600,-24600,41400" +xt "-26400,40600,-25600,41400" radius 400 ) @@ -18916,5 +18812,5 @@ on &188 ) -*651 (Wire +*652 (Wire uid 4948,0 shape (OrthoPolyLine @@ -18954,5 +18850,5 @@ on &230 ) -*652 (Wire +*653 (Wire uid 4962,0 shape (OrthoPolyLine @@ -18992,5 +18888,5 @@ on &232 ) -*653 (Wire +*654 (Wire uid 5090,0 shape (OrthoPolyLine @@ -19031,5 +18927,5 @@ on &252 ) -*654 (Wire +*655 (Wire uid 5098,0 shape (OrthoPolyLine @@ -19065,5 +18961,5 @@ on &253 ) -*655 (Wire +*656 (Wire uid 5106,0 shape (OrthoPolyLine @@ -19102,5 +18998,5 @@ on &254 ) -*656 (Wire +*657 (Wire uid 5114,0 shape (OrthoPolyLine @@ -19141,5 +19037,5 @@ on &255 ) -*657 (Wire +*658 (Wire uid 5122,0 shape (OrthoPolyLine @@ -19178,5 +19074,5 @@ on &256 ) -*658 (Wire +*659 (Wire uid 5130,0 shape (OrthoPolyLine @@ -19215,8 +19111,8 @@ on &257 ) -*659 (Wire +*660 (Wire uid 5138,0 optionalChildren [ -*660 (BdJunction +*661 (BdJunction uid 5400,0 ps "OnConnectorStrategy" @@ -19268,5 +19164,5 @@ on &171 ) -*661 (Wire +*662 (Wire uid 5146,0 shape (OrthoPolyLine @@ -19304,5 +19200,5 @@ on &258 ) -*662 (Wire +*663 (Wire uid 5168,0 shape (OrthoPolyLine @@ -19319,5 +19215,5 @@ ] ) -start &660 +start &661 end &147 sat 32 @@ -19342,5 +19238,5 @@ on &171 ) -*663 (Wire +*664 (Wire uid 5184,0 shape (OrthoPolyLine @@ -19379,5 +19275,5 @@ on &259 ) -*664 (Wire +*665 (Wire uid 5190,0 shape (OrthoPolyLine @@ -19416,5 +19312,5 @@ on &260 ) -*665 (Wire +*666 (Wire uid 5222,0 shape (OrthoPolyLine @@ -19456,5 +19352,5 @@ on &261 ) -*666 (Wire +*667 (Wire uid 5404,0 shape (OrthoPolyLine @@ -19493,5 +19389,5 @@ on &264 ) -*667 (Wire +*668 (Wire uid 5474,0 shape (OrthoPolyLine @@ -19530,5 +19426,5 @@ on &262 ) -*668 (Wire +*669 (Wire uid 5480,0 shape (OrthoPolyLine @@ -19567,5 +19463,5 @@ on &263 ) -*669 (Wire +*670 (Wire uid 5582,0 shape (OrthoPolyLine @@ -19602,8 +19498,8 @@ on &187 ) -*670 (Wire +*671 (Wire uid 5602,0 optionalChildren [ -&650 +&651 ] shape (OrthoPolyLine @@ -19613,9 +19509,9 @@ lineColor "0,32896,0" ) -xt "-25000,41000,36250,51000" +xt "-26000,41000,36250,51000" pts [ "-21750,51000" -"-25000,51000" -"-25000,41000" +"-26000,51000" +"-26000,41000" "28000,41000" "28000,47000" @@ -19647,5 +19543,5 @@ on &188 ) -*671 (Wire +*672 (Wire uid 5626,0 shape (OrthoPolyLine @@ -19683,5 +19579,5 @@ on &266 ) -*672 (Wire +*673 (Wire uid 5634,0 shape (OrthoPolyLine @@ -19721,5 +19617,5 @@ on &265 ) -*673 (Wire +*674 (Wire uid 5646,0 shape (OrthoPolyLine @@ -19757,5 +19653,5 @@ on &185 ) -*674 (Wire +*675 (Wire uid 5745,0 shape (OrthoPolyLine @@ -19795,5 +19691,5 @@ on &276 ) -*675 (Wire +*676 (Wire uid 5805,0 shape (OrthoPolyLine @@ -19829,5 +19725,5 @@ on &187 ) -*676 (Wire +*677 (Wire uid 5813,0 shape (OrthoPolyLine @@ -19867,5 +19763,5 @@ on &293 ) -*677 (Wire +*678 (Wire uid 5821,0 shape (OrthoPolyLine @@ -19905,5 +19801,5 @@ on &294 ) -*678 (Wire +*679 (Wire uid 5829,0 shape (OrthoPolyLine @@ -19943,5 +19839,5 @@ on &295 ) -*679 (Wire +*680 (Wire uid 5837,0 shape (OrthoPolyLine @@ -19983,5 +19879,5 @@ on &296 ) -*680 (Wire +*681 (Wire uid 5950,0 shape (OrthoPolyLine @@ -20021,5 +19917,5 @@ on &301 ) -*681 (Wire +*682 (Wire uid 5962,0 shape (OrthoPolyLine @@ -20059,5 +19955,5 @@ on &302 ) -*682 (Wire +*683 (Wire uid 6002,0 shape (OrthoPolyLine @@ -20097,5 +19993,5 @@ on &304 ) -*683 (Wire +*684 (Wire uid 6008,0 shape (OrthoPolyLine @@ -20135,5 +20031,5 @@ on &303 ) -*684 (Wire +*685 (Wire uid 6018,0 shape (OrthoPolyLine @@ -20171,5 +20067,5 @@ on &305 ) -*685 (Wire +*686 (Wire uid 6064,0 shape (OrthoPolyLine @@ -20206,5 +20102,5 @@ on &258 ) -*686 (Wire +*687 (Wire uid 6072,0 shape (OrthoPolyLine @@ -20214,13 +20110,13 @@ lineColor "0,32896,0" ) -xt "-41250,23000,-25000,41000" +xt "-41250,23000,-26000,41000" pts [ "-41250,23000" -"-25000,23000" -"-25000,41000" +"-26000,23000" +"-26000,41000" ] ) start &366 -end &649 +end &650 sat 32 eat 32 @@ -20245,5 +20141,5 @@ on &188 ) -*687 (Wire +*688 (Wire uid 6160,0 shape (OrthoPolyLine @@ -20283,5 +20179,5 @@ on &306 ) -*688 (Wire +*689 (Wire uid 6276,0 shape (OrthoPolyLine @@ -20317,5 +20213,5 @@ on &185 ) -*689 (Wire +*690 (Wire uid 6362,0 shape (OrthoPolyLine @@ -20356,5 +20252,5 @@ on &308 ) -*690 (Wire +*691 (Wire uid 6452,0 shape (OrthoPolyLine @@ -20392,5 +20288,5 @@ on &310 ) -*691 (Wire +*692 (Wire uid 6540,0 shape (OrthoPolyLine @@ -20429,5 +20325,5 @@ on &329 ) -*692 (Wire +*693 (Wire uid 6548,0 shape (OrthoPolyLine @@ -20466,5 +20362,5 @@ on &310 ) -*693 (Wire +*694 (Wire uid 8416,0 shape (OrthoPolyLine @@ -20502,5 +20398,5 @@ on &341 ) -*694 (Wire +*695 (Wire uid 8732,0 shape (OrthoPolyLine @@ -20540,5 +20436,5 @@ on &360 ) -*695 (Wire +*696 (Wire uid 8738,0 shape (OrthoPolyLine @@ -20576,5 +20472,5 @@ on &361 ) -*696 (Wire +*697 (Wire uid 8752,0 shape (OrthoPolyLine @@ -20611,5 +20507,5 @@ on &361 ) -*697 (Wire +*698 (Wire uid 9006,0 shape (OrthoPolyLine @@ -20649,5 +20545,5 @@ on &362 ) -*698 (Wire +*699 (Wire uid 9233,0 shape (OrthoPolyLine @@ -20684,5 +20580,5 @@ on &376 ) -*699 (Wire +*700 (Wire uid 9241,0 shape (OrthoPolyLine @@ -20719,5 +20615,5 @@ on &377 ) -*700 (Wire +*701 (Wire uid 9253,0 shape (OrthoPolyLine @@ -20753,5 +20649,5 @@ on &376 ) -*701 (Wire +*702 (Wire uid 9261,0 shape (OrthoPolyLine @@ -20787,5 +20683,5 @@ on &377 ) -*702 (Wire +*703 (Wire uid 9943,0 shape (OrthoPolyLine @@ -20822,5 +20718,5 @@ on &378 ) -*703 (Wire +*704 (Wire uid 9951,0 shape (OrthoPolyLine @@ -20857,5 +20753,5 @@ on &379 ) -*704 (Wire +*705 (Wire uid 10010,0 shape (OrthoPolyLine @@ -20895,5 +20791,5 @@ on &398 ) -*705 (Wire +*706 (Wire uid 10018,0 shape (OrthoPolyLine @@ -20931,5 +20827,5 @@ on &379 ) -*706 (Wire +*707 (Wire uid 10036,0 shape (OrthoPolyLine @@ -20965,5 +20861,5 @@ on &378 ) -*707 (Wire +*708 (Wire uid 10194,0 shape (OrthoPolyLine @@ -21005,5 +20901,5 @@ on &399 ) -*708 (Wire +*709 (Wire uid 10202,0 shape (OrthoPolyLine @@ -21043,5 +20939,5 @@ on &400 ) -*709 (Wire +*710 (Wire uid 10266,0 shape (OrthoPolyLine @@ -21078,5 +20974,5 @@ on &498 ) -*710 (Wire +*711 (Wire uid 10298,0 shape (OrthoPolyLine @@ -21114,5 +21010,5 @@ on &402 ) -*711 (Wire +*712 (Wire uid 10304,0 shape (OrthoPolyLine @@ -21150,5 +21046,5 @@ on &403 ) -*712 (Wire +*713 (Wire uid 10310,0 shape (OrthoPolyLine @@ -21186,5 +21082,5 @@ on &404 ) -*713 (Wire +*714 (Wire uid 10316,0 shape (OrthoPolyLine @@ -21224,5 +21120,5 @@ on &405 ) -*714 (Wire +*715 (Wire uid 10322,0 shape (OrthoPolyLine @@ -21262,5 +21158,5 @@ on &406 ) -*715 (Wire +*716 (Wire uid 10431,0 shape (OrthoPolyLine @@ -21299,5 +21195,5 @@ on &401 ) -*716 (Wire +*717 (Wire uid 10467,0 shape (OrthoPolyLine @@ -21336,5 +21232,5 @@ on &431 ) -*717 (Wire +*718 (Wire uid 10629,0 shape (OrthoPolyLine @@ -21371,5 +21267,5 @@ on &432 ) -*718 (Wire +*719 (Wire uid 10637,0 shape (OrthoPolyLine @@ -21406,5 +21302,5 @@ on &433 ) -*719 (Wire +*720 (Wire uid 10685,0 shape (OrthoPolyLine @@ -21441,5 +21337,5 @@ on &433 ) -*720 (Wire +*721 (Wire uid 10691,0 shape (OrthoPolyLine @@ -21476,5 +21372,5 @@ on &432 ) -*721 (Wire +*722 (Wire uid 10699,0 shape (OrthoPolyLine @@ -21512,5 +21408,5 @@ on &187 ) -*722 (Wire +*723 (Wire uid 10707,0 shape (OrthoPolyLine @@ -21547,5 +21443,5 @@ on &452 ) -*723 (Wire +*724 (Wire uid 10723,0 shape (OrthoPolyLine @@ -21585,5 +21481,5 @@ on &434 ) -*724 (Wire +*725 (Wire uid 10737,0 shape (OrthoPolyLine @@ -21623,5 +21519,5 @@ on &436 ) -*725 (Wire +*726 (Wire uid 10751,0 shape (OrthoPolyLine @@ -21661,5 +21557,5 @@ on &438 ) -*726 (Wire +*727 (Wire uid 11405,0 shape (OrthoPolyLine @@ -21697,5 +21593,5 @@ on &452 ) -*727 (Wire +*728 (Wire uid 11858,0 shape (OrthoPolyLine @@ -21732,5 +21628,5 @@ on &453 ) -*728 (Wire +*729 (Wire uid 11952,0 shape (OrthoPolyLine @@ -21768,5 +21664,5 @@ on &453 ) -*729 (Wire +*730 (Wire uid 12306,0 shape (OrthoPolyLine @@ -21806,5 +21702,5 @@ on &472 ) -*730 (Wire +*731 (Wire uid 12643,0 shape (OrthoPolyLine @@ -21846,5 +21742,5 @@ on &483 ) -*731 (Wire +*732 (Wire uid 12649,0 shape (OrthoPolyLine @@ -21882,5 +21778,5 @@ on &484 ) -*732 (Wire +*733 (Wire uid 12655,0 shape (OrthoPolyLine @@ -21919,5 +21815,5 @@ on &485 ) -*733 (Wire +*734 (Wire uid 12687,0 shape (OrthoPolyLine @@ -21957,5 +21853,5 @@ on &188 ) -*734 (Wire +*735 (Wire uid 12707,0 shape (OrthoPolyLine @@ -21995,5 +21891,5 @@ on &486 ) -*735 (Wire +*736 (Wire uid 13143,0 shape (OrthoPolyLine @@ -22030,5 +21926,5 @@ on &188 ) -*736 (Wire +*737 (Wire uid 13159,0 shape (OrthoPolyLine @@ -22068,5 +21964,5 @@ on &496 ) -*737 (Wire +*738 (Wire uid 13165,0 shape (OrthoPolyLine @@ -22108,5 +22004,5 @@ on &497 ) -*738 (Wire +*739 (Wire uid 13210,0 shape (OrthoPolyLine @@ -22144,5 +22040,5 @@ on &499 ) -*739 (Wire +*740 (Wire uid 13216,0 shape (OrthoPolyLine @@ -22180,5 +22076,5 @@ on &498 ) -*740 (Wire +*741 (Wire uid 13224,0 shape (OrthoPolyLine @@ -22216,5 +22112,5 @@ on &401 ) -*741 (Wire +*742 (Wire uid 13695,0 shape (OrthoPolyLine @@ -22255,5 +22151,5 @@ on &524 ) -*742 (Wire +*743 (Wire uid 13921,0 shape (OrthoPolyLine @@ -22292,5 +22188,5 @@ on &71 ) -*743 (Wire +*744 (Wire uid 13929,0 shape (OrthoPolyLine @@ -22329,5 +22225,5 @@ on &122 ) -*744 (Wire +*745 (Wire uid 14048,0 shape (OrthoPolyLine @@ -22366,5 +22262,5 @@ on &526 ) -*745 (Wire +*746 (Wire uid 14171,0 shape (OrthoPolyLine @@ -22404,5 +22300,5 @@ on &528 ) -*746 (Wire +*747 (Wire uid 14427,0 shape (OrthoPolyLine @@ -22439,5 +22335,5 @@ on &187 ) -*747 (Wire +*748 (Wire uid 14479,0 shape (OrthoPolyLine @@ -22477,5 +22373,5 @@ on &538 ) -*748 (Wire +*749 (Wire uid 14493,0 shape (OrthoPolyLine @@ -22515,5 +22411,5 @@ on &540 ) -*749 (Wire +*750 (Wire uid 14622,0 shape (OrthoPolyLine @@ -22555,5 +22451,5 @@ on &542 ) -*750 (Wire +*751 (Wire uid 15071,0 shape (OrthoPolyLine @@ -22591,5 +22487,5 @@ on &595 ) -*751 (Wire +*752 (Wire uid 15081,0 shape (OrthoPolyLine @@ -22629,5 +22525,5 @@ on &596 ) -*752 (Wire +*753 (Wire uid 15122,0 shape (OrthoPolyLine @@ -22667,5 +22563,5 @@ on &597 ) -*753 (Wire +*754 (Wire uid 15130,0 shape (OrthoPolyLine @@ -22705,5 +22601,5 @@ on &540 ) -*754 (Wire +*755 (Wire uid 15138,0 shape (OrthoPolyLine @@ -22743,5 +22639,5 @@ on &538 ) -*755 (Wire +*756 (Wire uid 15379,0 shape (OrthoPolyLine @@ -22778,4 +22674,92 @@ on &188 ) +*757 (Wire +uid 15494,0 +optionalChildren [ +*758 (BdJunction +uid 15502,0 +ps "OnConnectorStrategy" +shape (Circle +uid 15503,0 +va (VaSet +vasetType 1 +) +xt "-54400,71600,-53600,72400" +radius 400 +) +) +] +shape (OrthoPolyLine +uid 15495,0 +va (VaSet +vasetType 3 +) +xt "-55250,72000,-21750,72000" +pts [ +"-55250,72000" +"-21750,72000" +] +) +start &475 +end &30 +sat 32 +eat 32 +st 0 +sf 1 +si 0 +tg (WTG +uid 15496,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 15497,0 +va (VaSet +) +xt "-53250,71000,-48650,72000" +st "trigger_out" +blo "-53250,71800" +tm "WireNameMgr" +) +) +on &598 +) +*759 (Wire +uid 15498,0 +shape (OrthoPolyLine +uid 15499,0 +va (VaSet +vasetType 3 +) +xt "-54000,69000,-52750,72000" +pts [ +"-52750,69000" +"-54000,69000" +"-54000,72000" +] +) +start &125 +end &758 +sat 32 +eat 32 +stc 0 +st 0 +sf 1 +si 0 +tg (WTG +uid 15500,0 +ps "ConnStartEndStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 15501,0 +va (VaSet +) +xt "-58000,69000,-53400,70000" +st "trigger_out" +blo "-58000,69800" +tm "WireNameMgr" +) +) +on &598 +) ] bg "65535,65535,65535" @@ -22790,9 +22774,9 @@ color "26368,26368,26368" ) -packageList *756 (PackageList +packageList *760 (PackageList uid 41,0 stg "VerticalLayoutStrategy" textVec [ -*757 (Text +*761 (Text uid 42,0 va (VaSet @@ -22803,5 +22787,5 @@ blo "-163000,-15200" ) -*758 (MLText +*762 (MLText uid 43,0 va (VaSet @@ -22828,5 +22812,5 @@ stg "VerticalLayoutStrategy" textVec [ -*759 (Text +*763 (Text uid 45,0 va (VaSet @@ -22838,5 +22822,5 @@ blo "20000,800" ) -*760 (Text +*764 (Text uid 46,0 va (VaSet @@ -22848,5 +22832,5 @@ blo "20000,1800" ) -*761 (MLText +*765 (MLText uid 47,0 va (VaSet @@ -22858,5 +22842,5 @@ tm "BdCompilerDirectivesTextMgr" ) -*762 (Text +*766 (Text uid 48,0 va (VaSet @@ -22868,5 +22852,5 @@ blo "20000,4800" ) -*763 (MLText +*767 (MLText uid 49,0 va (VaSet @@ -22876,5 +22860,5 @@ tm "BdCompilerDirectivesTextMgr" ) -*764 (Text +*768 (Text uid 50,0 va (VaSet @@ -22886,5 +22870,5 @@ blo "20000,5800" ) -*765 (MLText +*769 (MLText uid 51,0 va (VaSet @@ -22898,5 +22882,5 @@ ) windowSize "0,0,1281,1024" -viewArea "-65668,47481,1175,102606" +viewArea "-115714,18689,-11272,104822" cachedDiagramExtent "-174000,-25425,428157,346294" pageSetupInfo (PageSetupInfo @@ -22924,5 +22908,5 @@ hasePageBreakOrigin 1 pageBreakOrigin "-73000,0" -lastUid 15388,0 +lastUid 15608,0 defaultCommentText (CommentText shape (Rectangle @@ -22986,5 +22970,5 @@ stg "VerticalLayoutStrategy" textVec [ -*766 (Text +*770 (Text va (VaSet font "Arial,8,1" @@ -22995,5 +22979,5 @@ tm "BdLibraryNameMgr" ) -*767 (Text +*771 (Text va (VaSet font "Arial,8,1" @@ -23004,5 +22988,5 @@ tm "BlkNameMgr" ) -*768 (Text +*772 (Text va (VaSet font "Arial,8,1" @@ -23055,5 +23039,5 @@ stg "VerticalLayoutStrategy" textVec [ -*769 (Text +*773 (Text va (VaSet font "Arial,8,1" @@ -23063,5 +23047,5 @@ blo "550,4300" ) -*770 (Text +*774 (Text va (VaSet font "Arial,8,1" @@ -23071,5 +23055,5 @@ blo "550,5300" ) -*771 (Text +*775 (Text va (VaSet font "Arial,8,1" @@ -23120,5 +23104,5 @@ stg "VerticalLayoutStrategy" textVec [ -*772 (Text +*776 (Text va (VaSet font "Arial,8,1" @@ -23129,5 +23113,5 @@ tm "BdLibraryNameMgr" ) -*773 (Text +*777 (Text va (VaSet font "Arial,8,1" @@ -23138,5 +23122,5 @@ tm "CptNameMgr" ) -*774 (Text +*778 (Text va (VaSet font "Arial,8,1" @@ -23192,5 +23176,5 @@ stg "VerticalLayoutStrategy" textVec [ -*775 (Text +*779 (Text va (VaSet font "Arial,8,1" @@ -23200,5 +23184,5 @@ blo "500,4300" ) -*776 (Text +*780 (Text va (VaSet font "Arial,8,1" @@ -23208,5 +23192,5 @@ blo "500,5300" ) -*777 (Text +*781 (Text va (VaSet font "Arial,8,1" @@ -23253,5 +23237,5 @@ stg "VerticalLayoutStrategy" textVec [ -*778 (Text +*782 (Text va (VaSet font "Arial,8,1" @@ -23261,5 +23245,5 @@ blo "50,4300" ) -*779 (Text +*783 (Text va (VaSet font "Arial,8,1" @@ -23269,5 +23253,5 @@ blo "50,5300" ) -*780 (Text +*784 (Text va (VaSet font "Arial,8,1" @@ -23310,5 +23294,5 @@ stg "VerticalLayoutStrategy" textVec [ -*781 (Text +*785 (Text va (VaSet font "Arial,8,1" @@ -23319,5 +23303,5 @@ tm "HdlTextNameMgr" ) -*782 (Text +*786 (Text va (VaSet font "Arial,8,1" @@ -23722,5 +23706,5 @@ stg "VerticalLayoutStrategy" textVec [ -*783 (Text +*787 (Text va (VaSet font "Arial,8,1" @@ -23730,5 +23714,5 @@ blo "14100,20800" ) -*784 (MLText +*788 (MLText va (VaSet ) @@ -23782,5 +23766,5 @@ stg "VerticalLayoutStrategy" textVec [ -*785 (Text +*789 (Text va (VaSet font "Arial,8,1" @@ -23790,5 +23774,5 @@ blo "14100,20800" ) -*786 (MLText +*790 (MLText va (VaSet ) @@ -23915,7 +23899,7 @@ font "Arial,8,1" ) -xt "-174000,106800,-169300,107800" +xt "-174000,107600,-169300,108600" st "Post User:" -blo "-174000,107600" +blo "-174000,108400" ) postUserText (MLText @@ -23930,44 +23914,44 @@ commonDM (CommonDM ldm (LogicalDM -suid 300,0 +suid 301,0 usingSuid 1 -emptyRow *787 (LEmptyRow +emptyRow *791 (LEmptyRow ) uid 54,0 optionalChildren [ -*788 (RefLabelRowHdr -) -*789 (TitleRowHdr -) -*790 (FilterRowHdr -) -*791 (RefLabelColHdr +*792 (RefLabelRowHdr +) +*793 (TitleRowHdr +) +*794 (FilterRowHdr +) +*795 (RefLabelColHdr tm "RefLabelColHdrMgr" ) -*792 (RowExpandColHdr +*796 (RowExpandColHdr tm "RowExpandColHdrMgr" ) -*793 (GroupColHdr +*797 (GroupColHdr tm "GroupColHdrMgr" ) -*794 (NameColHdr +*798 (NameColHdr tm "BlockDiagramNameColHdrMgr" ) -*795 (ModeColHdr +*799 (ModeColHdr tm "BlockDiagramModeColHdrMgr" ) -*796 (TypeColHdr +*800 (TypeColHdr tm "BlockDiagramTypeColHdrMgr" ) -*797 (BoundsColHdr +*801 (BoundsColHdr tm "BlockDiagramBoundsColHdrMgr" ) -*798 (InitColHdr +*802 (InitColHdr tm "BlockDiagramInitColHdrMgr" ) -*799 (EolColHdr +*803 (EolColHdr tm "BlockDiagramEolColHdrMgr" ) -*800 (LeafLogPort +*804 (LeafLogPort port (LogicalPort m 4 @@ -23983,5 +23967,5 @@ uid 516,0 ) -*801 (LeafLogPort +*805 (LeafLogPort port (LogicalPort m 4 @@ -23996,5 +23980,5 @@ uid 518,0 ) -*802 (LeafLogPort +*806 (LeafLogPort port (LogicalPort m 4 @@ -24009,5 +23993,5 @@ uid 520,0 ) -*803 (LeafLogPort +*807 (LeafLogPort port (LogicalPort m 4 @@ -24022,5 +24006,5 @@ uid 530,0 ) -*804 (LeafLogPort +*808 (LeafLogPort port (LogicalPort m 4 @@ -24035,5 +24019,5 @@ uid 532,0 ) -*805 (LeafLogPort +*809 (LeafLogPort port (LogicalPort m 1 @@ -24048,5 +24032,5 @@ uid 534,0 ) -*806 (LeafLogPort +*810 (LeafLogPort port (LogicalPort m 1 @@ -24061,5 +24045,5 @@ uid 536,0 ) -*807 (LeafLogPort +*811 (LeafLogPort port (LogicalPort m 2 @@ -24074,5 +24058,5 @@ uid 538,0 ) -*808 (LeafLogPort +*812 (LeafLogPort port (LogicalPort m 1 @@ -24087,5 +24071,5 @@ uid 540,0 ) -*809 (LeafLogPort +*813 (LeafLogPort port (LogicalPort m 1 @@ -24100,5 +24084,5 @@ uid 542,0 ) -*810 (LeafLogPort +*814 (LeafLogPort port (LogicalPort m 1 @@ -24113,5 +24097,5 @@ uid 546,0 ) -*811 (LeafLogPort +*815 (LeafLogPort port (LogicalPort decl (Decl @@ -24124,5 +24108,5 @@ uid 548,0 ) -*812 (LeafLogPort +*816 (LeafLogPort port (LogicalPort decl (Decl @@ -24136,5 +24120,5 @@ uid 1455,0 ) -*813 (LeafLogPort +*817 (LeafLogPort port (LogicalPort decl (Decl @@ -24149,5 +24133,5 @@ uid 1457,0 ) -*814 (LeafLogPort +*818 (LeafLogPort port (LogicalPort decl (Decl @@ -24161,5 +24145,5 @@ uid 1694,0 ) -*815 (LeafLogPort +*819 (LeafLogPort port (LogicalPort lang 2 @@ -24177,5 +24161,5 @@ uid 1993,0 ) -*816 (LeafLogPort +*820 (LeafLogPort port (LogicalPort m 4 @@ -24192,5 +24176,5 @@ uid 2305,0 ) -*817 (LeafLogPort +*821 (LeafLogPort port (LogicalPort lang 2 @@ -24205,5 +24189,5 @@ uid 2510,0 ) -*818 (LeafLogPort +*822 (LeafLogPort port (LogicalPort lang 2 @@ -24219,5 +24203,5 @@ uid 2512,0 ) -*819 (LeafLogPort +*823 (LeafLogPort port (LogicalPort lang 2 @@ -24234,5 +24218,5 @@ uid 2514,0 ) -*820 (LeafLogPort +*824 (LeafLogPort port (LogicalPort lang 2 @@ -24250,5 +24234,5 @@ uid 2516,0 ) -*821 (LeafLogPort +*825 (LeafLogPort port (LogicalPort lang 2 @@ -24265,5 +24249,5 @@ uid 2518,0 ) -*822 (LeafLogPort +*826 (LeafLogPort port (LogicalPort lang 2 @@ -24279,5 +24263,5 @@ uid 2520,0 ) -*823 (LeafLogPort +*827 (LeafLogPort port (LogicalPort lang 2 @@ -24293,5 +24277,5 @@ uid 2522,0 ) -*824 (LeafLogPort +*828 (LeafLogPort port (LogicalPort m 4 @@ -24305,5 +24289,5 @@ uid 2604,0 ) -*825 (LeafLogPort +*829 (LeafLogPort port (LogicalPort m 4 @@ -24318,5 +24302,5 @@ uid 2606,0 ) -*826 (LeafLogPort +*830 (LeafLogPort port (LogicalPort m 4 @@ -24331,5 +24315,5 @@ uid 2608,0 ) -*827 (LeafLogPort +*831 (LeafLogPort port (LogicalPort m 4 @@ -24343,5 +24327,5 @@ uid 2610,0 ) -*828 (LeafLogPort +*832 (LeafLogPort port (LogicalPort m 4 @@ -24355,5 +24339,5 @@ uid 2612,0 ) -*829 (LeafLogPort +*833 (LeafLogPort port (LogicalPort m 4 @@ -24368,5 +24352,5 @@ uid 2646,0 ) -*830 (LeafLogPort +*834 (LeafLogPort port (LogicalPort m 1 @@ -24381,5 +24365,5 @@ uid 2812,0 ) -*831 (LeafLogPort +*835 (LeafLogPort port (LogicalPort m 4 @@ -24393,5 +24377,5 @@ uid 2962,0 ) -*832 (LeafLogPort +*836 (LeafLogPort port (LogicalPort m 1 @@ -24405,5 +24389,5 @@ uid 3902,0 ) -*833 (LeafLogPort +*837 (LeafLogPort port (LogicalPort m 1 @@ -24417,5 +24401,5 @@ uid 4070,0 ) -*834 (LeafLogPort +*838 (LeafLogPort port (LogicalPort m 4 @@ -24429,5 +24413,5 @@ uid 4212,0 ) -*835 (LeafLogPort +*839 (LeafLogPort port (LogicalPort decl (Decl @@ -24440,5 +24424,5 @@ uid 4234,0 ) -*836 (LeafLogPort +*840 (LeafLogPort port (LogicalPort decl (Decl @@ -24452,5 +24436,5 @@ uid 4262,0 ) -*837 (LeafLogPort +*841 (LeafLogPort port (LogicalPort decl (Decl @@ -24463,5 +24447,5 @@ uid 4276,0 ) -*838 (LeafLogPort +*842 (LeafLogPort port (LogicalPort m 4 @@ -24476,5 +24460,5 @@ uid 4563,0 ) -*839 (LeafLogPort +*843 (LeafLogPort port (LogicalPort m 4 @@ -24488,5 +24472,5 @@ uid 4565,0 ) -*840 (LeafLogPort +*844 (LeafLogPort port (LogicalPort m 4 @@ -24501,5 +24485,5 @@ uid 4569,0 ) -*841 (LeafLogPort +*845 (LeafLogPort port (LogicalPort m 1 @@ -24515,5 +24499,5 @@ uid 4585,0 ) -*842 (LeafLogPort +*846 (LeafLogPort port (LogicalPort m 1 @@ -24528,5 +24512,5 @@ uid 4587,0 ) -*843 (LeafLogPort +*847 (LeafLogPort port (LogicalPort decl (Decl @@ -24539,5 +24523,5 @@ uid 4733,0 ) -*844 (LeafLogPort +*848 (LeafLogPort port (LogicalPort decl (Decl @@ -24550,5 +24534,5 @@ uid 4735,0 ) -*845 (LeafLogPort +*849 (LeafLogPort port (LogicalPort decl (Decl @@ -24561,5 +24545,5 @@ uid 4737,0 ) -*846 (LeafLogPort +*850 (LeafLogPort port (LogicalPort decl (Decl @@ -24572,5 +24556,5 @@ uid 4739,0 ) -*847 (LeafLogPort +*851 (LeafLogPort port (LogicalPort m 4 @@ -24584,5 +24568,5 @@ uid 4749,0 ) -*848 (LeafLogPort +*852 (LeafLogPort port (LogicalPort m 1 @@ -24597,5 +24581,5 @@ uid 4974,0 ) -*849 (LeafLogPort +*853 (LeafLogPort port (LogicalPort m 1 @@ -24610,5 +24594,5 @@ uid 4976,0 ) -*850 (LeafLogPort +*854 (LeafLogPort port (LogicalPort m 4 @@ -24623,5 +24607,5 @@ uid 5198,0 ) -*851 (LeafLogPort +*855 (LeafLogPort port (LogicalPort m 4 @@ -24635,5 +24619,5 @@ uid 5200,0 ) -*852 (LeafLogPort +*856 (LeafLogPort port (LogicalPort m 4 @@ -24647,5 +24631,5 @@ uid 5202,0 ) -*853 (LeafLogPort +*857 (LeafLogPort port (LogicalPort m 4 @@ -24660,5 +24644,5 @@ uid 5204,0 ) -*854 (LeafLogPort +*858 (LeafLogPort port (LogicalPort m 4 @@ -24672,5 +24656,5 @@ uid 5206,0 ) -*855 (LeafLogPort +*859 (LeafLogPort port (LogicalPort m 4 @@ -24684,5 +24668,5 @@ uid 5208,0 ) -*856 (LeafLogPort +*860 (LeafLogPort port (LogicalPort m 4 @@ -24696,5 +24680,5 @@ uid 5210,0 ) -*857 (LeafLogPort +*861 (LeafLogPort port (LogicalPort m 4 @@ -24708,5 +24692,5 @@ uid 5212,0 ) -*858 (LeafLogPort +*862 (LeafLogPort port (LogicalPort m 4 @@ -24720,5 +24704,5 @@ uid 5214,0 ) -*859 (LeafLogPort +*863 (LeafLogPort port (LogicalPort m 1 @@ -24735,5 +24719,5 @@ uid 5226,0 ) -*860 (LeafLogPort +*864 (LeafLogPort port (LogicalPort m 4 @@ -24747,5 +24731,5 @@ uid 5502,0 ) -*861 (LeafLogPort +*865 (LeafLogPort port (LogicalPort m 4 @@ -24759,5 +24743,5 @@ uid 5504,0 ) -*862 (LeafLogPort +*866 (LeafLogPort port (LogicalPort m 4 @@ -24771,5 +24755,5 @@ uid 5600,0 ) -*863 (LeafLogPort +*867 (LeafLogPort port (LogicalPort lang 10 @@ -24785,5 +24769,5 @@ uid 5642,0 ) -*864 (LeafLogPort +*868 (LeafLogPort port (LogicalPort m 4 @@ -24797,5 +24781,5 @@ uid 5644,0 ) -*865 (LeafLogPort +*869 (LeafLogPort port (LogicalPort m 4 @@ -24810,5 +24794,5 @@ uid 5751,0 ) -*866 (LeafLogPort +*870 (LeafLogPort port (LogicalPort m 1 @@ -24822,5 +24806,5 @@ uid 5867,0 ) -*867 (LeafLogPort +*871 (LeafLogPort port (LogicalPort m 2 @@ -24836,5 +24820,5 @@ uid 5869,0 ) -*868 (LeafLogPort +*872 (LeafLogPort port (LogicalPort m 1 @@ -24848,5 +24832,5 @@ uid 5871,0 ) -*869 (LeafLogPort +*873 (LeafLogPort port (LogicalPort m 1 @@ -24861,5 +24845,5 @@ uid 5873,0 ) -*870 (LeafLogPort +*874 (LeafLogPort port (LogicalPort m 4 @@ -24874,5 +24858,5 @@ uid 5966,0 ) -*871 (LeafLogPort +*875 (LeafLogPort port (LogicalPort m 4 @@ -24886,5 +24870,5 @@ uid 5968,0 ) -*872 (LeafLogPort +*876 (LeafLogPort port (LogicalPort m 4 @@ -24899,5 +24883,5 @@ uid 6022,0 ) -*873 (LeafLogPort +*877 (LeafLogPort port (LogicalPort m 4 @@ -24912,5 +24896,5 @@ uid 6024,0 ) -*874 (LeafLogPort +*878 (LeafLogPort port (LogicalPort m 4 @@ -24924,5 +24908,5 @@ uid 6026,0 ) -*875 (LeafLogPort +*879 (LeafLogPort port (LogicalPort m 1 @@ -24937,5 +24921,5 @@ uid 6172,0 ) -*876 (LeafLogPort +*880 (LeafLogPort port (LogicalPort m 1 @@ -24952,5 +24936,5 @@ uid 6374,0 ) -*877 (LeafLogPort +*881 (LeafLogPort port (LogicalPort m 4 @@ -24965,5 +24949,5 @@ uid 6464,0 ) -*878 (LeafLogPort +*882 (LeafLogPort port (LogicalPort m 4 @@ -24978,5 +24962,5 @@ uid 6554,0 ) -*879 (LeafLogPort +*883 (LeafLogPort port (LogicalPort lang 2 @@ -24991,5 +24975,5 @@ uid 8420,0 ) -*880 (LeafLogPort +*884 (LeafLogPort port (LogicalPort m 4 @@ -25003,5 +24987,5 @@ uid 8758,0 ) -*881 (LeafLogPort +*885 (LeafLogPort port (LogicalPort m 4 @@ -25015,5 +24999,5 @@ uid 8760,0 ) -*882 (LeafLogPort +*886 (LeafLogPort port (LogicalPort m 1 @@ -25028,5 +25012,5 @@ uid 9018,0 ) -*883 (LeafLogPort +*887 (LeafLogPort port (LogicalPort m 4 @@ -25043,5 +25027,5 @@ uid 9247,0 ) -*884 (LeafLogPort +*888 (LeafLogPort port (LogicalPort m 4 @@ -25059,5 +25043,5 @@ uid 9249,0 ) -*885 (LeafLogPort +*889 (LeafLogPort port (LogicalPort m 4 @@ -25074,5 +25058,5 @@ uid 10024,0 ) -*886 (LeafLogPort +*890 (LeafLogPort port (LogicalPort m 4 @@ -25087,5 +25071,5 @@ uid 10026,0 ) -*887 (LeafLogPort +*891 (LeafLogPort port (LogicalPort m 4 @@ -25100,5 +25084,5 @@ uid 10028,0 ) -*888 (LeafLogPort +*892 (LeafLogPort port (LogicalPort m 4 @@ -25116,5 +25100,5 @@ uid 10208,0 ) -*889 (LeafLogPort +*893 (LeafLogPort port (LogicalPort m 4 @@ -25132,5 +25116,5 @@ uid 10210,0 ) -*890 (LeafLogPort +*894 (LeafLogPort port (LogicalPort m 4 @@ -25144,5 +25128,5 @@ uid 10294,0 ) -*891 (LeafLogPort +*895 (LeafLogPort port (LogicalPort m 4 @@ -25156,5 +25140,5 @@ uid 10334,0 ) -*892 (LeafLogPort +*896 (LeafLogPort port (LogicalPort m 4 @@ -25169,5 +25153,5 @@ uid 10336,0 ) -*893 (LeafLogPort +*897 (LeafLogPort port (LogicalPort m 4 @@ -25182,5 +25166,5 @@ uid 10338,0 ) -*894 (LeafLogPort +*898 (LeafLogPort port (LogicalPort m 4 @@ -25196,5 +25180,5 @@ uid 10340,0 ) -*895 (LeafLogPort +*899 (LeafLogPort port (LogicalPort m 1 @@ -25209,5 +25193,5 @@ uid 10342,0 ) -*896 (LeafLogPort +*900 (LeafLogPort port (LogicalPort lang 2 @@ -25226,5 +25210,5 @@ uid 10475,0 ) -*897 (LeafLogPort +*901 (LeafLogPort port (LogicalPort m 4 @@ -25237,52 +25221,4 @@ ) uid 10763,0 -) -*898 (LeafLogPort -port (LogicalPort -m 4 -decl (Decl -n "socks_waiting" -t "std_logic" -o 112 -suid 244,0 -) -) -uid 10765,0 -) -*899 (LeafLogPort -port (LogicalPort -m 1 -decl (Decl -n "green" -t "std_logic" -o 34 -suid 248,0 -) -) -uid 10767,0 -) -*900 (LeafLogPort -port (LogicalPort -m 1 -decl (Decl -n "amber" -t "std_logic" -o 29 -suid 249,0 -) -) -uid 10769,0 -) -*901 (LeafLogPort -port (LogicalPort -m 1 -decl (Decl -n "red" -t "std_logic" -o 39 -suid 250,0 -) -) -uid 10771,0 ) *902 (LeafLogPort @@ -25290,4 +25226,52 @@ m 4 decl (Decl +n "socks_waiting" +t "std_logic" +o 112 +suid 244,0 +) +) +uid 10765,0 +) +*903 (LeafLogPort +port (LogicalPort +m 1 +decl (Decl +n "green" +t "std_logic" +o 34 +suid 248,0 +) +) +uid 10767,0 +) +*904 (LeafLogPort +port (LogicalPort +m 1 +decl (Decl +n "amber" +t "std_logic" +o 29 +suid 249,0 +) +) +uid 10769,0 +) +*905 (LeafLogPort +port (LogicalPort +m 1 +decl (Decl +n "red" +t "std_logic" +o 39 +suid 250,0 +) +) +uid 10771,0 +) +*906 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl n "drs_readout_started" t "std_logic" @@ -25298,5 +25282,5 @@ uid 11411,0 ) -*903 (LeafLogPort +*907 (LeafLogPort port (LogicalPort m 4 @@ -25310,5 +25294,5 @@ uid 11966,0 ) -*904 (LeafLogPort +*908 (LeafLogPort port (LogicalPort m 4 @@ -25324,5 +25308,5 @@ uid 12310,0 ) -*905 (LeafLogPort +*909 (LeafLogPort port (LogicalPort m 4 @@ -25338,5 +25322,5 @@ uid 12659,0 ) -*906 (LeafLogPort +*910 (LeafLogPort port (LogicalPort m 4 @@ -25355,5 +25339,5 @@ uid 12661,0 ) -*907 (LeafLogPort +*911 (LeafLogPort port (LogicalPort m 4 @@ -25367,5 +25351,5 @@ uid 12663,0 ) -*908 (LeafLogPort +*912 (LeafLogPort port (LogicalPort m 1 @@ -25379,5 +25363,5 @@ uid 12719,0 ) -*909 (LeafLogPort +*913 (LeafLogPort port (LogicalPort m 4 @@ -25392,5 +25376,5 @@ uid 13275,0 ) -*910 (LeafLogPort +*914 (LeafLogPort port (LogicalPort m 4 @@ -25408,5 +25392,5 @@ uid 13277,0 ) -*911 (LeafLogPort +*915 (LeafLogPort port (LogicalPort m 4 @@ -25420,5 +25404,5 @@ uid 13279,0 ) -*912 (LeafLogPort +*916 (LeafLogPort port (LogicalPort m 4 @@ -25432,5 +25416,5 @@ uid 13281,0 ) -*913 (LeafLogPort +*917 (LeafLogPort port (LogicalPort decl (Decl @@ -25445,5 +25429,5 @@ scheme 0 ) -*914 (LeafLogPort +*918 (LeafLogPort port (LogicalPort decl (Decl @@ -25458,5 +25442,5 @@ scheme 0 ) -*915 (LeafLogPort +*919 (LeafLogPort port (LogicalPort decl (Decl @@ -25472,5 +25456,5 @@ scheme 0 ) -*916 (LeafLogPort +*920 (LeafLogPort port (LogicalPort m 1 @@ -25487,5 +25471,5 @@ uid 14507,0 ) -*917 (LeafLogPort +*921 (LeafLogPort port (LogicalPort m 1 @@ -25502,5 +25486,5 @@ uid 14509,0 ) -*918 (LeafLogPort +*922 (LeafLogPort port (LogicalPort m 1 @@ -25516,5 +25500,5 @@ uid 14634,0 ) -*919 (LeafLogPort +*923 (LeafLogPort port (LogicalPort m 4 @@ -25531,5 +25515,5 @@ uid 15144,0 ) -*920 (LeafLogPort +*924 (LeafLogPort port (LogicalPort m 4 @@ -25546,5 +25530,5 @@ uid 15146,0 ) -*921 (LeafLogPort +*925 (LeafLogPort port (LogicalPort m 4 @@ -25561,4 +25545,17 @@ uid 15148,0 ) +*926 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "trigger_out" +t "std_logic" +o 123 +suid 301,0 +i "'0'" +) +) +uid 15504,0 +) ] ) @@ -25568,5 +25565,5 @@ uid 67,0 optionalChildren [ -*922 (Sheet +*927 (Sheet sheetRow (SheetRow headerVa (MVa @@ -25585,25 +25582,25 @@ font "Tahoma,10,0" ) -emptyMRCItem *923 (MRCItem -litem &787 -pos 122 +emptyMRCItem *928 (MRCItem +litem &791 +pos 123 dimension 20 ) uid 69,0 optionalChildren [ -*924 (MRCItem -litem &788 +*929 (MRCItem +litem &792 pos 0 dimension 20 uid 70,0 ) -*925 (MRCItem -litem &789 +*930 (MRCItem +litem &793 pos 1 dimension 23 uid 71,0 ) -*926 (MRCItem -litem &790 +*931 (MRCItem +litem &794 pos 2 hidden 1 @@ -25611,735 +25608,741 @@ uid 72,0 ) -*927 (MRCItem -litem &800 +*932 (MRCItem +litem &804 pos 37 dimension 20 uid 517,0 ) -*928 (MRCItem -litem &801 +*933 (MRCItem +litem &805 pos 38 dimension 20 uid 519,0 ) -*929 (MRCItem -litem &802 +*934 (MRCItem +litem &806 pos 39 dimension 20 uid 521,0 ) -*930 (MRCItem -litem &803 +*935 (MRCItem +litem &807 pos 40 dimension 20 uid 531,0 ) -*931 (MRCItem -litem &804 +*936 (MRCItem +litem &808 pos 41 dimension 20 uid 533,0 ) -*932 (MRCItem -litem &805 +*937 (MRCItem +litem &809 pos 0 dimension 20 uid 535,0 ) -*933 (MRCItem -litem &806 +*938 (MRCItem +litem &810 pos 1 dimension 20 uid 537,0 ) -*934 (MRCItem -litem &807 +*939 (MRCItem +litem &811 pos 2 dimension 20 uid 539,0 ) -*935 (MRCItem -litem &808 +*940 (MRCItem +litem &812 pos 3 dimension 20 uid 541,0 ) -*936 (MRCItem -litem &809 +*941 (MRCItem +litem &813 pos 4 dimension 20 uid 543,0 ) -*937 (MRCItem -litem &810 +*942 (MRCItem +litem &814 pos 5 dimension 20 uid 547,0 ) -*938 (MRCItem -litem &811 +*943 (MRCItem +litem &815 pos 6 dimension 20 uid 549,0 ) -*939 (MRCItem -litem &812 +*944 (MRCItem +litem &816 pos 8 dimension 20 uid 1456,0 ) -*940 (MRCItem -litem &813 +*945 (MRCItem +litem &817 pos 7 dimension 20 uid 1458,0 ) -*941 (MRCItem -litem &814 +*946 (MRCItem +litem &818 pos 9 dimension 20 uid 1695,0 ) -*942 (MRCItem -litem &815 +*947 (MRCItem +litem &819 pos 42 dimension 20 uid 1994,0 ) -*943 (MRCItem -litem &816 +*948 (MRCItem +litem &820 pos 43 dimension 20 uid 2306,0 ) -*944 (MRCItem -litem &817 +*949 (MRCItem +litem &821 pos 44 dimension 20 uid 2511,0 ) -*945 (MRCItem -litem &818 +*950 (MRCItem +litem &822 pos 45 dimension 20 uid 2513,0 ) -*946 (MRCItem -litem &819 +*951 (MRCItem +litem &823 pos 46 dimension 20 uid 2515,0 ) -*947 (MRCItem -litem &820 +*952 (MRCItem +litem &824 pos 47 dimension 20 uid 2517,0 ) -*948 (MRCItem -litem &821 +*953 (MRCItem +litem &825 pos 48 dimension 20 uid 2519,0 ) -*949 (MRCItem -litem &822 +*954 (MRCItem +litem &826 pos 49 dimension 20 uid 2521,0 ) -*950 (MRCItem -litem &823 +*955 (MRCItem +litem &827 pos 50 dimension 20 uid 2523,0 ) -*951 (MRCItem -litem &824 +*956 (MRCItem +litem &828 pos 51 dimension 20 uid 2605,0 ) -*952 (MRCItem -litem &825 +*957 (MRCItem +litem &829 pos 52 dimension 20 uid 2607,0 ) -*953 (MRCItem -litem &826 +*958 (MRCItem +litem &830 pos 53 dimension 20 uid 2609,0 ) -*954 (MRCItem -litem &827 +*959 (MRCItem +litem &831 pos 54 dimension 20 uid 2611,0 ) -*955 (MRCItem -litem &828 +*960 (MRCItem +litem &832 pos 55 dimension 20 uid 2613,0 ) -*956 (MRCItem -litem &829 +*961 (MRCItem +litem &833 pos 56 dimension 20 uid 2647,0 ) -*957 (MRCItem -litem &830 +*962 (MRCItem +litem &834 pos 10 dimension 20 uid 2813,0 ) -*958 (MRCItem -litem &831 +*963 (MRCItem +litem &835 pos 57 dimension 20 uid 2963,0 ) -*959 (MRCItem -litem &832 +*964 (MRCItem +litem &836 pos 11 dimension 20 uid 3903,0 ) -*960 (MRCItem -litem &833 +*965 (MRCItem +litem &837 pos 12 dimension 20 uid 4071,0 ) -*961 (MRCItem -litem &834 +*966 (MRCItem +litem &838 pos 58 dimension 20 uid 4213,0 ) -*962 (MRCItem -litem &835 +*967 (MRCItem +litem &839 pos 13 dimension 20 uid 4235,0 ) -*963 (MRCItem -litem &836 +*968 (MRCItem +litem &840 pos 14 dimension 20 uid 4263,0 ) -*964 (MRCItem -litem &837 +*969 (MRCItem +litem &841 pos 15 dimension 20 uid 4277,0 ) -*965 (MRCItem -litem &838 +*970 (MRCItem +litem &842 pos 59 dimension 20 uid 4564,0 ) -*966 (MRCItem -litem &839 +*971 (MRCItem +litem &843 pos 60 dimension 20 uid 4566,0 ) -*967 (MRCItem -litem &840 +*972 (MRCItem +litem &844 pos 61 dimension 20 uid 4570,0 ) -*968 (MRCItem -litem &841 +*973 (MRCItem +litem &845 pos 16 dimension 20 uid 4586,0 ) -*969 (MRCItem -litem &842 +*974 (MRCItem +litem &846 pos 17 dimension 20 uid 4588,0 ) -*970 (MRCItem -litem &843 +*975 (MRCItem +litem &847 pos 18 dimension 20 uid 4734,0 ) -*971 (MRCItem -litem &844 +*976 (MRCItem +litem &848 pos 19 dimension 20 uid 4736,0 ) -*972 (MRCItem -litem &845 +*977 (MRCItem +litem &849 pos 20 dimension 20 uid 4738,0 ) -*973 (MRCItem -litem &846 +*978 (MRCItem +litem &850 pos 21 dimension 20 uid 4740,0 ) -*974 (MRCItem -litem &847 +*979 (MRCItem +litem &851 pos 62 dimension 20 uid 4750,0 ) -*975 (MRCItem -litem &848 +*980 (MRCItem +litem &852 pos 22 dimension 20 uid 4975,0 ) -*976 (MRCItem -litem &849 +*981 (MRCItem +litem &853 pos 23 dimension 20 uid 4977,0 ) -*977 (MRCItem -litem &850 +*982 (MRCItem +litem &854 pos 63 dimension 20 uid 5199,0 ) -*978 (MRCItem -litem &851 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20 uid 5601,0 ) -*990 (MRCItem -litem &863 +*995 (MRCItem +litem &867 pos 75 dimension 20 uid 5643,0 ) -*991 (MRCItem -litem &864 +*996 (MRCItem +litem &868 pos 76 dimension 20 uid 5645,0 ) -*992 (MRCItem -litem &865 +*997 (MRCItem +litem &869 pos 77 dimension 20 uid 5752,0 ) -*993 (MRCItem -litem &866 +*998 (MRCItem +litem &870 pos 25 dimension 20 uid 5868,0 ) -*994 (MRCItem -litem &867 +*999 (MRCItem +litem &871 pos 26 dimension 20 uid 5870,0 ) -*995 (MRCItem -litem &868 +*1000 (MRCItem +litem &872 pos 27 dimension 20 uid 5872,0 ) -*996 (MRCItem -litem &869 +*1001 (MRCItem +litem &873 pos 28 dimension 20 uid 5874,0 ) -*997 (MRCItem -litem &870 +*1002 (MRCItem +litem &874 pos 78 dimension 20 uid 5967,0 ) -*998 (MRCItem -litem &871 +*1003 (MRCItem +litem &875 pos 79 dimension 20 uid 5969,0 ) -*999 (MRCItem -litem &872 +*1004 (MRCItem +litem &876 pos 80 dimension 20 uid 6023,0 ) -*1000 (MRCItem -litem &873 +*1005 (MRCItem +litem &877 pos 81 dimension 20 uid 6025,0 ) -*1001 (MRCItem -litem &874 +*1006 (MRCItem +litem &878 pos 82 dimension 20 uid 6027,0 ) -*1002 (MRCItem -litem &875 +*1007 (MRCItem +litem &879 pos 29 dimension 20 uid 6173,0 ) -*1003 (MRCItem -litem &876 +*1008 (MRCItem +litem &880 pos 30 dimension 20 uid 6375,0 ) -*1004 (MRCItem -litem &877 +*1009 (MRCItem +litem &881 pos 83 dimension 20 uid 6465,0 ) -*1005 (MRCItem -litem &878 +*1010 (MRCItem +litem &882 pos 84 dimension 20 uid 6555,0 ) -*1006 (MRCItem -litem &879 +*1011 (MRCItem +litem &883 pos 85 dimension 20 uid 8421,0 ) -*1007 (MRCItem -litem &880 +*1012 (MRCItem +litem &884 pos 86 dimension 20 uid 8759,0 ) -*1008 (MRCItem -litem &881 +*1013 (MRCItem +litem &885 pos 87 dimension 20 uid 8761,0 ) -*1009 (MRCItem -litem &882 +*1014 (MRCItem +litem &886 pos 31 dimension 20 uid 9019,0 ) -*1010 (MRCItem -litem &883 +*1015 (MRCItem +litem &887 pos 88 dimension 20 uid 9248,0 ) -*1011 (MRCItem -litem &884 +*1016 (MRCItem +litem &888 pos 89 dimension 20 uid 9250,0 ) -*1012 (MRCItem -litem &885 +*1017 (MRCItem +litem &889 pos 90 dimension 20 uid 10025,0 ) -*1013 (MRCItem -litem &886 +*1018 (MRCItem +litem &890 pos 91 dimension 20 uid 10027,0 ) -*1014 (MRCItem -litem &887 +*1019 (MRCItem +litem &891 pos 92 dimension 20 uid 10029,0 ) -*1015 (MRCItem -litem &888 +*1020 (MRCItem +litem &892 pos 93 dimension 20 uid 10209,0 ) -*1016 (MRCItem -litem &889 +*1021 (MRCItem +litem &893 pos 94 dimension 20 uid 10211,0 ) -*1017 (MRCItem -litem &890 +*1022 (MRCItem +litem &894 pos 95 dimension 20 uid 10295,0 ) -*1018 (MRCItem -litem &891 +*1023 (MRCItem +litem &895 pos 96 dimension 20 uid 10335,0 ) -*1019 (MRCItem -litem &892 +*1024 (MRCItem +litem &896 pos 97 dimension 20 uid 10337,0 ) -*1020 (MRCItem -litem &893 +*1025 (MRCItem +litem &897 pos 98 dimension 20 uid 10339,0 ) -*1021 (MRCItem -litem &894 +*1026 (MRCItem +litem &898 pos 99 dimension 20 uid 10341,0 ) -*1022 (MRCItem -litem &895 +*1027 (MRCItem +litem &899 pos 32 dimension 20 uid 10343,0 ) -*1023 (MRCItem -litem &896 +*1028 (MRCItem +litem &900 pos 100 dimension 20 uid 10476,0 ) -*1024 (MRCItem -litem &897 +*1029 (MRCItem +litem &901 pos 101 dimension 20 uid 10764,0 ) -*1025 (MRCItem -litem &898 +*1030 (MRCItem +litem &902 pos 102 dimension 20 uid 10766,0 ) -*1026 (MRCItem -litem &899 +*1031 (MRCItem +litem &903 pos 33 dimension 20 uid 10768,0 ) -*1027 (MRCItem -litem &900 +*1032 (MRCItem +litem &904 pos 34 dimension 20 uid 10770,0 ) -*1028 (MRCItem -litem &901 +*1033 (MRCItem +litem &905 pos 35 dimension 20 uid 10772,0 ) -*1029 (MRCItem -litem &902 +*1034 (MRCItem +litem &906 pos 103 dimension 20 uid 11412,0 ) -*1030 (MRCItem -litem &903 +*1035 (MRCItem +litem &907 pos 104 dimension 20 uid 11967,0 ) -*1031 (MRCItem -litem &904 +*1036 (MRCItem +litem &908 pos 105 dimension 20 uid 12311,0 ) -*1032 (MRCItem -litem &905 +*1037 (MRCItem +litem &909 pos 106 dimension 20 uid 12660,0 ) -*1033 (MRCItem -litem &906 +*1038 (MRCItem +litem &910 pos 107 dimension 20 uid 12662,0 ) -*1034 (MRCItem -litem &907 +*1039 (MRCItem +litem &911 pos 108 dimension 20 uid 12664,0 ) -*1035 (MRCItem -litem &908 +*1040 (MRCItem +litem &912 pos 36 dimension 20 uid 12720,0 ) -*1036 (MRCItem -litem &909 +*1041 (MRCItem +litem &913 pos 109 dimension 20 uid 13276,0 ) -*1037 (MRCItem -litem &910 +*1042 (MRCItem +litem &914 pos 110 dimension 20 uid 13278,0 ) -*1038 (MRCItem -litem &911 +*1043 (MRCItem +litem &915 pos 111 dimension 20 uid 13280,0 ) -*1039 (MRCItem -litem &912 +*1044 (MRCItem +litem &916 pos 112 dimension 20 uid 13282,0 ) -*1040 (MRCItem -litem &913 +*1045 (MRCItem +litem &917 pos 113 dimension 20 uid 13688,0 ) -*1041 (MRCItem -litem &914 +*1046 (MRCItem +litem &918 pos 114 dimension 20 uid 14041,0 ) -*1042 (MRCItem -litem &915 +*1047 (MRCItem +litem &919 pos 115 dimension 20 uid 14164,0 ) -*1043 (MRCItem -litem &916 +*1048 (MRCItem +litem &920 pos 116 dimension 20 uid 14508,0 ) -*1044 (MRCItem -litem &917 +*1049 (MRCItem +litem &921 pos 117 dimension 20 uid 14510,0 ) -*1045 (MRCItem -litem &918 +*1050 (MRCItem +litem &922 pos 118 dimension 20 uid 14635,0 ) -*1046 (MRCItem -litem &919 +*1051 (MRCItem +litem &923 pos 119 dimension 20 uid 15145,0 ) -*1047 (MRCItem -litem &920 +*1052 (MRCItem +litem &924 pos 120 dimension 20 uid 15147,0 ) -*1048 (MRCItem -litem &921 +*1053 (MRCItem +litem &925 pos 121 dimension 20 uid 15149,0 +) +*1054 (MRCItem +litem &926 +pos 122 +dimension 20 +uid 15505,0 ) ] @@ -26354,48 +26357,48 @@ uid 73,0 optionalChildren [ -*1049 (MRCItem -litem &791 +*1055 (MRCItem +litem &795 pos 0 dimension 20 uid 74,0 ) -*1050 (MRCItem -litem &793 +*1056 (MRCItem +litem &797 pos 1 dimension 50 uid 75,0 ) -*1051 (MRCItem -litem &794 +*1057 (MRCItem +litem &798 pos 2 dimension 100 uid 76,0 ) -*1052 (MRCItem -litem &795 +*1058 (MRCItem +litem &799 pos 3 dimension 50 uid 77,0 ) -*1053 (MRCItem -litem &796 +*1059 (MRCItem +litem &800 pos 4 dimension 100 uid 78,0 ) -*1054 (MRCItem -litem &797 +*1060 (MRCItem +litem &801 pos 5 dimension 100 uid 79,0 ) -*1055 (MRCItem -litem &798 +*1061 (MRCItem +litem &802 pos 6 dimension 50 uid 80,0 ) -*1056 (MRCItem -litem &799 +*1062 (MRCItem +litem &803 pos 7 dimension 290 @@ -26417,39 +26420,39 @@ genericsCommonDM (CommonDM ldm (LogicalDM -emptyRow *1057 (LEmptyRow +emptyRow *1063 (LEmptyRow ) uid 83,0 optionalChildren [ -*1058 (RefLabelRowHdr -) -*1059 (TitleRowHdr -) -*1060 (FilterRowHdr -) -*1061 (RefLabelColHdr +*1064 (RefLabelRowHdr +) +*1065 (TitleRowHdr +) +*1066 (FilterRowHdr +) +*1067 (RefLabelColHdr tm "RefLabelColHdrMgr" ) -*1062 (RowExpandColHdr +*1068 (RowExpandColHdr tm "RowExpandColHdrMgr" ) -*1063 (GroupColHdr +*1069 (GroupColHdr tm "GroupColHdrMgr" ) -*1064 (NameColHdr +*1070 (NameColHdr tm "GenericNameColHdrMgr" ) -*1065 (TypeColHdr +*1071 (TypeColHdr tm "GenericTypeColHdrMgr" ) -*1066 (InitColHdr +*1072 (InitColHdr tm "GenericValueColHdrMgr" ) -*1067 (PragmaColHdr +*1073 (PragmaColHdr tm "GenericPragmaColHdrMgr" ) -*1068 (EolColHdr +*1074 (EolColHdr tm "GenericEolColHdrMgr" ) -*1069 (LogGeneric +*1075 (LogGeneric generic (GiElement name "RAMADDRWIDTH64b" @@ -26466,5 +26469,5 @@ uid 95,0 optionalChildren [ -*1070 (Sheet +*1076 (Sheet sheetRow (SheetRow headerVa (MVa @@ -26483,6 +26486,6 @@ font "Tahoma,10,0" ) -emptyMRCItem *1071 (MRCItem -litem &1057 +emptyMRCItem *1077 (MRCItem +litem &1063 pos 1 dimension 20 @@ -26490,18 +26493,18 @@ uid 97,0 optionalChildren [ -*1072 (MRCItem -litem &1058 +*1078 (MRCItem +litem &1064 pos 0 dimension 20 uid 98,0 ) -*1073 (MRCItem -litem &1059 +*1079 (MRCItem +litem &1065 pos 1 dimension 23 uid 99,0 ) -*1074 (MRCItem -litem &1060 +*1080 (MRCItem +litem &1066 pos 2 hidden 1 @@ -26509,6 +26512,6 @@ uid 100,0 ) -*1075 (MRCItem -litem &1069 +*1081 (MRCItem +litem &1075 pos 0 dimension 20 @@ -26526,42 +26529,42 @@ uid 101,0 optionalChildren [ -*1076 (MRCItem -litem &1061 +*1082 (MRCItem +litem &1067 pos 0 dimension 20 uid 102,0 ) -*1077 (MRCItem -litem &1063 +*1083 (MRCItem +litem &1069 pos 1 dimension 50 uid 103,0 ) -*1078 (MRCItem -litem &1064 +*1084 (MRCItem +litem &1070 pos 2 dimension 186 uid 104,0 ) -*1079 (MRCItem -litem &1065 +*1085 (MRCItem +litem &1071 pos 3 dimension 96 uid 105,0 ) -*1080 (MRCItem -litem &1066 +*1086 (MRCItem +litem &1072 pos 4 dimension 50 uid 106,0 ) -*1081 (MRCItem -litem &1067 +*1087 (MRCItem +litem &1073 pos 5 dimension 50 uid 107,0 ) -*1082 (MRCItem -litem &1068 +*1088 (MRCItem +litem &1074 pos 6 dimension 80 Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/symbol.sb =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/symbol.sb (revision 10154) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_main/symbol.sb (revision 10155) @@ -1199,5 +1199,5 @@ (vvPair variable "date" -value "08.02.2011" +value "15.02.2011" ) (vvPair @@ -1211,5 +1211,5 @@ (vvPair variable "dd" -value "08" +value "15" ) (vvPair @@ -1351,5 +1351,5 @@ (vvPair variable "time" -value "11:06:22" +value "09:27:14" ) (vvPair @@ -4000,5 +4000,5 @@ ) ) -lastUid 5942,0 +lastUid 5988,0 okToSyncOnLoad 1 OkToSyncGenericsOnLoad 1 Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/_dna_gen._epf =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/_dna_gen._epf (revision 10155) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/_dna_gen._epf (revision 10155) @@ -0,0 +1,2 @@ +DEFAULT_FILE atom dna_gen.vhd +DEFAULT_ARCHITECTURE atom Behavioral Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/clock_generator_var_ps/struct.bd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/clock_generator_var_ps/struct.bd (revision 10154) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/clock_generator_var_ps/struct.bd (revision 10155) @@ -15,4 +15,8 @@ unitName "numeric_std" ) +(DmPackageRef +library "FACT_FAD_lib" +unitName "fad_definitions" +) ] instances [ @@ -57,4 +61,5 @@ "ieee" "UNISIM" +"FACT_FAD_lib" ] ) @@ -107,17 +112,17 @@ (vvPair variable "date" -value "04.02.2011" +value "12.02.2011" ) (vvPair variable "day" -value "Fr" +value "Sa" ) (vvPair variable "day_long" -value "Freitag" +value "Samstag" ) (vvPair variable "dd" -value "04" +value "12" ) (vvPair @@ -255,5 +260,5 @@ (vvPair variable "time" -value "12:52:25" +value "13:16:51" ) (vvPair @@ -761,5 +766,6 @@ ) xt "11000,-9200,24000,-8400" -st "CLK_50 : std_logic" +st "CLK_50 : std_logic +" ) ) @@ -778,5 +784,6 @@ ) xt "11000,-10800,24000,-10000" -st "CLK_25 : std_logic" +st "CLK_25 : std_logic +" ) ) @@ -795,5 +802,6 @@ ) xt "11000,-14000,24000,-13200" -st "CLK : std_logic" +st "CLK : std_logic +" ) ) @@ -1563,5 +1571,6 @@ ) xt "11000,-6600,27500,-5800" -st "SIGNAL CLK0_OUT : std_logic" +st "SIGNAL CLK0_OUT : std_logic +" ) ) @@ -1580,5 +1589,6 @@ ) xt "11000,-5000,27500,-4200" -st "SIGNAL PSCLK_IN : std_logic" +st "SIGNAL PSCLK_IN : std_logic +" ) ) @@ -1597,5 +1607,6 @@ ) xt "11000,-3400,27500,-2600" -st "SIGNAL PSEN_IN : std_logic" +st "SIGNAL PSEN_IN : std_logic +" ) ) @@ -1614,5 +1625,6 @@ ) xt "11000,-2600,27500,-1800" -st "SIGNAL PSINCDEC_IN : std_logic" +st "SIGNAL PSINCDEC_IN : std_logic +" ) ) @@ -1631,5 +1643,6 @@ ) xt "11000,-4200,27500,-3400" -st "SIGNAL PSDONE_OUT : std_logic" +st "SIGNAL PSDONE_OUT : std_logic +" ) ) @@ -1648,5 +1661,6 @@ ) xt "11000,-5800,27500,-5000" -st "SIGNAL LOCKED_OUT : std_logic" +st "SIGNAL LOCKED_OUT : std_logic +" ) ) @@ -1874,4 +1888,5 @@ n "LOCKED" t "std_logic" +eolc "-- when is this going high?" preAdd 0 posAdd 0 @@ -1989,5 +2004,5 @@ preAdd 0 posAdd 0 -o 10 +o 11 suid 10,0 i "'0'" @@ -2028,5 +2043,5 @@ preAdd 0 posAdd 0 -o 11 +o 12 suid 11,0 i "'0'" @@ -2068,5 +2083,5 @@ preAdd 0 posAdd 0 -o 12 +o 13 suid 12,0 i "(OTHERS => '0')" @@ -2075,47 +2090,8 @@ ) *62 (CptPort -uid 815,0 -ps "OnEdgeStrategy" -shape (Triangle -uid 816,0 -ro 90 -va (VaSet -vasetType 1 -fg "0,65535,0" -) -xt "64000,32625,64750,33375" -) -tg (CPTG -uid 817,0 -ps "CptPortTextPlaceStrategy" -stg "RightVerticalLayoutStrategy" -f (Text -uid 818,0 -va (VaSet -) -xt "57800,32500,63000,33500" -st "DCM_locked" -ju 2 -blo "63000,33300" -) -) -thePort (LogicalPort -m 1 -decl (Decl -n "DCM_locked" -t "std_logic" -preAdd 0 -posAdd 0 -o 13 -suid 13,0 -) -) -) -*63 (CptPort uid 1621,0 ps "OnEdgeStrategy" shape (Triangle -uid 1622,0 -ro 90 +ro 270 va (VaSet vasetType 1 @@ -2138,4 +2114,5 @@ ) thePort (LogicalPort +m 1 decl (Decl n "rst" @@ -2145,4 +2122,41 @@ o 2 suid 15,0 +i "'0'" +) +) +) +*63 (CptPort +uid 1975,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1976,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "37250,41625,38000,42375" +) +tg (CPTG +uid 1977,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1978,0 +va (VaSet +) +xt "39000,41500,43400,42500" +st "reset_DCM" +blo "39000,42300" +) +) +thePort (LogicalPort +decl (Decl +n "reset_DCM" +t "std_logic" +eolc "-- asynch in: orders us, to reset the DCM" +posAdd 0 +o 10 +suid 17,0 ) ) @@ -2157,5 +2171,5 @@ lineWidth 2 ) -xt "38000,28000,64000,43000" +xt "38000,28000,64000,44000" ) oxt "50000,7000,63000,25000" @@ -2221,5 +2235,5 @@ fg "49152,49152,49152" ) -xt "38250,41250,39750,42750" +xt "38250,42250,39750,43750" iconName "VhdlFileViewIcon.png" iconMaskName "VhdlFileViewIcon.msk" @@ -2291,5 +2305,6 @@ ) xt "11000,-10000,24000,-9200" -st "CLK_25_PS : std_logic" +st "CLK_25_PS : std_logic +" ) ) @@ -2354,5 +2369,6 @@ ) xt "11000,-11600,24000,-10800" -st "do_shift : std_logic" +st "do_shift : std_logic +" ) ) @@ -2417,5 +2433,6 @@ ) xt "11000,-12400,24000,-11600" -st "direction : std_logic" +st "direction : std_logic +" ) ) @@ -2434,5 +2451,6 @@ ) xt "11000,-13200,24000,-12400" -st "RST_IN : std_logic" +st "RST_IN : std_logic +" ) ) @@ -2450,5 +2468,5 @@ sl 0 ro 270 -xt "6000,35625,7500,36375" +xt "28000,42625,29500,43375" ) (Line @@ -2456,8 +2474,8 @@ sl 0 ro 270 -xt "7500,36000,8000,36000" +xt "29500,43000,30000,43000" pts [ -"7500,36000" -"8000,36000" +"29500,43000" +"30000,43000" ] ) @@ -2475,8 +2493,8 @@ font "arial,8,0" ) -xt "1800,35500,5000,36500" +xt "23800,42500,27000,43500" st "RST_IN" ju 2 -blo "5000,36300" +blo "27000,43300" tm "WireNameMgr" ) @@ -2501,5 +2519,6 @@ ) xt "11000,-8400,43500,-7600" -st "offset : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" +st "offset : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') +" ) ) @@ -2549,5 +2568,26 @@ ) ) -*77 (Wire +*77 (Net +uid 1979,0 +decl (Decl +n "rst" +t "std_logic" +eolc "--asynch in of DCM" +posAdd 0 +o 15 +suid 40,0 +i "'0'" +) +declText (MLText +uid 1980,0 +va (VaSet +font "Courier New,8,0" +) +xt "11000,-1800,50500,-1000" +st "SIGNAL rst : std_logic := '0' --asynch in of DCM +" +) +) +*78 (Wire uid 163,0 shape (OrthoPolyLine @@ -2588,5 +2628,5 @@ on &17 ) -*78 (Wire +*79 (Wire uid 191,0 shape (OrthoPolyLine @@ -2627,8 +2667,8 @@ on &15 ) -*79 (Wire +*80 (Wire uid 209,0 optionalChildren [ -*80 (BdJunction +*81 (BdJunction uid 233,0 ps "OnConnectorStrategy" @@ -2680,5 +2720,5 @@ on &16 ) -*81 (Wire +*82 (Wire uid 229,0 shape (OrthoPolyLine @@ -2694,5 +2734,5 @@ ] ) -start &80 +start &81 end &19 sat 32 @@ -2719,5 +2759,5 @@ on &16 ) -*82 (Wire +*83 (Wire uid 526,0 shape (OrthoPolyLine @@ -2760,5 +2800,5 @@ on &44 ) -*83 (Wire +*84 (Wire uid 532,0 shape (OrthoPolyLine @@ -2803,5 +2843,5 @@ on &45 ) -*84 (Wire +*85 (Wire uid 546,0 shape (OrthoPolyLine @@ -2846,5 +2886,5 @@ on &46 ) -*85 (Wire +*86 (Wire uid 588,0 shape (OrthoPolyLine @@ -2885,5 +2925,5 @@ on &48 ) -*86 (Wire +*87 (Wire uid 602,0 shape (OrthoPolyLine @@ -2924,5 +2964,5 @@ on &49 ) -*87 (Wire +*88 (Wire uid 841,0 shape (OrthoPolyLine @@ -2967,5 +3007,5 @@ on &47 ) -*88 (Wire +*89 (Wire uid 1254,0 shape (OrthoPolyLine @@ -3006,5 +3046,5 @@ on &68 ) -*89 (Wire +*90 (Wire uid 1272,0 shape (OrthoPolyLine @@ -3045,5 +3085,5 @@ on &70 ) -*90 (Wire +*91 (Wire uid 1286,0 shape (OrthoPolyLine @@ -3084,5 +3124,5 @@ on &72 ) -*91 (Wire +*92 (Wire uid 1458,0 shape (OrthoPolyLine @@ -3121,20 +3161,6 @@ on &44 ) -*92 (Wire +*93 (Wire uid 1493,0 -optionalChildren [ -*93 (BdJunction -uid 1629,0 -ps "OnConnectorStrategy" -shape (Circle -uid 1630,0 -va (VaSet -vasetType 1 -) -xt "9600,35600,10400,36400" -radius 400 -) -) -] shape (OrthoPolyLine uid 1494,0 @@ -3142,12 +3168,13 @@ vasetType 3 ) -xt "8000,36000,13250,36000" +xt "30000,42000,37250,43000" pts [ -"8000,36000" -"13250,36000" +"30000,43000" +"37250,42000" ] ) start &74 -end &40 +end &63 +es 0 sat 32 eat 32 @@ -3166,7 +3193,7 @@ font "arial,8,0" ) -xt "9000,35000,12200,36000" +xt "31000,42000,34200,43000" st "RST_IN" -blo "9000,35800" +blo "31000,42800" tm "WireNameMgr" ) @@ -3216,41 +3243,41 @@ ) *95 (Wire -uid 1625,0 +uid 1981,0 shape (OrthoPolyLine -uid 1626,0 +uid 1982,0 va (VaSet vasetType 3 ) -xt "10000,36000,37250,41000" +xt "8000,36000,37250,41000" pts [ "37250,41000" -"10000,41000" -"10000,36000" -] -) -start &63 -end &93 +"8000,41000" +"8000,36000" +"13250,36000" +] +) +start &62 +end &40 sat 32 eat 32 -stc 0 st 0 sf 1 si 0 tg (WTG -uid 1627,0 +uid 1983,0 ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text -uid 1628,0 -va (VaSet -font "arial,8,0" -) -xt "33250,40000,36450,41000" -st "RST_IN" -blo "33250,40800" +uid 1984,0 +va (VaSet +font "arial,8,0" +) +xt "35250,40000,36550,41000" +st "rst" +blo "35250,40800" tm "WireNameMgr" ) ) -on &73 +on &77 ) ] @@ -3284,5 +3311,5 @@ font "arial,8,0" ) -xt "0,1000,12300,7000" +xt "0,1000,14500,9000" st "LIBRARY ieee; USE ieee.std_logic_1164.all; @@ -3290,5 +3317,7 @@ USE ieee.numeric_std.all; LIBRARY UNISIM; ---USE UNISIM.Vcomponents.all;" +--USE UNISIM.Vcomponents.all; +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all;" tm "PackageList" ) @@ -3372,5 +3401,5 @@ ) windowSize "0,0,1281,1024" -viewArea "-5415,-5866,75221,60634" +viewArea "-5400,-10460,75236,56040" cachedDiagramExtent "0,-16000,73000,46000" pageSetupInfo (PageSetupInfo @@ -3384,6 +3413,6 @@ ) hasePageBreakOrigin 1 -pageBreakOrigin "0,0" -lastUid 1655,0 +pageBreakOrigin "0,-49000" +lastUid 1986,0 defaultCommentText (CommentText shape (Rectangle @@ -4415,5 +4444,5 @@ commonDM (CommonDM ldm (LogicalDM -suid 39,0 +suid 40,0 usingSuid 1 emptyRow *127 (LEmptyRow @@ -4625,4 +4654,19 @@ uid 1631,0 ) +*154 (LeafLogPort +port (LogicalPort +m 4 +decl (Decl +n "rst" +t "std_logic" +eolc "--asynch in of DCM" +posAdd 0 +o 15 +suid 40,0 +i "'0'" +) +) +uid 1985,0 +) ] ) @@ -4632,5 +4676,5 @@ uid 67,0 optionalChildren [ -*154 (Sheet +*155 (Sheet sheetRow (SheetRow headerVa (MVa @@ -4649,12 +4693,12 @@ font "Tahoma,10,0" ) -emptyMRCItem *155 (MRCItem +emptyMRCItem *156 (MRCItem litem &127 -pos 14 +pos 15 dimension 20 ) uid 69,0 optionalChildren [ -*156 (MRCItem +*157 (MRCItem litem &128 pos 0 @@ -4662,5 +4706,5 @@ uid 70,0 ) -*157 (MRCItem +*158 (MRCItem litem &129 pos 1 @@ -4668,5 +4712,5 @@ uid 71,0 ) -*158 (MRCItem +*159 (MRCItem litem &130 pos 2 @@ -4675,5 +4719,5 @@ uid 72,0 ) -*159 (MRCItem +*160 (MRCItem litem &140 pos 0 @@ -4681,5 +4725,5 @@ uid 238,0 ) -*160 (MRCItem +*161 (MRCItem litem &141 pos 1 @@ -4687,5 +4731,5 @@ uid 240,0 ) -*161 (MRCItem +*162 (MRCItem litem &142 pos 2 @@ -4693,5 +4737,5 @@ uid 296,0 ) -*162 (MRCItem +*163 (MRCItem litem &143 pos 8 @@ -4699,5 +4743,5 @@ uid 615,0 ) -*163 (MRCItem +*164 (MRCItem litem &144 pos 3 @@ -4705,5 +4749,5 @@ uid 617,0 ) -*164 (MRCItem +*165 (MRCItem litem &145 pos 4 @@ -4711,5 +4755,5 @@ uid 619,0 ) -*165 (MRCItem +*166 (MRCItem litem &146 pos 5 @@ -4717,5 +4761,5 @@ uid 621,0 ) -*166 (MRCItem +*167 (MRCItem litem &147 pos 6 @@ -4723,5 +4767,5 @@ uid 625,0 ) -*167 (MRCItem +*168 (MRCItem litem &148 pos 7 @@ -4729,5 +4773,5 @@ uid 627,0 ) -*168 (MRCItem +*169 (MRCItem litem &149 pos 9 @@ -4735,5 +4779,5 @@ uid 1247,0 ) -*169 (MRCItem +*170 (MRCItem litem &150 pos 10 @@ -4741,5 +4785,5 @@ uid 1263,0 ) -*170 (MRCItem +*171 (MRCItem litem &151 pos 11 @@ -4747,5 +4791,5 @@ uid 1265,0 ) -*171 (MRCItem +*172 (MRCItem litem &152 pos 12 @@ -4753,9 +4797,15 @@ uid 1506,0 ) -*172 (MRCItem +*173 (MRCItem litem &153 pos 13 dimension 20 uid 1632,0 +) +*174 (MRCItem +litem &154 +pos 14 +dimension 20 +uid 1986,0 ) ] @@ -4770,5 +4820,5 @@ uid 73,0 optionalChildren [ -*173 (MRCItem +*175 (MRCItem litem &131 pos 0 @@ -4776,5 +4826,5 @@ uid 74,0 ) -*174 (MRCItem +*176 (MRCItem litem &133 pos 1 @@ -4782,5 +4832,5 @@ uid 75,0 ) -*175 (MRCItem +*177 (MRCItem litem &134 pos 2 @@ -4788,5 +4838,5 @@ uid 76,0 ) -*176 (MRCItem +*178 (MRCItem litem &135 pos 3 @@ -4794,5 +4844,5 @@ uid 77,0 ) -*177 (MRCItem +*179 (MRCItem litem &136 pos 4 @@ -4800,5 +4850,5 @@ uid 78,0 ) -*178 (MRCItem +*180 (MRCItem litem &137 pos 5 @@ -4806,5 +4856,5 @@ uid 79,0 ) -*179 (MRCItem +*181 (MRCItem litem &138 pos 6 @@ -4812,5 +4862,5 @@ uid 80,0 ) -*180 (MRCItem +*182 (MRCItem litem &139 pos 7 @@ -4833,36 +4883,36 @@ genericsCommonDM (CommonDM ldm (LogicalDM -emptyRow *181 (LEmptyRow +emptyRow *183 (LEmptyRow ) uid 83,0 optionalChildren [ -*182 (RefLabelRowHdr -) -*183 (TitleRowHdr -) -*184 (FilterRowHdr -) -*185 (RefLabelColHdr +*184 (RefLabelRowHdr +) +*185 (TitleRowHdr +) +*186 (FilterRowHdr +) +*187 (RefLabelColHdr tm "RefLabelColHdrMgr" ) -*186 (RowExpandColHdr +*188 (RowExpandColHdr tm "RowExpandColHdrMgr" ) -*187 (GroupColHdr +*189 (GroupColHdr tm "GroupColHdrMgr" ) -*188 (NameColHdr +*190 (NameColHdr tm "GenericNameColHdrMgr" ) -*189 (TypeColHdr +*191 (TypeColHdr tm "GenericTypeColHdrMgr" ) -*190 (InitColHdr +*192 (InitColHdr tm "GenericValueColHdrMgr" ) -*191 (PragmaColHdr +*193 (PragmaColHdr tm "GenericPragmaColHdrMgr" ) -*192 (EolColHdr +*194 (EolColHdr tm "GenericEolColHdrMgr" ) @@ -4874,5 +4924,5 @@ uid 95,0 optionalChildren [ -*193 (Sheet +*195 (Sheet sheetRow (SheetRow headerVa (MVa @@ -4891,6 +4941,6 @@ font "Tahoma,10,0" ) -emptyMRCItem *194 (MRCItem -litem &181 +emptyMRCItem *196 (MRCItem +litem &183 pos 0 dimension 20 @@ -4898,18 +4948,18 @@ uid 97,0 optionalChildren [ -*195 (MRCItem -litem &182 +*197 (MRCItem +litem &184 pos 0 dimension 20 uid 98,0 ) -*196 (MRCItem -litem &183 +*198 (MRCItem +litem &185 pos 1 dimension 23 uid 99,0 ) -*197 (MRCItem -litem &184 +*199 (MRCItem +litem &186 pos 2 hidden 1 @@ -4928,42 +4978,42 @@ uid 101,0 optionalChildren [ -*198 (MRCItem -litem &185 +*200 (MRCItem +litem &187 pos 0 dimension 20 uid 102,0 ) -*199 (MRCItem -litem &187 +*201 (MRCItem +litem &189 pos 1 dimension 50 uid 103,0 ) -*200 (MRCItem -litem &188 +*202 (MRCItem +litem &190 pos 2 dimension 100 uid 104,0 ) -*201 (MRCItem -litem &189 +*203 (MRCItem +litem &191 pos 3 dimension 100 uid 105,0 ) -*202 (MRCItem -litem &190 +*204 (MRCItem +litem &192 pos 4 dimension 50 uid 106,0 ) -*203 (MRCItem -litem &191 +*205 (MRCItem +litem &193 pos 5 dimension 50 uid 107,0 ) -*204 (MRCItem -litem &192 +*206 (MRCItem +litem &194 pos 6 dimension 80 Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/clock_generator_var_ps/struct.bd.bak =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/clock_generator_var_ps/struct.bd.bak (revision 10154) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/clock_generator_var_ps/struct.bd.bak (revision 10155) @@ -15,4 +15,8 @@ unitName "numeric_std" ) +(DmPackageRef +library "FACT_FAD_lib" +unitName "fad_definitions" +) ] instances [ @@ -57,4 +61,5 @@ "ieee" "UNISIM" +"FACT_FAD_lib" ] ) @@ -107,17 +112,17 @@ (vvPair variable "date" -value "04.02.2011" +value "12.02.2011" ) (vvPair variable "day" -value "Fr" +value "Sa" ) (vvPair variable "day_long" -value "Freitag" +value "Samstag" ) (vvPair variable "dd" -value "04" +value "12" ) (vvPair @@ -255,5 +260,5 @@ (vvPair variable "time" -value "12:51:51" +value "13:14:23" ) (vvPair @@ -760,6 +765,7 @@ font "Courier New,8,0" ) -xt "22000,6800,35000,7600" -st "CLK_50 : std_logic" +xt "11000,-9200,24000,-8400" +st "CLK_50 : std_logic +" ) ) @@ -777,6 +783,7 @@ font "Courier New,8,0" ) -xt "22000,5200,35000,6000" -st "CLK_25 : std_logic" +xt "11000,-10800,24000,-10000" +st "CLK_25 : std_logic +" ) ) @@ -794,6 +801,7 @@ font "Courier New,8,0" ) -xt "22000,2000,35000,2800" -st "CLK : std_logic" +xt "11000,-14000,24000,-13200" +st "CLK : std_logic +" ) ) @@ -1562,6 +1570,7 @@ font "Courier New,8,0" ) -xt "22000,9400,38500,10200" -st "SIGNAL CLK0_OUT : std_logic" +xt "11000,-6600,27500,-5800" +st "SIGNAL CLK0_OUT : std_logic +" ) ) @@ -1579,6 +1588,7 @@ font "Courier New,8,0" ) -xt "22000,11000,38500,11800" -st "SIGNAL PSCLK_IN : std_logic" +xt "11000,-5000,27500,-4200" +st "SIGNAL PSCLK_IN : std_logic +" ) ) @@ -1596,6 +1606,7 @@ font "Courier New,8,0" ) -xt "22000,12600,38500,13400" -st "SIGNAL PSEN_IN : std_logic" +xt "11000,-3400,27500,-2600" +st "SIGNAL PSEN_IN : std_logic +" ) ) @@ -1613,6 +1624,7 @@ font "Courier New,8,0" ) -xt "22000,13400,38500,14200" -st "SIGNAL PSINCDEC_IN : std_logic" +xt "11000,-2600,27500,-1800" +st "SIGNAL PSINCDEC_IN : std_logic +" ) ) @@ -1630,6 +1642,7 @@ font "Courier New,8,0" ) -xt "22000,11800,38500,12600" -st "SIGNAL PSDONE_OUT : std_logic" +xt "11000,-4200,27500,-3400" +st "SIGNAL PSDONE_OUT : std_logic +" ) ) @@ -1647,6 +1660,7 @@ font "Courier New,8,0" ) -xt "22000,10200,38500,11000" -st "SIGNAL LOCKED_OUT : std_logic" +xt "11000,-5800,27500,-5000" +st "SIGNAL LOCKED_OUT : std_logic +" ) ) @@ -2290,6 +2304,7 @@ font "Courier New,8,0" ) -xt "22000,6000,35000,6800" -st "CLK_25_PS : std_logic" +xt "11000,-10000,24000,-9200" +st "CLK_25_PS : std_logic +" ) ) @@ -2353,6 +2368,7 @@ font "Courier New,8,0" ) -xt "22000,4400,35000,5200" -st "do_shift : std_logic" +xt "11000,-11600,24000,-10800" +st "do_shift : std_logic +" ) ) @@ -2416,6 +2432,7 @@ font "Courier New,8,0" ) -xt "22000,3600,35000,4400" -st "direction : std_logic" +xt "11000,-12400,24000,-11600" +st "direction : std_logic +" ) ) @@ -2433,6 +2450,7 @@ font "Courier New,8,0" ) -xt "22000,2800,35000,3600" -st "RST_IN : std_logic" +xt "11000,-13200,24000,-12400" +st "RST_IN : std_logic +" ) ) @@ -2500,6 +2518,7 @@ font "Courier New,8,0" ) -xt "22000,7600,54500,8400" -st "offset : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" +xt "11000,-8400,43500,-7600" +st "offset : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0') +" ) ) @@ -3284,5 +3303,5 @@ font "arial,8,0" ) -xt "0,1000,12300,7000" +xt "0,1000,14500,9000" st "LIBRARY ieee; USE ieee.std_logic_1164.all; @@ -3290,5 +3309,7 @@ USE ieee.numeric_std.all; LIBRARY UNISIM; ---USE UNISIM.Vcomponents.all;" +--USE UNISIM.Vcomponents.all; +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all;" tm "PackageList" ) @@ -3372,6 +3393,6 @@ ) windowSize "0,0,1281,1024" -viewArea "-28103,-9825,97891,94082" -cachedDiagramExtent "0,0,73000,46000" +viewArea "-5400,-10460,75236,56040" +cachedDiagramExtent "0,-16000,73000,46000" pageSetupInfo (PageSetupInfo ptrCmd "" @@ -3384,6 +3405,6 @@ ) hasePageBreakOrigin 1 -pageBreakOrigin "0,0" -lastUid 1655,0 +pageBreakOrigin "0,-49000" +lastUid 1830,0 defaultCommentText (CommentText shape (Rectangle @@ -4352,7 +4373,7 @@ font "arial,8,1" ) -xt "20000,0,25400,1000" +xt "9000,-16000,14400,-15000" st "Declarations" -blo "20000,800" +blo "9000,-15200" ) portLabel (Text @@ -4361,7 +4382,7 @@ font "arial,8,1" ) -xt "20000,1000,22700,2000" +xt "9000,-15000,11700,-14000" st "Ports:" -blo "20000,1800" +blo "9000,-14200" ) preUserLabel (Text @@ -4371,7 +4392,7 @@ font "arial,8,1" ) -xt "20000,0,23800,1000" +xt "9000,-16000,12800,-15000" st "Pre User:" -blo "20000,800" +blo "9000,-15200" ) preUserText (MLText @@ -4381,5 +4402,5 @@ font "Courier New,8,0" ) -xt "20000,0,20000,0" +xt "9000,-16000,9000,-16000" tm "BdDeclarativeTextMgr" ) @@ -4389,7 +4410,7 @@ font "arial,8,1" ) -xt "20000,8400,27100,9400" +xt "9000,-7600,16100,-6600" st "Diagram Signals:" -blo "20000,9200" +blo "9000,-6800" ) postUserLabel (Text @@ -4399,7 +4420,7 @@ font "arial,8,1" ) -xt "20000,0,24700,1000" +xt "9000,-16000,13700,-15000" st "Post User:" -blo "20000,800" +blo "9000,-15200" ) postUserText (MLText @@ -4409,5 +4430,5 @@ font "Courier New,8,0" ) -xt "20000,0,20000,0" +xt "9000,-16000,9000,-16000" tm "BdDeclarativeTextMgr" ) Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/clock_generator_var_ps/symbol.sb =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/clock_generator_var_ps/symbol.sb (revision 10154) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/clock_generator_var_ps/symbol.sb (revision 10155) @@ -523,17 +523,17 @@ (vvPair variable "date" -value "04.02.2011" +value "12.02.2011" ) (vvPair variable "day" -value "Fr" +value "Sa" ) (vvPair variable "day_long" -value "Freitag" +value "Samstag" ) (vvPair variable "dd" -value "04" +value "12" ) (vvPair @@ -671,5 +671,5 @@ (vvPair variable "time" -value "12:52:25" +value "13:16:51" ) (vvPair @@ -1752,5 +1752,5 @@ ) ) -lastUid 1044,0 +lastUid 1113,0 okToSyncOnLoad 1 OkToSyncGenericsOnLoad 1 Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/data_generator/symbol.sb =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/data_generator/symbol.sb (revision 10154) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/data_generator/symbol.sb (revision 10155) @@ -29,10 +29,10 @@ ) version "24.1" -appVersion "2009.1 (Build 12)" +appVersion "2009.2 (Build 10)" model (Symbol commonDM (CommonDM ldm (LogicalDM ordering 1 -suid 63,0 +suid 75,0 usingSuid 1 emptyRow *1 (LEmptyRow @@ -153,7 +153,10 @@ t "std_logic_vector" b "(3 downto 0)" +prec "-- + +-- EVT HEADER - part 4" preAdd 0 posAdd 0 -o 24 +o 31 suid 9,0 ) @@ -164,29 +167,16 @@ port (LogicalPort decl (Decl -n "trigger_id" -t "std_logic_vector" -b "(47 downto 0)" +n "trigger" +t "std_logic" +prec "--" preAdd 0 posAdd 0 -o 26 -suid 10,0 -) -) -uid 127,0 +o 38 +suid 11,0 +) +) +uid 129,0 ) *21 (LogPort -port (LogicalPort -decl (Decl -n "trigger" -t "std_logic" -preAdd 0 -posAdd 0 -o 27 -suid 11,0 -) -) -uid 129,0 -) -*22 (LogPort port (LogicalPort decl (Decl @@ -194,5 +184,6 @@ t "std_logic_vector" b "(1 downto 0)" -o 25 +posAdd 0 +o 32 suid 12,0 ) @@ -200,5 +191,5 @@ uid 290,0 ) -*23 (LogPort +*22 (LogPort port (LogicalPort decl (Decl @@ -211,5 +202,5 @@ uid 421,0 ) -*24 (LogPort +*23 (LogPort port (LogicalPort m 1 @@ -225,5 +216,5 @@ uid 423,0 ) -*25 (LogPort +*24 (LogPort port (LogicalPort decl (Decl @@ -236,5 +227,5 @@ uid 425,0 ) -*26 (LogPort +*25 (LogPort port (LogicalPort decl (Decl @@ -247,5 +238,5 @@ uid 478,0 ) -*27 (LogPort +*26 (LogPort port (LogicalPort decl (Decl @@ -253,4 +244,6 @@ t "std_logic_vector" b "(15 downto 0)" +prec "-- EVT HEADER - part 1" +preAdd 0 o 23 suid 20,0 @@ -259,5 +252,5 @@ uid 531,0 ) -*28 (LogPort +*27 (LogPort port (LogicalPort m 1 @@ -265,5 +258,5 @@ n "adc_oeb" t "std_logic" -o 31 +o 42 suid 23,0 i "'1'" @@ -272,5 +265,5 @@ uid 649,0 ) -*29 (LogPort +*28 (LogPort port (LogicalPort m 1 @@ -280,5 +273,5 @@ b "(3 downto 0)" posAdd 0 -o 34 +o 45 suid 25,0 i "(others => '0')" @@ -287,5 +280,5 @@ uid 701,0 ) -*30 (LogPort +*29 (LogPort port (LogicalPort m 1 @@ -296,5 +289,5 @@ preAdd 0 posAdd 0 -o 37 +o 48 suid 26,0 i "'0'" @@ -303,5 +296,5 @@ uid 703,0 ) -*31 (LogPort +*30 (LogPort port (LogicalPort m 1 @@ -311,5 +304,5 @@ prec "-- --" preAdd 0 -o 38 +o 49 suid 33,0 i "'0'" @@ -318,21 +311,21 @@ uid 816,0 ) +*31 (LogPort +port (LogicalPort +decl (Decl +n "drs_read_s_cell_ready" +t "std_logic" +o 54 +suid 34,0 +) +) +uid 818,0 +) *32 (LogPort -port (LogicalPort -decl (Decl -n "drs_read_s_cell_ready" -t "std_logic" -o 43 -suid 34,0 -) -) -uid 818,0 -) -*33 (LogPort port (LogicalPort decl (Decl n "drs_s_cell_array" t "drs_s_cell_array_type" -o 44 +o 55 suid 35,0 ) @@ -340,10 +333,10 @@ uid 820,0 ) -*34 (LogPort +*33 (LogPort port (LogicalPort decl (Decl n "adc_data_array" t "adc_data_array_type" -o 30 +o 41 suid 37,0 ) @@ -351,5 +344,5 @@ uid 903,0 ) -*35 (LogPort +*34 (LogPort port (LogicalPort decl (Decl @@ -362,5 +355,5 @@ uid 968,0 ) -*36 (LogPort +*35 (LogPort port (LogicalPort m 1 @@ -378,5 +371,5 @@ uid 970,0 ) -*37 (LogPort +*36 (LogPort port (LogicalPort decl (Decl @@ -389,5 +382,5 @@ uid 1058,0 ) -*38 (LogPort +*37 (LogPort port (LogicalPort decl (Decl @@ -400,5 +393,5 @@ uid 1060,0 ) -*39 (LogPort +*38 (LogPort port (LogicalPort decl (Decl @@ -411,5 +404,5 @@ uid 1095,0 ) -*40 (LogPort +*39 (LogPort port (LogicalPort decl (Decl @@ -422,5 +415,5 @@ uid 1097,0 ) -*41 (LogPort +*40 (LogPort port (LogicalPort m 1 @@ -438,5 +431,5 @@ uid 1132,0 ) -*42 (LogPort +*41 (LogPort port (LogicalPort m 1 @@ -453,5 +446,5 @@ uid 1134,0 ) -*43 (LogPort +*42 (LogPort port (LogicalPort m 1 @@ -459,5 +452,5 @@ n "config_started" t "std_logic" -o 29 +o 40 suid 48,0 i "'0'" @@ -466,5 +459,5 @@ uid 1169,0 ) -*44 (LogPort +*43 (LogPort port (LogicalPort decl (Decl @@ -473,5 +466,5 @@ prec "-- s_trigger : in std_logic;" preAdd 0 -o 28 +o 39 suid 49,0 ) @@ -479,5 +472,5 @@ uid 1171,0 ) -*45 (LogPort +*44 (LogPort port (LogicalPort decl (Decl @@ -490,5 +483,5 @@ uid 1211,0 ) -*46 (LogPort +*45 (LogPort port (LogicalPort decl (Decl @@ -501,5 +494,5 @@ uid 1213,0 ) -*47 (LogPort +*46 (LogPort port (LogicalPort decl (Decl @@ -512,9 +505,10 @@ uid 1215,0 ) -*48 (LogPort +*47 (LogPort port (LogicalPort decl (Decl n "dac_array" t "dac_array_type" +posAdd 0 o 22 suid 53,0 @@ -523,5 +517,5 @@ uid 1245,0 ) -*49 (LogPort +*48 (LogPort port (LogicalPort m 1 @@ -529,5 +523,5 @@ n "adc_clk_en" t "std_logic" -o 32 +o 43 suid 54,0 i "'0'" @@ -536,5 +530,5 @@ uid 1400,0 ) -*50 (LogPort +*49 (LogPort port (LogicalPort decl (Decl @@ -542,5 +536,5 @@ t "std_logic_vector" b "(3 downto 0)" -o 33 +o 44 suid 55,0 ) @@ -548,5 +542,5 @@ uid 1432,0 ) -*51 (LogPort +*50 (LogPort port (LogicalPort m 1 @@ -555,5 +549,5 @@ t "std_logic_vector" b "(7 downto 0)" -o 41 +o 52 suid 56,0 i "(others => '0')" @@ -562,5 +556,5 @@ uid 1484,0 ) -*52 (LogPort +*51 (LogPort port (LogicalPort m 1 @@ -568,5 +562,5 @@ n "drs_srin_write_8b" t "std_logic" -o 39 +o 50 suid 57,0 i "'0'" @@ -575,27 +569,27 @@ uid 1486,0 ) +*52 (LogPort +port (LogicalPort +decl (Decl +n "drs_srin_write_ack" +t "std_logic" +o 51 +suid 58,0 +) +) +uid 1488,0 +) *53 (LogPort port (LogicalPort decl (Decl -n "drs_srin_write_ack" -t "std_logic" -o 40 -suid 58,0 -) -) -uid 1488,0 +n "drs_srin_write_ready" +t "std_logic" +o 53 +suid 59,0 +) +) +uid 1490,0 ) *54 (LogPort -port (LogicalPort -decl (Decl -n "drs_srin_write_ready" -t "std_logic" -o 42 -suid 59,0 -) -) -uid 1490,0 -) -*55 (LogPort port (LogicalPort decl (Decl @@ -611,5 +605,5 @@ uid 1492,0 ) -*56 (LogPort +*55 (LogPort port (LogicalPort m 1 @@ -617,5 +611,5 @@ n "drs_readout_started" t "std_logic" -o 45 +o 56 suid 61,0 i "'0'" @@ -624,5 +618,5 @@ uid 1524,0 ) -*57 (LogPort +*56 (LogPort port (LogicalPort m 1 @@ -634,5 +628,5 @@ preAdd 0 posAdd 0 -o 35 +o 46 suid 62,0 i "'0'" @@ -641,14 +635,181 @@ uid 1556,0 ) +*57 (LogPort +port (LogicalPort +decl (Decl +n "drs_readout_ready_ack" +t "std_logic" +o 47 +suid 63,0 +) +) +uid 1588,0 +) *58 (LogPort port (LogicalPort decl (Decl -n "drs_readout_ready_ack" -t "std_logic" +n "pll_lock" +t "std_logic_vector" +b "( 3 downto 0)" +posAdd 0 +o 24 +suid 64,0 +) +) +uid 1620,0 +) +*59 (LogPort +port (LogicalPort +decl (Decl +n "fad_event_counter" +t "std_logic_vector" +b "(31 downto 0)" +prec "-- + +-- EVT HEADER - part 3" +preAdd 0 +o 27 +suid 65,0 +) +) +uid 1652,0 +) +*60 (LogPort +port (LogicalPort +decl (Decl +n "refclk_counter" +t "std_logic_vector" +b "(11 downto 0)" +o 28 +suid 66,0 +) +) +uid 1694,0 +) +*61 (LogPort +port (LogicalPort +decl (Decl +n "refclk_too_high" +t "std_logic" +o 29 +suid 67,0 +) +) +uid 1696,0 +) +*62 (LogPort +port (LogicalPort +decl (Decl +n "refclk_too_low" +t "std_logic" +posAdd 0 +o 30 +suid 68,0 +) +) +uid 1698,0 +) +*63 (LogPort +port (LogicalPort +decl (Decl +n "FTM_RS485_ready" +t "std_logic" +prec "-- + +-- EVT HEADER - part 2 --> FTM trigger informaton, comes in late ... +-- during EVT header wrinting, this field is left out ... and only written into event header, +-- when the DRS chip were read out already." +preAdd 0 +o 25 +suid 69,0 +) +) +uid 1735,0 +) +*64 (LogPort +port (LogicalPort +decl (Decl +n "FTM_trigger_info" +t "std_logic_vector" +b "(55 downto 0)" +eolc "--7 byte" +posAdd 0 +o 26 +suid 70,0 +) +) +uid 1737,0 +) +*65 (LogPort +port (LogicalPort +decl (Decl +n "DCM_PS_status" +t "std_logic_vector" +b "(7 downto 0)" +o 33 +suid 71,0 +) +) +uid 1779,0 +) +*66 (LogPort +port (LogicalPort +decl (Decl +n "TRG_GEN_div" +t "std_logic_vector" +b "(15 downto 0)" +posAdd 0 +o 35 +suid 72,0 +) +) +uid 1781,0 +) +*67 (LogPort +port (LogicalPort +decl (Decl +n "TRG_GEN_no" +t "std_logic_vector" +b "(15 downto 0)" +o 34 +suid 73,0 +) +) +uid 1783,0 +) +*68 (LogPort +port (LogicalPort +decl (Decl +n "dna" +t "std_logic_vector" +b "(63 downto 0)" +prec "-- + +-- EVT HEADER - part 5" +preAdd 0 +posAdd 0 o 36 -suid 63,0 -) -) -uid 1588,0 +suid 74,0 +) +) +uid 1815,0 +) +*69 (LogPort +port (LogicalPort +decl (Decl +n "timer_value" +t "std_logic_vector" +b "(31 downto 0)" +prec "-- + +-- EVT HEADER - part 6" +eolc "-- time in units of 100us" +preAdd 0 +posAdd 0 +o 37 +suid 75,0 +) +) +uid 1847,0 ) ] @@ -659,5 +820,5 @@ uid 149,0 optionalChildren [ -*59 (Sheet +*70 (Sheet sheetRow (SheetRow headerVa (MVa @@ -676,5 +837,5 @@ font "Tahoma,10,0" ) -emptyMRCItem *60 (MRCItem +emptyMRCItem *71 (MRCItem litem &1 pos 3 @@ -683,5 +844,5 @@ uid 151,0 optionalChildren [ -*61 (MRCItem +*72 (MRCItem litem &2 pos 0 @@ -689,5 +850,5 @@ uid 152,0 ) -*62 (MRCItem +*73 (MRCItem litem &3 pos 1 @@ -695,5 +856,5 @@ uid 153,0 ) -*63 (MRCItem +*74 (MRCItem litem &4 pos 2 @@ -702,5 +863,5 @@ uid 154,0 ) -*64 (MRCItem +*75 (MRCItem litem &14 pos 0 @@ -708,5 +869,5 @@ uid 110,0 ) -*65 (MRCItem +*76 (MRCItem litem &15 pos 1 @@ -714,5 +875,5 @@ uid 112,0 ) -*66 (MRCItem +*77 (MRCItem litem &16 pos 2 @@ -720,5 +881,5 @@ uid 114,0 ) -*67 (MRCItem +*78 (MRCItem litem &17 pos 3 @@ -726,5 +887,5 @@ uid 120,0 ) -*68 (MRCItem +*79 (MRCItem litem &18 pos 4 @@ -732,5 +893,5 @@ uid 122,0 ) -*69 (MRCItem +*80 (MRCItem litem &19 pos 5 @@ -738,237 +899,303 @@ uid 126,0 ) -*70 (MRCItem +*81 (MRCItem litem &20 pos 6 dimension 20 -uid 128,0 -) -*71 (MRCItem +uid 130,0 +) +*82 (MRCItem litem &21 pos 7 dimension 20 -uid 130,0 -) -*72 (MRCItem +uid 291,0 +) +*83 (MRCItem litem &22 pos 8 dimension 20 -uid 291,0 -) -*73 (MRCItem +uid 422,0 +) +*84 (MRCItem litem &23 pos 9 dimension 20 -uid 422,0 -) -*74 (MRCItem +uid 424,0 +) +*85 (MRCItem litem &24 pos 10 dimension 20 -uid 424,0 -) -*75 (MRCItem +uid 426,0 +) +*86 (MRCItem litem &25 pos 11 dimension 20 -uid 426,0 -) -*76 (MRCItem +uid 479,0 +) +*87 (MRCItem litem &26 pos 12 dimension 20 -uid 479,0 -) -*77 (MRCItem +uid 532,0 +) +*88 (MRCItem litem &27 pos 13 dimension 20 -uid 532,0 -) -*78 (MRCItem +uid 650,0 +) +*89 (MRCItem litem &28 pos 14 dimension 20 -uid 650,0 -) -*79 (MRCItem +uid 702,0 +) +*90 (MRCItem litem &29 pos 15 dimension 20 -uid 702,0 -) -*80 (MRCItem +uid 704,0 +) +*91 (MRCItem litem &30 pos 16 dimension 20 -uid 704,0 -) -*81 (MRCItem +uid 817,0 +) +*92 (MRCItem litem &31 pos 17 dimension 20 -uid 817,0 -) -*82 (MRCItem +uid 819,0 +) +*93 (MRCItem litem &32 pos 18 dimension 20 -uid 819,0 -) -*83 (MRCItem +uid 821,0 +) +*94 (MRCItem litem &33 pos 19 dimension 20 -uid 821,0 -) -*84 (MRCItem +uid 904,0 +) +*95 (MRCItem litem &34 pos 20 dimension 20 -uid 904,0 -) -*85 (MRCItem +uid 969,0 +) +*96 (MRCItem litem &35 pos 21 dimension 20 -uid 969,0 -) -*86 (MRCItem +uid 971,0 +) +*97 (MRCItem litem &36 pos 22 dimension 20 -uid 971,0 -) -*87 (MRCItem +uid 1059,0 +) +*98 (MRCItem litem &37 pos 23 dimension 20 -uid 1059,0 -) -*88 (MRCItem +uid 1061,0 +) +*99 (MRCItem litem &38 pos 24 dimension 20 -uid 1061,0 -) -*89 (MRCItem +uid 1096,0 +) +*100 (MRCItem litem &39 pos 25 dimension 20 -uid 1096,0 -) -*90 (MRCItem +uid 1098,0 +) +*101 (MRCItem litem &40 pos 26 dimension 20 -uid 1098,0 -) -*91 (MRCItem +uid 1133,0 +) +*102 (MRCItem litem &41 pos 27 dimension 20 -uid 1133,0 -) -*92 (MRCItem +uid 1135,0 +) +*103 (MRCItem litem &42 pos 28 dimension 20 -uid 1135,0 -) -*93 (MRCItem +uid 1170,0 +) +*104 (MRCItem litem &43 pos 29 dimension 20 -uid 1170,0 -) -*94 (MRCItem +uid 1172,0 +) +*105 (MRCItem litem &44 pos 30 dimension 20 -uid 1172,0 -) -*95 (MRCItem +uid 1212,0 +) +*106 (MRCItem litem &45 pos 31 dimension 20 -uid 1212,0 -) -*96 (MRCItem +uid 1214,0 +) +*107 (MRCItem litem &46 pos 32 dimension 20 -uid 1214,0 -) -*97 (MRCItem +uid 1216,0 +) +*108 (MRCItem litem &47 pos 33 dimension 20 -uid 1216,0 -) -*98 (MRCItem +uid 1246,0 +) +*109 (MRCItem litem &48 pos 34 dimension 20 -uid 1246,0 -) -*99 (MRCItem +uid 1401,0 +) +*110 (MRCItem litem &49 pos 35 dimension 20 -uid 1401,0 -) -*100 (MRCItem +uid 1433,0 +) +*111 (MRCItem litem &50 pos 36 dimension 20 -uid 1433,0 -) -*101 (MRCItem +uid 1485,0 +) +*112 (MRCItem litem &51 pos 37 dimension 20 -uid 1485,0 -) -*102 (MRCItem +uid 1487,0 +) +*113 (MRCItem litem &52 pos 38 dimension 20 -uid 1487,0 -) -*103 (MRCItem +uid 1489,0 +) +*114 (MRCItem litem &53 pos 39 dimension 20 -uid 1489,0 -) -*104 (MRCItem +uid 1491,0 +) +*115 (MRCItem litem &54 pos 40 dimension 20 -uid 1491,0 -) -*105 (MRCItem +uid 1493,0 +) +*116 (MRCItem litem &55 pos 41 dimension 20 -uid 1493,0 -) -*106 (MRCItem +uid 1525,0 +) +*117 (MRCItem litem &56 pos 42 dimension 20 -uid 1525,0 -) -*107 (MRCItem +uid 1557,0 +) +*118 (MRCItem litem &57 pos 43 dimension 20 -uid 1557,0 -) -*108 (MRCItem +uid 1589,0 +) +*119 (MRCItem litem &58 pos 44 dimension 20 -uid 1589,0 +uid 1621,0 +) +*120 (MRCItem +litem &59 +pos 45 +dimension 20 +uid 1653,0 +) +*121 (MRCItem +litem &60 +pos 46 +dimension 20 +uid 1695,0 +) +*122 (MRCItem +litem &61 +pos 47 +dimension 20 +uid 1697,0 +) +*123 (MRCItem +litem &62 +pos 48 +dimension 20 +uid 1699,0 +) +*124 (MRCItem +litem &63 +pos 49 +dimension 20 +uid 1736,0 +) +*125 (MRCItem +litem &64 +pos 50 +dimension 20 +uid 1738,0 +) +*126 (MRCItem +litem &65 +pos 51 +dimension 20 +uid 1780,0 +) +*127 (MRCItem +litem &66 +pos 52 +dimension 20 +uid 1782,0 +) +*128 (MRCItem +litem &67 +pos 53 +dimension 20 +uid 1784,0 +) +*129 (MRCItem +litem &68 +pos 54 +dimension 20 +uid 1816,0 +) +*130 (MRCItem +litem &69 +pos 55 +dimension 20 +uid 1848,0 ) ] @@ -983,5 +1210,5 @@ uid 155,0 optionalChildren [ -*109 (MRCItem +*131 (MRCItem litem &5 pos 0 @@ -989,5 +1216,5 @@ uid 156,0 ) -*110 (MRCItem +*132 (MRCItem litem &7 pos 1 @@ -995,5 +1222,5 @@ uid 157,0 ) -*111 (MRCItem +*133 (MRCItem litem &8 pos 2 @@ -1001,5 +1228,5 @@ uid 158,0 ) -*112 (MRCItem +*134 (MRCItem litem &9 pos 3 @@ -1007,5 +1234,5 @@ uid 159,0 ) -*113 (MRCItem +*135 (MRCItem litem &10 pos 4 @@ -1013,5 +1240,5 @@ uid 160,0 ) -*114 (MRCItem +*136 (MRCItem litem &11 pos 5 @@ -1019,5 +1246,5 @@ uid 161,0 ) -*115 (MRCItem +*137 (MRCItem litem &12 pos 6 @@ -1025,5 +1252,5 @@ uid 162,0 ) -*116 (MRCItem +*138 (MRCItem litem &13 pos 7 @@ -1046,39 +1273,39 @@ genericsCommonDM (CommonDM ldm (LogicalDM -emptyRow *117 (LEmptyRow +emptyRow *139 (LEmptyRow ) uid 165,0 optionalChildren [ -*118 (RefLabelRowHdr -) -*119 (TitleRowHdr -) -*120 (FilterRowHdr -) -*121 (RefLabelColHdr +*140 (RefLabelRowHdr +) +*141 (TitleRowHdr +) +*142 (FilterRowHdr +) +*143 (RefLabelColHdr tm "RefLabelColHdrMgr" ) -*122 (RowExpandColHdr +*144 (RowExpandColHdr tm "RowExpandColHdrMgr" ) -*123 (GroupColHdr +*145 (GroupColHdr tm "GroupColHdrMgr" ) -*124 (NameColHdr +*146 (NameColHdr tm "GenericNameColHdrMgr" ) -*125 (TypeColHdr +*147 (TypeColHdr tm "GenericTypeColHdrMgr" ) -*126 (InitColHdr +*148 (InitColHdr tm "GenericValueColHdrMgr" ) -*127 (PragmaColHdr +*149 (PragmaColHdr tm "GenericPragmaColHdrMgr" ) -*128 (EolColHdr +*150 (EolColHdr tm "GenericEolColHdrMgr" ) -*129 (LogGeneric +*151 (LogGeneric generic (GiElement name "RAM_ADDR_WIDTH" @@ -1086,5 +1313,5 @@ value "12" ) -uid 1590,0 +uid 1849,0 ) ] @@ -1095,5 +1322,5 @@ uid 177,0 optionalChildren [ -*130 (Sheet +*152 (Sheet sheetRow (SheetRow headerVa (MVa @@ -1112,6 +1339,6 @@ font "Tahoma,10,0" ) -emptyMRCItem *131 (MRCItem -litem &117 +emptyMRCItem *153 (MRCItem +litem &139 pos 3 dimension 20 @@ -1119,18 +1346,18 @@ uid 179,0 optionalChildren [ -*132 (MRCItem -litem &118 +*154 (MRCItem +litem &140 pos 0 dimension 20 uid 180,0 ) -*133 (MRCItem -litem &119 +*155 (MRCItem +litem &141 pos 1 dimension 23 uid 181,0 ) -*134 (MRCItem -litem &120 +*156 (MRCItem +litem &142 pos 2 hidden 1 @@ -1138,9 +1365,9 @@ uid 182,0 ) -*135 (MRCItem -litem &129 +*157 (MRCItem +litem &151 pos 0 dimension 20 -uid 1591,0 +uid 1850,0 ) ] @@ -1155,42 +1382,42 @@ uid 183,0 optionalChildren [ -*136 (MRCItem -litem &121 +*158 (MRCItem +litem &143 pos 0 dimension 20 uid 184,0 ) -*137 (MRCItem -litem &123 +*159 (MRCItem +litem &145 pos 1 dimension 50 uid 185,0 ) -*138 (MRCItem -litem &124 +*160 (MRCItem +litem &146 pos 2 dimension 100 uid 186,0 ) -*139 (MRCItem -litem &125 +*161 (MRCItem +litem &147 pos 3 dimension 100 uid 187,0 ) -*140 (MRCItem -litem &126 +*162 (MRCItem +litem &148 pos 4 dimension 50 uid 188,0 ) -*141 (MRCItem -litem &127 +*163 (MRCItem +litem &149 pos 5 dimension 50 uid 189,0 ) -*142 (MRCItem -litem &128 +*164 (MRCItem +litem &150 pos 6 dimension 80 @@ -1215,21 +1442,21 @@ (vvPair variable "HDLDir" -value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl" ) (vvPair variable "HDSDir" -value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" ) (vvPair variable "SideDataDesignDir" -value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb.info" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb.info" ) (vvPair variable "SideDataUserDir" -value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb.user" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb.user" ) (vvPair variable "SourceDir" -value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" ) (vvPair @@ -1247,25 +1474,25 @@ (vvPair variable "d" -value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator" ) (vvPair variable "d_logical" -value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator" ) (vvPair variable "date" -value "14.01.2011" +value "15.02.2011" ) (vvPair variable "day" -value "Fr" +value "Di" ) (vvPair variable "day_long" -value "Freitag" +value "Dienstag" ) (vvPair variable "dd" -value "14" +value "15" ) (vvPair @@ -1295,5 +1522,5 @@ (vvPair variable "host" -value "IHP110" +value "E5B-LABOR6" ) (vvPair @@ -1331,5 +1558,5 @@ (vvPair variable "mm" -value "01" +value "02" ) (vvPair @@ -1339,17 +1566,17 @@ (vvPair variable "month" -value "Jan" +value "Feb" ) (vvPair variable "month_long" -value "Januar" +value "Februar" ) (vvPair variable "p" -value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb" ) (vvPair variable "p_logical" -value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\data_generator\\symbol.sb" ) (vvPair @@ -1375,5 +1602,5 @@ (vvPair variable "task_ModelSimPath" -value "D:\\modeltech_6.5e\\win32" +value "C:\\modeltech_6.6a\\win32" ) (vvPair @@ -1407,5 +1634,5 @@ (vvPair variable "time" -value "11:17:29" +value "10:09:00" ) (vvPair @@ -1415,9 +1642,9 @@ (vvPair variable "user" -value "daqct3" +value "dneise" ) (vvPair variable "version" -value "2009.1 (Build 12)" +value "2009.2 (Build 10)" ) (vvPair @@ -1438,8 +1665,8 @@ uid 134,0 optionalChildren [ -*143 (SymbolBody +*165 (SymbolBody uid 8,0 optionalChildren [ -*144 (CptPort +*166 (CptPort uid 48,0 ps "OnEdgeStrategy" @@ -1489,5 +1716,5 @@ ) ) -*145 (CptPort +*167 (CptPort uid 53,0 ps "OnEdgeStrategy" @@ -1538,5 +1765,5 @@ ) ) -*146 (CptPort +*168 (CptPort uid 58,0 ps "OnEdgeStrategy" @@ -1587,5 +1814,5 @@ ) ) -*147 (CptPort +*169 (CptPort uid 73,0 ps "OnEdgeStrategy" @@ -1637,5 +1864,5 @@ ) ) -*148 (CptPort +*170 (CptPort uid 78,0 ps "OnEdgeStrategy" @@ -1685,5 +1912,5 @@ ) ) -*149 (CptPort +*171 (CptPort uid 88,0 ps "OnEdgeStrategy" @@ -1716,6 +1943,9 @@ font "Courier New,8,0" ) -xt "2000,34400,35000,35200" -st "board_id : IN std_logic_vector (3 downto 0) ; +xt "2000,47200,35000,50400" +st "-- + +-- EVT HEADER - part 4 +board_id : IN std_logic_vector (3 downto 0) ; " ) @@ -1725,59 +1955,15 @@ t "std_logic_vector" b "(3 downto 0)" +prec "-- + +-- EVT HEADER - part 4" preAdd 0 posAdd 0 -o 24 +o 31 suid 9,0 ) ) ) -*150 (CptPort -uid 93,0 -ps "OnEdgeStrategy" -shape (Triangle -uid 94,0 -ro 90 -va (VaSet -vasetType 1 -fg "0,65535,0" -) -xt "36250,11625,37000,12375" -) -tg (CPTG -uid 95,0 -ps "CptPortTextPlaceStrategy" -stg "VerticalLayoutStrategy" -f (Text -uid 96,0 -va (VaSet -) -xt "38000,11500,44800,12500" -st "trigger_id : (47:0)" -blo "38000,12300" -tm "CptPortNameMgr" -) -) -dt (MLText -uid 97,0 -va (VaSet -font "Courier New,8,0" -) -xt "2000,36000,35500,36800" -st "trigger_id : IN std_logic_vector (47 downto 0) ; -" -) -thePort (LogicalPort -decl (Decl -n "trigger_id" -t "std_logic_vector" -b "(47 downto 0)" -preAdd 0 -posAdd 0 -o 26 -suid 10,0 -) -) -) -*151 (CptPort +*172 (CptPort uid 98,0 ps "OnEdgeStrategy" @@ -1810,6 +1996,7 @@ font "Courier New,8,0" ) -xt "2000,36800,25500,37600" -st "trigger : IN std_logic ; +xt "2000,60000,25500,61600" +st "-- +trigger : IN std_logic ; " ) @@ -1818,12 +2005,13 @@ n "trigger" t "std_logic" +prec "--" preAdd 0 posAdd 0 -o 27 +o 38 suid 11,0 ) ) ) -*152 (CommentText +*173 (CommentText uid 106,0 ps "EdgeToEdgeStrategy" @@ -1859,5 +2047,5 @@ excludeCommentLeader 1 ) -*153 (CptPort +*174 (CptPort uid 285,0 ps "OnEdgeStrategy" @@ -1890,5 +2078,5 @@ font "Courier New,8,0" ) -xt "2000,35200,35000,36000" +xt "2000,50400,35000,51200" st "crate_id : IN std_logic_vector (1 downto 0) ; " @@ -1899,10 +2087,11 @@ t "std_logic_vector" b "(1 downto 0)" -o 25 +posAdd 0 +o 32 suid 12,0 ) ) ) -*154 (CptPort +*175 (CptPort uid 402,0 ps "OnEdgeStrategy" @@ -1948,5 +2137,5 @@ ) ) -*155 (CptPort +*176 (CptPort uid 407,0 ps "OnEdgeStrategy" @@ -1996,5 +2185,5 @@ ) ) -*156 (CptPort +*177 (CptPort uid 412,0 ps "OnEdgeStrategy" @@ -2040,5 +2229,5 @@ ) ) -*157 (CptPort +*178 (CptPort uid 473,0 ps "OnEdgeStrategy" @@ -2084,5 +2273,5 @@ ) ) -*158 (CptPort +*179 (CptPort uid 526,0 ps "OnEdgeStrategy" @@ -2115,6 +2304,7 @@ font "Courier New,8,0" ) -xt "2000,33600,35500,34400" -st "package_length : IN std_logic_vector (15 downto 0) ; +xt "2000,33600,35500,35200" +st "-- EVT HEADER - part 1 +package_length : IN std_logic_vector (15 downto 0) ; " ) @@ -2124,4 +2314,6 @@ t "std_logic_vector" b "(15 downto 0)" +prec "-- EVT HEADER - part 1" +preAdd 0 o 23 suid 20,0 @@ -2129,5 +2321,5 @@ ) ) -*159 (CptPort +*180 (CptPort uid 637,0 ps "OnEdgeStrategy" @@ -2161,5 +2353,5 @@ font "Courier New,8,0" ) -xt "2000,40800,38500,41600" +xt "2000,64800,38500,65600" st "adc_oeb : OUT std_logic := '1' ; " @@ -2170,5 +2362,5 @@ n "adc_oeb" t "std_logic" -o 31 +o 42 suid 23,0 i "'1'" @@ -2176,5 +2368,5 @@ ) ) -*160 (CptPort +*181 (CptPort uid 676,0 ps "OnEdgeStrategy" @@ -2208,5 +2400,5 @@ font "Courier New,8,0" ) -xt "2000,43200,44500,44000" +xt "2000,67200,44500,68000" st "drs_channel_id : OUT std_logic_vector (3 downto 0) := (others => '0') ; " @@ -2219,5 +2411,5 @@ b "(3 downto 0)" posAdd 0 -o 34 +o 45 suid 25,0 i "(others => '0')" @@ -2225,5 +2417,5 @@ ) ) -*161 (CptPort +*182 (CptPort uid 681,0 ps "OnEdgeStrategy" @@ -2257,5 +2449,5 @@ font "Courier New,8,0" ) -xt "2000,47200,38500,48800" +xt "2000,71200,38500,72800" st "-- -- drs_clk_en : OUT std_logic := '0' ; @@ -2270,5 +2462,5 @@ preAdd 0 posAdd 0 -o 37 +o 48 suid 26,0 i "'0'" @@ -2276,5 +2468,5 @@ ) ) -*162 (CptPort +*183 (CptPort uid 801,0 ps "OnEdgeStrategy" @@ -2308,5 +2500,5 @@ font "Courier New,8,0" ) -xt "2000,48800,38500,50400" +xt "2000,72800,38500,74400" st "-- -- drs_read_s_cell : OUT std_logic := '0' ; @@ -2320,5 +2512,5 @@ prec "-- --" preAdd 0 -o 38 +o 49 suid 33,0 i "'0'" @@ -2326,5 +2518,5 @@ ) ) -*163 (CptPort +*184 (CptPort uid 806,0 ps "OnEdgeStrategy" @@ -2357,5 +2549,5 @@ font "Courier New,8,0" ) -xt "2000,53600,25500,54400" +xt "2000,77600,25500,78400" st "drs_read_s_cell_ready : IN std_logic ; " @@ -2365,10 +2557,10 @@ n "drs_read_s_cell_ready" t "std_logic" -o 43 +o 54 suid 34,0 ) ) ) -*164 (CptPort +*185 (CptPort uid 811,0 ps "OnEdgeStrategy" @@ -2401,5 +2593,5 @@ font "Courier New,8,0" ) -xt "2000,54400,31500,55200" +xt "2000,78400,31500,79200" st "drs_s_cell_array : IN drs_s_cell_array_type ; " @@ -2409,10 +2601,10 @@ n "drs_s_cell_array" t "drs_s_cell_array_type" -o 44 +o 55 suid 35,0 ) ) ) -*165 (CptPort +*186 (CptPort uid 898,0 ps "OnEdgeStrategy" @@ -2445,5 +2637,5 @@ font "Courier New,8,0" ) -xt "2000,40000,30500,40800" +xt "2000,64000,30500,64800" st "adc_data_array : IN adc_data_array_type ; " @@ -2453,10 +2645,10 @@ n "adc_data_array" t "adc_data_array_type" -o 30 +o 41 suid 37,0 ) ) ) -*166 (CptPort +*187 (CptPort uid 958,0 ps "OnEdgeStrategy" @@ -2502,5 +2694,5 @@ ) ) -*167 (CptPort +*188 (CptPort uid 963,0 ps "OnEdgeStrategy" @@ -2553,5 +2745,5 @@ ) ) -*168 (CptPort +*189 (CptPort uid 1048,0 ps "OnEdgeStrategy" @@ -2597,5 +2789,5 @@ ) ) -*169 (CptPort +*190 (CptPort uid 1053,0 ps "OnEdgeStrategy" @@ -2641,5 +2833,5 @@ ) ) -*170 (CptPort +*191 (CptPort uid 1085,0 ps "OnEdgeStrategy" @@ -2685,5 +2877,5 @@ ) ) -*171 (CptPort +*192 (CptPort uid 1090,0 ps "OnEdgeStrategy" @@ -2729,5 +2921,5 @@ ) ) -*172 (CptPort +*193 (CptPort uid 1122,0 ps "OnEdgeStrategy" @@ -2780,5 +2972,5 @@ ) ) -*173 (CptPort +*194 (CptPort uid 1127,0 ps "OnEdgeStrategy" @@ -2830,5 +3022,5 @@ ) ) -*174 (CptPort +*195 (CptPort uid 1159,0 ps "OnEdgeStrategy" @@ -2862,5 +3054,5 @@ font "Courier New,8,0" ) -xt "2000,39200,38500,40000" +xt "2000,63200,38500,64000" st "config_started : OUT std_logic := '0' ; " @@ -2871,5 +3063,5 @@ n "config_started" t "std_logic" -o 29 +o 40 suid 48,0 i "'0'" @@ -2877,5 +3069,5 @@ ) ) -*175 (CptPort +*196 (CptPort uid 1164,0 ps "OnEdgeStrategy" @@ -2908,5 +3100,5 @@ font "Courier New,8,0" ) -xt "2000,37600,25500,39200" +xt "2000,61600,25500,63200" st "-- s_trigger : in std_logic; new_config : IN std_logic ; @@ -2919,10 +3111,10 @@ prec "-- s_trigger : in std_logic;" preAdd 0 -o 28 +o 39 suid 49,0 ) ) ) -*176 (CptPort +*197 (CptPort uid 1196,0 ps "OnEdgeStrategy" @@ -2968,5 +3160,5 @@ ) ) -*177 (CptPort +*198 (CptPort uid 1201,0 ps "OnEdgeStrategy" @@ -3012,5 +3204,5 @@ ) ) -*178 (CptPort +*199 (CptPort uid 1206,0 ps "OnEdgeStrategy" @@ -3056,5 +3248,5 @@ ) ) -*179 (CptPort +*200 (CptPort uid 1240,0 ps "OnEdgeStrategy" @@ -3095,4 +3287,5 @@ n "dac_array" t "dac_array_type" +posAdd 0 o 22 suid 53,0 @@ -3100,5 +3293,5 @@ ) ) -*180 (CptPort +*201 (CptPort uid 1395,0 ps "OnEdgeStrategy" @@ -3132,5 +3325,5 @@ font "Courier New,8,0" ) -xt "2000,41600,38500,42400" +xt "2000,65600,38500,66400" st "adc_clk_en : OUT std_logic := '0' ; " @@ -3141,5 +3334,5 @@ n "adc_clk_en" t "std_logic" -o 32 +o 43 suid 54,0 i "'0'" @@ -3147,5 +3340,5 @@ ) ) -*181 (CptPort +*202 (CptPort uid 1427,0 ps "OnEdgeStrategy" @@ -3178,5 +3371,5 @@ font "Courier New,8,0" ) -xt "2000,42400,35000,43200" +xt "2000,66400,35000,67200" st "adc_otr : IN std_logic_vector (3 downto 0) ; " @@ -3187,10 +3380,10 @@ t "std_logic_vector" b "(3 downto 0)" -o 33 +o 44 suid 55,0 ) ) ) -*182 (CptPort +*203 (CptPort uid 1459,0 ps "OnEdgeStrategy" @@ -3224,5 +3417,5 @@ font "Courier New,8,0" ) -xt "2000,52000,44500,52800" +xt "2000,76000,44500,76800" st "drs_srin_data : OUT std_logic_vector (7 downto 0) := (others => '0') ; " @@ -3234,5 +3427,5 @@ t "std_logic_vector" b "(7 downto 0)" -o 41 +o 52 suid 56,0 i "(others => '0')" @@ -3240,5 +3433,5 @@ ) ) -*183 (CptPort +*204 (CptPort uid 1464,0 ps "OnEdgeStrategy" @@ -3272,5 +3465,5 @@ font "Courier New,8,0" ) -xt "2000,50400,38500,51200" +xt "2000,74400,38500,75200" st "drs_srin_write_8b : OUT std_logic := '0' ; " @@ -3281,5 +3474,5 @@ n "drs_srin_write_8b" t "std_logic" -o 39 +o 50 suid 57,0 i "'0'" @@ -3287,5 +3480,5 @@ ) ) -*184 (CptPort +*205 (CptPort uid 1469,0 ps "OnEdgeStrategy" @@ -3318,5 +3511,5 @@ font "Courier New,8,0" ) -xt "2000,51200,25500,52000" +xt "2000,75200,25500,76000" st "drs_srin_write_ack : IN std_logic ; " @@ -3326,10 +3519,10 @@ n "drs_srin_write_ack" t "std_logic" -o 40 +o 51 suid 58,0 ) ) ) -*185 (CptPort +*206 (CptPort uid 1474,0 ps "OnEdgeStrategy" @@ -3362,5 +3555,5 @@ font "Courier New,8,0" ) -xt "2000,52800,25500,53600" +xt "2000,76800,25500,77600" st "drs_srin_write_ready : IN std_logic ; " @@ -3370,10 +3563,10 @@ n "drs_srin_write_ready" t "std_logic" -o 42 +o 53 suid 59,0 ) ) ) -*186 (CptPort +*207 (CptPort uid 1479,0 ps "OnEdgeStrategy" @@ -3423,5 +3616,5 @@ ) ) -*187 (CptPort +*208 (CptPort uid 1519,0 ps "OnEdgeStrategy" @@ -3455,5 +3648,5 @@ font "Courier New,8,0" ) -xt "2000,55200,37500,56000" +xt "2000,79200,37500,80000" st "drs_readout_started : OUT std_logic := '0' " @@ -3464,5 +3657,5 @@ n "drs_readout_started" t "std_logic" -o 45 +o 56 suid 61,0 i "'0'" @@ -3470,5 +3663,5 @@ ) ) -*188 (CptPort +*209 (CptPort uid 1551,0 ps "OnEdgeStrategy" @@ -3502,5 +3695,5 @@ font "Courier New,8,0" ) -xt "2000,44000,38500,46400" +xt "2000,68000,38500,70400" st "-- -- -- drs_dwrite : out std_logic := '1'; @@ -3517,5 +3710,5 @@ preAdd 0 posAdd 0 -o 35 +o 46 suid 62,0 i "'0'" @@ -3523,5 +3716,5 @@ ) ) -*189 (CptPort +*210 (CptPort uid 1583,0 ps "OnEdgeStrategy" @@ -3554,14 +3747,591 @@ font "Courier New,8,0" ) +xt "2000,70400,25500,71200" +st "drs_readout_ready_ack : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "drs_readout_ready_ack" +t "std_logic" +o 47 +suid 63,0 +) +) +) +*211 (CptPort +uid 1615,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1616,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,39625,37000,40375" +) +tg (CPTG +uid 1617,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1618,0 +va (VaSet +) +xt "38000,39500,43500,40500" +st "pll_lock : (3:0)" +blo "38000,40300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1619,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,35200,35500,36000" +st "pll_lock : IN std_logic_vector ( 3 downto 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "pll_lock" +t "std_logic_vector" +b "( 3 downto 0)" +posAdd 0 +o 24 +suid 64,0 +) +) +) +*212 (CptPort +uid 1647,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1648,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,40625,37000,41375" +) +tg (CPTG +uid 1649,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1650,0 +va (VaSet +) +xt "38000,40500,47800,41500" +st "fad_event_counter : (31:0)" +blo "38000,41300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1651,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,41600,35500,44800" +st "-- + +-- EVT HEADER - part 3 +fad_event_counter : IN std_logic_vector (31 downto 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "fad_event_counter" +t "std_logic_vector" +b "(31 downto 0)" +prec "-- + +-- EVT HEADER - part 3" +preAdd 0 +o 27 +suid 65,0 +) +) +) +*213 (CptPort +uid 1679,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1680,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,41625,37000,42375" +) +tg (CPTG +uid 1681,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1682,0 +va (VaSet +) +xt "38000,41500,46500,42500" +st "refclk_counter : (11:0)" +blo "38000,42300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1683,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,44800,35500,45600" +st "refclk_counter : IN std_logic_vector (11 downto 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "refclk_counter" +t "std_logic_vector" +b "(11 downto 0)" +o 28 +suid 66,0 +) +) +) +*214 (CptPort +uid 1684,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1685,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,42625,37000,43375" +) +tg (CPTG +uid 1686,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1687,0 +va (VaSet +) +xt "38000,42500,43900,43500" +st "refclk_too_high" +blo "38000,43300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1688,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,45600,25500,46400" +st "refclk_too_high : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "refclk_too_high" +t "std_logic" +o 29 +suid 67,0 +) +) +) +*215 (CptPort +uid 1689,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1690,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,43625,37000,44375" +) +tg (CPTG +uid 1691,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1692,0 +va (VaSet +) +xt "38000,43500,43500,44500" +st "refclk_too_low" +blo "38000,44300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1693,0 +va (VaSet +font "Courier New,8,0" +) xt "2000,46400,25500,47200" -st "drs_readout_ready_ack : IN std_logic ; -" -) -thePort (LogicalPort -decl (Decl -n "drs_readout_ready_ack" -t "std_logic" +st "refclk_too_low : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "refclk_too_low" +t "std_logic" +posAdd 0 +o 30 +suid 68,0 +) +) +) +*216 (CptPort +uid 1725,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1726,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,44625,37000,45375" +) +tg (CPTG +uid 1727,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1728,0 +va (VaSet +) +xt "38000,44500,45400,45500" +st "FTM_RS485_ready" +blo "38000,45300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1729,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,36000,50500,40800" +st "-- + +-- EVT HEADER - part 2 --> FTM trigger informaton, comes in late ... +-- during EVT header wrinting, this field is left out ... and only written into event header, +-- when the DRS chip were read out already. +FTM_RS485_ready : IN std_logic ; +" +) +thePort (LogicalPort +decl (Decl +n "FTM_RS485_ready" +t "std_logic" +prec "-- + +-- EVT HEADER - part 2 --> FTM trigger informaton, comes in late ... +-- during EVT header wrinting, this field is left out ... and only written into event header, +-- when the DRS chip were read out already." +preAdd 0 +o 25 +suid 69,0 +) +) +) +*217 (CptPort +uid 1730,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1731,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,45625,37000,46375" +) +tg (CPTG +uid 1732,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1733,0 +va (VaSet +) +xt "38000,45500,47900,46500" +st "FTM_trigger_info : (55:0)" +blo "38000,46300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1734,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,40800,40000,41600" +st "FTM_trigger_info : IN std_logic_vector (55 downto 0) ; --7 byte +" +) +thePort (LogicalPort +decl (Decl +n "FTM_trigger_info" +t "std_logic_vector" +b "(55 downto 0)" +eolc "--7 byte" +posAdd 0 +o 26 +suid 70,0 +) +) +) +*218 (CptPort +uid 1764,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1765,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,46625,37000,47375" +) +tg (CPTG +uid 1766,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1767,0 +va (VaSet +) +xt "38000,46500,47100,47500" +st "DCM_PS_status : (7:0)" +blo "38000,47300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1768,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,51200,35000,52000" +st "DCM_PS_status : IN std_logic_vector (7 downto 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "DCM_PS_status" +t "std_logic_vector" +b "(7 downto 0)" +o 33 +suid 71,0 +) +) +) +*219 (CptPort +uid 1769,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1770,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,47625,37000,48375" +) +tg (CPTG +uid 1771,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1772,0 +va (VaSet +) +xt "38000,47500,46900,48500" +st "TRG_GEN_div : (15:0)" +blo "38000,48300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1773,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,52800,35500,53600" +st "TRG_GEN_div : IN std_logic_vector (15 downto 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "TRG_GEN_div" +t "std_logic_vector" +b "(15 downto 0)" +posAdd 0 +o 35 +suid 72,0 +) +) +) +*220 (CptPort +uid 1774,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1775,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,48625,37000,49375" +) +tg (CPTG +uid 1776,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1777,0 +va (VaSet +) +xt "38000,48500,46400,49500" +st "TRG_GEN_no : (15:0)" +blo "38000,49300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1778,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,52000,35500,52800" +st "TRG_GEN_no : IN std_logic_vector (15 downto 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "TRG_GEN_no" +t "std_logic_vector" +b "(15 downto 0)" +o 34 +suid 73,0 +) +) +) +*221 (CptPort +uid 1810,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1811,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,49625,37000,50375" +) +tg (CPTG +uid 1812,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1813,0 +va (VaSet +) +xt "38000,49500,42600,50500" +st "dna : (63:0)" +blo "38000,50300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1814,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,53600,35500,56800" +st "-- + +-- EVT HEADER - part 5 +dna : IN std_logic_vector (63 downto 0) ; +" +) +thePort (LogicalPort +decl (Decl +n "dna" +t "std_logic_vector" +b "(63 downto 0)" +prec "-- + +-- EVT HEADER - part 5" +preAdd 0 +posAdd 0 o 36 -suid 63,0 +suid 74,0 +) +) +) +*222 (CptPort +uid 1842,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 1843,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "36250,50625,37000,51375" +) +tg (CPTG +uid 1844,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 1845,0 +va (VaSet +) +xt "38000,50500,45600,51500" +st "timer_value : (31:0)" +blo "38000,51300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 1846,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,56800,48500,60000" +st "-- + +-- EVT HEADER - part 6 +timer_value : IN std_logic_vector (31 downto 0) ; -- time in units of 100us +" +) +thePort (LogicalPort +decl (Decl +n "timer_value" +t "std_logic_vector" +b "(31 downto 0)" +prec "-- + +-- EVT HEADER - part 6" +eolc "-- time in units of 100us" +preAdd 0 +posAdd 0 +o 37 +suid 75,0 ) ) @@ -3576,5 +4346,5 @@ lineWidth 2 ) -xt "37000,1000,67000,40000" +xt "37000,1000,67000,52000" ) oxt "37000,1000,51000,21000" @@ -3602,5 +4372,5 @@ ) ) -gi *190 (GenericInterface +gi *223 (GenericInterface uid 13,0 ps "CenterOffsetStrategy" @@ -3635,8 +4405,8 @@ ) ) -*191 (Grouping +*224 (Grouping uid 16,0 optionalChildren [ -*192 (CommentText +*225 (CommentText uid 18,0 shape (Rectangle @@ -3669,5 +4439,5 @@ titleBlock 1 ) -*193 (CommentText +*226 (CommentText uid 21,0 shape (Rectangle @@ -3700,5 +4470,5 @@ titleBlock 1 ) -*194 (CommentText +*227 (CommentText uid 24,0 shape (Rectangle @@ -3731,5 +4501,5 @@ titleBlock 1 ) -*195 (CommentText +*228 (CommentText uid 27,0 shape (Rectangle @@ -3762,5 +4532,5 @@ titleBlock 1 ) -*196 (CommentText +*229 (CommentText uid 30,0 shape (Rectangle @@ -3792,5 +4562,5 @@ titleBlock 1 ) -*197 (CommentText +*230 (CommentText uid 33,0 shape (Rectangle @@ -3823,5 +4593,5 @@ titleBlock 1 ) -*198 (CommentText +*231 (CommentText uid 36,0 shape (Rectangle @@ -3854,5 +4624,5 @@ titleBlock 1 ) -*199 (CommentText +*232 (CommentText uid 39,0 shape (Rectangle @@ -3885,5 +4655,5 @@ titleBlock 1 ) -*200 (CommentText +*233 (CommentText uid 42,0 shape (Rectangle @@ -3916,5 +4686,5 @@ titleBlock 1 ) -*201 (CommentText +*234 (CommentText uid 45,0 shape (Rectangle @@ -3960,5 +4730,5 @@ oxt "14000,66000,55000,71000" ) -*202 (CommentText +*235 (CommentText uid 103,0 shape (Rectangle @@ -4003,9 +4773,9 @@ color "26368,26368,26368" ) -packageList *203 (PackageList +packageList *236 (PackageList uid 131,0 stg "VerticalLayoutStrategy" textVec [ -*204 (Text +*237 (Text uid 132,0 va (VaSet @@ -4016,5 +4786,5 @@ blo "0,1800" ) -*205 (MLText +*238 (MLText uid 133,0 va (VaSet @@ -4117,5 +4887,5 @@ ) ) -gi *206 (GenericInterface +gi *239 (GenericInterface ps "CenterOffsetStrategy" matrix (Matrix @@ -4214,5 +4984,5 @@ ) ) -DeclarativeBlock *207 (SymDeclBlock +DeclarativeBlock *240 (SymDeclBlock uid 1,0 stg "SymDeclLayoutStrategy" @@ -4240,7 +5010,7 @@ font "Arial,8,1" ) -xt "0,56000,2400,57000" +xt "0,80000,2400,81000" st "User:" -blo "0,56800" +blo "0,80800" ) internalLabel (Text @@ -4259,5 +5029,5 @@ font "Courier New,8,0" ) -xt "2000,57000,2000,57000" +xt "2000,81000,2000,81000" tm "SyDeclarativeTextMgr" ) @@ -4272,5 +5042,5 @@ ) ) -lastUid 1591,0 +lastUid 1850,0 activeModelName "Symbol:CDM" ) Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/dna_gen/@behavioral.bd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/dna_gen/@behavioral.bd (revision 10155) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/dna_gen/@behavioral.bd (revision 10155) @@ -0,0 +1,6989 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +] +instances [ +(Instance +name "DNA_PORT_inst" +duLibraryName "unisim" +duName "DNA_PORT" +elements [ +(GiElement +name "SIM_DNA_VALUE" +type "bit_vector" +value "DNA_FOR_SIM" +) +] +mwi 0 +uid 97,0 +) +] +embeddedInstances [ +(EmbeddedInstance +name "SM" +number "1" +view 1 +machine (Machine +name "FTU_dna_gen_State" +children [ +(Machine +name "FTU_dna_gen_State" +children [ +] +stateSignalName "FTU_dna_gen_State" +) +] +) +) +(EmbeddedInstance +name "eb1" +number "2" +) +] +) +version "29.1" +appVersion "2009.2 (Build 10)" +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable "HDLDir" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@t@u_dna_gen\\@behavioral.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@t@u_dna_gen\\@behavioral.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "Behavioral" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@t@u_dna_gen" +) +(vvPair +variable "d_logical" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FTU_dna_gen" +) +(vvPair +variable "date" +value "15.02.2011" +) +(vvPair +variable "day" +value "Di" +) +(vvPair +variable "day_long" +value "Dienstag" +) +(vvPair +variable "dd" +value "15" +) +(vvPair +variable "entity_name" +value "FTU_dna_gen" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "@behavioral.bd" +) +(vvPair +variable "f_logical" +value "Behavioral.bd" +) +(vvPair +variable "f_noext" +value "@behavioral" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "E5B-LABOR6" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_lib" +) +(vvPair +variable "library_downstream_HdsLintPlugin" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/designcheck" +) +(vvPair +variable "library_downstream_ISEPARInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ImpactInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/work" +) +(vvPair +variable "library_downstream_XSTDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "mm" +value "02" +) +(vvPair +variable "module_name" +value "FTU_dna_gen" +) +(vvPair +variable "month" +value "Feb" +) +(vvPair +variable "month_long" +value "Februar" +) +(vvPair +variable "p" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\@f@t@u_dna_gen\\@behavioral.bd" +) +(vvPair +variable "p_logical" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\FTU_dna_gen\\Behavioral.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "C:\\modeltech_6.6a\\win32" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "@behavioral" +) +(vvPair +variable "this_file_logical" +value "Behavioral" +) +(vvPair +variable "time" +value "09:15:09" +) +(vvPair +variable "unit" +value "FTU_dna_gen" +) +(vvPair +variable "user" +value "dneise" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable "view" +value "Behavioral" +) +(vvPair +variable "year" +value "2011" +) +(vvPair +variable "yy" +value "11" +) +] +) +LanguageMgr "VhdlLangMgr" +optionalChildren [ +*1 (Net +uid 9,0 +decl (Decl +n "dout_sig" +t "STD_LOGIC" +o 5 +suid 1,0 +i "'0'" +) +declText (MLText +uid 10,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "15000,32000,45000,32800" +st "SIGNAL dout_sig : STD_LOGIC := '0' +" +) +) +*2 (Net +uid 11,0 +decl (Decl +n "read_sig" +t "STD_LOGIC" +o 6 +suid 2,0 +i "'0'" +) +declText (MLText +uid 12,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "15000,32800,45000,33600" +st "SIGNAL read_sig : STD_LOGIC := '0' +" +) +) +*3 (Net +uid 13,0 +decl (Decl +n "shift_sig" +t "STD_LOGIC" +o 7 +suid 3,0 +i "'0'" +) +declText (MLText +uid 14,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "15000,33600,45000,34400" +st "SIGNAL shift_sig : STD_LOGIC := '0' +" +) +) +*4 (Net +uid 15,0 +decl (Decl +n "dna_sig" +t "STD_LOGIC_VECTOR" +b "(63 downto 0)" +o 8 +suid 4,0 +i "(others => '0')" +) +declText (MLText +uid 16,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "15000,34400,51000,35200" +st "SIGNAL dna_sig : STD_LOGIC_VECTOR(63 downto 0) := (others => '0') +" +) +) +*5 (Net +uid 19,0 +decl (Decl +n "shift_cntr" +t "INTEGER" +b "RANGE 0 to 64" +o 9 +suid 6,0 +i "0" +) +declText (MLText +uid 20,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "15000,35200,44000,36000" +st "SIGNAL shift_cntr : INTEGER RANGE 0 to 64 := 0 +" +) +) +*6 (PortIoIn +uid 21,0 +shape (CompositeShape +uid 22,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 23,0 +sl 0 +ro 270 +xt "-5000,17625,-3500,18375" +) +(Line +uid 24,0 +sl 0 +ro 270 +xt "-3500,18000,-3000,18000" +pts [ +"-3500,18000" +"-3000,18000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 25,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 26,0 +va (VaSet +) +xt "-7300,17500,-6000,18500" +st "clk" +ju 2 +blo "-6000,18300" +tm "WireNameMgr" +) +) +) +*7 (Net +uid 27,0 +decl (Decl +n "clk" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 1 +suid 7,0 +) +declText (MLText +uid 28,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "15000,26000,27500,26800" +st "clk : STD_LOGIC +" +) +) +*8 (PortIoIn +uid 35,0 +shape (CompositeShape +uid 36,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 37,0 +sl 0 +ro 270 +xt "4000,-1375,5500,-625" +) +(Line +uid 38,0 +sl 0 +ro 270 +xt "5500,-1000,6000,-1000" +pts [ +"5500,-1000" +"6000,-1000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 39,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 40,0 +va (VaSet +) +xt "1100,-1500,3000,-500" +st "start" +ju 2 +blo "3000,-700" +tm "WireNameMgr" +) +) +) +*9 (Net +uid 41,0 +decl (Decl +n "start" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 2 +suid 8,0 +) +declText (MLText +uid 42,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "15000,26800,27500,27600" +st "start : STD_LOGIC +" +) +) +*10 (PortIoOut +uid 49,0 +shape (CompositeShape +uid 50,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 51,0 +sl 0 +ro 270 +xt "28500,10625,30000,11375" +) +(Line +uid 52,0 +sl 0 +ro 270 +xt "28000,11000,28500,11000" +pts [ +"28000,11000" +"28500,11000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 53,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 54,0 +va (VaSet +) +xt "31000,10500,32600,11500" +st "dna" +blo "31000,11300" +tm "WireNameMgr" +) +) +) +*11 (Net +uid 55,0 +decl (Decl +n "dna" +t "STD_LOGIC_VECTOR" +b "(63 downto 0)" +preAdd 0 +posAdd 0 +o 3 +suid 9,0 +i "(others => '0')" +) +declText (MLText +uid 56,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "15000,27600,47500,28400" +st "dna : STD_LOGIC_VECTOR(63 downto 0) := (others => '0') +" +) +) +*12 (PortIoOut +uid 63,0 +shape (CompositeShape +uid 64,0 +va (VaSet +vasetType 1 +fg "0,0,32768" +) +optionalChildren [ +(Pentagon +uid 65,0 +sl 0 +ro 270 +xt "11500,-1375,13000,-625" +) +(Line +uid 66,0 +sl 0 +ro 270 +xt "11000,-1000,11500,-1000" +pts [ +"11000,-1000" +"11500,-1000" +] +) +] +) +stc 0 +sf 1 +tg (WTG +uid 67,0 +ps "PortIoTextPlaceStrategy" +stg "STSignalDisplayStrategy" +f (Text +uid 68,0 +va (VaSet +) +xt "14000,-1500,16200,-500" +st "ready" +blo "14000,-700" +tm "WireNameMgr" +) +) +) +*13 (Net +uid 69,0 +decl (Decl +n "ready" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 4 +suid 10,0 +i "'0'" +) +declText (MLText +uid 70,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "15000,28400,41500,29200" +st "ready : STD_LOGIC := '0' +" +) +) +*14 (SaComponent +uid 97,0 +optionalChildren [ +*15 (CptPort +uid 107,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 108,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "29000,2625,29750,3375" +) +tg (CPTG +uid 109,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 110,0 +va (VaSet +) +xt "25300,2500,28000,3500" +st "DOUT" +ju 2 +blo "28000,3300" +) +) +thePort (LogicalPort +m 1 +decl (Decl +n "DOUT" +t "std_ulogic" +preAdd 0 +posAdd 0 +o 1 +) +) +) +*16 (CptPort +uid 111,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 112,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "21250,1625,22000,2375" +) +tg (CPTG +uid 113,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 114,0 +va (VaSet +) +xt "23000,1500,24900,2500" +st "CLK" +blo "23000,2300" +) +) +thePort (LogicalPort +decl (Decl +n "CLK" +t "std_ulogic" +preAdd 0 +posAdd 0 +o 2 +) +) +) +*17 (CptPort +uid 115,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 116,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "21250,2625,22000,3375" +) +tg (CPTG +uid 117,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 118,0 +va (VaSet +) +xt "23000,2500,24800,3500" +st "DIN" +blo "23000,3300" +) +) +thePort (LogicalPort +decl (Decl +n "DIN" +t "std_ulogic" +preAdd 0 +posAdd 0 +o 3 +) +) +) +*18 (CptPort +uid 119,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 120,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "21250,625,22000,1375" +) +tg (CPTG +uid 121,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 122,0 +va (VaSet +) +xt "23000,500,25600,1500" +st "READ" +blo "23000,1300" +) +) +thePort (LogicalPort +decl (Decl +n "READ" +t "std_ulogic" +preAdd 0 +posAdd 0 +o 4 +) +) +) +*19 (CptPort +uid 123,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 124,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "21250,-375,22000,375" +) +tg (CPTG +uid 125,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 126,0 +va (VaSet +) +xt "23000,-500,25700,500" +st "SHIFT" +blo "23000,300" +) +) +thePort (LogicalPort +decl (Decl +n "SHIFT" +t "std_ulogic" +preAdd 0 +posAdd 0 +o 5 +) +) +) +*20 (PortMapFrame +uid 127,0 +ps "PortMapFrameStrategy" +shape (RectFrame +uid 128,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,0,32768" +lineWidth 2 +) +xt "20000,-3000,31000,6000" +) +portMapText (BiTextGroup +uid 129,0 +ps "BottomRightOffsetStrategy" +stg "VerticalLayoutStrategy" +first (MLText +uid 130,0 +va (VaSet +isHidden 1 +) +xt "31000,6000,38600,10000" +st "CLK => clk, +READ => read_sig, +SHIFT => shift_sig, +DOUT => dout_sig," +) +second (MLText +uid 131,0 +va (VaSet +isHidden 1 +) +xt "31000,10000,35400,11000" +st "DIN => '0'" +tm "PortMapTextMgr" +) +) +) +] +shape (Rectangle +uid 98,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "22000,-1000,29000,4000" +) +ttg (MlTextGroup +uid 99,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*21 (Text +uid 100,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "22050,3000,24950,4000" +st "unisim" +blo "22050,3800" +tm "BdLibraryNameMgr" +) +*22 (Text +uid 101,0 +va (VaSet +font "Arial,8,1" +) +xt "22050,4000,26750,5000" +st "DNA_PORT" +blo "22050,4800" +tm "CptNameMgr" +) +*23 (Text +uid 102,0 +va (VaSet +font "Arial,8,1" +) +xt "22050,5000,28950,6000" +st "DNA_PORT_inst" +blo "22050,5800" +tm "InstanceNameMgr" +) +] +) +ga (GenericAssociation +uid 103,0 +ps "EdgeToEdgeStrategy" +matrix (Matrix +uid 104,0 +text (MLText +uid 105,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "21150,-4300,46650,-3500" +st "SIM_DNA_VALUE = DNA_FOR_SIM ( bit_vector ) +" +) +header "" +) +elements [ +(GiElement +name "SIM_DNA_VALUE" +type "bit_vector" +value "DNA_FOR_SIM" +) +] +) +viewicon (ZoomableIcon +uid 106,0 +sl 0 +va (VaSet +vasetType 1 +fg "49152,49152,49152" +) +xt "22250,2250,23750,3750" +iconName "VhdlFileViewIcon.png" +iconMaskName "VhdlFileViewIcon.msk" +ftype 10 +) +viewiconposition 0 +portVis (PortSigDisplay +sTC 0 +) +archFileType "UNKNOWN" +) +*24 (HdlText +uid 156,0 +optionalChildren [ +*25 (SmEmbeddedModel +version "23.1" +model (StateMachine +uid 163,0 +optionalChildren [ +*26 (ConcurrentSM +uid 248,0 +topDiagram (StateDiagram +LanguageMgr "None" +uid 249,0 +optionalChildren [ +*27 (State +uid 285,0 +shape (Circle +uid 286,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "27477,4000,33477,10000" +radius 3000 +) +name (Text +uid 287,0 +va (VaSet +font "Arial,10,1" +) +xt "29027,6400,31927,7600" +st "IDLE" +ju 0 +blo "30477,7400" +tm "ONodeName" +) +wait (TextAssociate +uid 288,0 +ps "CenterOffsetStrategy" +text (Text +uid 289,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "arial,10,1" +) +xt "30577,7300,34177,8500" +st "wait 2" +blo "30577,8300" +tm "SmWaitText" +) +) +encoding (Text +uid 290,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "30477,8000,30477,8000" +blo "30477,8000" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 293,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 294,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "34377,10100,34577,10300" +) +autoResize 1 +tline (Line +uid 295,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "30477,7000,30477,7000" +pts [ +"30477,7000" +"30477,7000" +] +) +bline (Line +uid 296,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "30477,7000,30477,7000" +pts [ +"30477,7000" +"30477,7000" +] +) +ttri (Triangle +uid 297,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "30027,6825,30377,7175" +) +btri (Triangle +uid 298,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "30027,6825,30377,7175" +) +entryActions (MLText +uid 299,0 +va (VaSet +) +xt "30477,7000,30477,7000" +tm "Actions" +) +inActions (MLText +uid 300,0 +va (VaSet +) +xt "30477,7000,36677,10000" +st "ready <= '0'; +read_sig <= '0'; +shift_sig <= '0';" +tm "Actions" +) +exitActions (MLText +uid 301,0 +va (VaSet +) +xt "30477,7000,30477,7000" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 291,0 +ps "CenterOffsetStrategy" +text (MLText +uid 292,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "28877,8000,33877,9000" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*28 (State +uid 302,0 +shape (Circle +uid 303,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "52237,28740,59669,36172" +radius 3716 +) +name (Text +uid 304,0 +va (VaSet +font "Arial,10,1" +) +xt "52903,31856,59003,33056" +st "READ_DNA" +ju 0 +blo "55953,32856" +tm "ONodeName" +) +wait (TextAssociate +uid 305,0 +ps "CenterOffsetStrategy" +text (Text +uid 306,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "arial,10,1" +) +xt "56053,32756,59653,33956" +st "wait 2" +blo "56053,33756" +tm "SmWaitText" +) +) +encoding (Text +uid 307,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "55953,33456,55953,33456" +blo "55953,33456" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 310,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 311,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "59853,35556,60053,35756" +) +autoResize 1 +tline (Line +uid 312,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "55953,32456,55953,32456" +pts [ +"55953,32456" +"55953,32456" +] +) +bline (Line +uid 313,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "55953,32456,55953,32456" +pts [ +"55953,32456" +"55953,32456" +] +) +ttri (Triangle +uid 314,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "55503,32281,55853,32631" +) +btri (Triangle +uid 315,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "55503,32281,55853,32631" +) +entryActions (MLText +uid 316,0 +va (VaSet +) +xt "55953,32456,55953,32456" +tm "Actions" +) +inActions (MLText +uid 317,0 +va (VaSet +) +xt "55953,32456,62153,35456" +st "ready <= '0'; +read_sig <= '1'; +shift_sig <= '0';" +tm "Actions" +) +exitActions (MLText +uid 318,0 +va (VaSet +) +xt "55953,32456,55953,32456" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 308,0 +ps "CenterOffsetStrategy" +text (MLText +uid 309,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "54353,33456,59353,34456" +st "CASE: expr" +tm "SmCaseExpr" +) +) +impLoop 0 +) +*29 (State +uid 319,0 +shape (Circle +uid 320,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "26721,54237,34153,61669" +radius 3716 +) +name (Text +uid 321,0 +va (VaSet +font "Arial,10,1" +) +xt "27387,57353,33487,58553" +st "SHIFT_DNA" +ju 0 +blo "30437,58353" +tm "ONodeName" +) +wait (TextAssociate +uid 322,0 +ps "CenterOffsetStrategy" +text (Text +uid 323,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "arial,10,1" +) +xt "30537,58253,34137,59453" +st "wait 2" +blo "30537,59253" +tm "SmWaitText" +) +) +encoding (Text +uid 324,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "30437,58953,30437,58953" +blo "30437,58953" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 327,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 328,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "34337,61053,34537,61253" +) +autoResize 1 +tline (Line +uid 329,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "30437,57953,30437,57953" +pts [ +"30437,57953" +"30437,57953" +] +) +bline (Line +uid 330,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "30437,57953,30437,57953" +pts [ +"30437,57953" +"30437,57953" +] +) +ttri (Triangle +uid 331,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "29987,57778,30337,58128" +) +btri (Triangle +uid 332,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "29987,57778,30337,58128" +) +entryActions (MLText +uid 333,0 +va (VaSet +) +xt "30437,57953,30437,57953" +tm "Actions" +) +inActions (MLText +uid 334,0 +va (VaSet +) +xt "30437,57953,40737,60953" +st "shift_cntr <= shift_cntr + 1; +ready <= '0'; +read_sig <= '0';" +tm "Actions" +) +exitActions (MLText +uid 335,0 +va (VaSet +) +xt "30437,57953,30437,57953" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 325,0 +ps "CenterOffsetStrategy" +text (MLText +uid 326,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "28837,58953,33837,59953" +st "CASE: expr" +tm "SmCaseExpr" +) +) +impLoop 0 +) +*30 (State +uid 336,0 +shape (Circle +uid 337,0 +va (VaSet +vasetType 1 +fg "0,65535,65535" +lineColor "0,32768,49152" +lineWidth 2 +) +xt "949,28404,9053,36508" +radius 4052 +) +name (Text +uid 338,0 +va (VaSet +font "Arial,10,1" +) +xt "1601,31856,8401,33056" +st "DNA_READY" +ju 0 +blo "5001,32856" +tm "ONodeName" +) +wait (TextAssociate +uid 339,0 +ps "CenterOffsetStrategy" +text (Text +uid 340,0 +va (VaSet +isHidden 1 +fg "0,0,32768" +font "arial,10,1" +) +xt "5101,32756,8701,33956" +st "wait 2" +blo "5101,33756" +tm "SmWaitText" +) +) +encoding (Text +uid 341,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "5001,33456,5001,33456" +blo "5001,33456" +tm "SmEncodingMgr" +) +actionBlk (SmStateActionsBlock +uid 344,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 345,0 +va (VaSet +vasetType 1 +isHidden 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "8901,35556,9101,35756" +) +autoResize 1 +tline (Line +uid 346,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "5001,32456,5001,32456" +pts [ +"5001,32456" +"5001,32456" +] +) +bline (Line +uid 347,0 +va (VaSet +vasetType 3 +isHidden 1 +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "5001,32456,5001,32456" +pts [ +"5001,32456" +"5001,32456" +] +) +ttri (Triangle +uid 348,0 +ro 90 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "4551,32281,4901,32631" +) +btri (Triangle +uid 349,0 +ro 270 +va (VaSet +vasetType 1 +isHidden 1 +fg "0,32768,49152" +bg "0,0,0" +lineColor "39936,56832,65280" +lineWidth -1 +) +xt "4551,32281,4901,32631" +) +entryActions (MLText +uid 350,0 +va (VaSet +) +xt "5001,32456,5001,32456" +tm "Actions" +) +inActions (MLText +uid 351,0 +va (VaSet +) +xt "5001,32456,11201,35456" +st "ready <= '1'; +read_sig <= '0'; +shift_sig <= '0';" +tm "Actions" +) +exitActions (MLText +uid 352,0 +va (VaSet +) +xt "5001,32456,5001,32456" +tm "Actions" +) +) +caseExpr (TextAssociate +uid 342,0 +ps "CenterOffsetStrategy" +text (MLText +uid 343,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "3401,33456,8401,34456" +st "CASE: expr" +tm "SmCaseExpr" +) +) +) +*31 (SmClockPoint +uid 353,0 +shape (CompositeShape +uid 354,0 +va (VaSet +vasetType 1 +fg "65535,65535,0" +) +optionalChildren [ +(Pentagon +uid 355,0 +sl 0 +ro 270 +xt "-176,-1500,2074,-500" +) +(OrthoPolyLine +uid 356,0 +sl 0 +ro 270 +va (VaSet +vasetType 3 +isHidden 1 +) +xt "724,-1300,1323,-700" +pts [ +"724,-1300" +"1023,-1300" +"1023,-700" +"1323,-700" +] +) +(Arc2D +pts [ +"333,-847" +"78,-1153" +"333,-1153" +] +uid 357,0 +sl 0 +ro 270 +va (VaSet +vasetType 1 +transparent 1 +) +xt "78,-1153,333,-847" +) +] +) +name (TextAssociate +uid 358,0 +ps "CenterOffsetStrategy" +text (Text +uid 359,0 +va (VaSet +font "arial,8,0" +) +xt "-1976,-1500,-676,-500" +st "clk" +ju 2 +blo "-676,-700" +tm "SmControlSignalNameMgr" +) +) +cond (SmControlCondition +uid 360,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 361,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "0,32768,49152" +) +xt "2074,-1600,9474,-400" +) +autoResize 1 +cond (MLText +uid 362,0 +va (VaSet +font "arial,8,0" +) +xt "2174,-1500,9374,-500" +st " Falling_edge(clk) " +tm "SmControlConditionMgr" +) +) +edge 2 +) +*32 (CommentText +uid 403,0 +shape (Rectangle +uid 404,0 +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "2949,-4000,35949,2000" +) +text (MLText +uid 405,0 +va (VaSet +fg "0,0,32768" +font "Arial,10,0" +) +xt "3149,-3800,35149,1400" +st " +Created using Mentor Graphics HDL2Graphics(TM) Technology +on - 09:15:09 15.02.2011 +from - C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl\\dna_gen.vhd + +" +tm "CommentText" +wrapOption 3 +visibleHeight 5600 +visibleWidth 32600 +) +) +*33 (Grouping +uid 406,0 +optionalChildren [ +*34 (CommentText +uid 408,0 +shape (Rectangle +uid 409,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "34000,43000,51000,44000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 410,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "34200,43000,43800,44000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*35 (CommentText +uid 411,0 +shape (Rectangle +uid 412,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "51000,39000,55000,40000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 413,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "51200,39000,54200,40000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*36 (CommentText +uid 414,0 +shape (Rectangle +uid 415,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "34000,41000,51000,42000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 416,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "34200,41000,44200,42000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*37 (CommentText +uid 417,0 +shape (Rectangle +uid 418,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "30000,41000,34000,42000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 419,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "30200,41000,32300,42000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*38 (CommentText +uid 420,0 +shape (Rectangle +uid 421,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "51000,40000,71000,44000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 422,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "51200,40200,60400,41200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*39 (CommentText +uid 423,0 +shape (Rectangle +uid 424,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "55000,39000,71000,40000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 425,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "55200,39000,59700,40000" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*40 (CommentText +uid 426,0 +shape (Rectangle +uid 427,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "30000,39000,51000,41000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 428,0 +va (VaSet +fg "32768,0,0" +) +xt "37150,39500,43850,40500" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*41 (CommentText +uid 429,0 +shape (Rectangle +uid 430,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "30000,42000,34000,43000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 431,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "30200,42000,32300,43000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*42 (CommentText +uid 432,0 +shape (Rectangle +uid 433,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "30000,43000,34000,44000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 434,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "30200,43000,32900,44000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*43 (CommentText +uid 435,0 +shape (Rectangle +uid 436,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "34000,42000,51000,43000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 437,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "34200,42000,43200,43000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 407,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "30000,39000,71000,44000" +) +oxt "14000,66000,55000,71000" +) +*44 (Transition +uid 363,0 +shape (Spline +uid 364,0 +va (VaSet +vasetType 3 +) +xt "32281,9396,52983,30224" +pts [ +"32281,9396" +"41416,21528" +"52983,30224" +] +arrow 1 +) +start &27 +end &28 +ss 0 +es 0 +cond "(start = '1')" +tb (TransitionBlock +uid 365,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 366,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +lineColor "0,32768,49152" +) +xt "40916,21028,46516,23028" +) +autoResize 1 +lineShape (Line +uid 367,0 +va (VaSet +vasetType 3 +isHidden 1 +) +xt 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"C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\dna_gen\\symbol.sb.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\dna_gen\\symbol.sb.user" +) +(vvPair +variable "SourceDir" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "symbol" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\dna_gen" +) +(vvPair +variable "d_logical" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\dna_gen" +) +(vvPair +variable "date" +value "15.02.2011" +) +(vvPair +variable "day" +value "Di" +) +(vvPair +variable "day_long" +value "Dienstag" +) +(vvPair +variable "dd" +value "15" +) +(vvPair +variable "entity_name" +value "dna_gen" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "E5B-LABOR6" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "FACT_FAD_lib" +) +(vvPair +variable "library_downstream_HdsLintPlugin" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/designcheck" +) +(vvPair +variable "library_downstream_ISEPARInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ImpactInvoke" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/work" +) +(vvPair +variable "library_downstream_XSTDataPrep" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" +) +(vvPair +variable "mm" +value "02" +) +(vvPair +variable "module_name" +value "dna_gen" +) +(vvPair +variable "month" +value "Feb" +) +(vvPair +variable "month_long" +value "Februar" +) +(vvPair +variable "p" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\dna_gen\\symbol.sb" +) +(vvPair +variable "p_logical" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\dna_gen\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "FACT_FAD" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "C:\\modeltech_6.6a\\win32" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "09:17:34" +) +(vvPair +variable "unit" +value "dna_gen" +) +(vvPair +variable "user" +value "dneise" +) +(vvPair +variable "version" +value "2009.2 (Build 10)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2011" +) +(vvPair +variable "yy" +value "11" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 82,0 +optionalChildren [ +*59 (SymbolBody +uid 8,0 +optionalChildren [ +*60 (CptPort +uid 48,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 49,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "38250,3625,39000,4375" +) +tg (CPTG +uid 50,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 51,0 +va (VaSet +) +xt "40000,3500,41300,4500" +st "clk" +blo "40000,4300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 52,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,14000,17000,14800" +st "clk : IN STD_LOGIC ; +" +) +thePort (LogicalPort +decl (Decl +n "clk" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 1 +suid 1,0 +) +) +) +*61 (CptPort +uid 53,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 54,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "38250,5625,39000,6375" +) +tg (CPTG +uid 55,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 56,0 +va (VaSet +) +xt "40000,5500,41900,6500" +st "start" +blo "40000,6300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 57,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,14800,17000,15600" +st "start : IN STD_LOGIC ; +" +) +thePort (LogicalPort +decl (Decl +n "start" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 2 +suid 2,0 +) +) +) +*62 (CptPort +uid 58,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 59,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "49000,3625,49750,4375" +) +tg (CPTG +uid 60,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 61,0 +va (VaSet +) +xt "46400,3500,48000,4500" +st "dna" +ju 2 +blo "48000,4300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 62,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,15600,37000,16400" +st "dna : OUT STD_LOGIC_VECTOR (63 downto 0) := (others => '0') ; +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "dna" +t "STD_LOGIC_VECTOR" +b "(63 downto 0)" +preAdd 0 +posAdd 0 +o 3 +suid 3,0 +i "(others => '0')" +) +) +) +*63 (CptPort +uid 63,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 64,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "49000,5625,49750,6375" +) +tg (CPTG +uid 65,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 66,0 +va (VaSet +) +xt "45800,5500,48000,6500" +st "ready" +ju 2 +blo "48000,6300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 67,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,16400,30000,17200" +st "ready : OUT STD_LOGIC := '0' +" +) +thePort (LogicalPort +m 1 +decl (Decl +n "ready" +t "STD_LOGIC" +preAdd 0 +posAdd 0 +o 4 +suid 4,0 +i "'0'" +) +) +) +] +shape (Rectangle +uid 9,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "39000,2000,49000,12000" +) +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "Arial,8,1" +) +xt "42200,6000,48400,7000" +st "FACT_FAD_lib" +blo "42200,6800" +) +second (Text +uid 12,0 +va (VaSet +font "Arial,8,1" +) +xt "42200,7000,45800,8000" +st "dna_gen" +blo "42200,7800" +) +) +gi *64 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "Courier New,8,0" +) +xt "39000,200,50500,1000" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sTC 0 +) +) +*65 (Grouping +uid 16,0 +optionalChildren [ +*66 (CommentText +uid 18,0 +shape (Rectangle +uid 19,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "43000,20000,60000,21000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 20,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "43200,20000,52800,21000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*67 (CommentText +uid 21,0 +shape (Rectangle +uid 22,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "60000,16000,64000,17000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 23,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "60200,16000,63200,17000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*68 (CommentText +uid 24,0 +shape (Rectangle +uid 25,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "43000,18000,60000,19000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 26,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "43200,18000,53200,19000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*69 (CommentText +uid 27,0 +shape (Rectangle +uid 28,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,18000,43000,19000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 29,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "39200,18000,41300,19000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*70 (CommentText +uid 30,0 +shape (Rectangle +uid 31,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "60000,17000,80000,21000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 32,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "60200,17200,69400,18200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +titleBlock 1 +) +*71 (CommentText +uid 33,0 +shape (Rectangle +uid 34,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "64000,16000,80000,17000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 35,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "64200,16000,68700,17000" +st " +%project_name +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*72 (CommentText +uid 36,0 +shape (Rectangle +uid 37,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,16000,60000,18000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 38,0 +va (VaSet +fg "32768,0,0" +) +xt "46150,16500,52850,17500" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*73 (CommentText +uid 39,0 +shape (Rectangle +uid 40,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,19000,43000,20000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 41,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "39200,19000,41300,20000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*74 (CommentText +uid 42,0 +shape (Rectangle +uid 43,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,20000,43000,21000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 44,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "39200,20000,41900,21000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +*75 (CommentText +uid 45,0 +shape (Rectangle +uid 46,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "43000,19000,60000,20000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 47,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "43200,19000,55300,20000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +titleBlock 1 +) +] +shape (GroupingShape +uid 17,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "39000,16000,80000,21000" +) +oxt "14000,66000,55000,71000" +) +*76 (CommentText +uid 68,0 +shape (Rectangle +uid 69,0 +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,-6000,33000,0" +) +text (MLText +uid 70,0 +va (VaSet +fg "0,0,32768" +font "Arial,10,0" +) +xt "200,-5800,32200,-600" +st " +Created using Mentor Graphics HDL2Graphics(TM) Technology +on - 09:15:09 15.02.2011 +from - C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl\\dna_gen.vhd + +" +tm "CommentText" +wrapOption 3 +visibleHeight 5600 +visibleWidth 32600 +) +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "26368,26368,26368" +) +packageList *77 (PackageList +uid 79,0 +stg "VerticalLayoutStrategy" +textVec [ +*78 (Text +uid 80,0 +va (VaSet +font "arial,8,1" +) +xt "0,1000,5400,2000" +st "Package List" +blo "0,1800" +) +*79 (MLText +uid 81,0 +va (VaSet +) +xt "0,2000,22500,11000" +st "library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all;" +tm "PackageList" +) +] +) +windowSize "0,0,1015,690" +viewArea "0,0,0,0" +cachedDiagramExtent "0,0,0,0" +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +) +xt "200,200,2000,1200" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Arial,8,1" +) +xt "1000,1000,3800,2000" +st "Panel0" +blo "1000,1800" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "" +entityName "" +viewName "" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,33000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,15000,25800,16000" +st "" +blo "22200,15800" +) +second (Text +va (VaSet +font "Arial,8,1" +) +xt "22200,16000,24800,17000" +st "" +blo "22200,16800" +) +) +gi *80 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sIVOD 1 +) +portVis (PortSigDisplay +sIVOD 1 +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,1400,1750" +st "In0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,2800,1750" +st "Buffer0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *81 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "0,12000,5400,13000" +st "Declarations" +blo "0,12800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "0,13000,2700,14000" +st "Ports:" +blo "0,13800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "0,17200,2400,18200" +st "User:" +blo "0,18000" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "0,12000,5800,13000" +st "Internal User:" +blo "0,12800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,18200,2000,18200" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "0,12000,0,12000" +tm "SyDeclarativeTextMgr" +) +) +lastUid 138,0 +activeModelName "Symbol:CDM" +) Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/phase_shifter/symbol.sb =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/phase_shifter/symbol.sb (revision 10154) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/phase_shifter/symbol.sb (revision 10155) @@ -27,5 +27,5 @@ ldm (LogicalDM ordering 1 -suid 15,0 +suid 17,0 usingSuid 1 emptyRow *1 (LEmptyRow @@ -144,4 +144,5 @@ n "LOCKED" t "std_logic" +eolc "-- when is this going high?" preAdd 0 posAdd 0 @@ -189,5 +190,5 @@ preAdd 0 posAdd 0 -o 10 +o 11 suid 10,0 i "'0'" @@ -204,5 +205,5 @@ preAdd 0 posAdd 0 -o 11 +o 12 suid 11,0 i "'0'" @@ -220,5 +221,5 @@ preAdd 0 posAdd 0 -o 12 +o 13 suid 12,0 i "(OTHERS => '0')" @@ -231,26 +232,27 @@ m 1 decl (Decl -n "DCM_locked" -t "std_logic" -preAdd 0 -posAdd 0 -o 13 -suid 13,0 -) -) -uid 148,0 +n "rst" +t "std_logic" +eolc "--asynch in of DCM" +posAdd 0 +o 2 +suid 15,0 +i "'0'" +) +) +uid 286,0 ) *26 (LogPort port (LogicalPort decl (Decl -n "rst" -t "std_logic" -eolc "--asynch in of DCM" -posAdd 0 -o 2 -suid 15,0 -) -) -uid 286,0 +n "reset_DCM" +t "std_logic" +eolc "-- asynch in: orders us, to reset the DCM" +posAdd 0 +o 10 +suid 17,0 +) +) +uid 369,0 ) ] @@ -374,5 +376,5 @@ pos 11 dimension 20 -uid 149,0 +uid 287,0 ) *44 (MRCItem @@ -380,5 +382,5 @@ pos 12 dimension 20 -uid 287,0 +uid 370,0 ) ] @@ -651,17 +653,17 @@ (vvPair variable "date" -value "04.02.2011" +value "12.02.2011" ) (vvPair variable "day" -value "Fr" +value "Sa" ) (vvPair variable "day_long" -value "Freitag" +value "Samstag" ) (vvPair variable "dd" -value "04" +value "12" ) (vvPair @@ -799,5 +801,5 @@ (vvPair variable "time" -value "11:34:15" +value "13:16:20" ) (vvPair @@ -889,5 +891,5 @@ fg "0,65535,0" ) -xt "63000,8625,63750,9375" +xt "65000,8625,65750,9375" ) tg (CPTG @@ -899,8 +901,8 @@ va (VaSet ) -xt "59100,8500,62000,9500" +xt "61100,8500,64000,9500" st "PSCLK" ju 2 -blo "62000,9300" +blo "64000,9300" tm "CptPortNameMgr" ) @@ -939,5 +941,5 @@ fg "0,65535,0" ) -xt "63000,10625,63750,11375" +xt "65000,10625,65750,11375" ) tg (CPTG @@ -949,8 +951,8 @@ va (VaSet ) -xt "59500,10500,62000,11500" +xt "61500,10500,64000,11500" st "PSEN" ju 2 -blo "62000,11300" +blo "64000,11300" tm "CptPortNameMgr" ) @@ -988,5 +990,5 @@ fg "0,65535,0" ) -xt "63000,12625,63750,13375" +xt "65000,12625,65750,13375" ) tg (CPTG @@ -998,8 +1000,8 @@ va (VaSet ) -xt "57500,12500,62000,13500" +xt "59500,12500,64000,13500" st "PSINCDEC" ju 2 -blo "62000,13300" +blo "64000,13300" tm "CptPortNameMgr" ) @@ -1106,6 +1108,6 @@ font "Courier New,8,0" ) -xt "2000,13600,20000,14400" -st "LOCKED : IN std_logic ; +xt "2000,13600,34500,14400" +st "LOCKED : IN std_logic ; -- when is this going high? " ) @@ -1114,4 +1116,5 @@ n "LOCKED" t "std_logic" +eolc "-- when is this going high?" preAdd 0 posAdd 0 @@ -1226,5 +1229,5 @@ fg "0,65535,0" ) -xt "63000,14625,63750,15375" +xt "65000,14625,65750,15375" ) tg (CPTG @@ -1236,8 +1239,8 @@ va (VaSet ) -xt "59100,14500,62000,15500" +xt "61100,14500,64000,15500" st "shifting" ju 2 -blo "62000,15300" +blo "64000,15300" tm "CptPortNameMgr" ) @@ -1248,5 +1251,5 @@ font "Courier New,8,0" ) -xt "2000,16800,33500,18400" +xt "2000,17600,33500,19200" st "-- status: shifting : OUT std_logic := '0' ; @@ -1261,5 +1264,5 @@ preAdd 0 posAdd 0 -o 10 +o 11 suid 10,0 i "'0'" @@ -1277,5 +1280,5 @@ fg "0,65535,0" ) -xt "63000,16625,63750,17375" +xt "65000,16625,65750,17375" ) tg (CPTG @@ -1287,8 +1290,8 @@ va (VaSet ) -xt "59800,16500,62000,17500" +xt "61800,16500,64000,17500" st "ready" ju 2 -blo "62000,17300" +blo "64000,17300" tm "CptPortNameMgr" ) @@ -1299,5 +1302,5 @@ font "Courier New,8,0" ) -xt "2000,18400,33500,19200" +xt "2000,19200,33500,20000" st "ready : OUT std_logic := '0' ; " @@ -1310,5 +1313,5 @@ preAdd 0 posAdd 0 -o 11 +o 12 suid 11,0 i "'0'" @@ -1326,5 +1329,5 @@ fg "0,65535,0" ) -xt "63000,18625,63750,19375" +xt "65000,18625,65750,19375" ) tg (CPTG @@ -1336,8 +1339,8 @@ va (VaSet ) -xt "59800,18500,62000,19500" +xt "61800,18500,64000,19500" st "offset" ju 2 -blo "62000,19300" +blo "64000,19300" tm "CptPortNameMgr" ) @@ -1348,6 +1351,6 @@ font "Courier New,8,0" ) -xt "2000,19200,39500,20000" -st "offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') ; +xt "2000,20000,38500,20800" +st "offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') " ) @@ -1360,5 +1363,5 @@ preAdd 0 posAdd 0 -o 12 +o 13 suid 12,0 i "(OTHERS => '0')" @@ -1366,53 +1369,5 @@ ) ) -*89 (CptPort -uid 108,0 -ps "OnEdgeStrategy" -shape (Triangle -uid 109,0 -ro 90 -va (VaSet -vasetType 1 -fg "0,65535,0" -) -xt "63000,20625,63750,21375" -) -tg (CPTG -uid 110,0 -ps "CptPortTextPlaceStrategy" -stg "RightVerticalLayoutStrategy" -f (Text -uid 111,0 -va (VaSet -) -xt "56800,20500,62000,21500" -st "DCM_locked" -ju 2 -blo "62000,21300" -tm "CptPortNameMgr" -) -) -dt (MLText -uid 112,0 -va (VaSet -font "Courier New,8,0" -) -xt "2000,20000,19000,20800" -st "DCM_locked : OUT std_logic -" -) -thePort (LogicalPort -m 1 -decl (Decl -n "DCM_locked" -t "std_logic" -preAdd 0 -posAdd 0 -o 13 -suid 13,0 -) -) -) -*90 (CommentText +*89 (CommentText uid 121,0 ps "EdgeToEdgeStrategy" @@ -1445,10 +1400,10 @@ excludeCommentLeader 1 ) -*91 (CptPort +*90 (CptPort uid 281,0 ps "OnEdgeStrategy" shape (Triangle -uid 282,0 -ro 90 +uid 394,0 +ro 270 va (VaSet vasetType 1 @@ -1476,9 +1431,10 @@ font "Courier New,8,0" ) -xt "2000,8800,30000,9600" -st "rst : IN std_logic ; --asynch in of DCM +xt "2000,8800,43000,9600" +st "rst : OUT std_logic := '0' ; --asynch in of DCM " ) thePort (LogicalPort +m 1 decl (Decl n "rst" @@ -1488,4 +1444,51 @@ o 2 suid 15,0 +i "'0'" +) +) +) +*91 (CptPort +uid 362,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 363,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "49250,21625,50000,22375" +) +tg (CPTG +uid 364,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 365,0 +va (VaSet +) +xt "51000,21500,55400,22500" +st "reset_DCM" +blo "51000,22300" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 366,0 +va (VaSet +font "Courier New,8,0" +) +xt "2000,16800,41500,17600" +st "reset_DCM : IN std_logic ; -- asynch in: orders us, to reset the DCM +" +) +thePort (LogicalPort +decl (Decl +n "reset_DCM" +t "std_logic" +eolc "-- asynch in: orders us, to reset the DCM" +posAdd 0 +o 10 +suid 17,0 ) ) @@ -1500,6 +1503,7 @@ lineWidth 2 ) -xt "50000,7000,63000,25000" -) +xt "50000,7000,65000,25000" +) +oxt "50000,7000,63000,25000" biTextGroup (BiTextGroup uid 10,0 @@ -2189,5 +2193,5 @@ ) ) -lastUid 333,0 +lastUid 394,0 activeModelName "Symbol:CDM" ) Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/trigger_counter/symbol.sb =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/trigger_counter/symbol.sb (revision 10154) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/trigger_counter/symbol.sb (revision 10155) @@ -72,5 +72,5 @@ n "trigger_id" t "std_logic_vector" -b "(47 downto 0)" +b "(31 downto 0)" preAdd 0 posAdd 0 @@ -404,21 +404,21 @@ (vvPair variable "HDLDir" -value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hdl" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hdl" ) (vvPair variable "HDSDir" -value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" ) (vvPair variable "SideDataDesignDir" -value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\trigger_counter\\symbol.sb.info" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\trigger_counter\\symbol.sb.info" ) (vvPair variable "SideDataUserDir" -value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\trigger_counter\\symbol.sb.user" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\trigger_counter\\symbol.sb.user" ) (vvPair variable "SourceDir" -value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds" ) (vvPair @@ -436,13 +436,13 @@ (vvPair variable "d" -value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\trigger_counter" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\trigger_counter" ) (vvPair variable "d_logical" -value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\trigger_counter" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\trigger_counter" ) (vvPair variable "date" -value "22.06.2010" +value "15.02.2011" ) (vvPair @@ -456,5 +456,5 @@ (vvPair variable "dd" -value "22" +value "15" ) (vvPair @@ -484,5 +484,5 @@ (vvPair variable "host" -value "TU-CC4900F8C7D2" +value "E5B-LABOR6" ) (vvPair @@ -495,4 +495,8 @@ ) (vvPair +variable "library_downstream_HdsLintPlugin" +value "$HDS_PROJECT_DIR/FACT_FAD_lib/designcheck" +) +(vvPair variable "library_downstream_ISEPARInvoke" value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise" @@ -512,5 +516,5 @@ (vvPair variable "mm" -value "06" +value "02" ) (vvPair @@ -520,17 +524,17 @@ (vvPair variable "month" -value "Jun" +value "Feb" ) (vvPair variable "month_long" -value "Juni" +value "Februar" ) (vvPair variable "p" -value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\trigger_counter\\symbol.sb" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\trigger_counter\\symbol.sb" ) (vvPair variable "p_logical" -value "C:\\FPGA_projects\\FACT_FAD_22062010\\FACT_FAD_lib\\hds\\trigger_counter\\symbol.sb" +value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_lib\\hds\\trigger_counter\\symbol.sb" ) (vvPair @@ -556,5 +560,5 @@ (vvPair variable "task_ModelSimPath" -value "" +value "C:\\modeltech_6.6a\\win32" ) (vvPair @@ -588,5 +592,5 @@ (vvPair variable "time" -value "10:22:01" +value "09:26:17" ) (vvPair @@ -608,9 +612,9 @@ (vvPair variable "year" -value "2010" +value "2011" ) (vvPair variable "yy" -value "10" +value "11" ) ] @@ -655,5 +659,6 @@ ) xt "2000,9000,30000,9800" -st "trigger_id : OUT std_logic_vector (47 downto 0) ;" +st "trigger_id : OUT std_logic_vector (31 downto 0) ; +" ) thePort (LogicalPort @@ -663,5 +668,5 @@ n "trigger_id" t "std_logic_vector" -b "(47 downto 0)" +b "(31 downto 0)" preAdd 0 posAdd 0 @@ -703,5 +708,6 @@ ) xt "2000,9800,19500,10600" -st "trigger : IN std_logic ;" +st "trigger : IN std_logic ; +" ) thePort (LogicalPort @@ -749,5 +755,6 @@ ) xt "2000,10600,18500,11400" -st "clk : IN std_logic " +st "clk : IN std_logic +" ) thePort (LogicalPort @@ -844,5 +851,5 @@ bg "0,0,32768" ) -xt "36200,20000,44500,21000" +xt "36200,20000,45700,21000" st " by %user on %dd %month %year @@ -1460,5 +1467,5 @@ ) ) -lastUid 177,0 +lastUid 200,0 activeModelName "Symbol:CDM" ) Index: /firmware/FAD/doc/memory_manager.tex =================================================================== --- /firmware/FAD/doc/memory_manager.tex (revision 10154) +++ /firmware/FAD/doc/memory_manager.tex (revision 10155) @@ -194,7 +194,8 @@ 0x200A & trg pos 3 & trg pos 2 & trg pos 1 & trg pos 0 \\ 0x200B & ROI 3 & ROI 2 & ROI 1 & ROI 0 \\ -0x200C & data adc3 & data adc2 & data adc1 & data adc0 \\ +0x200C & -fill- & -fill- & -fill- & -fill- \\ +0x200D & data adc3 & data adc2 & data adc1 & data adc0 \\ 0x20.. &&&& ... \\ -0x206F & data adc3 & data adc2 & data adc1 & data adc0 \\ +0x2070 & data adc3 & data adc2 & data adc1 & data adc0 \\ \hline 0x20.. &&&& ... \\ @@ -203,4 +204,5 @@ 0x23?? & trg pos 3 & trg pos 2 & trg pos 1 & trg pos 0 \\ 0x23?? & ROI 3 & ROI 2 & ROI 1 & ROI 0 \\ +0x23?? & -fill- & -fill- & -fill- & -fill- \\ 0x23?? & data adc3 & data adc2 & data adc1 & data adc0 \\ 0x23.. &&&& ... \\ @@ -318,4 +320,5 @@ unsigned short start_cell; unsigned short roi; + unsigned short filling; unsigned short adc_data[]; } __attribute__((__packed__)) PCHANNEL; @@ -327,4 +330,34 @@ \end{verbatim} +\subsection{mem manager calculations} + +Memory manager knows the size of FADs internal data RAM. This is implemented as VHDL-Generics called {\tt RAM_ADD_WIDTH_64B} +and {\tt RAM_ADD_WIDTH_16B}. Since word width is 64bit on the input side and 16bit on the outpt two generics are used. +Currently the values are: +\begin{table}[htbp] +\begin{tabular}{ll} +RAM_ADD_WIDTH_64B & 12 \\ +RAM_ADD_WIDTH_16B & 14 \\ +\end {tabular} +\caption{values of RAM width} +\label{RAM_GENERICS} +\end{table} + +Which results in +\begin{equation} +\mathtt{RAM size} = 2^{12} \cdot 8 byte= 2^14 * 2 byte = 32768 byte . +\end{equation} + +Now the memory manager is able to calculate the number of Events, fitting into this RAM. + +The number of samples of each channel beeing digitized is called region of interest(ROI). Since the ROI of each of the 36 input channel may be defined independently, but the RAM is organized in 64bit words on the input side, the memory manager needs to calculate the effective ROI of each channel first. The DRS Chips are digitized in a parallel manner, but their 9 channels are digitized serially. So first each DRS is ordered to output its channel 0 data, until as many samples are digitized as the maximum of all channel 0 ROIs is. + +In the states called MAX_ROI0..2 the array containing the maxima of each group of channels is calculated. +In addition the so called channel size array is calculated. This is the number of 16bit words which is needed to store a group of +channels in the W5300 FIFO. The header is included into the group of channels 0, while the package footer is included into group of channels 9. + +In the next state called FIFO CALC. Here + + \end{document}