Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/dna_gen.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/dna_gen.vhd (revision 10169) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/dna_gen.vhd (revision 10170) @@ -32,5 +32,4 @@ Port ( clk : IN STD_LOGIC; - start : IN STD_LOGIC; dna : OUT STD_LOGIC_VECTOR(63 downto 0) := (others => '0'); ready : OUT STD_LOGIC := '0' @@ -49,4 +48,5 @@ signal shift_cntr : INTEGER range 0 to 64 := 0; + signal start_sig : std_logic := '0'; begin @@ -66,4 +66,7 @@ begin if Falling_edge(clk) then + if (start_sig = '0') then + start_sig <= '1'; + end if; case FTU_dna_gen_State is when IDLE => @@ -71,5 +74,5 @@ read_sig <= '0'; shift_sig <= '0'; - if (start = '1') then + if (start_sig = '1') then FTU_dna_gen_State <= READ_DNA; else @@ -99,4 +102,5 @@ when DNA_READY => ready <= '1'; + start_sig <= '0'; read_sig <= '0'; shift_sig <= '0'; Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd (revision 10169) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd (revision 10170) @@ -3,5 +3,5 @@ -- Created: -- by - dneise.UNKNOWN (E5B-LABOR6) --- at - 13:26:28 14.02.2011 +-- at - 17:38:00 16.02.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) @@ -76,5 +76,5 @@ -- Created: -- by - dneise.UNKNOWN (E5B-LABOR6) --- at - 13:26:28 14.02.2011 +-- at - 17:38:00 16.02.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd (revision 10169) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd (revision 10170) @@ -54,9 +54,9 @@ constant PACKAGE_VERSION : std_logic_vector(7 downto 0) := X"01"; constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"02"; - constant PACKAGE_HEADER_LENGTH : integer := 22; - constant PACKAGE_HEADER_ZEROS : integer := 6; + constant PACKAGE_HEADER_LENGTH : integer := 36; + constant PACKAGE_HEADER_ZEROS : integer := 0; constant PACKAGE_END_LENGTH : integer := 2; -- CRC and END-Flag constant PACKAGE_END_ZEROS : integer := 2; - constant CHANNEL_HEADER_SIZE : integer := 3; + constant CHANNEL_HEADER_SIZE : integer := 4; constant NUMBER_OF_DRS : integer := 4; Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd (revision 10169) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd (revision 10170) @@ -1,814 +1,0 @@ --- VHDL Entity FACT_FAD_lib.FAD_main.symbol --- --- Created: --- by - dneise.UNKNOWN (E5B-LABOR6) --- at - 13:26:27 14.02.2011 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) --- -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_arith.all; -LIBRARY FACT_FAD_lib; -USE FACT_FAD_lib.fad_definitions.all; - -ENTITY FAD_main IS - GENERIC( - RAMADDRWIDTH64b : integer := 12 - ); - PORT( - CLK : IN std_logic; - D_T_in : IN std_logic_vector (1 DOWNTO 0); - SROUT_in_0 : IN std_logic; - SROUT_in_1 : IN std_logic; - SROUT_in_2 : IN std_logic; - SROUT_in_3 : IN std_logic; - adc_data_array : IN adc_data_array_type; - adc_otr_array : IN std_logic_vector (3 DOWNTO 0); - board_id : IN std_logic_vector (3 DOWNTO 0); - crate_id : IN std_logic_vector (1 DOWNTO 0); - drs_refclk_in : IN std_logic; -- used to check if DRS REFCLK exsists, if not DENABLE inhibit - plllock_in : IN std_logic_vector (3 DOWNTO 0); -- high level, if dominowave is running and DRS PLL locked - trigger : IN std_logic; - wiz_int : IN std_logic; - CLK_25_PS : OUT std_logic; - CLK_50 : OUT std_logic; - RSRLOAD : OUT std_logic := '0'; - SRCLK : OUT std_logic := '0'; - SRIN_out : OUT std_logic := '0'; - adc_clk_en : OUT std_logic := '0'; - adc_oeb : OUT std_logic := '1'; - additional_flasher_out : OUT std_logic; - alarm_refclk_too_high : OUT std_logic := '0'; -- default domino wave off - alarm_refclk_too_low : OUT std_logic := '0'; -- default domino wave off - amber : OUT std_logic; - counter_result : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); - dac_cs : OUT std_logic; - denable : OUT std_logic := '0'; -- default domino wave off - drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); - drs_dwrite : OUT std_logic := '1'; - green : OUT std_logic; - led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); - mosi : OUT std_logic := '0'; - red : OUT std_logic; - sclk : OUT std_logic; - sensor_cs : OUT std_logic_vector (3 DOWNTO 0); - wiz_addr : OUT std_logic_vector (9 DOWNTO 0); - wiz_cs : OUT std_logic := '1'; - wiz_rd : OUT std_logic := '1'; - wiz_reset : OUT std_logic := '1'; - wiz_wr : OUT std_logic := '1'; - sio : INOUT std_logic; - wiz_data : INOUT std_logic_vector (15 DOWNTO 0) - ); - --- Declarations - -END FAD_main ; - --- --- VHDL Architecture FACT_FAD_lib.FAD_main.struct --- --- Created: --- by - dneise.UNKNOWN (E5B-LABOR6) --- at - 13:26:28 14.02.2011 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) --- -library ieee; -use ieee.std_logic_1164.all; -use IEEE.STD_LOGIC_ARITH.all; -use ieee.STD_LOGIC_UNSIGNED.all; - -library fact_fad_lib; -use fact_fad_lib.fad_definitions.all; - -library UNISIM; ---use UNISIM.VComponents.all; -USE IEEE.NUMERIC_STD.all; -USE IEEE.std_logic_signed.all; - -LIBRARY FACT_FAD_lib; - -ARCHITECTURE struct OF FAD_main IS - - -- Architecture declarations - - -- Internal signal declarations - SIGNAL CLK_25 : std_logic; - SIGNAL SRCLK1 : std_logic := '0'; - SIGNAL adc_data_array_int : adc_data_array_type; - SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0); - SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0); - SIGNAL c_trigger_enable : std_logic := '0'; - SIGNAL c_trigger_mult : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1'); --subject to changes - SIGNAL config_addr : std_logic_vector(7 DOWNTO 0); - SIGNAL config_busy : std_logic; - SIGNAL config_data : std_logic_vector(15 DOWNTO 0); - SIGNAL config_data_valid : std_logic; - SIGNAL config_rd_en : std_logic; - SIGNAL config_ready : std_logic; - SIGNAL config_ready_cm : std_logic; - SIGNAL config_ready_spi : std_logic; - -- -- - SIGNAL config_rw_ack : std_logic := '0'; - -- -- - SIGNAL config_rw_ready : std_logic := '0'; - SIGNAL config_start : std_logic := '0'; - SIGNAL config_start_cm : std_logic; - SIGNAL config_start_spi : std_logic := '0'; - SIGNAL config_started : std_logic; - SIGNAL config_started_cu : std_logic := '0'; - SIGNAL config_started_mm : std_logic; - SIGNAL config_started_spi : std_logic := '0'; - SIGNAL config_wr_en : std_logic; - SIGNAL dac_array : dac_array_type; - SIGNAL data_out : std_logic_vector(63 DOWNTO 0); - SIGNAL denable_inhibit : std_logic := '0'; -- default domino wave off - SIGNAL denable_prim : std_logic := '0'; -- default domino wave off - SIGNAL din1 : std_logic := '0'; -- default domino wave off - SIGNAL dout : std_logic; - SIGNAL dout1 : std_logic; - SIGNAL drs_clk_en : std_logic := '0'; - SIGNAL drs_read_s_cell : std_logic := '0'; - SIGNAL drs_read_s_cell_ready : std_logic; - -- -- --- drs_dwrite : out std_logic := '1'; - SIGNAL drs_readout_ready : std_logic := '0'; - SIGNAL drs_readout_ready_ack : std_logic; - SIGNAL drs_readout_started : std_logic; - SIGNAL drs_s_cell_array : drs_s_cell_array_type; - SIGNAL drs_srin_data : std_logic_vector(7 DOWNTO 0) := (others => '0'); - SIGNAL dwrite : std_logic := '1'; - SIGNAL dwrite_enable : std_logic := '1'; - SIGNAL new_config : std_logic := '0'; - SIGNAL package_length : std_logic_vector(15 DOWNTO 0); - SIGNAL ps_direction : std_logic := '1'; -- default phase shift upwards - SIGNAL ps_do_phase_shift : std_logic := '0'; --pulse this to phase shift once - SIGNAL ps_reset : std_logic := '0'; -- pulse this to reset the variable phase shift - SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0); - SIGNAL ram_data : std_logic_vector(15 DOWNTO 0); - SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0); - SIGNAL ram_write_ea : std_logic; - SIGNAL ram_write_ready : std_logic := '0'; - -- -- - SIGNAL ram_write_ready_ack : std_logic := '0'; - SIGNAL roi_array : roi_array_type; - SIGNAL roi_max : roi_max_type; - SIGNAL s_trigger : std_logic; - SIGNAL s_trigger_0 : std_logic; - SIGNAL sclk1 : std_logic; - SIGNAL sclk_enable : std_logic; - SIGNAL sensor_array : sensor_array_type; - SIGNAL sensor_ready : std_logic; - SIGNAL socks_connected : std_logic; - SIGNAL socks_waiting : std_logic; - SIGNAL srclk_enable : std_logic := '0'; - SIGNAL srin_write_ack : std_logic := '0'; - SIGNAL srin_write_ready : std_logic := '0'; - SIGNAL start_srin_write_8b : std_logic; - SIGNAL trigger1 : std_logic; - SIGNAL trigger_enable : std_logic; - SIGNAL trigger_id : std_logic_vector(47 DOWNTO 0); - SIGNAL trigger_out : std_logic := '0'; - SIGNAL wiz_ack : std_logic; - SIGNAL wiz_busy : std_logic; - SIGNAL wiz_number_of_channels : std_logic_vector(3 DOWNTO 0) := (others => '0'); - SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0'); - SIGNAL wiz_write_ea : std_logic := '0'; - SIGNAL wiz_write_end : std_logic := '0'; - SIGNAL wiz_write_header : std_logic := '0'; - SIGNAL wiz_write_length : std_logic_vector(16 DOWNTO 0) := (others => '0'); - SIGNAL write_ea : std_logic_vector(0 DOWNTO 0) := "0"; - - -- Implicit buffer signal declarations - SIGNAL CLK_25_PS_internal : std_logic; - SIGNAL CLK_50_internal : std_logic; - SIGNAL alarm_refclk_too_high_internal : std_logic; - SIGNAL alarm_refclk_too_low_internal : std_logic; - - - -- Component Declarations - COMPONENT REFCLK_counter - PORT ( - clk : IN std_logic; - refclk_in : IN std_logic; - alarm_refclk_too_high : OUT std_logic := '0'; - alarm_refclk_too_low : OUT std_logic := '0'; - counter_result : OUT std_logic_vector (11 DOWNTO 0) := (others => '0') - ); - END COMPONENT; - COMPONENT adc_buffer - PORT ( - adc_data_array : IN adc_data_array_type; - adc_otr_array : IN std_logic_vector (3 DOWNTO 0); - clk_ps : IN std_logic; - adc_data_array_int : OUT adc_data_array_type; - adc_otr : OUT std_logic_vector (3 DOWNTO 0) - ); - END COMPONENT; - COMPONENT clock_generator_var_ps - PORT ( - CLK : IN std_logic ; - RST_IN : IN std_logic ; - direction : IN std_logic ; - do_shift : IN std_logic ; - CLK_25 : OUT std_logic ; - CLK_25_PS : OUT std_logic ; - CLK_50 : OUT std_logic ; - offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') - ); - END COMPONENT; - COMPONENT continous_pulser - GENERIC ( - MINIMAL_TRIGGER_WAIT_TIME : integer := 250000 - ); - PORT ( - CLK : IN std_logic; - enable : IN std_logic; - multiplier : IN std_logic_vector (7 DOWNTO 0); - trigger : OUT std_logic - ); - END COMPONENT; - COMPONENT control_unit - PORT ( - clk : IN STD_LOGIC ; - config_addr : IN std_logic_vector (7 DOWNTO 0); - config_rd_en : IN std_logic ; - config_start : IN std_logic ; - config_wr_en : IN std_logic ; - config_busy : OUT std_logic ; - config_data_valid : OUT std_logic ; - config_ready : OUT std_logic ; - -- -- - config_rw_ack : OUT std_logic := '0'; - -- -- - config_rw_ready : OUT std_logic := '0'; - config_started : OUT std_logic := '0'; - dac_array : OUT dac_array_type ; - roi_array : OUT roi_array_type ; - config_data : INOUT std_logic_vector (15 DOWNTO 0) - ); - END COMPONENT; - COMPONENT dataRAM_64b_16b_width14_5 - PORT ( - clka : IN std_logic ; - dina : IN std_logic_VECTOR (63 DOWNTO 0); - addra : IN std_logic_VECTOR (14 DOWNTO 0); - wea : IN std_logic_VECTOR (0 DOWNTO 0); - clkb : IN std_logic ; - addrb : IN std_logic_VECTOR (16 DOWNTO 0); - doutb : OUT std_logic_VECTOR (15 DOWNTO 0) - ); - END COMPONENT; - COMPONENT data_generator - GENERIC ( - RAM_ADDR_WIDTH : integer := 12 - ); - PORT ( - -- led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); - clk : IN std_logic ; - data_out : OUT std_logic_vector (63 DOWNTO 0); - addr_out : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); - write_ea : OUT std_logic_vector (0 DOWNTO 0) := "0"; - ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); - ram_write_ea : IN std_logic ; - ram_write_ready : OUT std_logic := '0'; - -- -- - ram_write_ready_ack : IN std_logic ; - -- -- - config_start_mm : OUT std_logic := '0'; - -- -- - config_start_cm : OUT std_logic := '0'; - -- -- - config_start_spi : OUT std_logic := '0'; - config_ready_mm : IN std_logic ; - config_ready_cm : IN std_logic ; - config_ready_spi : IN std_logic ; - config_started_mm : IN std_logic ; - config_started_cm : IN std_logic ; - config_started_spi : IN std_logic ; - roi_array : IN roi_array_type ; - roi_max : IN roi_max_type ; - sensor_array : IN sensor_array_type ; - sensor_ready : IN std_logic ; - dac_array : IN dac_array_type ; - package_length : IN std_logic_vector (15 DOWNTO 0); - board_id : IN std_logic_vector (3 DOWNTO 0); - crate_id : IN std_logic_vector (1 DOWNTO 0); - trigger_id : IN std_logic_vector (47 DOWNTO 0); - trigger : IN std_logic ; - -- s_trigger : in std_logic; - new_config : IN std_logic ; - config_started : OUT std_logic := '0'; - adc_data_array : IN adc_data_array_type ; - adc_oeb : OUT std_logic := '1'; - adc_clk_en : OUT std_logic := '0'; - adc_otr : IN std_logic_vector (3 DOWNTO 0); - drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); - -- -- - -- drs_dwrite : out std_logic := '1'; - drs_readout_ready : OUT std_logic := '0'; - drs_readout_ready_ack : IN std_logic ; - -- -- - drs_clk_en : OUT std_logic := '0'; - -- -- - drs_read_s_cell : OUT std_logic := '0'; - drs_srin_write_8b : OUT std_logic := '0'; - drs_srin_write_ack : IN std_logic ; - drs_srin_data : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); - drs_srin_write_ready : IN std_logic ; - drs_read_s_cell_ready : IN std_logic ; - drs_s_cell_array : IN drs_s_cell_array_type ; - drs_readout_started : OUT std_logic := '0' - ); - END COMPONENT; - COMPONENT drs_pulser - PORT ( - CLK : IN std_logic; - SROUT_in_0 : IN std_logic; - SROUT_in_1 : IN std_logic; - SROUT_in_2 : IN std_logic; - SROUT_in_3 : IN std_logic; - srin_data : IN std_logic_vector (7 DOWNTO 0); - start_endless_mode : IN std_logic; - start_read_stop_pos_mode : IN std_logic; - start_srin_write_8b : IN std_logic; - RSRLOAD : OUT std_logic := '0'; - SRCLK : OUT std_logic := '0'; - SRIN_out : OUT std_logic := '0'; - srin_write_ack : OUT std_logic := '0'; - srin_write_ready : OUT std_logic := '0'; - stop_pos : OUT drs_s_cell_array_type; - stop_pos_valid : OUT std_logic := '0' - ); - END COMPONENT; - COMPONENT led_controller - GENERIC ( - HEARTBEAT_PWM_DIVIDER : integer := 500; - MAX_DELAY : integer := 100; --not used anymore at all :-( - WAITING_DIVIDER : integer := 500000000 - ); - PORT ( - CLK : IN std_logic; - socks_connected : IN std_logic; - socks_waiting : IN std_logic; - trigger : IN std_logic; - additional_flasher_out : OUT std_logic; - amber : OUT std_logic; - green : OUT std_logic; - red : OUT std_logic - ); - END COMPONENT; - COMPONENT memory_manager - GENERIC ( - RAM_ADDR_WIDTH_64B : integer := 12; - RAM_ADDR_WIDTH_16B : integer := 14 - ); - PORT ( - clk : IN std_logic ; - config_start : IN std_logic ; - ram_write_ready : IN std_logic ; - -- -- - ram_write_ready_ack : OUT std_logic := '0'; - -- -- - roi_array : IN roi_array_type ; - ram_write_ea : OUT std_logic := '0'; - config_ready : OUT std_logic := '0'; - config_started : OUT std_logic := '0'; - roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11)); - package_length : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); - wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 DOWNTO 0) := (others => '0'); - wiz_write_length : OUT std_logic_vector (16 DOWNTO 0) := (others => '0'); - wiz_number_of_channels : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); - wiz_write_ea : OUT std_logic := '0'; - wiz_write_header : OUT std_logic := '0'; - wiz_write_end : OUT std_logic := '0'; - wiz_busy : IN std_logic ; - wiz_ack : IN std_logic ; - ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0') - ); - END COMPONENT; - COMPONENT spi_interface - PORT ( - clk_50MHz : IN std_logic ; - config_start : IN std_logic ; - dac_array : IN dac_array_type ; - config_ready : OUT std_logic ; - config_started : OUT std_logic := '0'; - dac_cs : OUT std_logic ; - mosi : OUT std_logic := '0'; - sclk : OUT std_logic ; - sensor_array : OUT sensor_array_type ; - sensor_cs : OUT std_logic_vector (3 DOWNTO 0); - sensor_ready : OUT std_logic ; - miso : INOUT std_logic - ); - END COMPONENT; - COMPONENT trigger_counter - PORT ( - trigger_id : OUT std_logic_vector (47 DOWNTO 0); - trigger : IN std_logic ; - clk : IN std_logic - ); - END COMPONENT; - COMPONENT trigger_manager - PORT ( - clk : IN std_logic; - drs_readout_ready : IN std_logic; - trigger_in : IN std_logic; - drs_readout_ready_ack : OUT std_logic := '0'; - drs_write : OUT std_logic := '1'; - trigger_out : OUT std_logic := '0' - ); - END COMPONENT; - COMPONENT w5300_modul - GENERIC ( - RAM_ADDR_WIDTH : integer := 14 - ); - PORT ( - clk : IN std_logic ; - wiz_reset : OUT std_logic := '1'; - addr : OUT std_logic_vector (9 DOWNTO 0); - data : INOUT std_logic_vector (15 DOWNTO 0); - cs : OUT std_logic := '1'; - wr : OUT std_logic := '1'; - led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); - rd : OUT std_logic := '1'; - int : IN std_logic ; - write_length : IN std_logic_vector (16 DOWNTO 0); - ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); - ram_data : IN std_logic_vector (15 DOWNTO 0); - ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); - data_valid : IN std_logic ; - data_valid_ack : OUT std_logic := '0'; - busy : OUT std_logic := '1'; - write_header_flag : IN std_logic ; - write_end_flag : IN std_logic ; - fifo_channels : IN std_logic_vector (3 DOWNTO 0); - -- softtrigger: - s_trigger : OUT std_logic := '0'; - c_trigger_enable : OUT std_logic := '0'; - c_trigger_mult : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '1'); --subject TO changes - -- FAD configuration signals: - ------------------------------------------------------------------------------ - -- start entire configuration chain - new_config : OUT std_logic := '0'; - config_started : IN std_logic ; - -- read/write configRAM - config_addr : OUT std_logic_vector (7 DOWNTO 0); - config_data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); - config_wr_en : OUT std_logic := '0'; - config_rd_en : OUT std_logic := '0'; - config_rw_ack : IN std_logic ; - config_rw_ready : IN std_logic ; - config_busy : IN std_logic ; - ------------------------------------------------------------------------------ - - -- MAC/IP calculation signals: - ------------------------------------------------------------------------------ - MAC_jumper : IN std_logic_vector (1 DOWNTO 0); - BoardID : IN std_logic_vector (3 DOWNTO 0); - CrateID : IN std_logic_vector (1 DOWNTO 0); - ------------------------------------------------------------------------------ - - -- user controllable enable signals - ------------------------------------------------------------------------------ - trigger_enable : OUT std_logic := '0'; -- default triggers are NOT accepted - denable : OUT std_logic := '0'; -- default domino wave off - dwrite_enable : OUT std_logic := '0'; -- default DWRITE low. - sclk_enable : OUT std_logic := '1'; -- default DWRITE HIGH. - srclk_enable : OUT std_logic := '1'; -- default SRCLK on. - ------------------------------------------------------------------------------ - - -- ADC CLK generator, is able to shift phase with respect to X_50M - -- these signals control the behavior of the digital clock manager (DCM) - ------------------------------------------------------------------------------ - ps_direction : OUT std_logic := '1'; -- default phase shift upwards - ps_do_phase_shift : OUT std_logic := '0'; --pulse this TO phase shift once - ps_reset : OUT std_logic := '0'; -- pulse this TO reset the variable phase shift - ------------------------------------------------------------------------------ - - -- signals used to control FAD LED bahavior: - -- one of the three LEDs is used for com-status info - ------------------------------------------------------------------------------ - socks_waiting : OUT std_logic ; - socks_connected : OUT std_logic - ------------------------------------------------------------------------------ - ); - END COMPONENT; - - -- Optional embedded configurations - -- pragma synthesis_off - FOR ALL : REFCLK_counter USE ENTITY FACT_FAD_lib.REFCLK_counter; - FOR ALL : adc_buffer USE ENTITY FACT_FAD_lib.adc_buffer; - FOR ALL : clock_generator_var_ps USE ENTITY FACT_FAD_lib.clock_generator_var_ps; - FOR ALL : continous_pulser USE ENTITY FACT_FAD_lib.continous_pulser; - FOR ALL : control_unit USE ENTITY FACT_FAD_lib.control_unit; - FOR ALL : dataRAM_64b_16b_width14_5 USE ENTITY FACT_FAD_lib.dataRAM_64b_16b_width14_5; - FOR ALL : data_generator USE ENTITY FACT_FAD_lib.data_generator; - FOR ALL : drs_pulser USE ENTITY FACT_FAD_lib.drs_pulser; - FOR ALL : led_controller USE ENTITY FACT_FAD_lib.led_controller; - FOR ALL : memory_manager USE ENTITY FACT_FAD_lib.memory_manager; - FOR ALL : spi_interface USE ENTITY FACT_FAD_lib.spi_interface; - FOR ALL : trigger_counter USE ENTITY FACT_FAD_lib.trigger_counter; - FOR ALL : trigger_manager USE ENTITY FACT_FAD_lib.trigger_manager; - FOR ALL : w5300_modul USE ENTITY FACT_FAD_lib.w5300_modul; - -- pragma synthesis_on - - -BEGIN - - -- ModuleWare code(v1.9) for instance 'I5' of 'and' - drs_dwrite <= dwrite AND dwrite_enable; - - -- ModuleWare code(v1.9) for instance 'I6' of 'and' - SRCLK <= SRCLK1 AND srclk_enable; - - -- ModuleWare code(v1.9) for instance 'U_1' of 'and' - sclk <= sclk_enable AND sclk1; - - -- ModuleWare code(v1.9) for instance 'U_5' of 'and' - denable <= denable_prim AND din1; - - -- ModuleWare code(v1.9) for instance 'U_11' of 'and' - dout1 <= dout AND trigger_enable; - - -- ModuleWare code(v1.9) for instance 'U_7' of 'inv' - din1 <= NOT(denable_inhibit); - - -- ModuleWare code(v1.9) for instance 'U_6' of 'or' - denable_inhibit <= alarm_refclk_too_low_internal - OR alarm_refclk_too_high_internal; - - -- ModuleWare code(v1.9) for instance 'U_9' of 'or' - dout <= s_trigger OR trigger; - - -- ModuleWare code(v1.9) for instance 'U_13' of 'or' - s_trigger <= s_trigger_0 OR trigger1; - - -- Instance port mappings. - REFCLK_counter_main : REFCLK_counter - PORT MAP ( - clk => CLK_50_internal, - refclk_in => drs_refclk_in, - counter_result => counter_result, - alarm_refclk_too_high => alarm_refclk_too_high_internal, - alarm_refclk_too_low => alarm_refclk_too_low_internal - ); - I_main_adc_buffer : adc_buffer - PORT MAP ( - clk_ps => CLK_25_PS_internal, - adc_data_array => adc_data_array, - adc_otr_array => adc_otr_array, - adc_data_array_int => adc_data_array_int, - adc_otr => adc_otr - ); - U_2 : clock_generator_var_ps - PORT MAP ( - CLK => CLK, - RST_IN => ps_reset, - direction => ps_direction, - do_shift => ps_do_phase_shift, - CLK_25 => CLK_25, - CLK_25_PS => CLK_25_PS_internal, - CLK_50 => CLK_50_internal, - offset => OPEN - ); - U_3 : continous_pulser - GENERIC MAP ( - MINIMAL_TRIGGER_WAIT_TIME => 250000 - ) - PORT MAP ( - CLK => CLK_25, - enable => c_trigger_enable, - multiplier => c_trigger_mult, - trigger => trigger1 - ); - I_main_control_unit : control_unit - PORT MAP ( - clk => CLK_50_internal, - config_addr => config_addr, - config_rd_en => config_rd_en, - config_start => config_start_cm, - config_wr_en => config_wr_en, - config_busy => config_busy, - config_data_valid => config_data_valid, - config_ready => config_ready_cm, - config_rw_ack => config_rw_ack, - config_rw_ready => config_rw_ready, - config_started => config_started_cu, - dac_array => dac_array, - roi_array => roi_array, - config_data => config_data - ); - U_4 : dataRAM_64b_16b_width14_5 - PORT MAP ( - clka => CLK_25, - dina => data_out, - addra => addr_out, - wea => write_ea, - clkb => CLK_50_internal, - addrb => ram_addr, - doutb => ram_data - ); - I_main_data_generator : data_generator - GENERIC MAP ( - RAM_ADDR_WIDTH => RAMADDRWIDTH64b - ) - PORT MAP ( - clk => CLK_25, - data_out => data_out, - addr_out => addr_out, - write_ea => write_ea, - ram_start_addr => ram_start_addr, - ram_write_ea => ram_write_ea, - ram_write_ready => ram_write_ready, - ram_write_ready_ack => ram_write_ready_ack, - config_start_mm => config_start, - config_start_cm => config_start_cm, - config_start_spi => config_start_spi, - config_ready_mm => config_ready, - config_ready_cm => config_ready_cm, - config_ready_spi => config_ready_spi, - config_started_mm => config_started_mm, - config_started_cm => config_started_cu, - config_started_spi => config_started_spi, - roi_array => roi_array, - roi_max => roi_max, - sensor_array => sensor_array, - sensor_ready => sensor_ready, - dac_array => dac_array, - package_length => package_length, - board_id => board_id, - crate_id => crate_id, - trigger_id => trigger_id, - trigger => trigger_out, - new_config => new_config, - config_started => config_started, - adc_data_array => adc_data_array_int, - adc_oeb => adc_oeb, - adc_clk_en => adc_clk_en, - adc_otr => adc_otr, - drs_channel_id => drs_channel_id, - drs_readout_ready => drs_readout_ready, - drs_readout_ready_ack => drs_readout_ready_ack, - drs_clk_en => drs_clk_en, - drs_read_s_cell => drs_read_s_cell, - drs_srin_write_8b => start_srin_write_8b, - drs_srin_write_ack => srin_write_ack, - drs_srin_data => drs_srin_data, - drs_srin_write_ready => srin_write_ready, - drs_read_s_cell_ready => drs_read_s_cell_ready, - drs_s_cell_array => drs_s_cell_array, - drs_readout_started => drs_readout_started - ); - I_main_drs_pulser : drs_pulser - PORT MAP ( - CLK => CLK_25, - start_endless_mode => drs_clk_en, - start_read_stop_pos_mode => drs_read_s_cell, - SROUT_in_0 => SROUT_in_0, - SROUT_in_1 => SROUT_in_1, - SROUT_in_2 => SROUT_in_2, - SROUT_in_3 => SROUT_in_3, - stop_pos => drs_s_cell_array, - stop_pos_valid => drs_read_s_cell_ready, - start_srin_write_8b => start_srin_write_8b, - srin_write_ready => srin_write_ready, - srin_write_ack => srin_write_ack, - srin_data => drs_srin_data, - SRIN_out => SRIN_out, - RSRLOAD => RSRLOAD, - SRCLK => SRCLK1 - ); - U_10 : led_controller - GENERIC MAP ( - HEARTBEAT_PWM_DIVIDER => 50000, -- 10kHz @ 50 MHz - MAX_DELAY => 100, - WAITING_DIVIDER => 50000000 -- 1Hz @ 50 MHz - ) - PORT MAP ( - CLK => CLK_50_internal, - green => green, - amber => amber, - red => red, - additional_flasher_out => additional_flasher_out, - trigger => drs_readout_started, - socks_waiting => socks_waiting, - socks_connected => socks_connected - ); - I_main_memory_manager : memory_manager - GENERIC MAP ( - RAM_ADDR_WIDTH_64B => RAMADDRWIDTH64b, - RAM_ADDR_WIDTH_16B => RAMADDRWIDTH64b+2 - ) - PORT MAP ( - clk => CLK_25, - config_start => config_start, - ram_write_ready => ram_write_ready, - ram_write_ready_ack => ram_write_ready_ack, - roi_array => roi_array, - ram_write_ea => ram_write_ea, - config_ready => config_ready, - config_started => config_started_mm, - roi_max => roi_max, - package_length => package_length, - wiz_ram_start_addr => wiz_ram_start_addr, - wiz_write_length => wiz_write_length, - wiz_number_of_channels => wiz_number_of_channels, - wiz_write_ea => wiz_write_ea, - wiz_write_header => wiz_write_header, - wiz_write_end => wiz_write_end, - wiz_busy => wiz_busy, - wiz_ack => wiz_ack, - ram_start_addr => ram_start_addr - ); - I_main_SPI_interface : spi_interface - PORT MAP ( - clk_50MHz => CLK_50_internal, - config_start => config_start_spi, - dac_array => dac_array, - config_ready => config_ready_spi, - config_started => config_started_spi, - dac_cs => dac_cs, - mosi => mosi, - sclk => sclk1, - sensor_array => sensor_array, - sensor_cs => sensor_cs, - sensor_ready => sensor_ready, - miso => sio - ); - I_main_ext_trigger : trigger_counter - PORT MAP ( - trigger_id => trigger_id, - trigger => trigger_out, - clk => CLK_25_PS_internal - ); - U_12 : trigger_manager - PORT MAP ( - clk => CLK_25, - trigger_in => dout1, - trigger_out => trigger_out, - drs_write => dwrite, - drs_readout_ready => drs_readout_ready, - drs_readout_ready_ack => drs_readout_ready_ack - ); - I_main_ethernet : w5300_modul - GENERIC MAP ( - RAM_ADDR_WIDTH => RAMADDRWIDTH64b+2 - ) - PORT MAP ( - clk => CLK_50_internal, - wiz_reset => wiz_reset, - addr => wiz_addr, - data => wiz_data, - cs => wiz_cs, - wr => wiz_wr, - led => led, - rd => wiz_rd, - int => wiz_int, - write_length => wiz_write_length, - ram_start_addr => wiz_ram_start_addr, - ram_data => ram_data, - ram_addr => ram_addr, - data_valid => wiz_write_ea, - data_valid_ack => wiz_ack, - busy => wiz_busy, - write_header_flag => wiz_write_header, - write_end_flag => wiz_write_end, - fifo_channels => wiz_number_of_channels, - s_trigger => s_trigger_0, - c_trigger_enable => c_trigger_enable, - c_trigger_mult => c_trigger_mult, - new_config => new_config, - config_started => config_started, - config_addr => config_addr, - config_data => config_data, - config_wr_en => config_wr_en, - config_rd_en => config_rd_en, - config_rw_ack => config_rw_ack, - config_rw_ready => config_rw_ready, - config_busy => config_busy, - MAC_jumper => D_T_in, - BoardID => board_id, - CrateID => crate_id, - denable => denable_prim, - dwrite_enable => dwrite_enable, - sclk_enable => sclk_enable, - ps_direction => ps_direction, - ps_do_phase_shift => ps_do_phase_shift, - ps_reset => ps_reset, - srclk_enable => srclk_enable, - trigger_enable => trigger_enable, - socks_waiting => socks_waiting, - socks_connected => socks_connected - ); - - -- Implicit buffered output assignments - CLK_25_PS <= CLK_25_PS_internal; - CLK_50 <= CLK_50_internal; - alarm_refclk_too_high <= alarm_refclk_too_high_internal; - alarm_refclk_too_low <= alarm_refclk_too_low_internal; - -END struct; Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/mod7_beha.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/mod7_beha.vhd (revision 10170) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/mod7_beha.vhd (revision 10170) @@ -0,0 +1,152 @@ +-- +-- VHDL Architecture FACT_FAD_lib.mod7.beha +-- +-- Created: +-- by - dneise.UNKNOWN (E5B-LABOR6) +-- at - 09:55:28 16.02.2011 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +--USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; + +ENTITY mod7 IS + PORT( + clk : IN std_logic; + + number : in std_logic_vector(31 downto 0); + start : in std_logic; + + remainder : out std_logic_vector(2 downto 0) := (others => '0'); + started : out std_logic := '0'; + valid : out std_logic :='0' + ); +END ENTITY mod7; + +-- +ARCHITECTURE beha OF mod7 IS + signal local_number : std_logic_vector (32 downto 0) := (OTHERS => '0'); --33bit number, easy to divide into 3bit-words + + type state_type is ( + IDLE_STATE, + SUBMOD1_STATE, + SUM1_STATE, + SUBMOD2_STATE, + SUM2_STATE, + SUBMOD3_STATE, + SUM3_STATE, + RESULT_STATE); + + signal state : state_type := IDLE_STATE; + + signal sum1 : std_logic_vector (8 downto 0) := (OTHERS => '0'); -- eigentlich reichen 7bit, aber 9 lassen sich leichter teilen + signal sum2 : std_logic_vector (5 downto 0) := (OTHERS => '0'); -- eigentlich reichen 4 bit, aber 6 lassen sich leichter teilen + signal sum3 : std_logic_vector (2 downto 0) := (OTHERS => '0'); + signal result : std_logic_vector (2 downto 0) := (OTHERS => '0'); + + type sm1_type is array (0 to 10) of std_logic_vector (8 downto 0); -- eigentlich sind es 3 bit werte, aber wenn ich summiere brauche ich die breite (fast) + type sm2_type is array (0 to 2) of std_logic_vector (5 downto 0); -- eigentlich sind es 3 bit werte, aber wenn ich summiere brauche ich die breite (fast) + type sm3_type is array (0 to 1) of std_logic_vector (2 downto 0); + + + signal submod1 : sm1_type := (others => "000000000"); + signal submod2 : sm2_type := (others => "000000"); + signal submod3 : sm3_type := (others => "000"); + + +BEGIN + remainder <= result; + + process (clk) + begin + + + if rising_edge(clk) then + + case state is + + when IDLE_STATE => + started <= '0'; + if (start = '1') then + started <= '1'; + valid <= '0'; + local_number <= '0' & number; + state <= SUBMOD1_STATE; + else + state <= IDLE_STATE; + end if; + + when SUBMOD1_STATE => + for i in 0 to 10 loop + if (local_number( 3*i+2 downto 3*i ) = "111" ) then + submod1(i) <= "000000000"; + else + submod1(i) <= "000000" & local_number( 3*i+2 downto 3*i ); + end if; + end loop; + state <= SUM1_STATE; + + when SUM1_STATE => + sum1 <= submod1(0) + + submod1(1) + + submod1(2) + + submod1(3) + + submod1(4) + + submod1(5) + + submod1(6) + + submod1(7) + + submod1(8) + + submod1(9) + + submod1(10); + + state <= SUBMOD2_STATE; + + when SUBMOD2_STATE => + for i in 0 to 2 loop + if (sum1( 3*i+2 downto 3*i ) = "111" ) then + submod2(i) <= "000000"; + else + submod2(i) <= "000" & sum1( 3*i+2 downto 3*i ); + end if; + end loop; + state <= SUM2_STATE; + + when SUM2_STATE => + sum2 <= submod2(0) + submod2(1) + submod2(2); + state <= SUBMOD3_STATE; + + when SUBMOD3_STATE => + for i in 0 to 1 loop + if (sum2( 3*i+2 downto 3*i ) = "111" ) then + submod3(i) <= "000"; + else + submod3(i) <= sum2( 3*i+2 downto 3*i ); + end if; + end loop; + state <= SUM3_STATE; + + when SUM3_STATE => + sum3 <= submod3(0) + submod3(1); + state <= RESULT_STATE; + + when RESULT_STATE => + started <= '0'; + valid <= '1'; + if (sum3( 2 downto 0 ) = "111" ) then + result <= "000"; + else + result <= sum3( 2 downto 0 ); + end if; + state <= IDLE_STATE; + + when others => + null; + end case; + + end if; + end process; + +END ARCHITECTURE beha; + Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/timer_beha.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/timer_beha.vhd (revision 10170) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/timer_beha.vhd (revision 10170) @@ -0,0 +1,92 @@ +-- +-- VHDL Architecture FACT_FAD_lib.timer.beha +-- +-- Created: +-- by - dneise.UNKNOWN (E5B-LABOR6) +-- at - 13:44:41 22.02.2011 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.2 (Build 10) + +-- + + + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; + + +ENTITY timer IS + generic( + TIMER_WIDTH : integer := 32; + PRESCALER : integer := 5000 + ); + port ( + clk : in std_logic; -- assumed to be 25MHz, if not 25MHz adjust PRESCALER + time_o : out std_logic_vector ( TIMER_WIDTH-1 downto 0); + synch_i : in std_logic ; + synched_o : out std_logic := '0'; + enable_i : in std_logic + ); +END ENTITY timer; + +-- +ARCHITECTURE beha OF timer IS + signal prescale_counter : integer range 0 to PRESCALER - 1 := 0; + + --signal time_s : integer range 0 to 2**(TIMER_WIDTH-1); + signal time_s : std_logic_vector ( TIMER_WIDTH-1 downto 0); + + signal en_sr : std_logic_vector(1 downto 0) := "00"; + signal sy_sr : std_logic_vector(1 downto 0) := "00"; + + signal timer_proc_enabled : std_logic := '0'; +BEGIN + --time_o <= conv_std_logic_vector(time_s, TIMER_WIDTH); + time_o <= time_s; + + main_proc: process (clk) + begin + if rising_edge(clk) then + en_sr <= en_sr(0) & enable_i; + sy_sr <= sy_sr(0) & synch_i; + + if (sy_sr = "01") then -- rising edge on synchronizstion_input detected + time_s <= conv_std_logic_vector(0,TIMER_WIDTH); + prescale_counter <= 1; + synched_o <= '1'; + end if; + + if (en_sr = "01") then -- rising edge on enable_input detected + time_s <= conv_std_logic_vector(0,TIMER_WIDTH); + prescale_counter <= 1; + timer_proc_enabled <= '1'; + elsif (en_sr = "10") then -- falling edge on enable_input detected + time_s <= conv_std_logic_vector(0,TIMER_WIDTH); + prescale_counter <= 0; + timer_proc_enabled <= '0'; + end if; + + -- PRESCALER PART OF PROCESS + if (timer_proc_enabled = '1') then + if (prescale_counter < PRESCALER - 1) then + prescale_counter <= prescale_counter + 1; + else + prescale_counter <= 0; + end if; + if (prescale_counter = PRESCALER - 1) then + if ( time_s < conv_std_logic_vector(2**TIMER_WIDTH-1 ,TIMER_WIDTH) ) then + time_s <= time_s + conv_std_logic_vector(1,TIMER_WIDTH); + else + time_s <= conv_std_logic_vector(0,TIMER_WIDTH); + end if; + end if; + else -- not timer_proc_enabled + time_s <= conv_std_logic_vector(0,TIMER_WIDTH); + end if; -- if timer_proc_enabled + end if; -- rising_edge(clk) + end process main_proc; +END ARCHITECTURE beha; + Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd (revision 10169) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd (revision 10170) @@ -89,5 +89,11 @@ INIT, LOCATE, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA); -type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_05a, WR_05b, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2, +type state_write_type is ( + WR_START, + WR_GET_EVT_ID_WAIT1, WR_GET_EVT_ID1, WR_GET_EVT_ID_WAIT2, WR_GET_EVT_ID2, + WR_MOD7_STARTED, WR_WAIT_FOR_MOD7, + WR_CHECK_FOR_FIFO_SPACE_01, WR_CHECK_FOR_FIFO_SPACE_02, WR_CHECK_FOR_FIFO_SPACE_03, WR_CHECK_FOR_FIFO_SPACE_04, + + WR_05, WR_05a, WR_05b, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2, WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3); type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04); @@ -178,6 +184,37 @@ signal socket_nr_counter : integer range 1 to 7 :=1; --used to determine which socket is used for data sending signal socket_send_mode : std_logic := '0'; -- if 0 data is send via socket 0; if 1 data is send via the other sockets. +-- signals for Sockek Number calculation +signal event_number : std_logic_vector(31 downto 0); +signal mod7_start : std_logic := '0'; +signal mod7_started : std_logic; +signal mod7_valid : std_logic; +signal mod7_result : std_logic_vector(2 downto 0); + +COMPONENT mod7 + PORT ( + clk : IN std_logic; + number : IN std_logic_vector (31 DOWNTO 0); + start : IN std_logic; + remainder : OUT std_logic_vector (2 DOWNTO 0) := (others => '0'); + started : OUT std_logic := '0'; + valid : OUT std_logic := '0' + ); + END COMPONENT; + + begin + + mod7_calculator : mod7 + PORT MAP ( + --locals => actuals + clk =>clk , + number =>event_number , + start =>mod7_start , + remainder =>mod7_result , + started =>mod7_started , + valid =>mod7_valid + ); + --synthesis translate_off @@ -613,4 +650,8 @@ when MAIN3 => -- led <= local_ram_start_addr (7 downto 0); + + -- needed for the check: if there is enough space in W5300 FIFO + write_length_bytes <= local_write_length (15 downto 0) & '0'; -- shift left (*2) + data_valid_ack <= '1'; next_state <= MAIN; @@ -780,55 +821,74 @@ when WRITE_DATA => case state_write is + when WR_START => if (local_write_header_flag = '1') then - ram_addr <= local_ram_start_addr + 5; -- Address of Trigger-ID (15 downto 0) ???? + ram_addr <= local_ram_start_addr + 6; -- Address of HIGH word of Event ID + state_write <= WR_GET_EVT_ID_WAIT1; + else + state_write <= WR_CHECK_FOR_FIFO_SPACE_01; end if; - state_write <= WR_WAIT1; - when WR_WAIT1 => - state_write <= WR_LENGTH; - when WR_LENGTH => - if (local_write_header_flag = '1') then - if (socket_send_mode = '1') then -- send via all sockets - local_socket_nr <= conv_std_logic_vector(socket_nr_counter, 3); - if (socket_nr_counter < 7) then - socket_nr_counter <= socket_nr_counter + 1; - else - socket_nr_counter <= 1; - end if; - else -- only send via socket 0\ - local_socket_nr <= "000"; - end if; - end if; - next_state_tmp <= next_state; - write_length_bytes <= local_write_length (15 downto 0) & '0'; -- shift left (*2) - data_cnt <= 0; - state_write <= WR_01; + + when WR_GET_EVT_ID_WAIT1 => + state_write <= WR_GET_EVT_ID1; + when WR_GET_EVT_ID1 => + event_number(31 downto 16) <= ram_data; + ram_addr <= local_ram_start_addr + 7; -- Address of LOW word of Event ID + state_write <= WR_GET_EVT_ID_WAIT2; + when WR_GET_EVT_ID_WAIT2 => + state_write <= WR_GET_EVT_ID2; + when WR_GET_EVT_ID2 => + event_number(15 downto 0) <= ram_data; + if (mod7_valid = '1') then + mod7_start <= '1'; + state_write <= WR_MOD7_STARTED; + else + state_write <= WR_GET_EVT_ID2; + end if; + + when WR_MOD7_STARTED => + if (mod7_started = '1') then + mod7_start <= '0'; + state_write <= WR_WAIT_FOR_MOD7; + end if; + + when WR_WAIT_FOR_MOD7 => + if (mod7_valid = '1') then + if (socket_send_mode = '1') then -- send via all sockets + local_socket_nr <= mod7_result; + else -- only send via socket 0\ + local_socket_nr <= "000"; + end if; + next_state_tmp <= next_state; + data_cnt <= 0; + state_write <= WR_CHECK_FOR_FIFO_SPACE_01; + else + state_write <= WR_WAIT_FOR_MOD7; + end if; + -- Check FIFO Size - when WR_01 => + when WR_CHECK_FOR_FIFO_SPACE_01 => par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC; state_init <= READ_REG; next_state <= WRITE_DATA; - state_write <= WR_02; - when WR_02 => + state_write <= WR_CHECK_FOR_FIFO_SPACE_02; + when WR_CHECK_FOR_FIFO_SPACE_02 => socket_tx_free (31 downto 16) <= data_read; par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2"; state_init <= READ_REG; next_state <= WRITE_DATA; - state_write <= WR_03; - when WR_03 => + state_write <= WR_CHECK_FOR_FIFO_SPACE_03; + when WR_CHECK_FOR_FIFO_SPACE_03 => socket_tx_free (15 downto 0) <= data_read; - state_write <= WR_04; - when WR_04 => - --- led <= socket_tx_free (15 downto 8); - + state_write <= WR_CHECK_FOR_FIFO_SPACE_04; + when WR_CHECK_FOR_FIFO_SPACE_04 => -- if (socket_tx_free (16 downto 0) < write_length_bytes) then - if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then + if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then state_write <= WR_01; else - if (local_write_header_flag = '1') then - state_write <= WR_FIFO; + if (local_write_header_flag = '1') then + state_write <= WR_FIFO; else - state_write <= WR_ADC; + state_write <= WR_ADC; end if; end if; @@ -838,16 +898,16 @@ -- Write Header when WR_FIFO => - ram_addr <= local_ram_start_addr + local_ram_addr; - state_write <= WR_FIFO1; + ram_addr <= local_ram_start_addr + local_ram_addr; + state_write <= WR_FIFO1; when WR_FIFO1 => data_cnt <= data_cnt + 1; if (data_cnt < PACKAGE_HEADER_LENGTH) then --??? local_ram_addr <= local_ram_addr + 1; - if (data_cnt = 2 or data_cnt = 5 or data_cnt = 8 ) then -- skip empty words - local_ram_addr <= local_ram_addr + 2; - end if; - if (data_cnt = 9) then -- skip empty words - local_ram_addr <= local_ram_addr + 4; - end if; +-- if (data_cnt = 2 or data_cnt = 5 or data_cnt = 8 ) then -- skip empty words +-- local_ram_addr <= local_ram_addr + 2; +-- end if; +-- if (data_cnt = 9) then -- skip empty words +-- local_ram_addr <= local_ram_addr + 4; +-- end if; par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; ram_access <= '1';