Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/RS485_receiver_fake_beha.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/RS485_receiver_fake_beha.vhd (revision 10172) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/RS485_receiver_fake_beha.vhd (revision 10172) @@ -0,0 +1,33 @@ +-- +-- VHDL Architecture FACT_FAD_lib.RS485_receiver_fake.beha +-- +-- Created: +-- by - dneise.UNKNOWN (E5B-LABOR6) +-- at - 12:34:27 23.02.2011 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +ENTITY RS485_receiver_fake IS +Port( + trigger_no : in std_logic_vector(31 downto 0); + trigger_type1 : in std_logic_vector(7 downto 0); + trigger_type2 : in std_logic_vector(7 downto 0); + crc : in std_logic_vector(7 downto 0); + + rs465_data : out std_logic_vector(55 downto 0); + rs485_ready : out std_logic +); +END ENTITY RS485_receiver_fake; + +-- +ARCHITECTURE beha OF RS485_receiver_fake IS +BEGIN + rs485_ready <= '1'; + rs465_data <= trigger_no & trigger_type1 & trigger_type2 & crc; + +END ARCHITECTURE beha; + Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/continous_pulser_beha.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/continous_pulser_beha.vhd (revision 10171) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/continous_pulser_beha.vhd (revision 10172) @@ -21,13 +21,12 @@ GENERIC( - MINIMAL_TRIGGER_WAIT_TIME : integer := 250000 + MINIMAL_TRIGGER_WAIT_TIME : integer := 250000; + TRIGGER_WIDTH : integer := 5 ); PORT( CLK : IN std_logic; -- 25MHz = 40ns - enable : in std_logic; - multiplier : IN std_logic_vector (7 downto 0); - - trigger : out std_logic + multiplier : IN std_logic_vector (15 downto 0); + trigger : out std_logic ); END ENTITY continous_pulser; @@ -40,5 +39,6 @@ -- noninverted logic signal trigger_loc : std_logic := '0'; - signal mult_int : integer range 0 to 1023 :=0; + signal mult_int : integer range 0 to 65535 :=0; + BEGIN trigger <= trigger_loc and enable; @@ -68,5 +68,5 @@ trigger_loc <= '1'; end if; - if (Y = 5) then + if (Y = TRIGGER_WIDTH) then trigger_loc <= '0'; end if; Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_manager_beha.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_manager_beha.vhd (revision 10171) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_manager_beha.vhd (revision 10172) @@ -118,18 +118,18 @@ when CTRL_LOAD_WAIT => ctrl_state <= CTRL_LOAD_DATA; - when CTRL_LOAD_DATA => - addr_cntr <= addr_cntr + 1; - if (addr_cntr < NO_OF_ROI) then - roi_array(addr_cntr) <= conv_integer(ram_data_out); - ctrl_state <= CTRL_LOAD_ADDR; - elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC) then - dac_array(addr_cntr - NO_OF_ROI) <= conv_integer(ram_data_out); - ctrl_state <= CTRL_LOAD_ADDR; - else - addr_cntr <= 0; - config_started <= '0'; - config_ready <= '1'; - ctrl_state <= CTRL_WAIT_IDLE; - end if; + when CTRL_LOAD_DATA => + addr_cntr <= addr_cntr + 1; + if (addr_cntr < NO_OF_ROI) then + roi_array(addr_cntr) <= conv_integer(ram_data_out); + ctrl_state <= CTRL_LOAD_ADDR; + elsif (addr_cntr < NO_OF_ROI + NO_OF_DAC) then + dac_array(addr_cntr - NO_OF_ROI) <= conv_integer(ram_data_out); + ctrl_state <= CTRL_LOAD_ADDR; + else + addr_cntr <= 0; + config_started <= '0'; + config_ready <= '1'; + ctrl_state <= CTRL_WAIT_IDLE; + end if; when CTRL_WRITE => Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_unit_struct.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_unit_struct.vhd (revision 10171) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/control_unit_struct.vhd (revision 10172) @@ -3,5 +3,5 @@ -- Created: -- by - dneise.UNKNOWN (E5B-LABOR6) --- at - 13:10:37 12.02.2011 +-- at - 14:02:35 23.02.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) @@ -42,5 +42,5 @@ -- Created: -- by - dneise.UNKNOWN (E5B-LABOR6) --- at - 13:10:37 12.02.2011 +-- at - 14:02:35 23.02.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd (revision 10171) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd (revision 10172) @@ -69,5 +69,4 @@ crate_id : in std_logic_vector (1 downto 0); DCM_PS_status : in std_logic_vector (7 downto 0); - TRG_GEN_no : in std_logic_vector (15 downto 0); TRG_GEN_div : in std_logic_vector (15 downto 0); -- @@ -143,37 +142,33 @@ begin - - drs_readout_started <= sig_drs_readout_started; - - generate_data : process (clk) - begin - if rising_edge (clk) then - trigger_flag <= trigger; - - addr_out <= start_addr + conv_std_logic_vector(addr_cntr, RAM_ADDR_WIDTH); - - case state_generate is - when INIT => - state_generate <= CONFIG; - - when CONFIG => - config_started <= '1'; - if (new_config = '0') then - config_started <= '0'; - -- config config manager - config_start_cm <= '1'; - if (config_started_cm = '1') then - config_start_cm <= '0'; - state_generate <= CONFIG1; - end if; - end if; - when CONFIG1 => - if (config_ready_cm = '1') then - config_start_mm <= '1'; - end if; - if (config_started_mm = '1') then - config_start_mm <= '0'; - state_generate <= CONFIG2; - end if; +drs_readout_started <= sig_drs_readout_started; + +generate_data : process (clk) +begin + if rising_edge (clk) then + trigger_flag <= trigger; + addr_out <= start_addr + conv_std_logic_vector(addr_cntr, RAM_ADDR_WIDTH); + case state_generate is + when INIT => + state_generate <= CONFIG; + when CONFIG => + config_started <= '1'; + if (new_config = '0') then + config_started <= '0'; + -- config config manager + config_start_cm <= '1'; + if (config_started_cm = '1') then + config_start_cm <= '0'; + state_generate <= CONFIG1; + end if; + end if; + when CONFIG1 => + if (config_ready_cm = '1') then + config_start_mm <= '1'; + end if; + if (config_started_mm = '1') then + config_start_mm <= '0'; + state_generate <= CONFIG2; + end if; when CONFIG2 => if (config_ready_mm = '1') then @@ -261,5 +256,5 @@ -- status of the trigger generator when WRITE_BOARD_ID => - data_out <= TRG_GEN_div & TRG_GEN_no & X"00" & DCM_PS_status & "000000" & crate_id & "1000" & board_id; + data_out <= TRG_GEN_div & X"0000" & X"00" & DCM_PS_status & "000000" & crate_id & "1000" & board_id; addr_cntr <= addr_cntr + 1; state_generate <= WRITE_DNA; Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd (revision 10171) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd (revision 10172) @@ -3,5 +3,5 @@ -- Created: -- by - dneise.UNKNOWN (E5B-LABOR6) --- at - 17:38:00 16.02.2011 +-- at - 14:09:41 23.02.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) @@ -76,5 +76,5 @@ -- Created: -- by - dneise.UNKNOWN (E5B-LABOR6) --- at - 17:38:00 16.02.2011 +-- at - 14:09:41 23.02.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) @@ -126,35 +126,35 @@ board_id : IN std_logic_vector (3 DOWNTO 0); crate_id : IN std_logic_vector (1 DOWNTO 0); - drs_refclk_in : IN std_logic ; -- used TO check if DRS REFCLK exsists, if not DENABLE inhibit - plllock_in : IN std_logic_vector (3 DOWNTO 0); -- high level, if dominowave is running and DRS PLL locked + drs_refclk_in : IN std_logic ; -- used TO check if DRS REFCLK exsists, if not DENABLE inhibit + plllock_in : IN std_logic_vector (3 DOWNTO 0); -- high level, if dominowave is running and DRS PLL locked trigger : IN std_logic ; wiz_int : IN std_logic ; CLK_25_PS : OUT std_logic ; CLK_50 : OUT std_logic ; - RSRLOAD : OUT std_logic := '0'; - SRCLK : OUT std_logic := '0'; - SRIN_out : OUT std_logic := '0'; - adc_clk_en : OUT std_logic := '0'; - adc_oeb : OUT std_logic := '1'; + RSRLOAD : OUT std_logic := '0'; + SRCLK : OUT std_logic := '0'; + SRIN_out : OUT std_logic := '0'; + adc_clk_en : OUT std_logic := '0'; + adc_oeb : OUT std_logic := '1'; additional_flasher_out : OUT std_logic ; - alarm_refclk_too_high : OUT std_logic := '0'; -- default domino wave off - alarm_refclk_too_low : OUT std_logic := '0'; -- default domino wave off + alarm_refclk_too_high : OUT std_logic ; + alarm_refclk_too_low : OUT std_logic ; amber : OUT std_logic ; - counter_result : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); + counter_result : OUT std_logic_vector (11 DOWNTO 0); dac_cs : OUT std_logic ; - denable : OUT std_logic := '0'; -- default domino wave off - drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); - drs_dwrite : OUT std_logic := '1'; + denable : OUT std_logic := '0'; -- default domino wave off + drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); + drs_dwrite : OUT std_logic := '1'; green : OUT std_logic ; - led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); - mosi : OUT std_logic := '0'; + led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + mosi : OUT std_logic := '0'; red : OUT std_logic ; sclk : OUT std_logic ; sensor_cs : OUT std_logic_vector (3 DOWNTO 0); wiz_addr : OUT std_logic_vector (9 DOWNTO 0); - wiz_cs : OUT std_logic := '1'; - wiz_rd : OUT std_logic := '1'; - wiz_reset : OUT std_logic := '1'; - wiz_wr : OUT std_logic := '1'; + wiz_cs : OUT std_logic := '1'; + wiz_rd : OUT std_logic := '1'; + wiz_reset : OUT std_logic := '1'; + wiz_wr : OUT std_logic := '1'; sio : INOUT std_logic ; wiz_data : INOUT std_logic_vector (15 DOWNTO 0) Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd (revision 10171) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd (revision 10172) @@ -133,36 +133,30 @@ -- Commands - constant CMD_START : std_logic_vector := X"C0"; - constant CMD_STOP : std_logic_vector := X"30"; - constant CMD_TRIGGER : std_logic_vector := X"A0"; - - constant CMD_TRIGGER_C : std_logic_vector := X"B0"; - constant CMD_TRIGGER_S : std_logic_vector := X"20"; - constant CMD_READ : std_logic_vector := X"0A"; - constant CMD_WRITE : std_logic_vector := X"05"; --- Config-RAM - constant BADDR_ROI : std_logic_vector := X"00"; -- Baseaddress ROI-Values - constant BADDR_DAC : std_logic_vector := X"24"; -- Baseaddress DAC-Values - - constant CMD_DENABLE : std_logic_vector := X"06"; - constant CMD_DDISABLE : std_logic_vector := X"07"; - constant CMD_DWRITE_RUN : std_logic_vector := X"08"; - constant CMD_DWRITE_STOP : std_logic_vector := X"09"; - constant CMD_SCLK_ON : std_logic_vector := X"10"; - constant CMD_SCLK_OFF : std_logic_vector := X"11"; - - constant CMD_PS_DIRINC : std_logic_vector := X"12"; - constant CMD_PS_DIRDEC : std_logic_vector := X"13"; - constant CMD_PS_DO : std_logic_vector := X"14"; - -constant CMD_SRCLK_ON : std_logic_vector := X"15"; -constant CMD_SRCLK_OFF : std_logic_vector := X"16"; - -constant CMD_TRIGGERS_ON : std_logic_vector := X"18"; -constant CMD_TRIGGERS_OFF : std_logic_vector := X"19"; - -constant CMD_PS_RESET : std_logic_vector := X"17"; - -constant CMD_SET_TRIGGER_MULT : std_logic_vector := X"21"; +constant BADDR_ROI : std_logic_vector := X"00"; -- Baseaddress ROI-Values +constant CMD_WRITE : std_logic_vector := X"05"; +constant CMD_DENABLE : std_logic_vector := X"06"; +constant CMD_DDISABLE : std_logic_vector := X"07"; +constant CMD_DWRITE_RUN : std_logic_vector := X"08"; +constant CMD_DWRITE_STOP : std_logic_vector := X"09"; +constant CMD_READ : std_logic_vector := X"0A"; +constant CMD_SCLK_ON : std_logic_vector := X"10"; +constant CMD_SCLK_OFF : std_logic_vector := X"11"; +constant CMD_PS_DIRINC : std_logic_vector := X"12"; +constant CMD_PS_DIRDEC : std_logic_vector := X"13"; +constant CMD_PS_DO : std_logic_vector := X"14"; +constant CMD_SRCLK_ON : std_logic_vector := X"15"; +constant CMD_SRCLK_OFF : std_logic_vector := X"16"; +constant CMD_PS_RESET : std_logic_vector := X"17"; +constant CMD_TRIGGERS_ON : std_logic_vector := X"18"; +constant CMD_TRIGGERS_OFF : std_logic_vector := X"19"; +constant CMD_TRIGGER_S : std_logic_vector := X"20"; +constant CMD_SET_TRIGGER_MULT : std_logic_vector := X"21"; +constant CMD_START : std_logic_vector := X"22"; -- set data generator in RUN-mnode +constant CMD_STOP : std_logic_vector := X"23"; -- set data generator in STOP-mode +constant BADDR_DAC : std_logic_vector := X"24"; -- Baseaddress DAC-Values +constant CMC_MODE_COMMAND : std_logic_vector := X"30"; +constant CMD_TRIGGER : std_logic_vector := X"A0"; +constant CMD_TRIGGER_C : std_logic_vector := X"B0"; +constant CMD_MODE_ALL_SOCKETS : std_logic_vector := X"C0"; -- DRS Registers Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd (revision 10171) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd (revision 10172) @@ -0,0 +1,948 @@ +-- VHDL Entity FACT_FAD_lib.FAD_main.symbol +-- +-- Created: +-- by - dneise.UNKNOWN (E5B-LABOR6) +-- at - 14:08:52 23.02.2011 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all; + +ENTITY FAD_main IS + GENERIC( + RAMADDRWIDTH64b : integer := 12 + ); + PORT( + CLK : IN std_logic; + D_T_in : IN std_logic_vector (1 DOWNTO 0); + SROUT_in_0 : IN std_logic; + SROUT_in_1 : IN std_logic; + SROUT_in_2 : IN std_logic; + SROUT_in_3 : IN std_logic; + adc_data_array : IN adc_data_array_type; + adc_otr_array : IN std_logic_vector (3 DOWNTO 0); + board_id : IN std_logic_vector (3 DOWNTO 0); + crate_id : IN std_logic_vector (1 DOWNTO 0); + drs_refclk_in : IN std_logic; -- used to check if DRS REFCLK exsists, if not DENABLE inhibit + plllock_in : IN std_logic_vector (3 DOWNTO 0); -- high level, if dominowave is running and DRS PLL locked + trigger : IN std_logic; + wiz_int : IN std_logic; + CLK_25_PS : OUT std_logic; + CLK_50 : OUT std_logic; + RSRLOAD : OUT std_logic := '0'; + SRCLK : OUT std_logic := '0'; + SRIN_out : OUT std_logic := '0'; + adc_clk_en : OUT std_logic := '0'; + adc_oeb : OUT std_logic := '1'; + additional_flasher_out : OUT std_logic; + alarm_refclk_too_high : OUT std_logic; + alarm_refclk_too_low : OUT std_logic; + amber : OUT std_logic; + counter_result : OUT std_logic_vector (11 DOWNTO 0); + dac_cs : OUT std_logic; + denable : OUT std_logic := '0'; -- default domino wave off + drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); + drs_dwrite : OUT std_logic := '1'; + green : OUT std_logic; + led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + mosi : OUT std_logic := '0'; + red : OUT std_logic; + sclk : OUT std_logic; + sensor_cs : OUT std_logic_vector (3 DOWNTO 0); + wiz_addr : OUT std_logic_vector (9 DOWNTO 0); + wiz_cs : OUT std_logic := '1'; + wiz_rd : OUT std_logic := '1'; + wiz_reset : OUT std_logic := '1'; + wiz_wr : OUT std_logic := '1'; + sio : INOUT std_logic; + wiz_data : INOUT std_logic_vector (15 DOWNTO 0) + ); + +-- Declarations + +END FAD_main ; + +-- +-- VHDL Architecture FACT_FAD_lib.FAD_main.struct +-- +-- Created: +-- by - dneise.UNKNOWN (E5B-LABOR6) +-- at - 14:08:53 23.02.2011 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use ieee.STD_LOGIC_UNSIGNED.all; + +library fact_fad_lib; +use fact_fad_lib.fad_definitions.all; + +library UNISIM; +--use UNISIM.VComponents.all; +USE IEEE.NUMERIC_STD.all; +USE IEEE.std_logic_signed.all; +USE UNISIM.VComponents.all; + +LIBRARY FACT_FAD_lib; + +ARCHITECTURE struct OF FAD_main IS + + -- Architecture declarations + + -- Internal signal declarations + SIGNAL CLK_25 : std_logic; + SIGNAL DCM_PS_status : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); + -- + +-- EVT HEADER - part 2 --> FTM trigger informaton, comes in late ... +-- during EVT header wrinting, this field is left out ... and only written into event header, +-- when the DRS chip were read out already. + SIGNAL FTM_RS485_ready : std_logic; + SIGNAL SRCLK1 : std_logic := '0'; + SIGNAL adc_data_array_int : adc_data_array_type; + SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0); + SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0); + SIGNAL c_trigger_enable : std_logic := '0'; + SIGNAL c_trigger_mult : std_logic_vector(15 DOWNTO 0); + SIGNAL config_addr : std_logic_vector(7 DOWNTO 0); + SIGNAL config_busy : std_logic; + SIGNAL config_data : std_logic_vector(15 DOWNTO 0); + SIGNAL config_data_valid : std_logic; + SIGNAL config_rd_en : std_logic; + SIGNAL config_ready : std_logic; + SIGNAL config_ready_cm : std_logic; + SIGNAL config_ready_spi : std_logic; + -- -- + SIGNAL config_rw_ack : std_logic := '0'; + -- -- + SIGNAL config_rw_ready : std_logic := '0'; + SIGNAL config_start : std_logic := '0'; + SIGNAL config_start_cm : std_logic; + SIGNAL config_start_spi : std_logic := '0'; + SIGNAL config_started : std_logic; + SIGNAL config_started_cu : std_logic := '0'; + SIGNAL config_started_mm : std_logic; + SIGNAL config_started_spi : std_logic := '0'; + SIGNAL config_wr_en : std_logic; + SIGNAL crc : std_logic_vector(7 DOWNTO 0); + SIGNAL dac_array : dac_array_type; + SIGNAL data_out : std_logic_vector(63 DOWNTO 0); + SIGNAL denable_inhibit : std_logic := '0'; -- default domino wave off + SIGNAL denable_prim : std_logic := '0'; -- default domino wave off + SIGNAL din1 : std_logic := '0'; -- default domino wave off + SIGNAL dna : STD_LOGIC_VECTOR(63 DOWNTO 0) := (others => '0'); + SIGNAL dout : std_logic; + SIGNAL dout1 : std_logic; + SIGNAL drs_clk_en : std_logic := '0'; + SIGNAL drs_read_s_cell : std_logic := '0'; + SIGNAL drs_read_s_cell_ready : std_logic; + -- -- +-- drs_dwrite : out std_logic := '1'; + SIGNAL drs_readout_ready : std_logic := '0'; + SIGNAL drs_readout_ready_ack : std_logic; + SIGNAL drs_readout_started : std_logic; + SIGNAL drs_s_cell_array : drs_s_cell_array_type; + SIGNAL drs_srin_data : std_logic_vector(7 DOWNTO 0) := (others => '0'); + SIGNAL dwrite : std_logic := '1'; + SIGNAL dwrite_enable : std_logic := '1'; + SIGNAL enable_i : std_logic; + SIGNAL new_config : std_logic := '0'; + SIGNAL package_length : std_logic_vector(15 DOWNTO 0); + SIGNAL ps_direction : std_logic := '1'; -- default phase shift upwards + SIGNAL ps_do_phase_shift : std_logic := '0'; --pulse this to phase shift once + SIGNAL ps_reset : std_logic := '0'; -- pulse this to reset the variable phase shift + SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0); + SIGNAL ram_data : std_logic_vector(15 DOWNTO 0); + SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0); + SIGNAL ram_write_ea : std_logic; + SIGNAL ram_write_ready : std_logic := '0'; + -- -- + SIGNAL ram_write_ready_ack : std_logic := '0'; + SIGNAL ready : STD_LOGIC := '0'; + SIGNAL reset_synch_i : std_logic; + SIGNAL roi_array : roi_array_type; + SIGNAL roi_max : roi_max_type; + SIGNAL rs465_data : std_logic_vector(55 DOWNTO 0); --7 byte + SIGNAL s_trigger : std_logic; + SIGNAL s_trigger_0 : std_logic; + SIGNAL sclk1 : std_logic; + SIGNAL sclk_enable : std_logic; + SIGNAL sensor_array : sensor_array_type; + SIGNAL sensor_ready : std_logic; + SIGNAL socks_connected : std_logic; + SIGNAL socks_waiting : std_logic; + SIGNAL srclk_enable : std_logic := '0'; + SIGNAL srin_write_ack : std_logic := '0'; + SIGNAL srin_write_ready : std_logic := '0'; + SIGNAL start_srin_write_8b : std_logic; + SIGNAL time : std_logic_vector(31 DOWNTO 0); + SIGNAL trigger1 : std_logic; + SIGNAL trigger_enable : std_logic; + SIGNAL trigger_id : std_logic_vector(31 DOWNTO 0); + SIGNAL trigger_out : std_logic; + SIGNAL trigger_type1 : std_logic_vector(7 DOWNTO 0); + SIGNAL trigger_type2 : std_logic_vector(7 DOWNTO 0); + SIGNAL wiz_ack : std_logic; + SIGNAL wiz_busy : std_logic; + SIGNAL wiz_number_of_channels : std_logic_vector(3 DOWNTO 0) := (others => '0'); + SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0'); + SIGNAL wiz_write_ea : std_logic := '0'; + SIGNAL wiz_write_end : std_logic := '0'; + SIGNAL wiz_write_header : std_logic := '0'; + SIGNAL wiz_write_length : std_logic_vector(16 DOWNTO 0) := (others => '0'); + SIGNAL write_ea : std_logic_vector(0 DOWNTO 0) := "0"; + + -- Implicit buffer signal declarations + SIGNAL CLK_25_PS_internal : std_logic; + SIGNAL CLK_50_internal : std_logic; + SIGNAL alarm_refclk_too_high_internal : std_logic; + SIGNAL alarm_refclk_too_low_internal : std_logic; + SIGNAL counter_result_internal : std_logic_vector (11 DOWNTO 0); + + + -- Component Declarations + COMPONENT REFCLK_counter + PORT ( + clk : IN std_logic; + refclk_in : IN std_logic; + alarm_refclk_too_high : OUT std_logic := '0'; + alarm_refclk_too_low : OUT std_logic := '0'; + counter_result : OUT std_logic_vector (11 DOWNTO 0) := (others => '0') + ); + END COMPONENT; + COMPONENT RS485_receiver_fake + PORT ( + crc : IN std_logic_vector (7 DOWNTO 0); + trigger_no : IN std_logic_vector (31 DOWNTO 0); + trigger_type1 : IN std_logic_vector (7 DOWNTO 0); + trigger_type2 : IN std_logic_vector (7 DOWNTO 0); + rs465_data : OUT std_logic_vector (55 DOWNTO 0); + rs485_ready : OUT std_logic + ); + END COMPONENT; + COMPONENT adc_buffer + PORT ( + adc_data_array : IN adc_data_array_type; + adc_otr_array : IN std_logic_vector (3 DOWNTO 0); + clk_ps : IN std_logic; + adc_data_array_int : OUT adc_data_array_type; + adc_otr : OUT std_logic_vector (3 DOWNTO 0) + ); + END COMPONENT; + COMPONENT clock_generator_var_ps + PORT ( + CLK : IN std_logic ; + RST_IN : IN std_logic ; + direction : IN std_logic ; + do_shift : IN std_logic ; + CLK_25 : OUT std_logic ; + CLK_25_PS : OUT std_logic ; + CLK_50 : OUT std_logic ; + offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0') + ); + END COMPONENT; + COMPONENT continous_pulser + GENERIC ( + MINIMAL_TRIGGER_WAIT_TIME : integer := 250000; + TRIGGER_WIDTH : integer := 5 + ); + PORT ( + CLK : IN std_logic; + enable : IN std_logic; + multiplier : IN std_logic_vector (15 DOWNTO 0); + trigger : OUT std_logic + ); + END COMPONENT; + COMPONENT control_unit + PORT ( + clk : IN STD_LOGIC ; + config_addr : IN std_logic_vector (7 DOWNTO 0); + config_rd_en : IN std_logic ; + config_start : IN std_logic ; + config_wr_en : IN std_logic ; + config_busy : OUT std_logic ; + config_data_valid : OUT std_logic ; + config_ready : OUT std_logic ; + -- -- + config_rw_ack : OUT std_logic := '0'; + -- -- + config_rw_ready : OUT std_logic := '0'; + config_started : OUT std_logic := '0'; + dac_array : OUT dac_array_type ; + roi_array : OUT roi_array_type ; + config_data : INOUT std_logic_vector (15 DOWNTO 0) + ); + END COMPONENT; + COMPONENT dataRAM_64b_16b_width14_5 + PORT ( + clka : IN std_logic ; + dina : IN std_logic_VECTOR (63 DOWNTO 0); + addra : IN std_logic_VECTOR (14 DOWNTO 0); + wea : IN std_logic_VECTOR (0 DOWNTO 0); + clkb : IN std_logic ; + addrb : IN std_logic_VECTOR (16 DOWNTO 0); + doutb : OUT std_logic_VECTOR (15 DOWNTO 0) + ); + END COMPONENT; + COMPONENT data_generator + GENERIC ( + RAM_ADDR_WIDTH : integer := 12 + ); + PORT ( + -- led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + clk : IN std_logic ; + data_out : OUT std_logic_vector (63 DOWNTO 0); + addr_out : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + write_ea : OUT std_logic_vector (0 DOWNTO 0) := "0"; + ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + ram_write_ea : IN std_logic ; + ram_write_ready : OUT std_logic := '0'; + -- -- + ram_write_ready_ack : IN std_logic ; + -- -- + config_start_mm : OUT std_logic := '0'; + -- -- + config_start_cm : OUT std_logic := '0'; + -- -- + config_start_spi : OUT std_logic := '0'; + config_ready_mm : IN std_logic ; + config_ready_cm : IN std_logic ; + config_ready_spi : IN std_logic ; + config_started_mm : IN std_logic ; + config_started_cm : IN std_logic ; + config_started_spi : IN std_logic ; + roi_array : IN roi_array_type ; + roi_max : IN roi_max_type ; + sensor_array : IN sensor_array_type ; + sensor_ready : IN std_logic ; + dac_array : IN dac_array_type ; + -- EVT HEADER - part 1 + package_length : IN std_logic_vector (15 DOWNTO 0); + pll_lock : IN std_logic_vector ( 3 DOWNTO 0); + -- + + -- EVT HEADER - part 2 --> FTM trigger informaton, comes in late ... + -- during EVT header wrinting, this field is left out ... and only written into event header, + -- when the DRS chip were read out already. + FTM_RS485_ready : IN std_logic ; + FTM_trigger_info : IN std_logic_vector (55 DOWNTO 0); --7 byte + -- + + -- EVT HEADER - part 3 + fad_event_counter : IN std_logic_vector (31 DOWNTO 0); + refclk_counter : IN std_logic_vector (11 DOWNTO 0); + refclk_too_high : IN std_logic ; + refclk_too_low : IN std_logic ; + -- + + -- EVT HEADER - part 4 + board_id : IN std_logic_vector (3 DOWNTO 0); + crate_id : IN std_logic_vector (1 DOWNTO 0); + DCM_PS_status : IN std_logic_vector (7 DOWNTO 0); + TRG_GEN_div : IN std_logic_vector (15 DOWNTO 0); + -- + + -- EVT HEADER - part 5 + dna : IN std_logic_vector (63 DOWNTO 0); + -- + + -- EVT HEADER - part 6 + timer_value : IN std_logic_vector (31 DOWNTO 0); -- time in units of 100us + -- + trigger : IN std_logic ; + -- s_trigger : in std_logic; + new_config : IN std_logic ; + config_started : OUT std_logic := '0'; + adc_data_array : IN adc_data_array_type ; + adc_oeb : OUT std_logic := '1'; + adc_clk_en : OUT std_logic := '0'; + adc_otr : IN std_logic_vector (3 DOWNTO 0); + drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); + -- -- + -- drs_dwrite : out std_logic := '1'; + drs_readout_ready : OUT std_logic := '0'; + drs_readout_ready_ack : IN std_logic ; + -- -- + drs_clk_en : OUT std_logic := '0'; + -- -- + drs_read_s_cell : OUT std_logic := '0'; + drs_srin_write_8b : OUT std_logic := '0'; + drs_srin_write_ack : IN std_logic ; + drs_srin_data : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); + drs_srin_write_ready : IN std_logic ; + drs_read_s_cell_ready : IN std_logic ; + drs_s_cell_array : IN drs_s_cell_array_type ; + drs_readout_started : OUT std_logic := '0' + ); + END COMPONENT; + COMPONENT dna_gen + PORT ( + clk : IN STD_LOGIC ; + dna : OUT STD_LOGIC_VECTOR (63 DOWNTO 0) := (others => '0'); + ready : OUT STD_LOGIC := '0' + ); + END COMPONENT; + COMPONENT drs_pulser + PORT ( + CLK : IN std_logic; + SROUT_in_0 : IN std_logic; + SROUT_in_1 : IN std_logic; + SROUT_in_2 : IN std_logic; + SROUT_in_3 : IN std_logic; + srin_data : IN std_logic_vector (7 DOWNTO 0); + start_endless_mode : IN std_logic; + start_read_stop_pos_mode : IN std_logic; + start_srin_write_8b : IN std_logic; + RSRLOAD : OUT std_logic := '0'; + SRCLK : OUT std_logic := '0'; + SRIN_out : OUT std_logic := '0'; + srin_write_ack : OUT std_logic := '0'; + srin_write_ready : OUT std_logic := '0'; + stop_pos : OUT drs_s_cell_array_type; + stop_pos_valid : OUT std_logic := '0' + ); + END COMPONENT; + COMPONENT led_controller + GENERIC ( + HEARTBEAT_PWM_DIVIDER : integer := 500; + MAX_DELAY : integer := 100; --not used anymore at all :-( + WAITING_DIVIDER : integer := 500000000 + ); + PORT ( + CLK : IN std_logic; + socks_connected : IN std_logic; + socks_waiting : IN std_logic; + trigger : IN std_logic; + additional_flasher_out : OUT std_logic; + amber : OUT std_logic; + green : OUT std_logic; + red : OUT std_logic + ); + END COMPONENT; + COMPONENT memory_manager + GENERIC ( + RAM_ADDR_WIDTH_64B : integer := 12; + RAM_ADDR_WIDTH_16B : integer := 14 + ); + PORT ( + clk : IN std_logic ; + config_start : IN std_logic ; + ram_write_ready : IN std_logic ; + -- -- + ram_write_ready_ack : OUT std_logic := '0'; + -- -- + roi_array : IN roi_array_type ; + ram_write_ea : OUT std_logic := '0'; + config_ready : OUT std_logic := '0'; + config_started : OUT std_logic := '0'; + roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11)); + package_length : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 DOWNTO 0) := (others => '0'); + wiz_write_length : OUT std_logic_vector (16 DOWNTO 0) := (others => '0'); + wiz_number_of_channels : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); + wiz_write_ea : OUT std_logic := '0'; + wiz_write_header : OUT std_logic := '0'; + wiz_write_end : OUT std_logic := '0'; + wiz_busy : IN std_logic ; + wiz_ack : IN std_logic ; + ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0') + ); + END COMPONENT; + COMPONENT spi_interface + PORT ( + clk_50MHz : IN std_logic ; + config_start : IN std_logic ; + dac_array : IN dac_array_type ; + config_ready : OUT std_logic ; + config_started : OUT std_logic := '0'; + dac_cs : OUT std_logic ; + mosi : OUT std_logic := '0'; + sclk : OUT std_logic ; + sensor_array : OUT sensor_array_type ; + sensor_cs : OUT std_logic_vector (3 DOWNTO 0); + sensor_ready : OUT std_logic ; + miso : INOUT std_logic + ); + END COMPONENT; + COMPONENT timer + GENERIC ( + TIMER_WIDTH : integer := 32; + PRESCALER : integer := 5000 + ); + PORT ( + clk : IN std_logic; + enable_i : IN std_logic; + reset_synch_i : IN std_logic; + synch_i : IN std_logic; + synched_o : OUT std_logic := '0'; + time_o : OUT std_logic_vector ( TIMER_WIDTH-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT trigger_counter + PORT ( + trigger_id : OUT std_logic_vector (31 DOWNTO 0); + trigger : IN std_logic ; + clk : IN std_logic + ); + END COMPONENT; + COMPONENT trigger_manager + PORT ( + clk : IN std_logic; + drs_readout_ready : IN std_logic; + trigger_in : IN std_logic; + drs_readout_ready_ack : OUT std_logic := '0'; + drs_write : OUT std_logic := '1'; + trigger_out : OUT std_logic := '0' + ); + END COMPONENT; + COMPONENT w5300_modul + GENERIC ( + RAM_ADDR_WIDTH : integer := 14 + ); + PORT ( + clk : IN std_logic ; + wiz_reset : OUT std_logic := '1'; + addr : OUT std_logic_vector (9 DOWNTO 0); + data : INOUT std_logic_vector (15 DOWNTO 0); + cs : OUT std_logic := '1'; + wr : OUT std_logic := '1'; + led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + rd : OUT std_logic := '1'; + int : IN std_logic ; + write_length : IN std_logic_vector (16 DOWNTO 0); + ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + ram_data : IN std_logic_vector (15 DOWNTO 0); + ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + data_valid : IN std_logic ; + data_valid_ack : OUT std_logic := '0'; + busy : OUT std_logic := '1'; + write_header_flag : IN std_logic ; + write_end_flag : IN std_logic ; + fifo_channels : IN std_logic_vector (3 DOWNTO 0); + -- softtrigger: + s_trigger : OUT std_logic := '0'; + c_trigger_enable : OUT std_logic := '0'; + c_trigger_mult : OUT std_logic_vector (15 DOWNTO 0) := conv_std_logic_vector(100 ,16); --subject TO changes + -- FAD configuration signals: + ------------------------------------------------------------------------------ + -- start entire configuration chain + new_config : OUT std_logic := '0'; + config_started : IN std_logic ; + -- read/write configRAM + config_addr : OUT std_logic_vector (7 DOWNTO 0); + config_data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); + config_wr_en : OUT std_logic := '0'; + config_rd_en : OUT std_logic := '0'; + config_rw_ack : IN std_logic ; + config_rw_ready : IN std_logic ; + config_busy : IN std_logic ; + ------------------------------------------------------------------------------ + + -- MAC/IP calculation signals: + ------------------------------------------------------------------------------ + MAC_jumper : IN std_logic_vector (1 DOWNTO 0); + BoardID : IN std_logic_vector (3 DOWNTO 0); + CrateID : IN std_logic_vector (1 DOWNTO 0); + ------------------------------------------------------------------------------ + + -- user controllable enable signals + ------------------------------------------------------------------------------ + trigger_enable : OUT std_logic := '0'; -- default triggers are NOT accepted + denable : OUT std_logic := '0'; -- default domino wave off + dwrite_enable : OUT std_logic := '0'; -- default DWRITE low. + sclk_enable : OUT std_logic := '1'; -- default DWRITE HIGH. + srclk_enable : OUT std_logic := '1'; -- default SRCLK on. + ------------------------------------------------------------------------------ + + -- ADC CLK generator, is able to shift phase with respect to X_50M + -- these signals control the behavior of the digital clock manager (DCM) + ------------------------------------------------------------------------------ + ps_direction : OUT std_logic := '1'; -- default phase shift upwards + ps_do_phase_shift : OUT std_logic := '0'; --pulse this TO phase shift once + ps_reset : OUT std_logic := '0'; -- pulse this TO reset the variable phase shift + ------------------------------------------------------------------------------ + + -- signals used to control FAD LED bahavior: + -- one of the three LEDs is used for com-status info + ------------------------------------------------------------------------------ + socks_waiting : OUT std_logic ; + socks_connected : OUT std_logic + ------------------------------------------------------------------------------ + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : REFCLK_counter USE ENTITY FACT_FAD_lib.REFCLK_counter; + FOR ALL : RS485_receiver_fake USE ENTITY FACT_FAD_lib.RS485_receiver_fake; + FOR ALL : adc_buffer USE ENTITY FACT_FAD_lib.adc_buffer; + FOR ALL : clock_generator_var_ps USE ENTITY FACT_FAD_lib.clock_generator_var_ps; + FOR ALL : continous_pulser USE ENTITY FACT_FAD_lib.continous_pulser; + FOR ALL : control_unit USE ENTITY FACT_FAD_lib.control_unit; + FOR ALL : dataRAM_64b_16b_width14_5 USE ENTITY FACT_FAD_lib.dataRAM_64b_16b_width14_5; + FOR ALL : data_generator USE ENTITY FACT_FAD_lib.data_generator; + FOR ALL : dna_gen USE ENTITY FACT_FAD_lib.dna_gen; + FOR ALL : drs_pulser USE ENTITY FACT_FAD_lib.drs_pulser; + FOR ALL : led_controller USE ENTITY FACT_FAD_lib.led_controller; + FOR ALL : memory_manager USE ENTITY FACT_FAD_lib.memory_manager; + FOR ALL : spi_interface USE ENTITY FACT_FAD_lib.spi_interface; + FOR ALL : timer USE ENTITY FACT_FAD_lib.timer; + FOR ALL : trigger_counter USE ENTITY FACT_FAD_lib.trigger_counter; + FOR ALL : trigger_manager USE ENTITY FACT_FAD_lib.trigger_manager; + FOR ALL : w5300_modul USE ENTITY FACT_FAD_lib.w5300_modul; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb1 + trigger_type1 <= "00000010"; + trigger_type2 <= "00000000"; + crc <= X"5A"; + + + -- ModuleWare code(v1.9) for instance 'I5' of 'and' + drs_dwrite <= dwrite AND dwrite_enable; + + -- ModuleWare code(v1.9) for instance 'I6' of 'and' + SRCLK <= SRCLK1 AND srclk_enable; + + -- ModuleWare code(v1.9) for instance 'U_1' of 'and' + sclk <= sclk_enable AND sclk1; + + -- ModuleWare code(v1.9) for instance 'U_5' of 'and' + denable <= denable_prim AND din1; + + -- ModuleWare code(v1.9) for instance 'U_11' of 'and' + dout1 <= dout AND trigger_enable; + + -- ModuleWare code(v1.9) for instance 'U_15' of 'gnd' + reset_synch_i <= '0'; + + -- ModuleWare code(v1.9) for instance 'U_7' of 'inv' + din1 <= NOT(denable_inhibit); + + -- ModuleWare code(v1.9) for instance 'U_6' of 'or' + denable_inhibit <= alarm_refclk_too_low_internal + OR alarm_refclk_too_high_internal; + + -- ModuleWare code(v1.9) for instance 'U_9' of 'or' + dout <= s_trigger OR trigger; + + -- ModuleWare code(v1.9) for instance 'U_13' of 'or' + s_trigger <= s_trigger_0 OR trigger1; + + -- ModuleWare code(v1.9) for instance 'U_14' of 'vdd' + enable_i <= '1'; + + -- Instance port mappings. + REFCLK_counter_main : REFCLK_counter + PORT MAP ( + clk => CLK_50_internal, + refclk_in => drs_refclk_in, + counter_result => counter_result_internal, + alarm_refclk_too_high => alarm_refclk_too_high_internal, + alarm_refclk_too_low => alarm_refclk_too_low_internal + ); + U_16 : RS485_receiver_fake + PORT MAP ( + trigger_no => trigger_id, + trigger_type1 => trigger_type1, + trigger_type2 => trigger_type2, + crc => crc, + rs465_data => rs465_data, + rs485_ready => FTM_RS485_ready + ); + I_main_adc_buffer : adc_buffer + PORT MAP ( + clk_ps => CLK_25_PS_internal, + adc_data_array => adc_data_array, + adc_otr_array => adc_otr_array, + adc_data_array_int => adc_data_array_int, + adc_otr => adc_otr + ); + U_2 : clock_generator_var_ps + PORT MAP ( + CLK => CLK, + RST_IN => ps_reset, + direction => ps_direction, + do_shift => ps_do_phase_shift, + CLK_25 => CLK_25, + CLK_25_PS => CLK_25_PS_internal, + CLK_50 => CLK_50_internal, + offset => DCM_PS_status + ); + U_3 : continous_pulser + GENERIC MAP ( + MINIMAL_TRIGGER_WAIT_TIME => 250000, + TRIGGER_WIDTH => 5 + ) + PORT MAP ( + CLK => CLK_25, + enable => c_trigger_enable, + multiplier => c_trigger_mult, + trigger => trigger1 + ); + I_main_control_unit : control_unit + PORT MAP ( + clk => CLK_50_internal, + config_addr => config_addr, + config_rd_en => config_rd_en, + config_start => config_start_cm, + config_wr_en => config_wr_en, + config_busy => config_busy, + config_data_valid => config_data_valid, + config_ready => config_ready_cm, + config_rw_ack => config_rw_ack, + config_rw_ready => config_rw_ready, + config_started => config_started_cu, + dac_array => dac_array, + roi_array => roi_array, + config_data => config_data + ); + U_4 : dataRAM_64b_16b_width14_5 + PORT MAP ( + clka => CLK_25, + dina => data_out, + addra => addr_out, + wea => write_ea, + clkb => CLK_50_internal, + addrb => ram_addr, + doutb => ram_data + ); + I_main_data_generator : data_generator + GENERIC MAP ( + RAM_ADDR_WIDTH => RAMADDRWIDTH64b + ) + PORT MAP ( + clk => CLK_25, + data_out => data_out, + addr_out => addr_out, + write_ea => write_ea, + ram_start_addr => ram_start_addr, + ram_write_ea => ram_write_ea, + ram_write_ready => ram_write_ready, + ram_write_ready_ack => ram_write_ready_ack, + config_start_mm => config_start, + config_start_cm => config_start_cm, + config_start_spi => config_start_spi, + config_ready_mm => config_ready, + config_ready_cm => config_ready_cm, + config_ready_spi => config_ready_spi, + config_started_mm => config_started_mm, + config_started_cm => config_started_cu, + config_started_spi => config_started_spi, + roi_array => roi_array, + roi_max => roi_max, + sensor_array => sensor_array, + sensor_ready => sensor_ready, + dac_array => dac_array, + package_length => package_length, + pll_lock => plllock_in, + FTM_RS485_ready => FTM_RS485_ready, + FTM_trigger_info => rs465_data, + fad_event_counter => trigger_id, + refclk_counter => counter_result_internal, + refclk_too_high => alarm_refclk_too_high_internal, + refclk_too_low => alarm_refclk_too_low_internal, + board_id => board_id, + crate_id => crate_id, + DCM_PS_status => DCM_PS_status, + TRG_GEN_div => c_trigger_mult, + dna => dna, + timer_value => time, + trigger => trigger_out, + new_config => new_config, + config_started => config_started, + adc_data_array => adc_data_array_int, + adc_oeb => adc_oeb, + adc_clk_en => adc_clk_en, + adc_otr => adc_otr, + drs_channel_id => drs_channel_id, + drs_readout_ready => drs_readout_ready, + drs_readout_ready_ack => drs_readout_ready_ack, + drs_clk_en => drs_clk_en, + drs_read_s_cell => drs_read_s_cell, + drs_srin_write_8b => start_srin_write_8b, + drs_srin_write_ack => srin_write_ack, + drs_srin_data => drs_srin_data, + drs_srin_write_ready => srin_write_ready, + drs_read_s_cell_ready => drs_read_s_cell_ready, + drs_s_cell_array => drs_s_cell_array, + drs_readout_started => drs_readout_started + ); + U_0 : dna_gen + PORT MAP ( + clk => CLK_25, + dna => dna, + ready => ready + ); + I_main_drs_pulser : drs_pulser + PORT MAP ( + CLK => CLK_25, + start_endless_mode => drs_clk_en, + start_read_stop_pos_mode => drs_read_s_cell, + SROUT_in_0 => SROUT_in_0, + SROUT_in_1 => SROUT_in_1, + SROUT_in_2 => SROUT_in_2, + SROUT_in_3 => SROUT_in_3, + stop_pos => drs_s_cell_array, + stop_pos_valid => drs_read_s_cell_ready, + start_srin_write_8b => start_srin_write_8b, + srin_write_ready => srin_write_ready, + srin_write_ack => srin_write_ack, + srin_data => drs_srin_data, + SRIN_out => SRIN_out, + RSRLOAD => RSRLOAD, + SRCLK => SRCLK1 + ); + U_10 : led_controller + GENERIC MAP ( + HEARTBEAT_PWM_DIVIDER => 50000, -- 10kHz @ 50 MHz + MAX_DELAY => 100, + WAITING_DIVIDER => 50000000 -- 1Hz @ 50 MHz + ) + PORT MAP ( + CLK => CLK_50_internal, + green => green, + amber => amber, + red => red, + additional_flasher_out => additional_flasher_out, + trigger => drs_readout_started, + socks_waiting => socks_waiting, + socks_connected => socks_connected + ); + I_main_memory_manager : memory_manager + GENERIC MAP ( + RAM_ADDR_WIDTH_64B => RAMADDRWIDTH64b, + RAM_ADDR_WIDTH_16B => RAMADDRWIDTH64b+2 + ) + PORT MAP ( + clk => CLK_25, + config_start => config_start, + ram_write_ready => ram_write_ready, + ram_write_ready_ack => ram_write_ready_ack, + roi_array => roi_array, + ram_write_ea => ram_write_ea, + config_ready => config_ready, + config_started => config_started_mm, + roi_max => roi_max, + package_length => package_length, + wiz_ram_start_addr => wiz_ram_start_addr, + wiz_write_length => wiz_write_length, + wiz_number_of_channels => wiz_number_of_channels, + wiz_write_ea => wiz_write_ea, + wiz_write_header => wiz_write_header, + wiz_write_end => wiz_write_end, + wiz_busy => wiz_busy, + wiz_ack => wiz_ack, + ram_start_addr => ram_start_addr + ); + I_main_SPI_interface : spi_interface + PORT MAP ( + clk_50MHz => CLK_50_internal, + config_start => config_start_spi, + dac_array => dac_array, + config_ready => config_ready_spi, + config_started => config_started_spi, + dac_cs => dac_cs, + mosi => mosi, + sclk => sclk1, + sensor_array => sensor_array, + sensor_cs => sensor_cs, + sensor_ready => sensor_ready, + miso => sio + ); + U_8 : timer + GENERIC MAP ( + TIMER_WIDTH => 32, + PRESCALER => 5000 + ) + PORT MAP ( + clk => CLK_50_internal, + time_o => time, + synch_i => trigger_out, + synched_o => OPEN, + reset_synch_i => reset_synch_i, + enable_i => enable_i + ); + I_main_ext_trigger : trigger_counter + PORT MAP ( + trigger_id => trigger_id, + trigger => trigger_out, + clk => CLK_25_PS_internal + ); + U_12 : trigger_manager + PORT MAP ( + clk => CLK_25, + trigger_in => dout1, + trigger_out => trigger_out, + drs_write => dwrite, + drs_readout_ready => drs_readout_ready, + drs_readout_ready_ack => drs_readout_ready_ack + ); + I_main_ethernet : w5300_modul + GENERIC MAP ( + RAM_ADDR_WIDTH => RAMADDRWIDTH64b+2 + ) + PORT MAP ( + clk => CLK_50_internal, + wiz_reset => wiz_reset, + addr => wiz_addr, + data => wiz_data, + cs => wiz_cs, + wr => wiz_wr, + led => led, + rd => wiz_rd, + int => wiz_int, + write_length => wiz_write_length, + ram_start_addr => wiz_ram_start_addr, + ram_data => ram_data, + ram_addr => ram_addr, + data_valid => wiz_write_ea, + data_valid_ack => wiz_ack, + busy => wiz_busy, + write_header_flag => wiz_write_header, + write_end_flag => wiz_write_end, + fifo_channels => wiz_number_of_channels, + s_trigger => s_trigger_0, + c_trigger_enable => c_trigger_enable, + c_trigger_mult => c_trigger_mult, + new_config => new_config, + config_started => config_started, + config_addr => config_addr, + config_data => config_data, + config_wr_en => config_wr_en, + config_rd_en => config_rd_en, + config_rw_ack => config_rw_ack, + config_rw_ready => config_rw_ready, + config_busy => config_busy, + MAC_jumper => D_T_in, + BoardID => board_id, + CrateID => crate_id, + trigger_enable => trigger_enable, + denable => denable_prim, + dwrite_enable => dwrite_enable, + sclk_enable => sclk_enable, + srclk_enable => srclk_enable, + ps_direction => ps_direction, + ps_do_phase_shift => ps_do_phase_shift, + ps_reset => ps_reset, + socks_waiting => socks_waiting, + socks_connected => socks_connected + ); + + -- Implicit buffered output assignments + CLK_25_PS <= CLK_25_PS_internal; + CLK_50 <= CLK_50_internal; + alarm_refclk_too_high <= alarm_refclk_too_high_internal; + alarm_refclk_too_low <= alarm_refclk_too_low_internal; + counter_result <= counter_result_internal; + +END struct; Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd (revision 10171) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd (revision 10172) @@ -52,4 +52,5 @@ wiz_busy : IN std_logic; wiz_ack : IN std_logic; + buffer_ram_empty : out std_logic; ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0') ); @@ -104,4 +105,5 @@ -- led <= conv_std_logic_vector (events_in_ram, 4) & "00" & wiz_ack & wiz_busy; + buffer_ram_empty <= '0' when events_in_ram=0 else '1'; mm : process (clk) Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/timer_beha.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/timer_beha.vhd (revision 10171) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/timer_beha.vhd (revision 10172) @@ -8,14 +8,8 @@ -- using Mentor Graphics HDL Designer(TM) 2009.2 (Build 10) --- - - - - LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; - ENTITY timer IS @@ -29,4 +23,5 @@ synch_i : in std_logic ; synched_o : out std_logic := '0'; + reset_synch_i : in std_logic; enable_i : in std_logic ); @@ -42,9 +37,14 @@ signal en_sr : std_logic_vector(1 downto 0) := "00"; signal sy_sr : std_logic_vector(1 downto 0) := "00"; + signal reset_synch_sr : std_logic_vector(1 downto 0) := "00"; signal timer_proc_enabled : std_logic := '0'; + signal synched : std_logic := '0'; + BEGIN --time_o <= conv_std_logic_vector(time_s, TIMER_WIDTH); time_o <= time_s; + synched_o <= synched; + main_proc: process (clk) @@ -53,9 +53,14 @@ en_sr <= en_sr(0) & enable_i; sy_sr <= sy_sr(0) & synch_i; + reset_synch_sr <= reset_synch_sr(0) & reset_synch_i; - if (sy_sr = "01") then -- rising edge on synchronizstion_input detected + if ( reset_synch_sr = "01" ) then + synched <= '0'; + end if; + + if (sy_sr = "01" and synched = '0') then -- rising edge on synchronizstion_input detected AND if not already synched time_s <= conv_std_logic_vector(0,TIMER_WIDTH); prescale_counter <= 1; - synched_o <= '1'; + synched <= '1'; end if; Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd (revision 10171) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd (revision 10172) @@ -33,5 +33,5 @@ s_trigger : OUT std_logic := '0'; c_trigger_enable: out std_logic := '0'; - c_trigger_mult: out std_logic_vector (7 DOWNTO 0) := (OTHERS => '1'); --subject to changes + c_trigger_mult: out std_logic_vector (15 DOWNTO 0) := conv_std_logic_vector(100 ,16); --subject to changes -- FAD configuration signals: @@ -59,4 +59,5 @@ ------------------------------------------------------------------------------ trigger_enable : out std_logic := '0'; -- default triggers are NOT accepted + data_generator_run_mode : out std_logic := '0'; -- default triggers are NOT accepted denable : out std_logic := '0'; -- default domino wave off dwrite_enable : out std_logic := '0'; -- default DWRITE low. @@ -191,4 +192,6 @@ signal mod7_result : std_logic_vector(2 downto 0); +signal set_new_CONT_TRIGGER_MULT_FACTOR : std_logic := '0'; + COMPONENT mod7 PORT ( @@ -209,5 +212,5 @@ PORT MAP ( --locals => actuals - clk =>clk , + clk =>clk , number =>event_number , start =>mod7_start , @@ -620,10 +623,10 @@ --data_valid_int <= data_valid; when MAIN1 => - if (chk_recv_cntr = 1000) then - chk_recv_cntr <= 0; - state_read_data <= RD_1; - state_init <= READ_DATA; - busy <= '1'; - else + if (chk_recv_cntr = 1000) then + chk_recv_cntr <= 0; + state_read_data <= RD_1; + state_init <= READ_DATA; + busy <= '1'; + else chk_recv_cntr <= chk_recv_cntr + 1; state_init <= MAIN2; @@ -705,11 +708,18 @@ case data_read (15 downto 8) is - when CMD_START => -- all data will be send via socket 1..7 - socket_send_mode <= '1'; + when CMD_START => + data_generator_run_mode <= '1'; state_read_data <= RD_5; - when CMD_STOP => -- all data will be send via socket 0 - socket_send_mode <= '0'; - state_read_data <= RD_5; + when CMD_STOP => + data_generator_run_mode <= '0'; + state_read_data <= RD_5; + when CMD_MODE_ALL_SOCKETS => -- all data will be send via socket 1..7 + socket_send_mode <= '1'; + state_read_data <= RD_5; + + when CMC_MODE_COMMAND => -- all data will be send via socket 0 + socket_send_mode <= '0'; + state_read_data <= RD_5; when CMD_TRIGGER => @@ -745,6 +755,7 @@ state_read_data <= RD_5; when CMD_SET_TRIGGER_MULT => - c_trigger_mult <= data_read (7 downto 0); - state_read_data <= RD_5; + set_new_CONT_TRIGGER_MULT_FACTOR <= '1'; + next_packet_data <= '1'; + state_read_data <= RD_5; -- phase shift commands here: @@ -778,7 +789,7 @@ state_read_data <= RD_5; when CMD_WRITE => - next_packet_data <= '1'; - config_addr <= data_read (7 downto 0); - state_read_data <= RD_5; + config_addr <= data_read (7 downto 0); + next_packet_data <= '1'; + state_read_data <= RD_5; when others => state_read_data <= RD_5; @@ -786,11 +797,17 @@ -- read data else - if (config_busy = '0') then - config_data <= data_read; - config_wr_en <= '1'; - new_config_flag <= '1'; - next_packet_data <= '0'; - state_read_data <= RD_WAIT; - end if; + if ( set_new_CONT_TRIGGER_MULT_FACTOR = '1' ) then + set_new_CONT_TRIGGER_MULT_FACTOR <= '0'; + c_trigger_mult <= data_read; + state_read_data <= RD_5; + else + if (config_busy = '0') then + config_data <= data_read; + config_wr_en <= '1'; + new_config_flag <= '1'; + next_packet_data <= '0'; + state_read_data <= RD_WAIT; + end if; + end if; end if; when RD_WAIT => @@ -885,5 +902,5 @@ -- if (socket_tx_free (16 downto 0) < write_length_bytes) then if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then - state_write <= WR_01; + state_write <= WR_CHECK_FOR_FIFO_SPACE_01; else if (local_write_header_flag = '1') then