Ignore:
Timestamp:
Feb 24, 2011, 2:58:17 PM (9 years ago)
Author:
neise
Message:
 
File:
1 edited

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  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd

    r10174 r10176  
    2828
    2929ENTITY memory_manager IS
    30   generic(
    31      RAM_ADDR_WIDTH_64B : integer := 12;
    32      RAM_ADDR_WIDTH_16B : integer := 14
    33    );
    34    PORT(
    35       clk : IN std_logic;
    36       config_start : IN std_logic;
    37       ram_write_ready : IN std_logic;
    38       -- --
    39       ram_write_ready_ack : OUT std_logic := '0';
    40       -- --
    41       roi_array : IN roi_array_type;
    42       ram_write_ea : OUT std_logic := '0';
    43       config_ready, config_started : OUT std_logic := '0';
    44       roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11));
    45       package_length : OUT std_logic_vector (15 downto 0) := (others => '0');
    46       wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 downto 0) := (others => '0');
    47       wiz_write_length : OUT std_logic_vector (16 downto 0) := (others => '0');
    48       wiz_number_of_channels : OUT std_logic_vector (3 downto 0) := (others => '0');
    49       wiz_write_ea : OUT std_logic := '0';
    50       wiz_write_header : OUT std_logic := '0';
    51       wiz_write_end : OUT std_logic := '0';
    52       wiz_busy : IN std_logic;
     30generic(
     31        RAM_ADDR_WIDTH_64B : integer := 12;
     32        RAM_ADDR_WIDTH_16B : integer := 14
     33);
     34PORT(
     35        clk : IN std_logic;
     36        config_start : IN std_logic;
     37        ram_write_ready : IN std_logic;
     38        -- --
     39        ram_write_ready_ack : OUT std_logic := '0';
     40        -- --
     41        roi_array : IN roi_array_type;
     42        ram_write_ea : OUT std_logic := '0';
     43        config_ready, config_started : OUT std_logic := '0';
     44        roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11));
     45        package_length : OUT std_logic_vector (15 downto 0) := (others => '0');
     46        wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 downto 0) := (others => '0');
     47        wiz_write_length : OUT std_logic_vector (16 downto 0) := (others => '0');
     48        wiz_number_of_channels : OUT std_logic_vector (3 downto 0) := (others => '0');
     49        wiz_write_ea : OUT std_logic := '0';
     50        wiz_write_header : OUT std_logic := '0';
     51        wiz_write_end : OUT std_logic := '0';
     52        wiz_busy : IN std_logic;
    5353        wiz_ack : IN std_logic;
    54         buffer_ram_empty : out std_logic;
    55       ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0')
    56    );
     54        ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0');
     55        buffer_ram_empty : out std_logic
     56);
    5757
    5858-- Declarations
     
    105105
    106106--  led <= conv_std_logic_vector (events_in_ram, 4) & "00" & wiz_ack & wiz_busy;
    107   buffer_ram_empty <= '0' when events_in_ram=0 else '1';
     107  buffer_ram_empty <= '1' when events_in_ram = 0 else '0';
    108108 
    109109  mm : process (clk)
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