Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd (revision 10174) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd (revision 10176) @@ -32,7 +32,5 @@ ram_write_ea : in std_logic; ram_write_ready : out std_logic := '0'; - ram_write_ready_ack : IN std_logic; - config_start_mm : out std_logic := '0'; config_start_cm : out std_logic := '0'; @@ -49,5 +47,8 @@ sensor_ready : in std_logic; dac_array : in dac_array_type; - + + mode : in std_logic := '0'; -- 0: config mode | 1: run mode + idling : out std_logic; + -- EVT HEADER - part 1 package_length : in std_logic_vector (15 downto 0); @@ -109,5 +110,5 @@ type state_generate_type is ( - CONFIG_CHAIN_START, -- WRITE_DATA_IDLE branches into this state, if needed. + CONFIG_CHAIN_START, -- IDLE branches into this state, if needed. CONFIG_MEMORY_MANAGER, CONFIG_SPI_INTERFACE, @@ -118,5 +119,5 @@ WAIT_FOR_DRS_CONFIG_READY, - WRITE_DATA_IDLE, + IDLE, WRITE_HEADER, WRITE_FTM_INFO, WRITE_EVENTCOUNTER_AND_REFCLK_COUNTER, WRITE_BOARD_ID, WRITE_DNA, WRITE_TIMER, WRITE_TEMPERATURES, @@ -138,5 +139,5 @@ signal start_config_chain_sr : std_logic_vector(1 downto 0); -signal state_generate : state_generate_type := CONFIG; +signal state_generate : state_generate_type := CONFIG_CHAIN_START; signal start_addr : std_logic_vector (RAM_ADDR_WIDTH-1 downto 0) := (others => '0'); @@ -155,7 +156,9 @@ signal sig_drs_readout_started : std_logic := '0'; +signal sig_idling : std_logic := '1'; + begin drs_readout_started <= sig_drs_readout_started; - +idling <= sig_idling; generate_data : process (clk) begin @@ -164,5 +167,5 @@ if (start_config_chain_sr = "01") then start_config_chain_flag <= '1'; - config_chain_done = '0'; + config_chain_done <= '0'; end if; trigger_sr <= trigger_sr(0) & trigger; --synching in of asynchrounous trigger signal. @@ -227,28 +230,36 @@ drs_channel_id <= DRS_ADDR_IDLE; -- to make sure not to write accidentally into DRS shift registers roi_max_int <= roi_max; - config_chain_done = '1'; - state_generate <= WRITE_DATA_IDLE; + config_chain_done <= '1'; + state_generate <= IDLE; end if; -- end configure DRS + when IDLE => + if (mode = '0') then -- do not accept any triggers ! stay in idle, or do a configuration. + sig_idling <= '1'; + if (start_config_chain_flag = '1') then + sig_idling <= '0'; + start_config_chain_flag <= '0'; + state_generate <= CONFIG_CHAIN_START; + else + state_generate <= IDLE; + end if; + else --mode = '1' -- check if trigger arrived. + sig_idling<= '0'; + if (ram_write_ea = '1' and trigger_sr = "01") then + sig_drs_readout_started <= '1'; -- is set to '0' in next state ... just a pulse. + start_read_drs_stop_cell <= '1'; + adc_output_enable_inverted <= '0'; + -- at this moment the ADC ist beeing clocked. + -- this is not the start of the readout. + -- the DRS needs to be clocked as well. + adc_clk_en <= '1'; + start_addr <= ram_start_addr; + state_generate <= WRITE_HEADER; + end if; + end if; - when WRITE_DATA_IDLE => - if (start_config_chain_flag = '1') then - start_config_chain_flag = '0'; - state_generate <= CONFIG_CHAIN_START; - end if; - if (ram_write_ea = '1' and trigger_sr = "01") then - sig_drs_readout_started <= '1'; -- is set to '0' in next state ... just a pulse. - start_read_drs_stop_cell <= '1'; - adc_output_enable_inverted <= '0'; - -- at this moment the ADC ist beeing clocked. - -- this is not the start of the readout. - -- the DRS needs to be clocked as well. - adc_clk_en <= '1'; - start_addr <= ram_start_addr; - state_generate <= WRITE_HEADER; - end if; when WRITE_HEADER => - sig_drs_readout_started <= '0'; -- is set to '1' in state WRITE_DATA_IDLE + sig_drs_readout_started <= '0'; -- is set to '1' in state IDLE dataRAM_write_ea_o <= "1"; data_out <= X"000" & pll_lock & PACKAGE_VERSION & PACKAGE_SUB_VERSION & package_length & X"FB01"; @@ -434,9 +445,9 @@ channel_id <= 0; state_generate <= WRITE_DATA_STOP1; - end if; + end if; when WRITE_DATA_STOP1 => if (drs_readout_ready_ack = '1') then drs_readout_ready <= '0'; - state_generate <= WRITE_DATA_IDLE; + state_generate <= IDLE; end if; when others => Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd (revision 10174) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd (revision 10176) @@ -3,5 +3,5 @@ -- Created: -- by - dneise.UNKNOWN (E5B-LABOR6) --- at - 14:09:41 23.02.2011 +-- at - 15:55:14 24.02.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) @@ -76,5 +76,5 @@ -- Created: -- by - dneise.UNKNOWN (E5B-LABOR6) --- at - 14:09:41 23.02.2011 +-- at - 15:55:15 24.02.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd (revision 10174) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd (revision 10176) @@ -130,8 +130,9 @@ constant DEFAULT_DRSADDR_MODE : std_logic := '0'; - +-- config RAM addresses +constant BADDR_ROI : std_logic_vector := X"00"; -- Baseaddress ROI-Values +constant BADDR_DAC : std_logic_vector := X"24"; -- Baseaddress DAC-Values -- Commands -constant BADDR_ROI : std_logic_vector := X"00"; -- Baseaddress ROI-Values constant CMD_WRITE : std_logic_vector := X"05"; constant CMD_DENABLE : std_logic_vector := X"06"; @@ -154,5 +155,4 @@ constant CMD_START : std_logic_vector := X"22"; -- set data generator in RUN-mnode constant CMD_STOP : std_logic_vector := X"23"; -- set data generator in STOP-mode -constant BADDR_DAC : std_logic_vector := X"24"; -- Baseaddress DAC-Values constant CMC_MODE_COMMAND : std_logic_vector := X"30"; constant CMD_TRIGGER : std_logic_vector := X"A0"; Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd (revision 10174) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd (revision 10176) @@ -3,5 +3,5 @@ -- Created: -- by - dneise.UNKNOWN (E5B-LABOR6) --- at - 14:08:52 23.02.2011 +-- at - 15:55:13 24.02.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) @@ -72,5 +72,5 @@ -- Created: -- by - dneise.UNKNOWN (E5B-LABOR6) --- at - 14:08:53 23.02.2011 +-- at - 15:55:14 24.02.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) @@ -97,6 +97,6 @@ -- Internal signal declarations - SIGNAL CLK_25 : std_logic; - SIGNAL DCM_PS_status : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL CLK_25 : std_logic; + SIGNAL DCM_PS_status : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); -- @@ -104,98 +104,99 @@ -- during EVT header wrinting, this field is left out ... and only written into event header, -- when the DRS chip were read out already. - SIGNAL FTM_RS485_ready : std_logic; - SIGNAL SRCLK1 : std_logic := '0'; - SIGNAL adc_data_array_int : adc_data_array_type; - SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0); - SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0); - SIGNAL c_trigger_enable : std_logic := '0'; - SIGNAL c_trigger_mult : std_logic_vector(15 DOWNTO 0); - SIGNAL config_addr : std_logic_vector(7 DOWNTO 0); - SIGNAL config_busy : std_logic; - SIGNAL config_data : std_logic_vector(15 DOWNTO 0); - SIGNAL config_data_valid : std_logic; - SIGNAL config_rd_en : std_logic; - SIGNAL config_ready : std_logic; - SIGNAL config_ready_cm : std_logic; - SIGNAL config_ready_spi : std_logic; + SIGNAL FTM_RS485_ready : std_logic; + SIGNAL SRCLK1 : std_logic := '0'; + SIGNAL adc_data_array_int : adc_data_array_type; + SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0); + SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0); + SIGNAL c_trigger_enable : std_logic := '0'; + SIGNAL c_trigger_mult : std_logic_vector(15 DOWNTO 0); + SIGNAL config_addr : std_logic_vector(7 DOWNTO 0); + SIGNAL config_busy : std_logic; + SIGNAL config_data : std_logic_vector(15 DOWNTO 0); + SIGNAL config_data_valid : std_logic; + SIGNAL config_rd_en : std_logic; + SIGNAL config_ready : std_logic; + SIGNAL config_ready_cm : std_logic; + SIGNAL config_ready_spi : std_logic; -- -- - SIGNAL config_rw_ack : std_logic := '0'; + SIGNAL config_rw_ack : std_logic := '0'; -- -- - SIGNAL config_rw_ready : std_logic := '0'; - SIGNAL config_start : std_logic := '0'; - SIGNAL config_start_cm : std_logic; - SIGNAL config_start_spi : std_logic := '0'; - SIGNAL config_started : std_logic; - SIGNAL config_started_cu : std_logic := '0'; - SIGNAL config_started_mm : std_logic; - SIGNAL config_started_spi : std_logic := '0'; - SIGNAL config_wr_en : std_logic; - SIGNAL crc : std_logic_vector(7 DOWNTO 0); - SIGNAL dac_array : dac_array_type; - SIGNAL data_out : std_logic_vector(63 DOWNTO 0); - SIGNAL denable_inhibit : std_logic := '0'; -- default domino wave off - SIGNAL denable_prim : std_logic := '0'; -- default domino wave off - SIGNAL din1 : std_logic := '0'; -- default domino wave off - SIGNAL dna : STD_LOGIC_VECTOR(63 DOWNTO 0) := (others => '0'); - SIGNAL dout : std_logic; - SIGNAL dout1 : std_logic; - SIGNAL drs_clk_en : std_logic := '0'; - SIGNAL drs_read_s_cell : std_logic := '0'; - SIGNAL drs_read_s_cell_ready : std_logic; + SIGNAL config_rw_ready : std_logic := '0'; + SIGNAL config_start : std_logic := '0'; + SIGNAL config_start_cm : std_logic; + SIGNAL config_start_spi : std_logic := '0'; + SIGNAL config_started : std_logic; + SIGNAL config_started_cu : std_logic := '0'; + SIGNAL config_started_mm : std_logic; + SIGNAL config_started_spi : std_logic := '0'; + SIGNAL config_wr_en : std_logic; + SIGNAL crc : std_logic_vector(7 DOWNTO 0); + SIGNAL dac_array : dac_array_type; + SIGNAL data_generator_run_mode : std_logic := '0'; -- default triggers are NOT accepted + SIGNAL data_out : std_logic_vector(63 DOWNTO 0); + SIGNAL denable_inhibit : std_logic := '0'; -- default domino wave off + SIGNAL denable_prim : std_logic := '0'; -- default domino wave off + SIGNAL din1 : std_logic := '0'; -- default domino wave off + SIGNAL dna : STD_LOGIC_VECTOR(63 DOWNTO 0) := (others => '0'); + SIGNAL dout : std_logic; + SIGNAL dout1 : std_logic; + SIGNAL drs_clk_en : std_logic := '0'; + SIGNAL drs_read_s_cell : std_logic := '0'; + SIGNAL drs_read_s_cell_ready : std_logic; -- -- -- drs_dwrite : out std_logic := '1'; - SIGNAL drs_readout_ready : std_logic := '0'; - SIGNAL drs_readout_ready_ack : std_logic; - SIGNAL drs_readout_started : std_logic; - SIGNAL drs_s_cell_array : drs_s_cell_array_type; - SIGNAL drs_srin_data : std_logic_vector(7 DOWNTO 0) := (others => '0'); - SIGNAL dwrite : std_logic := '1'; - SIGNAL dwrite_enable : std_logic := '1'; - SIGNAL enable_i : std_logic; - SIGNAL new_config : std_logic := '0'; - SIGNAL package_length : std_logic_vector(15 DOWNTO 0); - SIGNAL ps_direction : std_logic := '1'; -- default phase shift upwards - SIGNAL ps_do_phase_shift : std_logic := '0'; --pulse this to phase shift once - SIGNAL ps_reset : std_logic := '0'; -- pulse this to reset the variable phase shift - SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0); - SIGNAL ram_data : std_logic_vector(15 DOWNTO 0); - SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0); - SIGNAL ram_write_ea : std_logic; - SIGNAL ram_write_ready : std_logic := '0'; + SIGNAL drs_readout_ready : std_logic := '0'; + SIGNAL drs_readout_ready_ack : std_logic; + SIGNAL drs_readout_started : std_logic; + SIGNAL drs_s_cell_array : drs_s_cell_array_type; + SIGNAL drs_srin_data : std_logic_vector(7 DOWNTO 0) := (others => '0'); + SIGNAL dwrite : std_logic := '1'; + SIGNAL dwrite_enable : std_logic := '1'; + SIGNAL enable_i : std_logic; + SIGNAL new_config : std_logic := '0'; + SIGNAL package_length : std_logic_vector(15 DOWNTO 0); + SIGNAL ps_direction : std_logic := '1'; -- default phase shift upwards + SIGNAL ps_do_phase_shift : std_logic := '0'; --pulse this to phase shift once + SIGNAL ps_reset : std_logic := '0'; -- pulse this to reset the variable phase shift + SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0); + SIGNAL ram_data : std_logic_vector(15 DOWNTO 0); + SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0); + SIGNAL ram_write_ea : std_logic; + SIGNAL ram_write_ready : std_logic := '0'; -- -- - SIGNAL ram_write_ready_ack : std_logic := '0'; - SIGNAL ready : STD_LOGIC := '0'; - SIGNAL reset_synch_i : std_logic; - SIGNAL roi_array : roi_array_type; - SIGNAL roi_max : roi_max_type; - SIGNAL rs465_data : std_logic_vector(55 DOWNTO 0); --7 byte - SIGNAL s_trigger : std_logic; - SIGNAL s_trigger_0 : std_logic; - SIGNAL sclk1 : std_logic; - SIGNAL sclk_enable : std_logic; - SIGNAL sensor_array : sensor_array_type; - SIGNAL sensor_ready : std_logic; - SIGNAL socks_connected : std_logic; - SIGNAL socks_waiting : std_logic; - SIGNAL srclk_enable : std_logic := '0'; - SIGNAL srin_write_ack : std_logic := '0'; - SIGNAL srin_write_ready : std_logic := '0'; - SIGNAL start_srin_write_8b : std_logic; - SIGNAL time : std_logic_vector(31 DOWNTO 0); - SIGNAL trigger1 : std_logic; - SIGNAL trigger_enable : std_logic; - SIGNAL trigger_id : std_logic_vector(31 DOWNTO 0); - SIGNAL trigger_out : std_logic; - SIGNAL trigger_type1 : std_logic_vector(7 DOWNTO 0); - SIGNAL trigger_type2 : std_logic_vector(7 DOWNTO 0); - SIGNAL wiz_ack : std_logic; - SIGNAL wiz_busy : std_logic; - SIGNAL wiz_number_of_channels : std_logic_vector(3 DOWNTO 0) := (others => '0'); - SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0'); - SIGNAL wiz_write_ea : std_logic := '0'; - SIGNAL wiz_write_end : std_logic := '0'; - SIGNAL wiz_write_header : std_logic := '0'; - SIGNAL wiz_write_length : std_logic_vector(16 DOWNTO 0) := (others => '0'); - SIGNAL write_ea : std_logic_vector(0 DOWNTO 0) := "0"; + SIGNAL ram_write_ready_ack : std_logic := '0'; + SIGNAL ready : STD_LOGIC := '0'; + SIGNAL reset_synch_i : std_logic; + SIGNAL roi_array : roi_array_type; + SIGNAL roi_max : roi_max_type; + SIGNAL rs465_data : std_logic_vector(55 DOWNTO 0); --7 byte + SIGNAL s_trigger : std_logic; + SIGNAL s_trigger_0 : std_logic; + SIGNAL sclk1 : std_logic; + SIGNAL sclk_enable : std_logic; + SIGNAL sensor_array : sensor_array_type; + SIGNAL sensor_ready : std_logic; + SIGNAL socks_connected : std_logic; + SIGNAL socks_waiting : std_logic; + SIGNAL srclk_enable : std_logic := '0'; + SIGNAL srin_write_ack : std_logic := '0'; + SIGNAL srin_write_ready : std_logic := '0'; + SIGNAL start_srin_write_8b : std_logic; + SIGNAL time : std_logic_vector(31 DOWNTO 0); + SIGNAL trigger1 : std_logic; + SIGNAL trigger_enable : std_logic; + SIGNAL trigger_id : std_logic_vector(31 DOWNTO 0); + SIGNAL trigger_out : std_logic; + SIGNAL trigger_type1 : std_logic_vector(7 DOWNTO 0); + SIGNAL trigger_type2 : std_logic_vector(7 DOWNTO 0); + SIGNAL wiz_ack : std_logic; + SIGNAL wiz_busy : std_logic; + SIGNAL wiz_number_of_channels : std_logic_vector(3 DOWNTO 0) := (others => '0'); + SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0'); + SIGNAL wiz_write_ea : std_logic := '0'; + SIGNAL wiz_write_end : std_logic := '0'; + SIGNAL wiz_write_header : std_logic := '0'; + SIGNAL wiz_write_length : std_logic_vector(16 DOWNTO 0) := (others => '0'); + SIGNAL write_ea : std_logic_vector(0 DOWNTO 0) := "0"; -- Implicit buffer signal declarations @@ -296,88 +297,70 @@ ); PORT ( - -- led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); - clk : IN std_logic ; - data_out : OUT std_logic_vector (63 DOWNTO 0); - addr_out : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); - write_ea : OUT std_logic_vector (0 DOWNTO 0) := "0"; - ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); - ram_write_ea : IN std_logic ; - ram_write_ready : OUT std_logic := '0'; - -- -- - ram_write_ready_ack : IN std_logic ; - -- -- - config_start_mm : OUT std_logic := '0'; - -- -- - config_start_cm : OUT std_logic := '0'; - -- -- - config_start_spi : OUT std_logic := '0'; - config_ready_mm : IN std_logic ; - config_ready_cm : IN std_logic ; - config_ready_spi : IN std_logic ; - config_started_mm : IN std_logic ; - config_started_cm : IN std_logic ; - config_started_spi : IN std_logic ; - roi_array : IN roi_array_type ; - roi_max : IN roi_max_type ; - sensor_array : IN sensor_array_type ; - sensor_ready : IN std_logic ; - dac_array : IN dac_array_type ; + clk : IN std_logic ; -- CLK_25. + data_out : OUT std_logic_vector (63 DOWNTO 0); + addr_out : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + dataRAM_write_ea_o : OUT std_logic_vector (0 DOWNTO 0) := "0"; + ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + ram_write_ea : IN std_logic ; + ram_write_ready : OUT std_logic := '0'; + ram_write_ready_ack : IN std_logic ; + config_start_mm : OUT std_logic := '0'; + config_start_cm : OUT std_logic := '0'; + config_start_spi : OUT std_logic := '0'; + config_ready_mm : IN std_logic ; + config_ready_cm : IN std_logic ; + config_ready_spi : IN std_logic ; + config_started_mm : IN std_logic ; + config_started_cm : IN std_logic ; + config_started_spi : IN std_logic ; + roi_array : IN roi_array_type ; + roi_max : IN roi_max_type ; + sensor_array : IN sensor_array_type ; + sensor_ready : IN std_logic ; + dac_array : IN dac_array_type ; + mode : IN std_logic := '0'; -- 0: config mode | 1: run mode + idling : OUT std_logic ; -- EVT HEADER - part 1 - package_length : IN std_logic_vector (15 DOWNTO 0); - pll_lock : IN std_logic_vector ( 3 DOWNTO 0); - -- - + package_length : IN std_logic_vector (15 DOWNTO 0); + pll_lock : IN std_logic_vector ( 3 DOWNTO 0); -- EVT HEADER - part 2 --> FTM trigger informaton, comes in late ... -- during EVT header wrinting, this field is left out ... and only written into event header, -- when the DRS chip were read out already. - FTM_RS485_ready : IN std_logic ; - FTM_trigger_info : IN std_logic_vector (55 DOWNTO 0); --7 byte - -- - + FTM_RS485_ready : IN std_logic ; + FTM_trigger_info : IN std_logic_vector (55 DOWNTO 0); --7 byte -- EVT HEADER - part 3 - fad_event_counter : IN std_logic_vector (31 DOWNTO 0); - refclk_counter : IN std_logic_vector (11 DOWNTO 0); - refclk_too_high : IN std_logic ; - refclk_too_low : IN std_logic ; - -- - + fad_event_counter : IN std_logic_vector (31 DOWNTO 0); + refclk_counter : IN std_logic_vector (11 DOWNTO 0); + refclk_too_high : IN std_logic ; + refclk_too_low : IN std_logic ; -- EVT HEADER - part 4 - board_id : IN std_logic_vector (3 DOWNTO 0); - crate_id : IN std_logic_vector (1 DOWNTO 0); - DCM_PS_status : IN std_logic_vector (7 DOWNTO 0); - TRG_GEN_div : IN std_logic_vector (15 DOWNTO 0); - -- - + board_id : IN std_logic_vector (3 DOWNTO 0); + crate_id : IN std_logic_vector (1 DOWNTO 0); + DCM_PS_status : IN std_logic_vector (7 DOWNTO 0); + TRG_GEN_div : IN std_logic_vector (15 DOWNTO 0); -- EVT HEADER - part 5 - dna : IN std_logic_vector (63 DOWNTO 0); - -- - + dna : IN std_logic_vector (63 DOWNTO 0); -- EVT HEADER - part 6 - timer_value : IN std_logic_vector (31 DOWNTO 0); -- time in units of 100us - -- - trigger : IN std_logic ; - -- s_trigger : in std_logic; - new_config : IN std_logic ; - config_started : OUT std_logic := '0'; - adc_data_array : IN adc_data_array_type ; - adc_oeb : OUT std_logic := '1'; - adc_clk_en : OUT std_logic := '0'; - adc_otr : IN std_logic_vector (3 DOWNTO 0); - drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); - -- -- - -- drs_dwrite : out std_logic := '1'; - drs_readout_ready : OUT std_logic := '0'; - drs_readout_ready_ack : IN std_logic ; - -- -- - drs_clk_en : OUT std_logic := '0'; - -- -- - drs_read_s_cell : OUT std_logic := '0'; - drs_srin_write_8b : OUT std_logic := '0'; - drs_srin_write_ack : IN std_logic ; - drs_srin_data : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); - drs_srin_write_ready : IN std_logic ; - drs_read_s_cell_ready : IN std_logic ; - drs_s_cell_array : IN drs_s_cell_array_type ; - drs_readout_started : OUT std_logic := '0' + timer_value : IN std_logic_vector (31 DOWNTO 0); -- time in units of 100us + trigger : IN std_logic ; + start_config_chain : IN std_logic ; -- here W5300_MODUL can start the whole config chain + config_chain_done : OUT std_logic ; + adc_data_array : IN adc_data_array_type ; + adc_output_enable_inverted : OUT std_logic := '1'; + adc_clk_en : OUT std_logic := '0'; + adc_otr : IN std_logic_vector (3 DOWNTO 0); + drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); + --drs_dwrite : out std_logic := '1'; + drs_readout_ready : OUT std_logic := '0'; + drs_readout_ready_ack : IN std_logic ; + drs_clk_en : OUT std_logic := '0'; + start_read_drs_stop_cell : OUT std_logic := '0'; + drs_srin_write_8b : OUT std_logic := '0'; + drs_srin_write_ack : IN std_logic ; + drs_srin_data : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); + drs_srin_write_ready : IN std_logic ; + drs_read_s_cell_ready : IN std_logic ; + drs_s_cell_array : IN drs_s_cell_array_type ; + drs_readout_started : OUT std_logic := '0' ); END COMPONENT; @@ -452,4 +435,5 @@ wiz_busy : IN std_logic ; wiz_ack : IN std_logic ; + buffer_ram_empty : OUT std_logic ; ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0') ); @@ -507,56 +491,57 @@ ); PORT ( - clk : IN std_logic ; - wiz_reset : OUT std_logic := '1'; - addr : OUT std_logic_vector (9 DOWNTO 0); - data : INOUT std_logic_vector (15 DOWNTO 0); - cs : OUT std_logic := '1'; - wr : OUT std_logic := '1'; - led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); - rd : OUT std_logic := '1'; - int : IN std_logic ; - write_length : IN std_logic_vector (16 DOWNTO 0); - ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); - ram_data : IN std_logic_vector (15 DOWNTO 0); - ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); - data_valid : IN std_logic ; - data_valid_ack : OUT std_logic := '0'; - busy : OUT std_logic := '1'; - write_header_flag : IN std_logic ; - write_end_flag : IN std_logic ; - fifo_channels : IN std_logic_vector (3 DOWNTO 0); + clk : IN std_logic ; + wiz_reset : OUT std_logic := '1'; + addr : OUT std_logic_vector (9 DOWNTO 0); + data : INOUT std_logic_vector (15 DOWNTO 0); + cs : OUT std_logic := '1'; + wr : OUT std_logic := '1'; + led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + rd : OUT std_logic := '1'; + int : IN std_logic ; + write_length : IN std_logic_vector (16 DOWNTO 0); + ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + ram_data : IN std_logic_vector (15 DOWNTO 0); + ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + data_valid : IN std_logic ; + data_valid_ack : OUT std_logic := '0'; + busy : OUT std_logic := '1'; + write_header_flag : IN std_logic ; + write_end_flag : IN std_logic ; + fifo_channels : IN std_logic_vector (3 DOWNTO 0); -- softtrigger: - s_trigger : OUT std_logic := '0'; - c_trigger_enable : OUT std_logic := '0'; - c_trigger_mult : OUT std_logic_vector (15 DOWNTO 0) := conv_std_logic_vector(100 ,16); --subject TO changes + s_trigger : OUT std_logic := '0'; + c_trigger_enable : OUT std_logic := '0'; + c_trigger_mult : OUT std_logic_vector (15 DOWNTO 0) := conv_std_logic_vector(100 ,16); --subject TO changes -- FAD configuration signals: ------------------------------------------------------------------------------ -- start entire configuration chain - new_config : OUT std_logic := '0'; - config_started : IN std_logic ; + new_config : OUT std_logic := '0'; + config_chain_done : IN std_logic ; -- read/write configRAM - config_addr : OUT std_logic_vector (7 DOWNTO 0); - config_data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); - config_wr_en : OUT std_logic := '0'; - config_rd_en : OUT std_logic := '0'; - config_rw_ack : IN std_logic ; - config_rw_ready : IN std_logic ; - config_busy : IN std_logic ; + config_addr : OUT std_logic_vector (7 DOWNTO 0); + config_data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); + config_wr_en : OUT std_logic := '0'; + config_rd_en : OUT std_logic := '0'; + config_rw_ack : IN std_logic ; + config_rw_ready : IN std_logic ; + config_busy : IN std_logic ; ------------------------------------------------------------------------------ -- MAC/IP calculation signals: ------------------------------------------------------------------------------ - MAC_jumper : IN std_logic_vector (1 DOWNTO 0); - BoardID : IN std_logic_vector (3 DOWNTO 0); - CrateID : IN std_logic_vector (1 DOWNTO 0); + MAC_jumper : IN std_logic_vector (1 DOWNTO 0); + BoardID : IN std_logic_vector (3 DOWNTO 0); + CrateID : IN std_logic_vector (1 DOWNTO 0); ------------------------------------------------------------------------------ -- user controllable enable signals ------------------------------------------------------------------------------ - trigger_enable : OUT std_logic := '0'; -- default triggers are NOT accepted - denable : OUT std_logic := '0'; -- default domino wave off - dwrite_enable : OUT std_logic := '0'; -- default DWRITE low. - sclk_enable : OUT std_logic := '1'; -- default DWRITE HIGH. - srclk_enable : OUT std_logic := '1'; -- default SRCLK on. + trigger_enable : OUT std_logic := '0'; -- default triggers are NOT accepted + data_generator_run_mode : OUT std_logic := '0'; -- default triggers are NOT accepted + denable : OUT std_logic := '0'; -- default domino wave off + dwrite_enable : OUT std_logic := '0'; -- default DWRITE low. + sclk_enable : OUT std_logic := '1'; -- default DWRITE HIGH. + srclk_enable : OUT std_logic := '1'; -- default SRCLK on. ------------------------------------------------------------------------------ @@ -564,7 +549,7 @@ -- these signals control the behavior of the digital clock manager (DCM) ------------------------------------------------------------------------------ - ps_direction : OUT std_logic := '1'; -- default phase shift upwards - ps_do_phase_shift : OUT std_logic := '0'; --pulse this TO phase shift once - ps_reset : OUT std_logic := '0'; -- pulse this TO reset the variable phase shift + ps_direction : OUT std_logic := '1'; -- default phase shift upwards + ps_do_phase_shift : OUT std_logic := '0'; --pulse this TO phase shift once + ps_reset : OUT std_logic := '0'; -- pulse this TO reset the variable phase shift ------------------------------------------------------------------------------ @@ -572,6 +557,6 @@ -- one of the three LEDs is used for com-status info ------------------------------------------------------------------------------ - socks_waiting : OUT std_logic ; - socks_connected : OUT std_logic + socks_waiting : OUT std_logic ; + socks_connected : OUT std_logic ------------------------------------------------------------------------------ ); @@ -722,59 +707,61 @@ ) PORT MAP ( - clk => CLK_25, - data_out => data_out, - addr_out => addr_out, - write_ea => write_ea, - ram_start_addr => ram_start_addr, - ram_write_ea => ram_write_ea, - ram_write_ready => ram_write_ready, - ram_write_ready_ack => ram_write_ready_ack, - config_start_mm => config_start, - config_start_cm => config_start_cm, - config_start_spi => config_start_spi, - config_ready_mm => config_ready, - config_ready_cm => config_ready_cm, - config_ready_spi => config_ready_spi, - config_started_mm => config_started_mm, - config_started_cm => config_started_cu, - config_started_spi => config_started_spi, - roi_array => roi_array, - roi_max => roi_max, - sensor_array => sensor_array, - sensor_ready => sensor_ready, - dac_array => dac_array, - package_length => package_length, - pll_lock => plllock_in, - FTM_RS485_ready => FTM_RS485_ready, - FTM_trigger_info => rs465_data, - fad_event_counter => trigger_id, - refclk_counter => counter_result_internal, - refclk_too_high => alarm_refclk_too_high_internal, - refclk_too_low => alarm_refclk_too_low_internal, - board_id => board_id, - crate_id => crate_id, - DCM_PS_status => DCM_PS_status, - TRG_GEN_div => c_trigger_mult, - dna => dna, - timer_value => time, - trigger => trigger_out, - new_config => new_config, - config_started => config_started, - adc_data_array => adc_data_array_int, - adc_oeb => adc_oeb, - adc_clk_en => adc_clk_en, - adc_otr => adc_otr, - drs_channel_id => drs_channel_id, - drs_readout_ready => drs_readout_ready, - drs_readout_ready_ack => drs_readout_ready_ack, - drs_clk_en => drs_clk_en, - drs_read_s_cell => drs_read_s_cell, - drs_srin_write_8b => start_srin_write_8b, - drs_srin_write_ack => srin_write_ack, - drs_srin_data => drs_srin_data, - drs_srin_write_ready => srin_write_ready, - drs_read_s_cell_ready => drs_read_s_cell_ready, - drs_s_cell_array => drs_s_cell_array, - drs_readout_started => drs_readout_started + clk => CLK_25, + data_out => data_out, + addr_out => addr_out, + dataRAM_write_ea_o => write_ea, + ram_start_addr => ram_start_addr, + ram_write_ea => ram_write_ea, + ram_write_ready => ram_write_ready, + ram_write_ready_ack => ram_write_ready_ack, + config_start_mm => config_start, + config_start_cm => config_start_cm, + config_start_spi => config_start_spi, + config_ready_mm => config_ready, + config_ready_cm => config_ready_cm, + config_ready_spi => config_ready_spi, + config_started_mm => config_started_mm, + config_started_cm => config_started_cu, + config_started_spi => config_started_spi, + roi_array => roi_array, + roi_max => roi_max, + sensor_array => sensor_array, + sensor_ready => sensor_ready, + dac_array => dac_array, + mode => OPEN, + idling => OPEN, + package_length => package_length, + pll_lock => plllock_in, + FTM_RS485_ready => FTM_RS485_ready, + FTM_trigger_info => rs465_data, + fad_event_counter => trigger_id, + refclk_counter => counter_result_internal, + refclk_too_high => alarm_refclk_too_high_internal, + refclk_too_low => alarm_refclk_too_low_internal, + board_id => board_id, + crate_id => crate_id, + DCM_PS_status => DCM_PS_status, + TRG_GEN_div => c_trigger_mult, + dna => dna, + timer_value => time, + trigger => trigger_out, + start_config_chain => new_config, + config_chain_done => config_started, + adc_data_array => adc_data_array_int, + adc_output_enable_inverted => adc_oeb, + adc_clk_en => adc_clk_en, + adc_otr => adc_otr, + drs_channel_id => drs_channel_id, + drs_readout_ready => drs_readout_ready, + drs_readout_ready_ack => drs_readout_ready_ack, + drs_clk_en => drs_clk_en, + start_read_drs_stop_cell => drs_read_s_cell, + drs_srin_write_8b => start_srin_write_8b, + drs_srin_write_ack => srin_write_ack, + drs_srin_data => drs_srin_data, + drs_srin_write_ready => srin_write_ready, + drs_read_s_cell_ready => drs_read_s_cell_ready, + drs_s_cell_array => drs_s_cell_array, + drs_readout_started => drs_readout_started ); U_0 : dna_gen @@ -843,4 +830,5 @@ wiz_busy => wiz_busy, wiz_ack => wiz_ack, + buffer_ram_empty => OPEN, ram_start_addr => ram_start_addr ); @@ -888,53 +876,54 @@ drs_readout_ready_ack => drs_readout_ready_ack ); - I_main_ethernet : w5300_modul + w5300_modul_instance : w5300_modul GENERIC MAP ( RAM_ADDR_WIDTH => RAMADDRWIDTH64b+2 ) PORT MAP ( - clk => CLK_50_internal, - wiz_reset => wiz_reset, - addr => wiz_addr, - data => wiz_data, - cs => wiz_cs, - wr => wiz_wr, - led => led, - rd => wiz_rd, - int => wiz_int, - write_length => wiz_write_length, - ram_start_addr => wiz_ram_start_addr, - ram_data => ram_data, - ram_addr => ram_addr, - data_valid => wiz_write_ea, - data_valid_ack => wiz_ack, - busy => wiz_busy, - write_header_flag => wiz_write_header, - write_end_flag => wiz_write_end, - fifo_channels => wiz_number_of_channels, - s_trigger => s_trigger_0, - c_trigger_enable => c_trigger_enable, - c_trigger_mult => c_trigger_mult, - new_config => new_config, - config_started => config_started, - config_addr => config_addr, - config_data => config_data, - config_wr_en => config_wr_en, - config_rd_en => config_rd_en, - config_rw_ack => config_rw_ack, - config_rw_ready => config_rw_ready, - config_busy => config_busy, - MAC_jumper => D_T_in, - BoardID => board_id, - CrateID => crate_id, - trigger_enable => trigger_enable, - denable => denable_prim, - dwrite_enable => dwrite_enable, - sclk_enable => sclk_enable, - srclk_enable => srclk_enable, - ps_direction => ps_direction, - ps_do_phase_shift => ps_do_phase_shift, - ps_reset => ps_reset, - socks_waiting => socks_waiting, - socks_connected => socks_connected + clk => CLK_50_internal, + wiz_reset => wiz_reset, + addr => wiz_addr, + data => wiz_data, + cs => wiz_cs, + wr => wiz_wr, + led => led, + rd => wiz_rd, + int => wiz_int, + write_length => wiz_write_length, + ram_start_addr => wiz_ram_start_addr, + ram_data => ram_data, + ram_addr => ram_addr, + data_valid => wiz_write_ea, + data_valid_ack => wiz_ack, + busy => wiz_busy, + write_header_flag => wiz_write_header, + write_end_flag => wiz_write_end, + fifo_channels => wiz_number_of_channels, + s_trigger => s_trigger_0, + c_trigger_enable => c_trigger_enable, + c_trigger_mult => c_trigger_mult, + new_config => new_config, + config_chain_done => config_started, + config_addr => config_addr, + config_data => config_data, + config_wr_en => config_wr_en, + config_rd_en => config_rd_en, + config_rw_ack => config_rw_ack, + config_rw_ready => config_rw_ready, + config_busy => config_busy, + MAC_jumper => D_T_in, + BoardID => board_id, + CrateID => crate_id, + trigger_enable => trigger_enable, + data_generator_run_mode => data_generator_run_mode, + denable => denable_prim, + dwrite_enable => dwrite_enable, + sclk_enable => sclk_enable, + srclk_enable => srclk_enable, + ps_direction => ps_direction, + ps_do_phase_shift => ps_do_phase_shift, + ps_reset => ps_reset, + socks_waiting => socks_waiting, + socks_connected => socks_connected ); Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd (revision 10174) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd (revision 10176) @@ -28,31 +28,31 @@ ENTITY memory_manager IS - generic( - RAM_ADDR_WIDTH_64B : integer := 12; - RAM_ADDR_WIDTH_16B : integer := 14 - ); - PORT( - clk : IN std_logic; - config_start : IN std_logic; - ram_write_ready : IN std_logic; - -- -- - ram_write_ready_ack : OUT std_logic := '0'; - -- -- - roi_array : IN roi_array_type; - ram_write_ea : OUT std_logic := '0'; - config_ready, config_started : OUT std_logic := '0'; - roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11)); - package_length : OUT std_logic_vector (15 downto 0) := (others => '0'); - wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 downto 0) := (others => '0'); - wiz_write_length : OUT std_logic_vector (16 downto 0) := (others => '0'); - wiz_number_of_channels : OUT std_logic_vector (3 downto 0) := (others => '0'); - wiz_write_ea : OUT std_logic := '0'; - wiz_write_header : OUT std_logic := '0'; - wiz_write_end : OUT std_logic := '0'; - wiz_busy : IN std_logic; +generic( + RAM_ADDR_WIDTH_64B : integer := 12; + RAM_ADDR_WIDTH_16B : integer := 14 +); +PORT( + clk : IN std_logic; + config_start : IN std_logic; + ram_write_ready : IN std_logic; + -- -- + ram_write_ready_ack : OUT std_logic := '0'; + -- -- + roi_array : IN roi_array_type; + ram_write_ea : OUT std_logic := '0'; + config_ready, config_started : OUT std_logic := '0'; + roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11)); + package_length : OUT std_logic_vector (15 downto 0) := (others => '0'); + wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 downto 0) := (others => '0'); + wiz_write_length : OUT std_logic_vector (16 downto 0) := (others => '0'); + wiz_number_of_channels : OUT std_logic_vector (3 downto 0) := (others => '0'); + wiz_write_ea : OUT std_logic := '0'; + wiz_write_header : OUT std_logic := '0'; + wiz_write_end : OUT std_logic := '0'; + wiz_busy : IN std_logic; wiz_ack : IN std_logic; - buffer_ram_empty : out std_logic; - ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0') - ); + ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0'); + buffer_ram_empty : out std_logic +); -- Declarations @@ -105,5 +105,5 @@ -- led <= conv_std_logic_vector (events_in_ram, 4) & "00" & wiz_ack & wiz_busy; - buffer_ram_empty <= '0' when events_in_ram=0 else '1'; + buffer_ram_empty <= '1' when events_in_ram = 0 else '0'; mm : process (clk) Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd (revision 10174) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd (revision 10176) @@ -40,5 +40,5 @@ new_config : OUT std_logic := '0'; config_chain_done : IN std_logic; - config_started : in std_logic; + -- read/write configRAM config_addr : out std_logic_vector (7 downto 0); @@ -88,18 +88,36 @@ architecture Behavioral of w5300_modul is -type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA, - INIT, LOCATE, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, - SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA); +type state_init_type is ( + INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA, + INIT, LOCATE, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, + SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, + CONFIG, WAIT_FOR_CONFIG_DONE, + MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA +); type state_write_type is ( WR_START, WR_GET_EVT_ID_WAIT1, WR_GET_EVT_ID1, WR_GET_EVT_ID_WAIT2, WR_GET_EVT_ID2, WR_MOD7_STARTED, WR_WAIT_FOR_MOD7, - WR_CHECK_FOR_FIFO_SPACE_01, WR_CHECK_FOR_FIFO_SPACE_02, WR_CHECK_FOR_FIFO_SPACE_03, WR_CHECK_FOR_FIFO_SPACE_04, - + WR_CHECK_FOR_FIFO_SPACE_01, WR_CHECK_FOR_FIFO_SPACE_02, WR_CHECK_FOR_FIFO_SPACE_03, WR_CHECK_FOR_FIFO_SPACE_04, WR_05, WR_05a, WR_05b, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2, - WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3); + WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3 +); type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04); type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06); -type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_6, RD_WAIT, RD_WAIT1, RD_END); +type state_read_data_type is ( + RD_1, + RD_2, + RD_3, + RD_4, + RD_5, + RD_6, + READ_COMMAND_DATA_SECTION, + PUT_COMMAND_DATA_SECTION, + NEW_CONT_TRIGGER_MULT_FACTOR_READ, + NEW_CONT_TRIGGER_MULT_FACTOR_PUT, + RD_WAIT, + RD_WAIT1, + RD_END +); signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120"; @@ -140,5 +158,4 @@ signal rx_packets_cnt : std_logic_vector (15 downto 0); -signal next_packet_data : std_logic := '0'; signal new_config_flag : std_logic := '0'; @@ -192,6 +209,4 @@ signal mod7_valid : std_logic; signal mod7_result : std_logic_vector(2 downto 0); - -signal set_new_CONT_TRIGGER_MULT_FACTOR : std_logic := '0'; COMPONENT mod7 @@ -577,22 +592,20 @@ when ESTABLISH => - socks_waiting <= '1'; - socks_connected <= '0'; + socks_waiting <= '1'; + socks_connected <= '0'; par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC; state_init <= READ_REG; next_state <= EST1; when EST1 => --- led <= data_read (7 downto 0); --- led <= X"00"; case data_read (7 downto 0) is when X"17" => -- established - if (socket_cnt = 7) then - socket_cnt <= "000"; - busy <= '0'; - state_init <= MAIN; - else - socket_cnt <= socket_cnt + 1; - state_init <= ESTABLISH; - end if; + if (socket_cnt = 7) then + socket_cnt <= "000"; + busy <= '0'; + state_init <= MAIN; + else + socket_cnt <= socket_cnt + 1; + state_init <= ESTABLISH; + end if; when others => state_init <= ESTABLISH; @@ -608,209 +621,212 @@ end if; - ----------------------------------------- - -- MAIN "loop" -------------------------- - ----------------------------------------- +---------------------------------------------------------------------------------- +-- MAIN "loop" ------------------------------------------------------------------- +---------------------------------------------------------------------------------- when MAIN => - socks_waiting <= '0'; - socks_connected <= '1'; - - ps_do_phase_shift <= '0'; - ps_reset <= '0'; - if (trigger_stop = '1') then - s_trigger <= '0'; - end if; - data_valid_ack <= '0'; - state_init <= MAIN1; - --data_valid_int <= data_valid; + socks_waiting <= '0'; + socks_connected <= '1'; + ps_do_phase_shift <= '0'; + ps_reset <= '0'; + if (trigger_stop = '1') then + s_trigger <= '0'; + end if; + data_valid_ack <= '0'; + state_init <= MAIN1; + --data_valid_int <= data_valid; when MAIN1 => - if (chk_recv_cntr = 1000) then - chk_recv_cntr <= 0; - state_read_data <= RD_1; - state_init <= READ_DATA; - busy <= '1'; - else - chk_recv_cntr <= chk_recv_cntr + 1; - state_init <= MAIN2; - end if; - when MAIN2 => - busy <= '0'; - --if (data_valid = '1') then - if (data_valid_sr = "01" or data_valid_sr = "11") then - --data_valid_int <= '0'; - busy <= '1'; - local_write_length <= write_length; - local_ram_start_addr <= ram_start_addr; - local_ram_addr <= (others => '0'); - local_write_header_flag <= write_header_flag; - local_write_end_flag <= write_end_flag; - local_fifo_channels <= fifo_channels; --- data_valid_ack <= '1'; --- next_state <= MAIN; --- state_init <= WRITE_DATA; - state_init <= MAIN3; - else - state_init <= MAIN1; - end if; - when MAIN3 => --- led <= local_ram_start_addr (7 downto 0); - + if (chk_recv_cntr = 1000) then + chk_recv_cntr <= 0; + state_read_data <= RD_1; + state_init <= READ_DATA; + busy <= '1'; + else + chk_recv_cntr <= chk_recv_cntr + 1; + state_init <= MAIN2; + end if; + when MAIN2 => + busy <= '0'; + --if (data_valid = '1') then + if (data_valid_sr = "01" or data_valid_sr = "11") then + --data_valid_int <= '0'; + busy <= '1'; + local_write_length <= write_length; + local_ram_start_addr <= ram_start_addr; + local_ram_addr <= (others => '0'); + local_write_header_flag <= write_header_flag; + local_write_end_flag <= write_end_flag; + local_fifo_channels <= fifo_channels; + -- data_valid_ack <= '1'; + -- next_state <= MAIN; + -- state_init <= WRITE_DATA; + state_init <= MAIN3; + else + state_init <= MAIN1; + end if; + when MAIN3 => -- needed for the check: if there is enough space in W5300 FIFO write_length_bytes <= local_write_length (15 downto 0) & '0'; -- shift left (*2) - - data_valid_ack <= '1'; - next_state <= MAIN; - state_init <= WRITE_DATA; - - ----------------------------------------- - -- END OF MAIN ------------------ - ----------------------------------------- - - + data_valid_ack <= '1'; + next_state <= MAIN; + state_init <= WRITE_DATA; + +---------------------------------------------------------------------------------- +-- END OF MAIN ----------------------------------------------------------- +---------------------------------------------------------------------------------- -- read data from socket 0 - when READ_DATA => - case state_read_data is - when RD_1 => - par_addr <= W5300_S0_RX_RSR; - state_init <= READ_REG; - next_state <= READ_DATA; - state_read_data <= RD_2; - when RD_2 => - socket_rx_received (31 downto 16) <= data_read; - par_addr <= W5300_S0_RX_RSR + X"2"; - state_init <= READ_REG; - next_state <= READ_DATA; - state_read_data <= RD_3; - when RD_3 => - socket_rx_received (15 downto 0) <= data_read; - state_read_data <= RD_4; - when RD_4 => - if (socket_rx_received (16 downto 0) > ('0' & X"000")) then - rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2 - state_read_data <= RD_5; - else - busy <= '0'; - state_init <= MAIN; - end if; - when RD_5 => - if (rx_packets_cnt > 0) then - rx_packets_cnt <= rx_packets_cnt - '1'; - par_addr <= W5300_S0_RX_FIFOR; - state_init <= READ_REG; - next_state <= READ_DATA; - state_read_data <= RD_6; - else - state_read_data <= RD_END; - end if; - when RD_6 => --- led <= data_read (15 downto 8); - -- read command - if (next_packet_data = '0') then - case data_read (15 downto 8) is - - when CMD_START => - data_generator_run_mode <= '1'; - state_read_data <= RD_5; - when CMD_STOP => - data_generator_run_mode <= '0'; - state_read_data <= RD_5; - - when CMD_MODE_ALL_SOCKETS => -- all data will be send via socket 1..7 - socket_send_mode <= '1'; - state_read_data <= RD_5; - - when CMC_MODE_COMMAND => -- all data will be send via socket 0 - socket_send_mode <= '0'; - state_read_data <= RD_5; - - when CMD_TRIGGER => - trigger_stop <= '1'; - s_trigger <= '1'; - state_read_data <= RD_5; - when CMD_DWRITE_RUN => - dwrite_enable <= '1'; - state_read_data <= RD_5; - when CMD_DWRITE_STOP => - dwrite_enable <= '0'; - state_read_data <= RD_5; - when CMD_SCLK_ON => - sclk_enable <= '1'; - state_read_data <= RD_5; - when CMD_SCLK_OFF => - sclk_enable <= '0'; - state_read_data <= RD_5; - when CMD_DENABLE => - denable <= '1'; - state_read_data <= RD_5; - when CMD_DDISABLE => - denable <= '0'; - state_read_data <= RD_5; - when CMD_TRIGGER_C => - c_trigger_enable <= '1'; - --trigger_stop <= '0'; - --s_trigger <= '1'; - state_read_data <= RD_5; - when CMD_TRIGGER_S => - c_trigger_enable <= '0'; - --trigger_stop <= '1'; - state_read_data <= RD_5; - when CMD_SET_TRIGGER_MULT => - set_new_CONT_TRIGGER_MULT_FACTOR <= '1'; - next_packet_data <= '1'; - state_read_data <= RD_5; - - -- phase shift commands here: - when CMD_PS_DO => - ps_do_phase_shift <= '1'; - state_read_data <= RD_5; - when CMD_PS_DIRINC => - ps_direction <= '1'; - state_read_data <= RD_5; - when CMD_PS_RESET => - ps_reset <= '1'; - state_read_data <= RD_5; - - when CMD_SRCLK_ON => - srclk_enable <= '1'; - state_read_data <= RD_5; - when CMD_SRCLK_OFF => - srclk_enable <= '0'; - state_read_data <= RD_5; - - when CMD_TRIGGERS_ON => - trigger_enable <= '1'; - state_read_data <= RD_5; - when CMD_TRIGGERS_OFF => - trigger_enable <= '0'; - state_read_data <= RD_5; - - - when CMD_PS_DIRDEC => - ps_direction <= '0'; - state_read_data <= RD_5; - when CMD_WRITE => - config_addr <= data_read (7 downto 0); - next_packet_data <= '1'; - state_read_data <= RD_5; - when others => - state_read_data <= RD_5; - end case; + when READ_DATA => + case state_read_data is + when RD_1 => + par_addr <= W5300_S0_RX_RSR; + state_init <= READ_REG; + next_state <= READ_DATA; + state_read_data <= RD_2; + when RD_2 => + socket_rx_received (31 downto 16) <= data_read; + par_addr <= W5300_S0_RX_RSR + X"2"; + state_init <= READ_REG; + next_state <= READ_DATA; + state_read_data <= RD_3; + when RD_3 => + socket_rx_received (15 downto 0) <= data_read; + state_read_data <= RD_4; + when RD_4 => + if (socket_rx_received (16 downto 0) > ('0' & X"000")) then + rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2 + state_read_data <= RD_5; + else + busy <= '0'; + state_init <= MAIN; + end if; + when RD_5 => + if (rx_packets_cnt > 0) then + rx_packets_cnt <= rx_packets_cnt - '1'; + par_addr <= W5300_S0_RX_FIFOR; + state_init <= READ_REG; + next_state <= READ_DATA; + state_read_data <= RD_6; + else + state_read_data <= RD_END; + end if; + + when RD_6 => + -- The next 16bit word is assumed to contain a 'command' so it is + -- beeing parsed in this state + case data_read (15 downto 8) is + when CMD_START => + data_generator_run_mode <= '1'; + state_read_data <= RD_5; + when CMD_STOP => + data_generator_run_mode <= '0'; + state_read_data <= RD_5; + when CMD_MODE_ALL_SOCKETS => -- all data will be send via socket 1..7 + socket_send_mode <= '1'; + state_read_data <= RD_5; + when CMC_MODE_COMMAND => -- all data will be send via socket 0 + socket_send_mode <= '0'; + state_read_data <= RD_5; + when CMD_TRIGGER => + trigger_stop <= '1'; + s_trigger <= '1'; + state_read_data <= RD_5; + when CMD_DWRITE_RUN => + dwrite_enable <= '1'; + state_read_data <= RD_5; + when CMD_DWRITE_STOP => + dwrite_enable <= '0'; + state_read_data <= RD_5; + when CMD_SCLK_ON => + sclk_enable <= '1'; + state_read_data <= RD_5; + when CMD_SCLK_OFF => + sclk_enable <= '0'; + state_read_data <= RD_5; + when CMD_DENABLE => + denable <= '1'; + state_read_data <= RD_5; + when CMD_DDISABLE => + denable <= '0'; + state_read_data <= RD_5; + when CMD_TRIGGER_C => + c_trigger_enable <= '1'; + state_read_data <= RD_5; + when CMD_TRIGGER_S => + c_trigger_enable <= '0'; + state_read_data <= RD_5; + when CMD_SET_TRIGGER_MULT => + state_read_data <= NEW_CONT_TRIGGER_MULT_FACTOR_READ; + -- phase shift commands here: + when CMD_PS_DO => + ps_do_phase_shift <= '1'; + state_read_data <= RD_5; + when CMD_PS_DIRINC => + ps_direction <= '1'; + state_read_data <= RD_5; + when CMD_PS_RESET => + ps_reset <= '1'; + state_read_data <= RD_5; + when CMD_SRCLK_ON => + srclk_enable <= '1'; + state_read_data <= RD_5; + when CMD_SRCLK_OFF => + srclk_enable <= '0'; + state_read_data <= RD_5; + when CMD_TRIGGERS_ON => + trigger_enable <= '1'; + state_read_data <= RD_5; + when CMD_TRIGGERS_OFF => + trigger_enable <= '0'; + state_read_data <= RD_5; + when CMD_PS_DIRDEC => + ps_direction <= '0'; + state_read_data <= RD_5; + when CMD_WRITE => + config_addr <= data_read (7 downto 0); + state_read_data <= READ_COMMAND_DATA_SECTION; + when others => + state_read_data <= RD_5; + end case; -- read data - else - if ( set_new_CONT_TRIGGER_MULT_FACTOR = '1' ) then - set_new_CONT_TRIGGER_MULT_FACTOR <= '0'; - c_trigger_mult <= data_read; - state_read_data <= RD_5; - else - if (config_busy = '0') then - config_data <= data_read; - config_wr_en <= '1'; - new_config_flag <= '1'; - next_packet_data <= '0'; - state_read_data <= RD_WAIT; - end if; - end if; - end if; + + -- these states are beeing precessed, if the 'command' was a 'write command' + -- so it is assumed, that some data in config RAM changed, and we need full (re)config + when READ_COMMAND_DATA_SECTION => + if (rx_packets_cnt > 0) then + rx_packets_cnt <= rx_packets_cnt - '1'; + par_addr <= W5300_S0_RX_FIFOR; + state_init <= READ_REG; + next_state <= READ_DATA; + state_read_data <= PUT_COMMAND_DATA_SECTION; + else + state_read_data <= RD_END; + end if; + + when PUT_COMMAND_DATA_SECTION => + if (config_busy = '0') then + config_data <= data_read; + config_wr_en <= '1'; + new_config_flag <= '1'; + state_read_data <= RD_WAIT; + end if; + + -- these states are beeing precessed, if the 'command' was a 'set new continouus trigger prescaler multiplication factor'-command + -- so the next 16bit word is just put out at the apropriate output. + when NEW_CONT_TRIGGER_MULT_FACTOR_READ => + if (rx_packets_cnt > 0) then + rx_packets_cnt <= rx_packets_cnt - '1'; + par_addr <= W5300_S0_RX_FIFOR; + state_init <= READ_REG; + next_state <= READ_DATA; + state_read_data <= NEW_CONT_TRIGGER_MULT_FACTOR_PUT; + else + state_read_data <= RD_END; + end if; + when NEW_CONT_TRIGGER_MULT_FACTOR_PUT => + c_trigger_mult <= data_read; + state_read_data <= RD_5; + + when RD_WAIT => if (config_rw_ack = '1') then