Changeset 10180
- Timestamp:
- 02/25/11 15:56:47 (11 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS
- Files:
-
- 78 added
- 26 edited
Legend:
- Unmodified
- Added
- Removed
-
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD.hdp
r10155 r10180 1 1 [DesignChecker] 2 2 FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/designcheck 3 FACT_FAD_TB_lib = $HDS_PROJECT_DIR\FACT_FAD_TB_lib\designcheck 3 4 [ModelSim] 4 5 FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/work -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/fad_main_tb_struct.vhd
r9912 r10180 2 2 -- 3 3 -- Created: 4 -- by - dneise.UNKNOWN ( TU-CC4900F8C7D2)5 -- at - 1 5:53:42 30.06.20104 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 16:10:14 25.02.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 20 20 -- 21 21 -- Created: 22 -- by - dneise.UNKNOWN ( TU-CC4900F8C7D2)23 -- at - 1 5:53:42 30.06.201022 -- by - dneise.UNKNOWN (E5B-LABOR6) 23 -- at - 16:10:15 25.02.2011 24 24 -- 25 25 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 44 44 45 45 -- Internal signal declarations 46 SIGNAL CLK_25_PS : std_logic; 47 SIGNAL CLK_50 : std_logic; 48 SIGNAL RSRLOAD : std_logic := '0'; 49 SIGNAL SRCLK : std_logic := '0'; 50 SIGNAL SROUT_in_0 : std_logic; 51 SIGNAL SROUT_in_1 : std_logic; 52 SIGNAL SROUT_in_2 : std_logic; 53 SIGNAL SROUT_in_3 : std_logic; 54 SIGNAL adc_data : std_logic_vector(11 DOWNTO 0); 55 SIGNAL adc_data_array : adc_data_array_type; 56 SIGNAL adc_oeb : std_logic; 57 SIGNAL adc_otr : STD_LOGIC; 58 SIGNAL adc_otr_array : std_logic_vector(3 DOWNTO 0); 59 SIGNAL board_id : std_logic_vector(3 DOWNTO 0); 60 SIGNAL clk : STD_LOGIC; 61 SIGNAL crate_id : std_logic_vector(1 DOWNTO 0); 62 SIGNAL dac_cs : std_logic; 63 SIGNAL denable : std_logic := '0'; -- default domino wave off 64 SIGNAL drs_channel_id : std_logic_vector(3 DOWNTO 0) := (others => '0'); 65 SIGNAL drs_dwrite : std_logic := '1'; 66 SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); 67 SIGNAL mosi : std_logic := '0'; 68 SIGNAL sclk : std_logic; 69 SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0); 70 SIGNAL sio : std_logic; 71 SIGNAL trigger : std_logic; 72 SIGNAL wiz_addr : std_logic_vector(9 DOWNTO 0); 73 SIGNAL wiz_cs : std_logic := '1'; 74 SIGNAL wiz_data : std_logic_vector(15 DOWNTO 0); 75 SIGNAL wiz_int : std_logic; 76 SIGNAL wiz_rd : std_logic := '1'; 77 SIGNAL wiz_reset : std_logic := '1'; 78 SIGNAL wiz_wr : std_logic := '1'; 46 SIGNAL ADC_CLK : std_logic; 47 SIGNAL CLK_25_PS : std_logic; 48 SIGNAL CLK_50 : std_logic; 49 SIGNAL D_T_in : std_logic_vector(1 DOWNTO 0); 50 SIGNAL REF_CLK : STD_LOGIC := '0'; 51 SIGNAL RSRLOAD : std_logic := '0'; 52 SIGNAL SRCLK : std_logic := '0'; 53 SIGNAL SRIN_out : std_logic := '0'; 54 SIGNAL SROUT_in_0 : std_logic; 55 SIGNAL SROUT_in_1 : std_logic; 56 SIGNAL SROUT_in_2 : std_logic; 57 SIGNAL SROUT_in_3 : std_logic; 58 SIGNAL adc_data : std_logic_vector(11 DOWNTO 0); 59 SIGNAL adc_data_array : adc_data_array_type; 60 SIGNAL adc_oeb : std_logic; 61 SIGNAL adc_otr : STD_LOGIC; 62 SIGNAL adc_otr_array : std_logic_vector(3 DOWNTO 0); 63 SIGNAL alarm_refclk_too_high : std_logic; 64 SIGNAL alarm_refclk_too_low : std_logic; 65 SIGNAL amber : std_logic; 66 SIGNAL board_id : std_logic_vector(3 DOWNTO 0); 67 SIGNAL clk : STD_LOGIC; 68 SIGNAL counter_result : std_logic_vector(11 DOWNTO 0); 69 SIGNAL crate_id : std_logic_vector(1 DOWNTO 0); 70 SIGNAL dac_cs : std_logic; 71 SIGNAL denable : std_logic := '0'; -- default domino wave off 72 SIGNAL drs_channel_id : std_logic_vector(3 DOWNTO 0) := (others => '0'); 73 SIGNAL drs_dwrite : std_logic := '1'; 74 SIGNAL green : std_logic; 75 SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); 76 SIGNAL mosi : std_logic := '0'; 77 SIGNAL plllock_in : std_logic_vector(3 DOWNTO 0); -- high level, if dominowave is running and DRS PLL locked 78 SIGNAL red : std_logic; 79 SIGNAL sclk : std_logic; 80 SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0); 81 SIGNAL sio : std_logic; 82 SIGNAL trigger : std_logic; 83 SIGNAL wiz_addr : std_logic_vector(9 DOWNTO 0); 84 SIGNAL wiz_cs : std_logic := '1'; 85 SIGNAL wiz_data : std_logic_vector(15 DOWNTO 0); 86 SIGNAL wiz_int : std_logic; 87 SIGNAL wiz_rd : std_logic := '1'; 88 SIGNAL wiz_reset : std_logic := '1'; 89 SIGNAL wiz_wr : std_logic := '1'; 79 90 80 91 … … 85 96 ); 86 97 PORT ( 87 CLK : IN std_logic ; 88 SROUT_in_0 : IN std_logic ; 89 SROUT_in_1 : IN std_logic ; 90 SROUT_in_2 : IN std_logic ; 91 SROUT_in_3 : IN std_logic ; 92 adc_data_array : IN adc_data_array_type ; 93 adc_otr_array : IN std_logic_vector (3 DOWNTO 0); 94 board_id : IN std_logic_vector (3 DOWNTO 0); 95 crate_id : IN std_logic_vector (1 DOWNTO 0); 96 trigger : IN std_logic ; 97 wiz_int : IN std_logic ; 98 CLK_25_PS : OUT std_logic ; 99 CLK_50 : OUT std_logic ; 100 RSRLOAD : OUT std_logic := '0'; 101 SRCLK : OUT std_logic := '0'; 102 adc_oeb : OUT std_logic := '1'; 103 dac_cs : OUT std_logic ; 104 denable : OUT std_logic := '0'; -- default domino wave off 105 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); 106 drs_dwrite : OUT std_logic := '1'; 107 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 108 mosi : OUT std_logic := '0'; 109 sclk : OUT std_logic ; 110 sensor_cs : OUT std_logic_vector (3 DOWNTO 0); 111 wiz_addr : OUT std_logic_vector (9 DOWNTO 0); 112 wiz_cs : OUT std_logic := '1'; 113 wiz_rd : OUT std_logic := '1'; 114 wiz_reset : OUT std_logic := '1'; 115 wiz_wr : OUT std_logic := '1'; 116 sio : INOUT std_logic ; 117 wiz_data : INOUT std_logic_vector (15 DOWNTO 0) 98 CLK : IN std_logic ; 99 D_T_in : IN std_logic_vector (1 DOWNTO 0); 100 SROUT_in_0 : IN std_logic ; 101 SROUT_in_1 : IN std_logic ; 102 SROUT_in_2 : IN std_logic ; 103 SROUT_in_3 : IN std_logic ; 104 adc_data_array : IN adc_data_array_type ; 105 adc_otr_array : IN std_logic_vector (3 DOWNTO 0); 106 board_id : IN std_logic_vector (3 DOWNTO 0); 107 crate_id : IN std_logic_vector (1 DOWNTO 0); 108 drs_refclk_in : IN std_logic ; -- used TO check if DRS REFCLK exsists, if not DENABLE inhibit 109 plllock_in : IN std_logic_vector (3 DOWNTO 0); -- high level, if dominowave is running and DRS PLL locked 110 trigger : IN std_logic ; 111 wiz_int : IN std_logic ; 112 ADC_CLK : OUT std_logic ; 113 CLK_25_PS : OUT std_logic ; 114 CLK_50 : OUT std_logic ; 115 RSRLOAD : OUT std_logic := '0'; 116 SRCLK : OUT std_logic := '0'; 117 SRIN_out : OUT std_logic := '0'; 118 adc_oeb : OUT std_logic := '1'; 119 alarm_refclk_too_high : OUT std_logic ; 120 alarm_refclk_too_low : OUT std_logic ; 121 amber : OUT std_logic ; 122 counter_result : OUT std_logic_vector (11 DOWNTO 0); 123 dac_cs : OUT std_logic ; 124 denable : OUT std_logic := '0'; -- default domino wave off 125 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); 126 drs_dwrite : OUT std_logic := '1'; 127 green : OUT std_logic ; 128 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 129 mosi : OUT std_logic := '0'; 130 red : OUT std_logic ; 131 sclk : OUT std_logic ; 132 sensor_cs : OUT std_logic_vector (3 DOWNTO 0); 133 wiz_addr : OUT std_logic_vector (9 DOWNTO 0); 134 wiz_cs : OUT std_logic := '1'; 135 wiz_rd : OUT std_logic := '1'; 136 wiz_reset : OUT std_logic := '1'; 137 wiz_wr : OUT std_logic := '1'; 138 sio : INOUT std_logic ; 139 wiz_data : INOUT std_logic_vector (15 DOWNTO 0) 118 140 ); 119 141 END COMPONENT; … … 160 182 COMPONENT w5300_emulator 161 183 PORT ( 184 int : OUT std_logic := '0'; 162 185 addr : IN std_logic_vector (9 DOWNTO 0); 163 186 data : INOUT std_logic_vector (15 DOWNTO 0); … … 196 219 adc_otr_array(3) <= adc_otr; 197 220 221 -- HDL Embedded Text Block 3 eb_mainTB_adc1 222 223 D_T_in(1 downto 0) <= "00"; 224 plllock_in(3 downto 0) <= "1111"; 225 SROUT_in_0 <= '1'; 226 SROUT_in_1 <= '0'; 227 SROUT_in_2 <= '1'; 228 SROUT_in_3 <= '0'; 229 198 230 199 231 -- Instance port mappings. … … 203 235 ) 204 236 PORT MAP ( 205 CLK => clk, 206 SROUT_in_0 => SROUT_in_0, 207 SROUT_in_1 => SROUT_in_1, 208 SROUT_in_2 => SROUT_in_2, 209 SROUT_in_3 => SROUT_in_3, 210 adc_data_array => adc_data_array, 211 adc_otr_array => adc_otr_array, 212 board_id => board_id, 213 crate_id => crate_id, 214 trigger => trigger, 215 wiz_int => wiz_int, 216 CLK_25_PS => CLK_25_PS, 217 CLK_50 => CLK_50, 218 RSRLOAD => RSRLOAD, 219 SRCLK => SRCLK, 220 adc_oeb => adc_oeb, 221 dac_cs => dac_cs, 222 denable => denable, 223 drs_channel_id => drs_channel_id, 224 drs_dwrite => drs_dwrite, 225 led => led, 226 mosi => mosi, 227 sclk => sclk, 228 sensor_cs => sensor_cs, 229 wiz_addr => wiz_addr, 230 wiz_cs => wiz_cs, 231 wiz_rd => wiz_rd, 232 wiz_reset => wiz_reset, 233 wiz_wr => wiz_wr, 234 sio => sio, 235 wiz_data => wiz_data 237 CLK => clk, 238 D_T_in => D_T_in, 239 SROUT_in_0 => SROUT_in_0, 240 SROUT_in_1 => SROUT_in_1, 241 SROUT_in_2 => SROUT_in_2, 242 SROUT_in_3 => SROUT_in_3, 243 adc_data_array => adc_data_array, 244 adc_otr_array => adc_otr_array, 245 board_id => board_id, 246 crate_id => crate_id, 247 drs_refclk_in => REF_CLK, 248 plllock_in => plllock_in, 249 trigger => trigger, 250 wiz_int => wiz_int, 251 ADC_CLK => ADC_CLK, 252 CLK_25_PS => CLK_25_PS, 253 CLK_50 => CLK_50, 254 RSRLOAD => RSRLOAD, 255 SRCLK => SRCLK, 256 SRIN_out => SRIN_out, 257 adc_oeb => adc_oeb, 258 alarm_refclk_too_high => alarm_refclk_too_high, 259 alarm_refclk_too_low => alarm_refclk_too_low, 260 amber => amber, 261 counter_result => counter_result, 262 dac_cs => dac_cs, 263 denable => denable, 264 drs_channel_id => drs_channel_id, 265 drs_dwrite => drs_dwrite, 266 green => green, 267 led => led, 268 mosi => mosi, 269 red => red, 270 sclk => sclk, 271 sensor_cs => sensor_cs, 272 wiz_addr => wiz_addr, 273 wiz_cs => wiz_cs, 274 wiz_rd => wiz_rd, 275 wiz_reset => wiz_reset, 276 wiz_wr => wiz_wr, 277 sio => sio, 278 wiz_data => wiz_data 236 279 ); 237 280 I_mainTB_adc : adc_emulator … … 240 283 ) 241 284 PORT MAP ( 242 clk => clk,285 clk => ADC_CLK, 243 286 data => adc_data, 244 287 otr => adc_otr, … … 254 297 rst => OPEN 255 298 ); 299 I_mainTB_clock1 : clock_generator 300 GENERIC MAP ( 301 clock_period => 1 us, 302 reset_time => 1 us 303 ) 304 PORT MAP ( 305 clk => REF_CLK, 306 rst => OPEN 307 ); 256 308 I_mainTB_max6662 : max6662_emulator 257 309 GENERIC MAP ( … … 273 325 I_mainTB_w5300 : w5300_emulator 274 326 PORT MAP ( 327 int => wiz_int, 275 328 addr => wiz_addr, 276 329 data => wiz_data, -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/w5300_emulator_beha.vhd
r9912 r10180 17 17 ENTITY w5300_emulator IS 18 18 PORT( 19 int : out std_logic := '0'; 19 20 addr : in std_logic_vector (9 DOWNTO 0); 20 21 data : inout std_logic_vector (15 DOWNTO 0); … … 71 72 elsif (addr = conv_integer(W5300_S0_RX_FIFOR)) then 72 73 if (FIFOR_CNT = 0) then 73 data_temp <= X" B000";74 --FIFOR_CNT <= 1;74 data_temp <= X"1800"; 75 FIFOR_CNT <= 1; 75 76 elsif (FIFOR_CNT = 1) then 76 data_temp <= X" 0500";77 data_temp <= X"2200"; 77 78 FIFOR_CNT <= 2; 78 79 elsif (FIFOR_CNT = 2) then 79 data_temp <= X"0000"; 80 end if; 80 data_temp <= X"A000"; 81 FIFOR_CNT <= 3; 82 83 elsif (FIFOR_CNT = 3) then 84 data_temp <= X"B000"; 85 end if; 81 86 else 82 87 null; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/.xrf/fad_main_tb_struct.xrf
r9912 r10180 25 25 DESIGN fad_main_tb 26 26 VIEW struct.bd 27 GRAPHIC 823,0 45 0 28 DESIGN fad_main_tb 29 VIEW struct.bd 30 GRAPHIC 831,0 46 0 31 DESIGN fad_main_tb 32 VIEW struct.bd 33 GRAPHIC 855,0 47 0 34 DESIGN fad_main_tb 35 VIEW struct.bd 36 GRAPHIC 863,0 48 0 37 DESIGN fad_main_tb 38 VIEW struct.bd 39 GRAPHIC 871,0 49 0 40 DESIGN fad_main_tb 41 VIEW struct.bd 42 GRAPHIC 879,0 50 0 43 DESIGN fad_main_tb 44 VIEW struct.bd 45 GRAPHIC 887,0 51 0 46 DESIGN fad_main_tb 47 VIEW struct.bd 48 GRAPHIC 895,0 52 0 49 DESIGN fad_main_tb 50 VIEW struct.bd 51 GRAPHIC 568,0 53 0 52 DESIGN fad_main_tb 53 VIEW struct.bd 54 GRAPHIC 536,0 54 0 55 DESIGN fad_main_tb 56 VIEW struct.bd 57 GRAPHIC 544,0 55 0 58 DESIGN fad_main_tb 59 VIEW struct.bd 60 GRAPHIC 560,0 56 0 61 DESIGN fad_main_tb 62 VIEW struct.bd 63 GRAPHIC 528,0 57 0 64 DESIGN fad_main_tb 65 VIEW struct.bd 66 GRAPHIC 440,0 58 0 67 DESIGN fad_main_tb 68 VIEW struct.bd 69 GRAPHIC 284,0 59 0 70 DESIGN fad_main_tb 71 VIEW struct.bd 72 GRAPHIC 448,0 60 0 73 DESIGN fad_main_tb 74 VIEW struct.bd 75 GRAPHIC 799,0 61 0 76 DESIGN fad_main_tb 77 VIEW struct.bd 78 GRAPHIC 815,0 62 0 79 DESIGN fad_main_tb 80 VIEW struct.bd 81 GRAPHIC 839,0 63 0 82 DESIGN fad_main_tb 83 VIEW struct.bd 84 GRAPHIC 847,0 64 0 85 DESIGN fad_main_tb 86 VIEW struct.bd 87 GRAPHIC 775,0 65 0 88 DESIGN fad_main_tb 89 VIEW struct.bd 90 GRAPHIC 807,0 66 0 91 DESIGN fad_main_tb 92 VIEW struct.bd 93 GRAPHIC 378,0 67 0 94 DESIGN fad_main_tb 95 VIEW struct.bd 96 GRAPHIC 372,0 68 0 97 DESIGN fad_main_tb 98 VIEW struct.bd 99 GRAPHIC 384,0 69 0 100 DESIGN fad_main_tb 101 VIEW struct.bd 102 GRAPHIC 424,0 70 0 103 DESIGN fad_main_tb 104 VIEW struct.bd 105 GRAPHIC 316,0 71 0 106 DESIGN fad_main_tb 107 VIEW struct.bd 108 GRAPHIC 783,0 72 0 109 DESIGN fad_main_tb 110 VIEW struct.bd 111 GRAPHIC 322,0 73 0 112 DESIGN fad_main_tb 113 VIEW struct.bd 114 GRAPHIC 791,0 74 0 115 DESIGN fad_main_tb 116 VIEW struct.bd 117 GRAPHIC 328,0 75 0 118 DESIGN fad_main_tb 119 VIEW struct.bd 120 GRAPHIC 767,0 76 0 121 DESIGN fad_main_tb 122 VIEW struct.bd 123 GRAPHIC 334,0 77 0 124 DESIGN fad_main_tb 125 VIEW struct.bd 126 NO_GRAPHIC 78 127 DESIGN fad_main_tb 128 VIEW struct.bd 129 NO_GRAPHIC 79 27 GRAPHIC 1682,0 45 0 28 DESIGN fad_main_tb 29 VIEW struct.bd 30 GRAPHIC 823,0 46 0 31 DESIGN fad_main_tb 32 VIEW struct.bd 33 GRAPHIC 831,0 47 0 34 DESIGN fad_main_tb 35 VIEW struct.bd 36 GRAPHIC 1501,0 48 0 37 DESIGN fad_main_tb 38 VIEW struct.bd 39 GRAPHIC 2001,0 49 0 40 DESIGN fad_main_tb 41 VIEW struct.bd 42 GRAPHIC 855,0 50 0 43 DESIGN fad_main_tb 44 VIEW struct.bd 45 GRAPHIC 863,0 51 0 46 DESIGN fad_main_tb 47 VIEW struct.bd 48 GRAPHIC 1435,0 52 0 49 DESIGN fad_main_tb 50 VIEW struct.bd 51 GRAPHIC 871,0 53 0 52 DESIGN fad_main_tb 53 VIEW struct.bd 54 GRAPHIC 879,0 54 0 55 DESIGN fad_main_tb 56 VIEW struct.bd 57 GRAPHIC 887,0 55 0 58 DESIGN fad_main_tb 59 VIEW struct.bd 60 GRAPHIC 895,0 56 0 61 DESIGN fad_main_tb 62 VIEW struct.bd 63 GRAPHIC 568,0 57 0 64 DESIGN fad_main_tb 65 VIEW struct.bd 66 GRAPHIC 536,0 58 0 67 DESIGN fad_main_tb 68 VIEW struct.bd 69 GRAPHIC 544,0 59 0 70 DESIGN fad_main_tb 71 VIEW struct.bd 72 GRAPHIC 560,0 60 0 73 DESIGN fad_main_tb 74 VIEW struct.bd 75 GRAPHIC 528,0 61 0 76 DESIGN fad_main_tb 77 VIEW struct.bd 78 GRAPHIC 1483,0 62 0 79 DESIGN fad_main_tb 80 VIEW struct.bd 81 GRAPHIC 1475,0 63 0 82 DESIGN fad_main_tb 83 VIEW struct.bd 84 GRAPHIC 1443,0 64 0 85 DESIGN fad_main_tb 86 VIEW struct.bd 87 GRAPHIC 440,0 65 0 88 DESIGN fad_main_tb 89 VIEW struct.bd 90 GRAPHIC 284,0 66 0 91 DESIGN fad_main_tb 92 VIEW struct.bd 93 GRAPHIC 1467,0 67 0 94 DESIGN fad_main_tb 95 VIEW struct.bd 96 GRAPHIC 448,0 68 0 97 DESIGN fad_main_tb 98 VIEW struct.bd 99 GRAPHIC 799,0 69 0 100 DESIGN fad_main_tb 101 VIEW struct.bd 102 GRAPHIC 815,0 70 0 103 DESIGN fad_main_tb 104 VIEW struct.bd 105 GRAPHIC 839,0 71 0 106 DESIGN fad_main_tb 107 VIEW struct.bd 108 GRAPHIC 847,0 72 0 109 DESIGN fad_main_tb 110 VIEW struct.bd 111 GRAPHIC 1459,0 73 0 112 DESIGN fad_main_tb 113 VIEW struct.bd 114 GRAPHIC 775,0 74 0 115 DESIGN fad_main_tb 116 VIEW struct.bd 117 GRAPHIC 807,0 75 0 118 DESIGN fad_main_tb 119 VIEW struct.bd 120 GRAPHIC 1559,0 76 0 121 DESIGN fad_main_tb 122 VIEW struct.bd 123 GRAPHIC 1451,0 77 0 124 DESIGN fad_main_tb 125 VIEW struct.bd 126 GRAPHIC 378,0 78 0 127 DESIGN fad_main_tb 128 VIEW struct.bd 129 GRAPHIC 372,0 79 0 130 DESIGN fad_main_tb 131 VIEW struct.bd 132 GRAPHIC 384,0 80 0 133 DESIGN fad_main_tb 134 VIEW struct.bd 135 GRAPHIC 424,0 81 0 136 DESIGN fad_main_tb 137 VIEW struct.bd 138 GRAPHIC 316,0 82 0 139 DESIGN fad_main_tb 140 VIEW struct.bd 141 GRAPHIC 783,0 83 0 142 DESIGN fad_main_tb 143 VIEW struct.bd 144 GRAPHIC 322,0 84 0 145 DESIGN fad_main_tb 146 VIEW struct.bd 147 GRAPHIC 791,0 85 0 148 DESIGN fad_main_tb 149 VIEW struct.bd 150 GRAPHIC 328,0 86 0 151 DESIGN fad_main_tb 152 VIEW struct.bd 153 GRAPHIC 767,0 87 0 154 DESIGN fad_main_tb 155 VIEW struct.bd 156 GRAPHIC 334,0 88 0 157 DESIGN fad_main_tb 158 VIEW struct.bd 159 NO_GRAPHIC 89 160 DESIGN fad_main_tb 161 VIEW struct.bd 162 NO_GRAPHIC 90 130 163 LIBRARY FACT_FAD_lib 131 164 DESIGN @f@a@d_main 132 165 VIEW struct 133 GRAPHIC 233,0 81 0 134 DESIGN @f@a@d_main 135 VIEW symbol.sb 136 GRAPHIC 14,0 82 1 137 DESIGN @f@a@d_main 138 VIEW symbol.sb 139 GRAPHIC 1755,0 86 0 140 DESIGN @f@a@d_main 141 VIEW symbol.sb 142 GRAPHIC 2710,0 87 0 143 DESIGN @f@a@d_main 144 VIEW symbol.sb 145 GRAPHIC 2715,0 88 0 146 DESIGN @f@a@d_main 147 VIEW symbol.sb 148 GRAPHIC 2720,0 89 0 149 DESIGN @f@a@d_main 150 VIEW symbol.sb 151 GRAPHIC 2725,0 90 0 152 DESIGN @f@a@d_main 153 VIEW symbol.sb 154 GRAPHIC 2282,0 91 0 155 DESIGN @f@a@d_main 156 VIEW symbol.sb 157 GRAPHIC 1976,0 92 0 158 DESIGN @f@a@d_main 159 VIEW symbol.sb 160 GRAPHIC 923,0 93 0 161 DESIGN @f@a@d_main 162 VIEW symbol.sb 163 GRAPHIC 928,0 94 0 164 DESIGN @f@a@d_main 165 VIEW symbol.sb 166 GRAPHIC 464,0 95 0 167 DESIGN @f@a@d_main 168 VIEW symbol.sb 169 GRAPHIC 1062,0 96 0 170 DESIGN @f@a@d_main 171 VIEW symbol.sb 172 GRAPHIC 1389,0 97 0 173 DESIGN @f@a@d_main 174 VIEW symbol.sb 175 GRAPHIC 1725,0 98 0 176 DESIGN @f@a@d_main 177 VIEW symbol.sb 178 GRAPHIC 2987,0 99 0 179 DESIGN @f@a@d_main 180 VIEW symbol.sb 181 GRAPHIC 2992,0 100 0 182 DESIGN @f@a@d_main 183 VIEW symbol.sb 184 GRAPHIC 833,0 101 0 185 DESIGN @f@a@d_main 186 VIEW symbol.sb 187 GRAPHIC 3641,0 102 0 188 DESIGN @f@a@d_main 189 VIEW symbol.sb 190 GRAPHIC 4144,0 103 0 191 DESIGN @f@a@d_main 192 VIEW symbol.sb 193 GRAPHIC 2448,0 104 0 194 DESIGN @f@a@d_main 195 VIEW symbol.sb 196 GRAPHIC 2453,0 105 0 197 DESIGN @f@a@d_main 198 VIEW symbol.sb 199 GRAPHIC 163,0 106 0 200 DESIGN @f@a@d_main 201 VIEW symbol.sb 202 GRAPHIC 4067,0 107 0 203 DESIGN @f@a@d_main 204 VIEW symbol.sb 205 GRAPHIC 3631,0 108 0 206 DESIGN @f@a@d_main 207 VIEW symbol.sb 208 GRAPHIC 3646,0 109 0 209 DESIGN @f@a@d_main 210 VIEW symbol.sb 211 GRAPHIC 1037,0 110 0 212 DESIGN @f@a@d_main 213 VIEW symbol.sb 214 GRAPHIC 1047,0 111 0 215 DESIGN @f@a@d_main 216 VIEW symbol.sb 217 GRAPHIC 1057,0 112 0 218 DESIGN @f@a@d_main 219 VIEW symbol.sb 220 GRAPHIC 135,0 113 0 221 DESIGN @f@a@d_main 222 VIEW symbol.sb 223 GRAPHIC 1052,0 114 0 224 DESIGN @f@a@d_main 225 VIEW symbol.sb 226 GRAPHIC 3636,0 115 0 227 DESIGN @f@a@d_main 228 VIEW symbol.sb 229 GRAPHIC 1042,0 116 0 166 GRAPHIC 233,0 92 0 167 DESIGN @f@a@d_main 168 VIEW symbol.sb 169 GRAPHIC 14,0 93 1 170 DESIGN @f@a@d_main 171 VIEW symbol.sb 172 GRAPHIC 1755,0 97 0 173 DESIGN @f@a@d_main 174 VIEW symbol.sb 175 GRAPHIC 5328,0 98 0 176 DESIGN @f@a@d_main 177 VIEW symbol.sb 178 GRAPHIC 2710,0 99 0 179 DESIGN @f@a@d_main 180 VIEW symbol.sb 181 GRAPHIC 2715,0 100 0 182 DESIGN @f@a@d_main 183 VIEW symbol.sb 184 GRAPHIC 2720,0 101 0 185 DESIGN @f@a@d_main 186 VIEW symbol.sb 187 GRAPHIC 2725,0 102 0 188 DESIGN @f@a@d_main 189 VIEW symbol.sb 190 GRAPHIC 2282,0 103 0 191 DESIGN @f@a@d_main 192 VIEW symbol.sb 193 GRAPHIC 1976,0 104 0 194 DESIGN @f@a@d_main 195 VIEW symbol.sb 196 GRAPHIC 923,0 105 0 197 DESIGN @f@a@d_main 198 VIEW symbol.sb 199 GRAPHIC 928,0 106 0 200 DESIGN @f@a@d_main 201 VIEW symbol.sb 202 GRAPHIC 5427,0 107 0 203 DESIGN @f@a@d_main 204 VIEW symbol.sb 205 GRAPHIC 5503,0 108 0 206 DESIGN @f@a@d_main 207 VIEW symbol.sb 208 GRAPHIC 464,0 109 0 209 DESIGN @f@a@d_main 210 VIEW symbol.sb 211 GRAPHIC 1062,0 110 0 212 DESIGN @f@a@d_main 213 VIEW symbol.sb 214 GRAPHIC 6704,0 111 0 215 DESIGN @f@a@d_main 216 VIEW symbol.sb 217 GRAPHIC 1389,0 112 0 218 DESIGN @f@a@d_main 219 VIEW symbol.sb 220 GRAPHIC 1725,0 113 0 221 DESIGN @f@a@d_main 222 VIEW symbol.sb 223 GRAPHIC 2987,0 114 0 224 DESIGN @f@a@d_main 225 VIEW symbol.sb 226 GRAPHIC 2992,0 115 0 227 DESIGN @f@a@d_main 228 VIEW symbol.sb 229 GRAPHIC 4780,0 116 0 230 DESIGN @f@a@d_main 231 VIEW symbol.sb 232 GRAPHIC 833,0 117 0 233 DESIGN @f@a@d_main 234 VIEW symbol.sb 235 GRAPHIC 5634,0 118 0 236 DESIGN @f@a@d_main 237 VIEW symbol.sb 238 GRAPHIC 5639,0 119 0 239 DESIGN @f@a@d_main 240 VIEW symbol.sb 241 GRAPHIC 4911,0 120 0 242 DESIGN @f@a@d_main 243 VIEW symbol.sb 244 GRAPHIC 5629,0 121 0 245 DESIGN @f@a@d_main 246 VIEW symbol.sb 247 GRAPHIC 3641,0 122 0 248 DESIGN @f@a@d_main 249 VIEW symbol.sb 250 GRAPHIC 4144,0 123 0 251 DESIGN @f@a@d_main 252 VIEW symbol.sb 253 GRAPHIC 2448,0 124 0 254 DESIGN @f@a@d_main 255 VIEW symbol.sb 256 GRAPHIC 2453,0 125 0 257 DESIGN @f@a@d_main 258 VIEW symbol.sb 259 GRAPHIC 4906,0 126 0 260 DESIGN @f@a@d_main 261 VIEW symbol.sb 262 GRAPHIC 163,0 127 0 263 DESIGN @f@a@d_main 264 VIEW symbol.sb 265 GRAPHIC 4067,0 128 0 266 DESIGN @f@a@d_main 267 VIEW symbol.sb 268 GRAPHIC 4916,0 129 0 269 DESIGN @f@a@d_main 270 VIEW symbol.sb 271 GRAPHIC 3631,0 130 0 272 DESIGN @f@a@d_main 273 VIEW symbol.sb 274 GRAPHIC 3646,0 131 0 275 DESIGN @f@a@d_main 276 VIEW symbol.sb 277 GRAPHIC 1037,0 132 0 278 DESIGN @f@a@d_main 279 VIEW symbol.sb 280 GRAPHIC 1047,0 133 0 281 DESIGN @f@a@d_main 282 VIEW symbol.sb 283 GRAPHIC 1057,0 134 0 284 DESIGN @f@a@d_main 285 VIEW symbol.sb 286 GRAPHIC 135,0 135 0 287 DESIGN @f@a@d_main 288 VIEW symbol.sb 289 GRAPHIC 1052,0 136 0 290 DESIGN @f@a@d_main 291 VIEW symbol.sb 292 GRAPHIC 3636,0 137 0 293 DESIGN @f@a@d_main 294 VIEW symbol.sb 295 GRAPHIC 1042,0 138 0 230 296 LIBRARY FACT_FAD_TB_lib 231 297 DESIGN adc_emulator 232 298 VIEW @behavioral 233 GRAPHIC 508,0 1 190299 GRAPHIC 508,0 141 0 234 300 DESIGN adc_emulator 235 301 VIEW symbol.sb 236 GRAPHIC 14,0 1 201302 GRAPHIC 14,0 142 1 237 303 DESIGN adc_emulator 238 304 VIEW @behavioral 239 GRAPHIC 48,0 1 240305 GRAPHIC 48,0 146 0 240 306 DESIGN adc_emulator 241 307 VIEW @behavioral 242 GRAPHIC 53,0 1 250308 GRAPHIC 53,0 147 0 243 309 DESIGN adc_emulator 244 310 VIEW @behavioral 245 GRAPHIC 58,0 1 260311 GRAPHIC 58,0 148 0 246 312 DESIGN adc_emulator 247 313 VIEW @behavioral 248 GRAPHIC 63,0 1 270249 DESIGN fad_main_tb 250 VIEW struct.bd 251 GRAPHIC 274,0 1 300314 GRAPHIC 63,0 149 0 315 DESIGN fad_main_tb 316 VIEW struct.bd 317 GRAPHIC 274,0 152 0 252 318 DESIGN clock_generator 253 319 VIEW symbol.sb 254 GRAPHIC 14,0 1 311320 GRAPHIC 14,0 153 1 255 321 DESIGN clock_generator 256 322 VIEW @behavioral 257 GRAPHIC 48,0 1 360323 GRAPHIC 48,0 158 0 258 324 DESIGN clock_generator 259 325 VIEW @behavioral 260 GRAPHIC 53,0 1 370261 DESIGN fad_main_tb 262 VIEW struct.bd 263 GRAPHIC 362,0 1 400326 GRAPHIC 53,0 159 0 327 DESIGN fad_main_tb 328 VIEW struct.bd 329 GRAPHIC 362,0 162 0 264 330 DESIGN max6662_emulator 265 331 VIEW symbol.sb 266 GRAPHIC 14,0 1 411332 GRAPHIC 14,0 163 1 267 333 DESIGN max6662_emulator 268 334 VIEW beha 269 GRAPHIC 48,0 1 450335 GRAPHIC 48,0 167 0 270 336 DESIGN max6662_emulator 271 337 VIEW beha 272 GRAPHIC 53,0 1 460338 GRAPHIC 53,0 168 0 273 339 DESIGN max6662_emulator 274 340 VIEW beha 275 GRAPHIC 58,0 1 470276 DESIGN fad_main_tb 277 VIEW struct.bd 278 GRAPHIC 414,0 1 500341 GRAPHIC 58,0 169 0 342 DESIGN fad_main_tb 343 VIEW struct.bd 344 GRAPHIC 414,0 172 0 279 345 DESIGN trigger_generator 280 346 VIEW symbol.sb 281 GRAPHIC 14,0 1 511347 GRAPHIC 14,0 173 1 282 348 DESIGN trigger_generator 283 349 VIEW beha 284 GRAPHIC 48,0 1 560285 DESIGN fad_main_tb 286 VIEW struct.bd 287 GRAPHIC 306,0 1 590350 GRAPHIC 48,0 178 0 351 DESIGN fad_main_tb 352 VIEW struct.bd 353 GRAPHIC 306,0 181 0 288 354 DESIGN w5300_emulator 289 355 VIEW beha 290 GRAPHIC 48,0 1610356 GRAPHIC 163,0 183 0 291 357 DESIGN w5300_emulator 292 358 VIEW beha 293 GRAPHIC 53,0 1620359 GRAPHIC 48,0 184 0 294 360 DESIGN w5300_emulator 295 361 VIEW beha 296 GRAPHIC 5 8,0 1630362 GRAPHIC 53,0 185 0 297 363 DESIGN w5300_emulator 298 364 VIEW beha 299 GRAPHIC 63,0 164 0 365 GRAPHIC 58,0 186 0 366 DESIGN w5300_emulator 367 VIEW beha 368 GRAPHIC 63,0 187 0 300 369 LIBRARY FACT_FAD_TB_lib 301 370 DESIGN fad_main_tb 302 371 VIEW struct.bd 303 NO_GRAPHIC 167 304 DESIGN fad_main_tb 305 VIEW struct.bd 306 GRAPHIC 233,0 170 0 307 DESIGN fad_main_tb 308 VIEW struct.bd 309 GRAPHIC 508,0 171 0 310 DESIGN fad_main_tb 311 VIEW struct.bd 312 GRAPHIC 274,0 172 0 313 DESIGN fad_main_tb 314 VIEW struct.bd 315 GRAPHIC 362,0 173 0 316 DESIGN fad_main_tb 317 VIEW struct.bd 318 GRAPHIC 414,0 174 0 319 DESIGN fad_main_tb 320 VIEW struct.bd 321 GRAPHIC 306,0 175 0 322 DESIGN fad_main_tb 323 VIEW struct.bd 324 NO_GRAPHIC 178 325 DESIGN fad_main_tb 326 VIEW struct.bd 327 GRAPHIC 430,0 181 0 328 DESIGN fad_main_tb 329 VIEW struct.bd 330 NO_GRAPHIC 185 331 DESIGN fad_main_tb 332 VIEW struct.bd 333 GRAPHIC 518,0 186 0 334 DESIGN fad_main_tb 335 VIEW struct.bd 336 NO_GRAPHIC 196 337 DESIGN fad_main_tb 338 VIEW struct.bd 339 NO_GRAPHIC 197 340 DESIGN fad_main_tb 341 VIEW struct.bd 342 GRAPHIC 233,0 199 0 343 DESIGN fad_main_tb 344 VIEW struct.bd 345 GRAPHIC 240,0 200 1 346 DESIGN fad_main_tb 347 VIEW struct.bd 348 GRAPHIC 286,0 204 0 349 DESIGN fad_main_tb 350 VIEW struct.bd 351 GRAPHIC 873,0 205 0 352 DESIGN fad_main_tb 353 VIEW struct.bd 354 GRAPHIC 881,0 206 0 355 DESIGN fad_main_tb 356 VIEW struct.bd 357 GRAPHIC 889,0 207 0 358 DESIGN fad_main_tb 359 VIEW struct.bd 360 GRAPHIC 897,0 208 0 361 DESIGN fad_main_tb 362 VIEW struct.bd 363 GRAPHIC 538,0 209 0 364 DESIGN fad_main_tb 365 VIEW struct.bd 366 GRAPHIC 530,0 210 0 367 DESIGN fad_main_tb 368 VIEW struct.bd 369 GRAPHIC 442,0 211 0 370 DESIGN fad_main_tb 371 VIEW struct.bd 372 GRAPHIC 450,0 212 0 373 DESIGN fad_main_tb 374 VIEW struct.bd 375 GRAPHIC 426,0 213 0 376 DESIGN fad_main_tb 377 VIEW struct.bd 378 GRAPHIC 793,0 214 0 379 DESIGN fad_main_tb 380 VIEW struct.bd 381 GRAPHIC 825,0 215 0 382 DESIGN fad_main_tb 383 VIEW struct.bd 384 GRAPHIC 833,0 216 0 385 DESIGN fad_main_tb 386 VIEW struct.bd 387 GRAPHIC 857,0 217 0 388 DESIGN fad_main_tb 389 VIEW struct.bd 390 GRAPHIC 865,0 218 0 391 DESIGN fad_main_tb 392 VIEW struct.bd 393 GRAPHIC 546,0 219 0 394 DESIGN fad_main_tb 395 VIEW struct.bd 396 GRAPHIC 801,0 220 0 397 DESIGN fad_main_tb 398 VIEW struct.bd 399 GRAPHIC 817,0 221 0 400 DESIGN fad_main_tb 401 VIEW struct.bd 402 GRAPHIC 841,0 222 0 403 DESIGN fad_main_tb 404 VIEW struct.bd 405 GRAPHIC 849,0 223 0 406 DESIGN fad_main_tb 407 VIEW struct.bd 408 GRAPHIC 777,0 224 0 409 DESIGN fad_main_tb 410 VIEW struct.bd 411 GRAPHIC 809,0 225 0 412 DESIGN fad_main_tb 413 VIEW struct.bd 414 GRAPHIC 380,0 226 0 415 DESIGN fad_main_tb 416 VIEW struct.bd 417 GRAPHIC 374,0 227 0 418 DESIGN fad_main_tb 419 VIEW struct.bd 420 GRAPHIC 318,0 228 0 421 DESIGN fad_main_tb 422 VIEW struct.bd 423 GRAPHIC 785,0 229 0 424 DESIGN fad_main_tb 425 VIEW struct.bd 426 GRAPHIC 330,0 230 0 427 DESIGN fad_main_tb 428 VIEW struct.bd 429 GRAPHIC 769,0 231 0 430 DESIGN fad_main_tb 431 VIEW struct.bd 432 GRAPHIC 336,0 232 0 433 DESIGN fad_main_tb 434 VIEW struct.bd 435 GRAPHIC 386,0 233 0 436 DESIGN fad_main_tb 437 VIEW struct.bd 438 GRAPHIC 324,0 234 0 439 DESIGN fad_main_tb 440 VIEW struct.bd 441 GRAPHIC 508,0 236 0 442 DESIGN fad_main_tb 443 VIEW struct.bd 444 GRAPHIC 515,0 237 1 445 DESIGN fad_main_tb 446 VIEW struct.bd 447 GRAPHIC 578,0 241 0 448 DESIGN fad_main_tb 449 VIEW struct.bd 450 GRAPHIC 570,0 242 0 451 DESIGN fad_main_tb 452 VIEW struct.bd 453 GRAPHIC 562,0 243 0 454 DESIGN fad_main_tb 455 VIEW struct.bd 456 GRAPHIC 554,0 244 0 457 DESIGN fad_main_tb 458 VIEW struct.bd 459 GRAPHIC 274,0 246 0 460 DESIGN fad_main_tb 461 VIEW struct.bd 462 GRAPHIC 281,0 247 1 463 DESIGN fad_main_tb 464 VIEW struct.bd 465 GRAPHIC 286,0 252 0 466 DESIGN fad_main_tb 467 VIEW struct.bd 468 GRAPHIC 362,0 255 0 469 DESIGN fad_main_tb 470 VIEW struct.bd 471 GRAPHIC 369,0 256 1 472 DESIGN fad_main_tb 473 VIEW struct.bd 474 GRAPHIC 380,0 260 0 475 DESIGN fad_main_tb 476 VIEW struct.bd 477 GRAPHIC 386,0 261 0 478 DESIGN fad_main_tb 479 VIEW struct.bd 480 GRAPHIC 374,0 262 0 481 DESIGN fad_main_tb 482 VIEW struct.bd 483 GRAPHIC 414,0 264 0 484 DESIGN fad_main_tb 485 VIEW struct.bd 486 GRAPHIC 421,0 265 1 487 DESIGN fad_main_tb 488 VIEW struct.bd 489 GRAPHIC 426,0 270 0 490 DESIGN fad_main_tb 491 VIEW struct.bd 492 GRAPHIC 306,0 272 0 493 DESIGN fad_main_tb 494 VIEW struct.bd 495 GRAPHIC 318,0 274 0 496 DESIGN fad_main_tb 497 VIEW struct.bd 498 GRAPHIC 324,0 275 0 499 DESIGN fad_main_tb 500 VIEW struct.bd 501 GRAPHIC 330,0 276 0 502 DESIGN fad_main_tb 503 VIEW struct.bd 504 GRAPHIC 336,0 277 0 505 DESIGN fad_main_tb 506 VIEW struct.bd 507 NO_GRAPHIC 280 372 NO_GRAPHIC 190 373 DESIGN fad_main_tb 374 VIEW struct.bd 375 GRAPHIC 233,0 193 0 376 DESIGN fad_main_tb 377 VIEW struct.bd 378 GRAPHIC 508,0 194 0 379 DESIGN fad_main_tb 380 VIEW struct.bd 381 GRAPHIC 274,0 195 0 382 DESIGN fad_main_tb 383 VIEW struct.bd 384 GRAPHIC 362,0 196 0 385 DESIGN fad_main_tb 386 VIEW struct.bd 387 GRAPHIC 414,0 197 0 388 DESIGN fad_main_tb 389 VIEW struct.bd 390 GRAPHIC 306,0 198 0 391 DESIGN fad_main_tb 392 VIEW struct.bd 393 NO_GRAPHIC 201 394 DESIGN fad_main_tb 395 VIEW struct.bd 396 GRAPHIC 430,0 204 0 397 DESIGN fad_main_tb 398 VIEW struct.bd 399 NO_GRAPHIC 208 400 DESIGN fad_main_tb 401 VIEW struct.bd 402 GRAPHIC 518,0 209 0 403 DESIGN fad_main_tb 404 VIEW struct.bd 405 NO_GRAPHIC 219 406 DESIGN fad_main_tb 407 VIEW struct.bd 408 GRAPHIC 1491,0 220 0 409 DESIGN fad_main_tb 410 VIEW struct.bd 411 NO_GRAPHIC 228 412 DESIGN fad_main_tb 413 VIEW struct.bd 414 NO_GRAPHIC 229 415 DESIGN fad_main_tb 416 VIEW struct.bd 417 GRAPHIC 233,0 231 0 418 DESIGN fad_main_tb 419 VIEW struct.bd 420 GRAPHIC 240,0 232 1 421 DESIGN fad_main_tb 422 VIEW struct.bd 423 GRAPHIC 286,0 236 0 424 DESIGN fad_main_tb 425 VIEW struct.bd 426 GRAPHIC 1503,0 237 0 427 DESIGN fad_main_tb 428 VIEW struct.bd 429 GRAPHIC 873,0 238 0 430 DESIGN fad_main_tb 431 VIEW struct.bd 432 GRAPHIC 881,0 239 0 433 DESIGN fad_main_tb 434 VIEW struct.bd 435 GRAPHIC 889,0 240 0 436 DESIGN fad_main_tb 437 VIEW struct.bd 438 GRAPHIC 897,0 241 0 439 DESIGN fad_main_tb 440 VIEW struct.bd 441 GRAPHIC 538,0 242 0 442 DESIGN fad_main_tb 443 VIEW struct.bd 444 GRAPHIC 530,0 243 0 445 DESIGN fad_main_tb 446 VIEW struct.bd 447 GRAPHIC 442,0 244 0 448 DESIGN fad_main_tb 449 VIEW struct.bd 450 GRAPHIC 450,0 245 0 451 DESIGN fad_main_tb 452 VIEW struct.bd 453 GRAPHIC 1529,0 246 0 454 DESIGN fad_main_tb 455 VIEW struct.bd 456 GRAPHIC 1561,0 247 0 457 DESIGN fad_main_tb 458 VIEW struct.bd 459 GRAPHIC 426,0 248 0 460 DESIGN fad_main_tb 461 VIEW struct.bd 462 GRAPHIC 793,0 249 0 463 DESIGN fad_main_tb 464 VIEW struct.bd 465 GRAPHIC 1684,0 250 0 466 DESIGN fad_main_tb 467 VIEW struct.bd 468 GRAPHIC 825,0 251 0 469 DESIGN fad_main_tb 470 VIEW struct.bd 471 GRAPHIC 833,0 252 0 472 DESIGN fad_main_tb 473 VIEW struct.bd 474 GRAPHIC 857,0 253 0 475 DESIGN fad_main_tb 476 VIEW struct.bd 477 GRAPHIC 865,0 254 0 478 DESIGN fad_main_tb 479 VIEW struct.bd 480 GRAPHIC 1437,0 255 0 481 DESIGN fad_main_tb 482 VIEW struct.bd 483 GRAPHIC 546,0 256 0 484 DESIGN fad_main_tb 485 VIEW struct.bd 486 GRAPHIC 1485,0 257 0 487 DESIGN fad_main_tb 488 VIEW struct.bd 489 GRAPHIC 1477,0 258 0 490 DESIGN fad_main_tb 491 VIEW struct.bd 492 GRAPHIC 1445,0 259 0 493 DESIGN fad_main_tb 494 VIEW struct.bd 495 GRAPHIC 1469,0 260 0 496 DESIGN fad_main_tb 497 VIEW struct.bd 498 GRAPHIC 801,0 261 0 499 DESIGN fad_main_tb 500 VIEW struct.bd 501 GRAPHIC 817,0 262 0 502 DESIGN fad_main_tb 503 VIEW struct.bd 504 GRAPHIC 841,0 263 0 505 DESIGN fad_main_tb 506 VIEW struct.bd 507 GRAPHIC 849,0 264 0 508 DESIGN fad_main_tb 509 VIEW struct.bd 510 GRAPHIC 1461,0 265 0 511 DESIGN fad_main_tb 512 VIEW struct.bd 513 GRAPHIC 777,0 266 0 514 DESIGN fad_main_tb 515 VIEW struct.bd 516 GRAPHIC 809,0 267 0 517 DESIGN fad_main_tb 518 VIEW struct.bd 519 GRAPHIC 1453,0 268 0 520 DESIGN fad_main_tb 521 VIEW struct.bd 522 GRAPHIC 380,0 269 0 523 DESIGN fad_main_tb 524 VIEW struct.bd 525 GRAPHIC 374,0 270 0 526 DESIGN fad_main_tb 527 VIEW struct.bd 528 GRAPHIC 318,0 271 0 529 DESIGN fad_main_tb 530 VIEW struct.bd 531 GRAPHIC 785,0 272 0 532 DESIGN fad_main_tb 533 VIEW struct.bd 534 GRAPHIC 330,0 273 0 535 DESIGN fad_main_tb 536 VIEW struct.bd 537 GRAPHIC 769,0 274 0 538 DESIGN fad_main_tb 539 VIEW struct.bd 540 GRAPHIC 336,0 275 0 541 DESIGN fad_main_tb 542 VIEW struct.bd 543 GRAPHIC 386,0 276 0 544 DESIGN fad_main_tb 545 VIEW struct.bd 546 GRAPHIC 324,0 277 0 547 DESIGN fad_main_tb 548 VIEW struct.bd 549 GRAPHIC 508,0 279 0 550 DESIGN fad_main_tb 551 VIEW struct.bd 552 GRAPHIC 515,0 280 1 553 DESIGN fad_main_tb 554 VIEW struct.bd 555 GRAPHIC 578,0 284 0 556 DESIGN fad_main_tb 557 VIEW struct.bd 558 GRAPHIC 570,0 285 0 559 DESIGN fad_main_tb 560 VIEW struct.bd 561 GRAPHIC 562,0 286 0 562 DESIGN fad_main_tb 563 VIEW struct.bd 564 GRAPHIC 554,0 287 0 565 DESIGN fad_main_tb 566 VIEW struct.bd 567 GRAPHIC 274,0 289 0 568 DESIGN fad_main_tb 569 VIEW struct.bd 570 GRAPHIC 281,0 290 1 571 DESIGN fad_main_tb 572 VIEW struct.bd 573 GRAPHIC 286,0 295 0 574 DESIGN fad_main_tb 575 VIEW struct.bd 576 GRAPHIC 1509,0 298 0 577 DESIGN fad_main_tb 578 VIEW struct.bd 579 GRAPHIC 1516,0 299 1 580 DESIGN fad_main_tb 581 VIEW struct.bd 582 GRAPHIC 1529,0 304 0 583 DESIGN fad_main_tb 584 VIEW struct.bd 585 GRAPHIC 362,0 307 0 586 DESIGN fad_main_tb 587 VIEW struct.bd 588 GRAPHIC 369,0 308 1 589 DESIGN fad_main_tb 590 VIEW struct.bd 591 GRAPHIC 380,0 312 0 592 DESIGN fad_main_tb 593 VIEW struct.bd 594 GRAPHIC 386,0 313 0 595 DESIGN fad_main_tb 596 VIEW struct.bd 597 GRAPHIC 374,0 314 0 598 DESIGN fad_main_tb 599 VIEW struct.bd 600 GRAPHIC 414,0 316 0 601 DESIGN fad_main_tb 602 VIEW struct.bd 603 GRAPHIC 421,0 317 1 604 DESIGN fad_main_tb 605 VIEW struct.bd 606 GRAPHIC 426,0 322 0 607 DESIGN fad_main_tb 608 VIEW struct.bd 609 GRAPHIC 306,0 324 0 610 DESIGN fad_main_tb 611 VIEW struct.bd 612 GRAPHIC 793,0 326 0 613 DESIGN fad_main_tb 614 VIEW struct.bd 615 GRAPHIC 318,0 327 0 616 DESIGN fad_main_tb 617 VIEW struct.bd 618 GRAPHIC 324,0 328 0 619 DESIGN fad_main_tb 620 VIEW struct.bd 621 GRAPHIC 330,0 329 0 622 DESIGN fad_main_tb 623 VIEW struct.bd 624 GRAPHIC 336,0 330 0 625 DESIGN fad_main_tb 626 VIEW struct.bd 627 NO_GRAPHIC 333 -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/fad_main_tb/struct.bd
r9912 r10180 118 118 uid 508,0 119 119 ) 120 (Instance 121 name "I_mainTB_clock1" 122 duLibraryName "FACT_FAD_TB_lib" 123 duName "clock_generator" 124 elements [ 125 (GiElement 126 name "clock_period" 127 type "time" 128 value "1 us" 129 ) 130 (GiElement 131 name "reset_time" 132 type "time" 133 value "1 us" 134 ) 135 ] 136 mwi 0 137 uid 1509,0 138 ) 120 139 ] 121 140 embeddedInstances [ … … 127 146 name "eb_mainTB_adc" 128 147 number "2" 148 ) 149 (EmbeddedInstance 150 name "eb_mainTB_adc1" 151 number "3" 129 152 ) 130 153 ] … … 143 166 (vvPair 144 167 variable "HDLDir" 145 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hdl"168 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl" 146 169 ) 147 170 (vvPair 148 171 variable "HDSDir" 149 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds"172 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds" 150 173 ) 151 174 (vvPair 152 175 variable "SideDataDesignDir" 153 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.info"176 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.info" 154 177 ) 155 178 (vvPair 156 179 variable "SideDataUserDir" 157 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.user"180 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.user" 158 181 ) 159 182 (vvPair 160 183 variable "SourceDir" 161 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds"184 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds" 162 185 ) 163 186 (vvPair … … 171 194 (vvPair 172 195 variable "config" 173 value "%(unit)_ config"196 value "%(unit)_%(view)_config" 174 197 ) 175 198 (vvPair 176 199 variable "d" 177 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb"200 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb" 178 201 ) 179 202 (vvPair 180 203 variable "d_logical" 181 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb"204 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb" 182 205 ) 183 206 (vvPair 184 207 variable "date" 185 value "25.0 6.2010"208 value "25.02.2011" 186 209 ) 187 210 (vvPair … … 223 246 (vvPair 224 247 variable "host" 225 value "E EPC8"248 value "E5B-LABOR6" 226 249 ) 227 250 (vvPair … … 234 257 ) 235 258 (vvPair 259 variable "library_downstream_HdsLintPlugin" 260 value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/designcheck" 261 ) 262 (vvPair 263 variable "library_downstream_ISEPARInvoke" 264 value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise" 265 ) 266 (vvPair 267 variable "library_downstream_ImpactInvoke" 268 value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise" 269 ) 270 (vvPair 236 271 variable "library_downstream_ModelSimCompiler" 237 272 value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/work" 238 273 ) 239 274 (vvPair 275 variable "library_downstream_XSTDataPrep" 276 value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise" 277 ) 278 (vvPair 240 279 variable "mm" 241 value "0 6"280 value "02" 242 281 ) 243 282 (vvPair … … 247 286 (vvPair 248 287 variable "month" 249 value " Jun"288 value "Feb" 250 289 ) 251 290 (vvPair 252 291 variable "month_long" 253 value " Juni"292 value "Februar" 254 293 ) 255 294 (vvPair 256 295 variable "p" 257 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"296 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd" 258 297 ) 259 298 (vvPair 260 299 variable "p_logical" 261 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"300 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd" 262 301 ) 263 302 (vvPair … … 283 322 (vvPair 284 323 variable "task_ModelSimPath" 285 value " $HDS_HOME/../Modeltech/win32"324 value "C:\\modeltech_6.6a\\win32" 286 325 ) 287 326 (vvPair … … 291 330 (vvPair 292 331 variable "task_PrecisionRTLPath" 293 value " $HDS_HOME/../Precision/Mgc_home/bin"332 value "<TBD>" 294 333 ) 295 334 (vvPair … … 315 354 (vvPair 316 355 variable "time" 317 value " 08:48:16"356 value "13:51:45" 318 357 ) 319 358 (vvPair … … 323 362 (vvPair 324 363 variable "user" 325 value " Benjamin Krumm"364 value "dneise" 326 365 ) 327 366 (vvPair … … 335 374 (vvPair 336 375 variable "year" 337 value "201 0"376 value "2011" 338 377 ) 339 378 (vvPair 340 379 variable "yy" 341 value "1 0"380 value "11" 342 381 ) 343 382 ] … … 367 406 bg "0,0,32768" 368 407 ) 369 xt "109200,97000,1 22200,98000"408 xt "109200,97000,118800,98000" 370 409 st " 371 410 by %user on %dd %month %year … … 706 745 n "wiz_reset" 707 746 t "std_logic" 708 o 28747 o 39 709 748 suid 2,0 710 749 i "'1'" … … 745 784 b "(7 DOWNTO 0)" 746 785 posAdd 0 747 o 21786 o 31 748 787 suid 7,0 749 788 i "(OTHERS => '0')" … … 782 821 preAdd 0 783 822 posAdd 0 784 o 1 0823 o 13 785 824 suid 18,0 786 825 ) … … 817 856 n "adc_oeb" 818 857 t "std_logic" 819 o 16858 o 21 820 859 suid 21,0 821 860 i "'1'" … … 852 891 n "board_id" 853 892 t "std_logic_vector" 854 b "(3 downto 0)" 855 preAdd 0 856 posAdd 0 857 o 8 893 b "(3 DOWNTO 0)" 894 o 9 858 895 suid 24,0 859 896 ) … … 889 926 n "crate_id" 890 927 t "std_logic_vector" 891 b "(1 downto0)"892 o 9928 b "(1 DOWNTO 0)" 929 o 10 893 930 suid 25,0 894 931 ) … … 927 964 t "std_logic_vector" 928 965 b "(9 DOWNTO 0)" 929 o 25966 o 36 930 967 suid 26,0 931 968 ) … … 964 1001 t "std_logic_vector" 965 1002 b "(15 DOWNTO 0)" 966 o 311003 o 42 967 1004 suid 27,0 968 1005 ) … … 1000 1037 n "wiz_cs" 1001 1038 t "std_logic" 1002 o 261039 o 37 1003 1040 suid 28,0 1004 1041 i "'1'" … … 1037 1074 n "wiz_wr" 1038 1075 t "std_logic" 1039 o 291076 o 40 1040 1077 suid 29,0 1041 1078 i "'1'" … … 1074 1111 n "wiz_rd" 1075 1112 t "std_logic" 1076 o 271113 o 38 1077 1114 suid 30,0 1078 1115 i "'1'" … … 1110 1147 n "wiz_int" 1111 1148 t "std_logic" 1112 o 1 11149 o 14 1113 1150 suid 31,0 1114 1151 ) … … 1145 1182 n "CLK_25_PS" 1146 1183 t "std_logic" 1147 o 1 21184 o 16 1148 1185 suid 35,0 1149 1186 ) … … 1180 1217 n "CLK_50" 1181 1218 t "std_logic" 1182 o 13 1219 preAdd 0 1220 posAdd 0 1221 o 17 1183 1222 suid 37,0 1184 1223 ) … … 1249 1288 t "std_logic_vector" 1250 1289 b "(3 DOWNTO 0)" 1251 o 71290 o 8 1252 1291 suid 40,0 1253 1292 ) … … 1283 1322 n "adc_data_array" 1284 1323 t "adc_data_array_type" 1285 o 61324 o 7 1286 1325 suid 41,0 1287 1326 ) … … 1319 1358 t "std_logic_vector" 1320 1359 b "(3 downto 0)" 1321 o 191360 o 28 1322 1361 suid 48,0 1323 1362 i "(others => '0')" … … 1355 1394 n "drs_dwrite" 1356 1395 t "std_logic" 1357 o 2 01396 o 29 1358 1397 suid 49,0 1359 1398 i "'1'" … … 1390 1429 n "SROUT_in_0" 1391 1430 t "std_logic" 1392 o 21431 o 3 1393 1432 suid 52,0 1394 1433 ) … … 1424 1463 n "SROUT_in_1" 1425 1464 t "std_logic" 1426 o 31465 o 4 1427 1466 suid 53,0 1428 1467 ) … … 1458 1497 n "SROUT_in_2" 1459 1498 t "std_logic" 1460 o 41499 o 5 1461 1500 suid 54,0 1462 1501 ) … … 1492 1531 n "SROUT_in_3" 1493 1532 t "std_logic" 1494 o 51533 o 6 1495 1534 suid 55,0 1496 1535 ) … … 1527 1566 n "RSRLOAD" 1528 1567 t "std_logic" 1529 o 1 41568 o 18 1530 1569 suid 56,0 1531 1570 i "'0'" … … 1563 1602 n "SRCLK" 1564 1603 t "std_logic" 1565 o 1 51604 o 19 1566 1605 suid 57,0 1567 1606 i "'0'" … … 1600 1639 n "sclk" 1601 1640 t "std_logic" 1602 o 231641 o 34 1603 1642 suid 62,0 1604 1643 ) … … 1638 1677 preAdd 0 1639 1678 posAdd 0 1640 o 301679 o 41 1641 1680 suid 63,0 1642 1681 ) … … 1674 1713 n "dac_cs" 1675 1714 t "std_logic" 1676 o 171715 o 26 1677 1716 suid 64,0 1678 1717 ) … … 1711 1750 t "std_logic_vector" 1712 1751 b "(3 DOWNTO 0)" 1713 o 241752 o 35 1714 1753 suid 65,0 1715 1754 ) … … 1747 1786 n "mosi" 1748 1787 t "std_logic" 1749 o 221788 o 32 1750 1789 suid 66,0 1751 1790 i "'0'" … … 1786 1825 eolc "-- default domino wave off" 1787 1826 posAdd 0 1788 o 181827 o 27 1789 1828 suid 67,0 1790 1829 i "'0'" 1830 ) 1831 ) 1832 ) 1833 *44 (CptPort 1834 uid 1395,0 1835 ps "OnEdgeStrategy" 1836 shape (Triangle 1837 uid 1396,0 1838 ro 90 1839 va (VaSet 1840 vasetType 1 1841 fg "0,65535,0" 1842 ) 1843 xt "109000,73625,109750,74375" 1844 ) 1845 tg (CPTG 1846 uid 1397,0 1847 ps "CptPortTextPlaceStrategy" 1848 stg "RightVerticalLayoutStrategy" 1849 f (Text 1850 uid 1398,0 1851 va (VaSet 1852 ) 1853 xt "99400,73500,108000,74500" 1854 st "alarm_refclk_too_high" 1855 ju 2 1856 blo "108000,74300" 1857 ) 1858 ) 1859 thePort (LogicalPort 1860 m 1 1861 decl (Decl 1862 n "alarm_refclk_too_high" 1863 t "std_logic" 1864 o 22 1865 suid 95,0 1866 ) 1867 ) 1868 ) 1869 *45 (CptPort 1870 uid 1399,0 1871 ps "OnEdgeStrategy" 1872 shape (Triangle 1873 uid 1400,0 1874 ro 90 1875 va (VaSet 1876 vasetType 1 1877 fg "0,65535,0" 1878 ) 1879 xt "109000,74625,109750,75375" 1880 ) 1881 tg (CPTG 1882 uid 1401,0 1883 ps "CptPortTextPlaceStrategy" 1884 stg "RightVerticalLayoutStrategy" 1885 f (Text 1886 uid 1402,0 1887 va (VaSet 1888 ) 1889 xt "99800,74500,108000,75500" 1890 st "alarm_refclk_too_low" 1891 ju 2 1892 blo "108000,75300" 1893 ) 1894 ) 1895 thePort (LogicalPort 1896 m 1 1897 decl (Decl 1898 n "alarm_refclk_too_low" 1899 t "std_logic" 1900 posAdd 0 1901 o 23 1902 suid 96,0 1903 ) 1904 ) 1905 ) 1906 *46 (CptPort 1907 uid 1403,0 1908 ps "OnEdgeStrategy" 1909 shape (Triangle 1910 uid 1404,0 1911 ro 90 1912 va (VaSet 1913 vasetType 1 1914 fg "0,65535,0" 1915 ) 1916 xt "109000,79625,109750,80375" 1917 ) 1918 tg (CPTG 1919 uid 1405,0 1920 ps "CptPortTextPlaceStrategy" 1921 stg "RightVerticalLayoutStrategy" 1922 f (Text 1923 uid 1406,0 1924 va (VaSet 1925 ) 1926 xt "105500,79500,108000,80500" 1927 st "amber" 1928 ju 2 1929 blo "108000,80300" 1930 ) 1931 ) 1932 thePort (LogicalPort 1933 m 1 1934 decl (Decl 1935 n "amber" 1936 t "std_logic" 1937 o 24 1938 suid 87,0 1939 ) 1940 ) 1941 ) 1942 *47 (CptPort 1943 uid 1407,0 1944 ps "OnEdgeStrategy" 1945 shape (Triangle 1946 uid 1408,0 1947 ro 90 1948 va (VaSet 1949 vasetType 1 1950 fg "0,65535,0" 1951 ) 1952 xt "109000,76625,109750,77375" 1953 ) 1954 tg (CPTG 1955 uid 1409,0 1956 ps "CptPortTextPlaceStrategy" 1957 stg "RightVerticalLayoutStrategy" 1958 f (Text 1959 uid 1410,0 1960 va (VaSet 1961 ) 1962 xt "99400,76500,108000,77500" 1963 st "counter_result : (11:0)" 1964 ju 2 1965 blo "108000,77300" 1966 ) 1967 ) 1968 thePort (LogicalPort 1969 m 1 1970 decl (Decl 1971 n "counter_result" 1972 t "std_logic_vector" 1973 b "(11 DOWNTO 0)" 1974 o 25 1975 suid 94,0 1976 ) 1977 ) 1978 ) 1979 *48 (CptPort 1980 uid 1411,0 1981 ps "OnEdgeStrategy" 1982 shape (Triangle 1983 uid 1412,0 1984 ro 90 1985 va (VaSet 1986 vasetType 1 1987 fg "0,65535,0" 1988 ) 1989 xt "80250,74625,81000,75375" 1990 ) 1991 tg (CPTG 1992 uid 1413,0 1993 ps "CptPortTextPlaceStrategy" 1994 stg "VerticalLayoutStrategy" 1995 f (Text 1996 uid 1414,0 1997 va (VaSet 1998 ) 1999 xt "82000,74500,87500,75500" 2000 st "D_T_in : (1:0)" 2001 blo "82000,75300" 2002 ) 2003 ) 2004 thePort (LogicalPort 2005 decl (Decl 2006 n "D_T_in" 2007 t "std_logic_vector" 2008 b "(1 DOWNTO 0)" 2009 o 2 2010 suid 91,0 2011 ) 2012 ) 2013 ) 2014 *49 (CptPort 2015 uid 1415,0 2016 ps "OnEdgeStrategy" 2017 shape (Triangle 2018 uid 1416,0 2019 ro 90 2020 va (VaSet 2021 vasetType 1 2022 fg "0,65535,0" 2023 ) 2024 xt "80250,75625,81000,76375" 2025 ) 2026 tg (CPTG 2027 uid 1417,0 2028 ps "CptPortTextPlaceStrategy" 2029 stg "VerticalLayoutStrategy" 2030 f (Text 2031 uid 1418,0 2032 va (VaSet 2033 ) 2034 xt "82000,75500,87100,76500" 2035 st "drs_refclk_in" 2036 blo "82000,76300" 2037 ) 2038 ) 2039 thePort (LogicalPort 2040 decl (Decl 2041 n "drs_refclk_in" 2042 t "std_logic" 2043 eolc "-- used to check if DRS REFCLK exsists, if not DENABLE inhibit" 2044 o 11 2045 suid 92,0 2046 ) 2047 ) 2048 ) 2049 *50 (CptPort 2050 uid 1419,0 2051 ps "OnEdgeStrategy" 2052 shape (Triangle 2053 uid 1420,0 2054 ro 90 2055 va (VaSet 2056 vasetType 1 2057 fg "0,65535,0" 2058 ) 2059 xt "109000,77625,109750,78375" 2060 ) 2061 tg (CPTG 2062 uid 1421,0 2063 ps "CptPortTextPlaceStrategy" 2064 stg "RightVerticalLayoutStrategy" 2065 f (Text 2066 uid 1422,0 2067 va (VaSet 2068 ) 2069 xt "105600,77500,108000,78500" 2070 st "green" 2071 ju 2 2072 blo "108000,78300" 2073 ) 2074 ) 2075 thePort (LogicalPort 2076 m 1 2077 decl (Decl 2078 n "green" 2079 t "std_logic" 2080 o 30 2081 suid 86,0 2082 ) 2083 ) 2084 ) 2085 *51 (CptPort 2086 uid 1423,0 2087 ps "OnEdgeStrategy" 2088 shape (Triangle 2089 uid 1424,0 2090 ro 90 2091 va (VaSet 2092 vasetType 1 2093 fg "0,65535,0" 2094 ) 2095 xt "80250,76625,81000,77375" 2096 ) 2097 tg (CPTG 2098 uid 1425,0 2099 ps "CptPortTextPlaceStrategy" 2100 stg "VerticalLayoutStrategy" 2101 f (Text 2102 uid 1426,0 2103 va (VaSet 2104 ) 2105 xt "82000,76500,88100,77500" 2106 st "plllock_in : (3:0)" 2107 blo "82000,77300" 2108 ) 2109 ) 2110 thePort (LogicalPort 2111 decl (Decl 2112 n "plllock_in" 2113 t "std_logic_vector" 2114 b "(3 DOWNTO 0)" 2115 eolc "-- high level, if dominowave is running and DRS PLL locked" 2116 o 12 2117 suid 93,0 2118 ) 2119 ) 2120 ) 2121 *52 (CptPort 2122 uid 1427,0 2123 ps "OnEdgeStrategy" 2124 shape (Triangle 2125 uid 1428,0 2126 ro 90 2127 va (VaSet 2128 vasetType 1 2129 fg "0,65535,0" 2130 ) 2131 xt "109000,78625,109750,79375" 2132 ) 2133 tg (CPTG 2134 uid 1429,0 2135 ps "CptPortTextPlaceStrategy" 2136 stg "RightVerticalLayoutStrategy" 2137 f (Text 2138 uid 1430,0 2139 va (VaSet 2140 ) 2141 xt "106500,78500,108000,79500" 2142 st "red" 2143 ju 2 2144 blo "108000,79300" 2145 ) 2146 ) 2147 thePort (LogicalPort 2148 m 1 2149 decl (Decl 2150 n "red" 2151 t "std_logic" 2152 o 33 2153 suid 88,0 2154 ) 2155 ) 2156 ) 2157 *53 (CptPort 2158 uid 1431,0 2159 ps "OnEdgeStrategy" 2160 shape (Triangle 2161 uid 1432,0 2162 ro 270 2163 va (VaSet 2164 vasetType 1 2165 fg "0,65535,0" 2166 ) 2167 xt "80250,71625,81000,72375" 2168 ) 2169 tg (CPTG 2170 uid 1433,0 2171 ps "CptPortTextPlaceStrategy" 2172 stg "VerticalLayoutStrategy" 2173 f (Text 2174 uid 1434,0 2175 va (VaSet 2176 ) 2177 xt "82000,71500,85700,72500" 2178 st "SRIN_out" 2179 blo "82000,72300" 2180 ) 2181 ) 2182 thePort (LogicalPort 2183 m 1 2184 decl (Decl 2185 n "SRIN_out" 2186 t "std_logic" 2187 o 20 2188 suid 85,0 2189 i "'0'" 2190 ) 2191 ) 2192 ) 2193 *54 (CptPort 2194 uid 1678,0 2195 ps "OnEdgeStrategy" 2196 shape (Triangle 2197 uid 1679,0 2198 ro 270 2199 va (VaSet 2200 vasetType 1 2201 fg "0,65535,0" 2202 ) 2203 xt "80250,23625,81000,24375" 2204 ) 2205 tg (CPTG 2206 uid 1680,0 2207 ps "CptPortTextPlaceStrategy" 2208 stg "VerticalLayoutStrategy" 2209 f (Text 2210 uid 1681,0 2211 va (VaSet 2212 ) 2213 xt "82000,23500,86000,24500" 2214 st "ADC_CLK" 2215 blo "82000,24300" 2216 ) 2217 ) 2218 thePort (LogicalPort 2219 lang 2 2220 m 1 2221 decl (Decl 2222 n "ADC_CLK" 2223 t "std_logic" 2224 o 15 2225 suid 97,0 1791 2226 ) 1792 2227 ) … … 1801 2236 lineWidth 2 1802 2237 ) 1803 xt "81000,19000,109000, 73000"2238 xt "81000,19000,109000,81000" 1804 2239 ) 1805 2240 oxt "15000,-8000,43000,46000" … … 1809 2244 stg "VerticalLayoutStrategy" 1810 2245 textVec [ 1811 * 44(Text2246 *55 (Text 1812 2247 uid 236,0 1813 2248 va (VaSet 1814 2249 font "Arial,8,1" 1815 2250 ) 1816 xt "8 1200,73000,87400,74000"2251 xt "83200,81000,89400,82000" 1817 2252 st "FACT_FAD_lib" 1818 blo "8 1200,73800"2253 blo "83200,81800" 1819 2254 tm "BdLibraryNameMgr" 1820 2255 ) 1821 * 45(Text2256 *56 (Text 1822 2257 uid 237,0 1823 2258 va (VaSet 1824 2259 font "Arial,8,1" 1825 2260 ) 1826 xt "8 1200,74000,85400,75000"2261 xt "83200,82000,87400,83000" 1827 2262 st "FAD_main" 1828 blo "8 1200,74800"2263 blo "83200,82800" 1829 2264 tm "CptNameMgr" 1830 2265 ) 1831 * 46(Text2266 *57 (Text 1832 2267 uid 238,0 1833 2268 va (VaSet 1834 2269 font "Arial,8,1" 1835 2270 ) 1836 xt "8 1200,75000,88000,76000"2271 xt "83200,83000,90000,84000" 1837 2272 st "I_mainTB_FPGA" 1838 blo "8 1200,75800"2273 blo "83200,83800" 1839 2274 tm "InstanceNameMgr" 1840 2275 ) … … 1871 2306 fg "49152,49152,49152" 1872 2307 ) 1873 xt "81250,7 1250,82750,72750"2308 xt "81250,79250,82750,80750" 1874 2309 iconName "BlockDiagram.png" 1875 2310 iconMaskName "BlockDiagram.msk" … … 1881 2316 archFileType "UNKNOWN" 1882 2317 ) 1883 * 47(SaComponent2318 *58 (SaComponent 1884 2319 uid 274,0 1885 2320 optionalChildren [ 1886 * 48(CptPort2321 *59 (CptPort 1887 2322 uid 266,0 1888 2323 ps "OnEdgeStrategy" … … 1920 2355 ) 1921 2356 ) 1922 * 49(CptPort2357 *60 (CptPort 1923 2358 uid 270,0 1924 2359 ps "OnEdgeStrategy" … … 1973 2408 stg "VerticalLayoutStrategy" 1974 2409 textVec [ 1975 * 50(Text2410 *61 (Text 1976 2411 uid 277,0 1977 2412 va (VaSet … … 1983 2418 tm "BdLibraryNameMgr" 1984 2419 ) 1985 * 51(Text2420 *62 (Text 1986 2421 uid 278,0 1987 2422 va (VaSet … … 1993 2428 tm "CptNameMgr" 1994 2429 ) 1995 * 52(Text2430 *63 (Text 1996 2431 uid 279,0 1997 2432 va (VaSet … … 2052 2487 archFileType "UNKNOWN" 2053 2488 ) 2054 * 53(Net2489 *64 (Net 2055 2490 uid 284,0 2056 2491 decl (Decl … … 2067 2502 font "Courier New,8,0" 2068 2503 ) 2069 xt " 2000,26800,20000,27600"2070 st "SIGNAL clk : STD_LOGIC"2071 ) 2072 ) 2073 * 54(SaComponent2504 xt "-90000,41400,-68000,42200" 2505 st "SIGNAL clk : STD_LOGIC" 2506 ) 2507 ) 2508 *65 (SaComponent 2074 2509 uid 306,0 2075 2510 optionalChildren [ 2076 * 55(CptPort2511 *66 (CptPort 2077 2512 uid 290,0 2078 2513 ps "OnEdgeStrategy" … … 2103 2538 n "addr" 2104 2539 t "std_logic_vector" 2105 b "(9 downto0)"2540 b "(9 DOWNTO 0)" 2106 2541 preAdd 0 2107 2542 posAdd 0 2108 o 12543 o 2 2109 2544 suid 1,0 2110 2545 ) 2111 2546 ) 2112 2547 ) 2113 * 56(CptPort2548 *67 (CptPort 2114 2549 uid 294,0 2115 2550 ps "OnEdgeStrategy" … … 2141 2576 n "data" 2142 2577 t "std_logic_vector" 2143 b "(15 downto0)"2578 b "(15 DOWNTO 0)" 2144 2579 preAdd 0 2145 2580 posAdd 0 2146 o 22581 o 3 2147 2582 suid 2,0 2148 2583 ) 2149 2584 ) 2150 2585 ) 2151 * 57(CptPort2586 *68 (CptPort 2152 2587 uid 298,0 2153 2588 ps "OnEdgeStrategy" … … 2180 2615 preAdd 0 2181 2616 posAdd 0 2182 o 32617 o 4 2183 2618 suid 3,0 2184 2619 ) 2185 2620 ) 2186 2621 ) 2187 * 58(CptPort2622 *69 (CptPort 2188 2623 uid 302,0 2189 2624 ps "OnEdgeStrategy" … … 2216 2651 preAdd 0 2217 2652 posAdd 0 2218 o 42653 o 5 2219 2654 suid 4,0 2655 ) 2656 ) 2657 ) 2658 *70 (CptPort 2659 uid 2108,0 2660 ps "OnEdgeStrategy" 2661 shape (Triangle 2662 uid 2109,0 2663 ro 270 2664 va (VaSet 2665 vasetType 1 2666 fg "0,65535,0" 2667 ) 2668 xt "122250,26625,123000,27375" 2669 ) 2670 tg (CPTG 2671 uid 2110,0 2672 ps "CptPortTextPlaceStrategy" 2673 stg "VerticalLayoutStrategy" 2674 f (Text 2675 uid 2111,0 2676 va (VaSet 2677 ) 2678 xt "124000,26500,125200,27500" 2679 st "int" 2680 blo "124000,27300" 2681 ) 2682 t (Text 2683 uid 2112,0 2684 va (VaSet 2685 ) 2686 xt "124000,27500,125200,28500" 2687 st "'0'" 2688 blo "124000,28300" 2689 ) 2690 ) 2691 thePort (LogicalPort 2692 m 1 2693 decl (Decl 2694 n "int" 2695 t "std_logic" 2696 o 1 2697 suid 5,0 2698 i "'0'" 2220 2699 ) 2221 2700 ) … … 2238 2717 stg "VerticalLayoutStrategy" 2239 2718 textVec [ 2240 * 59(Text2719 *71 (Text 2241 2720 uid 309,0 2242 2721 va (VaSet … … 2248 2727 tm "BdLibraryNameMgr" 2249 2728 ) 2250 * 60(Text2729 *72 (Text 2251 2730 uid 310,0 2252 2731 va (VaSet … … 2258 2737 tm "CptNameMgr" 2259 2738 ) 2260 * 61(Text2739 *73 (Text 2261 2740 uid 311,0 2262 2741 va (VaSet … … 2306 2785 archFileType "UNKNOWN" 2307 2786 ) 2308 * 62(Net2787 *74 (Net 2309 2788 uid 316,0 2310 2789 decl (Decl … … 2320 2799 font "Courier New,8,0" 2321 2800 ) 2322 xt " 2000,36400,30000,37200"2323 st "SIGNAL wiz_addr : std_logic_vector(9 DOWNTO 0)"2324 ) 2325 ) 2326 * 63(Net2801 xt "-90000,54200,-58500,55000" 2802 st "SIGNAL wiz_addr : std_logic_vector(9 DOWNTO 0)" 2803 ) 2804 ) 2805 *75 (Net 2327 2806 uid 322,0 2328 2807 decl (Decl … … 2338 2817 font "Courier New,8,0" 2339 2818 ) 2340 xt " 2000,38000,30500,38800"2341 st "SIGNAL wiz_data : std_logic_vector(15 DOWNTO 0)"2342 ) 2343 ) 2344 * 64(Net2819 xt "-90000,55800,-58000,56600" 2820 st "SIGNAL wiz_data : std_logic_vector(15 DOWNTO 0)" 2821 ) 2822 ) 2823 *76 (Net 2345 2824 uid 328,0 2346 2825 decl (Decl … … 2356 2835 font "Courier New,8,0" 2357 2836 ) 2358 xt " 2000,39600,33500,40400"2359 st "SIGNAL wiz_rd : std_logic := '1'"2360 ) 2361 ) 2362 * 65(Net2837 xt "-90000,57400,-55000,58200" 2838 st "SIGNAL wiz_rd : std_logic := '1'" 2839 ) 2840 ) 2841 *77 (Net 2363 2842 uid 334,0 2364 2843 decl (Decl … … 2374 2853 font "Courier New,8,0" 2375 2854 ) 2376 xt " 2000,41200,33500,42000"2377 st "SIGNAL wiz_wr : std_logic := '1'"2378 ) 2379 ) 2380 * 66(SaComponent2855 xt "-90000,59000,-55000,59800" 2856 st "SIGNAL wiz_wr : std_logic := '1'" 2857 ) 2858 ) 2859 *78 (SaComponent 2381 2860 uid 362,0 2382 2861 optionalChildren [ 2383 * 67(CptPort2862 *79 (CptPort 2384 2863 uid 350,0 2385 2864 ps "OnEdgeStrategy" … … 2417 2896 ) 2418 2897 ) 2419 * 68(CptPort2898 *80 (CptPort 2420 2899 uid 354,0 2421 2900 ps "OnEdgeStrategy" … … 2454 2933 ) 2455 2934 ) 2456 * 69(CptPort2935 *81 (CptPort 2457 2936 uid 358,0 2458 2937 ps "OnEdgeStrategy" … … 2508 2987 stg "VerticalLayoutStrategy" 2509 2988 textVec [ 2510 * 70(Text2989 *82 (Text 2511 2990 uid 365,0 2512 2991 va (VaSet … … 2518 2997 tm "BdLibraryNameMgr" 2519 2998 ) 2520 * 71(Text2999 *83 (Text 2521 3000 uid 366,0 2522 3001 va (VaSet … … 2528 3007 tm "CptNameMgr" 2529 3008 ) 2530 * 72(Text3009 *84 (Text 2531 3010 uid 367,0 2532 3011 va (VaSet … … 2582 3061 archFileType "UNKNOWN" 2583 3062 ) 2584 * 73(Net3063 *85 (Net 2585 3064 uid 372,0 2586 3065 decl (Decl … … 2596 3075 font "Courier New,8,0" 2597 3076 ) 2598 xt " 2000,34000,30000,34800"2599 st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0)"2600 ) 2601 ) 2602 * 74(Net3077 xt "-90000,51800,-58500,52600" 3078 st "SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0)" 3079 ) 3080 ) 3081 *86 (Net 2603 3082 uid 378,0 2604 3083 decl (Decl … … 2613 3092 font "Courier New,8,0" 2614 3093 ) 2615 xt " 2000,33200,20000,34000"2616 st "SIGNAL sclk : std_logic"2617 ) 2618 ) 2619 * 75(Net3094 xt "-90000,51000,-68000,51800" 3095 st "SIGNAL sclk : std_logic" 3096 ) 3097 ) 3098 *87 (Net 2620 3099 uid 384,0 2621 3100 decl (Decl … … 2632 3111 font "Courier New,8,0" 2633 3112 ) 2634 xt " 2000,34800,20000,35600"2635 st "SIGNAL sio : std_logic"2636 ) 2637 ) 2638 * 76(SaComponent3113 xt "-90000,52600,-68000,53400" 3114 st "SIGNAL sio : std_logic" 3115 ) 3116 ) 3117 *88 (SaComponent 2639 3118 uid 414,0 2640 3119 optionalChildren [ 2641 * 77(CptPort3120 *89 (CptPort 2642 3121 uid 410,0 2643 3122 ps "OnEdgeStrategy" … … 2694 3173 stg "VerticalLayoutStrategy" 2695 3174 textVec [ 2696 * 78(Text3175 *90 (Text 2697 3176 uid 417,0 2698 3177 va (VaSet … … 2704 3183 tm "BdLibraryNameMgr" 2705 3184 ) 2706 * 79(Text3185 *91 (Text 2707 3186 uid 418,0 2708 3187 va (VaSet … … 2714 3193 tm "CptNameMgr" 2715 3194 ) 2716 * 80(Text3195 *92 (Text 2717 3196 uid 419,0 2718 3197 va (VaSet … … 2774 3253 archFileType "UNKNOWN" 2775 3254 ) 2776 * 81(Net3255 *93 (Net 2777 3256 uid 424,0 2778 3257 decl (Decl … … 2789 3268 font "Courier New,8,0" 2790 3269 ) 2791 xt " 2000,35600,20000,36400"2792 st "SIGNAL trigger : std_logic"2793 ) 2794 ) 2795 * 82(HdlText3270 xt "-90000,53400,-68000,54200" 3271 st "SIGNAL trigger : std_logic" 3272 ) 3273 ) 3274 *94 (HdlText 2796 3275 uid 430,0 2797 3276 optionalChildren [ 2798 * 83(EmbeddedText3277 *95 (EmbeddedText 2799 3278 uid 436,0 2800 3279 commentText (CommentText … … 2847 3326 stg "VerticalLayoutStrategy" 2848 3327 textVec [ 2849 * 84(Text3328 *96 (Text 2850 3329 uid 433,0 2851 3330 va (VaSet … … 2857 3336 tm "HdlTextNameMgr" 2858 3337 ) 2859 * 85(Text3338 *97 (Text 2860 3339 uid 434,0 2861 3340 va (VaSet … … 2883 3362 viewiconposition 0 2884 3363 ) 2885 * 86(Net3364 *98 (Net 2886 3365 uid 440,0 2887 3366 decl (Decl … … 2899 3378 font "Courier New,8,0" 2900 3379 ) 2901 xt " 2000,26000,30000,26800"2902 st "SIGNAL board_id : std_logic_vector(3 downto 0)"2903 ) 2904 ) 2905 * 87(Net3380 xt "-90000,40600,-58500,41400" 3381 st "SIGNAL board_id : std_logic_vector(3 downto 0)" 3382 ) 3383 ) 3384 *99 (Net 2906 3385 uid 448,0 2907 3386 decl (Decl … … 2917 3396 font "Courier New,8,0" 2918 3397 ) 2919 xt " 2000,27600,30000,28400"2920 st "SIGNAL crate_id : std_logic_vector(1 downto 0)"2921 ) 2922 ) 2923 * 88(SaComponent3398 xt "-90000,43000,-58500,43800" 3399 st "SIGNAL crate_id : std_logic_vector(1 downto 0)" 3400 ) 3401 ) 3402 *100 (SaComponent 2924 3403 uid 508,0 2925 3404 optionalChildren [ 2926 * 89(CptPort3405 *101 (CptPort 2927 3406 uid 489,0 2928 3407 ps "OnEdgeStrategy" … … 2960 3439 ) 2961 3440 ) 2962 * 90(CptPort3441 *102 (CptPort 2963 3442 uid 493,0 2964 3443 ps "OnEdgeStrategy" … … 2999 3478 ) 3000 3479 ) 3001 * 91(CptPort3480 *103 (CptPort 3002 3481 uid 497,0 3003 3482 ps "OnEdgeStrategy" … … 3037 3516 ) 3038 3517 ) 3039 * 92(CptPort3518 *104 (CptPort 3040 3519 uid 501,0 3041 3520 ps "OnEdgeStrategy" … … 3091 3570 stg "VerticalLayoutStrategy" 3092 3571 textVec [ 3093 * 93(Text3572 *105 (Text 3094 3573 uid 511,0 3095 3574 va (VaSet … … 3101 3580 tm "BdLibraryNameMgr" 3102 3581 ) 3103 * 94(Text3582 *106 (Text 3104 3583 uid 512,0 3105 3584 va (VaSet … … 3111 3590 tm "CptNameMgr" 3112 3591 ) 3113 * 95(Text3592 *107 (Text 3114 3593 uid 513,0 3115 3594 va (VaSet … … 3165 3644 archFileType "UNKNOWN" 3166 3645 ) 3167 * 96(HdlText3646 *108 (HdlText 3168 3647 uid 518,0 3169 3648 optionalChildren [ 3170 * 97(EmbeddedText3649 *109 (EmbeddedText 3171 3650 uid 524,0 3172 3651 commentText (CommentText … … 3225 3704 stg "VerticalLayoutStrategy" 3226 3705 textVec [ 3227 * 98(Text3706 *110 (Text 3228 3707 uid 521,0 3229 3708 va (VaSet … … 3235 3714 tm "HdlTextNameMgr" 3236 3715 ) 3237 * 99(Text3716 *111 (Text 3238 3717 uid 522,0 3239 3718 va (VaSet … … 3261 3740 viewiconposition 0 3262 3741 ) 3263 *1 00(Net3742 *112 (Net 3264 3743 uid 528,0 3265 3744 decl (Decl … … 3275 3754 font "Courier New,8,0" 3276 3755 ) 3277 xt " 2000,25200,30000,26000"3278 st "SIGNAL adc_otr_array : std_logic_vector(3 DOWNTO 0)"3279 ) 3280 ) 3281 *1 01(Net3756 xt "-90000,37400,-58500,38200" 3757 st "SIGNAL adc_otr_array : std_logic_vector(3 DOWNTO 0)" 3758 ) 3759 ) 3760 *113 (Net 3282 3761 uid 536,0 3283 3762 decl (Decl … … 3292 3771 font "Courier New,8,0" 3293 3772 ) 3294 xt " 2000,22800,25500,23600"3295 st "SIGNAL adc_data_array : adc_data_array_type"3296 ) 3297 ) 3298 *1 02(Net3773 xt "-90000,35000,-63000,35800" 3774 st "SIGNAL adc_data_array : adc_data_array_type" 3775 ) 3776 ) 3777 *114 (Net 3299 3778 uid 544,0 3300 3779 decl (Decl … … 3311 3790 font "Courier New,8,0" 3312 3791 ) 3313 xt " 2000,23600,20000,24400"3314 st "SIGNAL adc_oeb : std_logic"3315 ) 3316 ) 3317 *1 03(Net3792 xt "-90000,35800,-68000,36600" 3793 st "SIGNAL adc_oeb : std_logic" 3794 ) 3795 ) 3796 *115 (Net 3318 3797 uid 560,0 3319 3798 decl (Decl … … 3330 3809 font "Courier New,8,0" 3331 3810 ) 3332 xt " 2000,24400,20000,25200"3333 st "SIGNAL adc_otr : STD_LOGIC"3334 ) 3335 ) 3336 *1 04(Net3811 xt "-90000,36600,-68000,37400" 3812 st "SIGNAL adc_otr : STD_LOGIC" 3813 ) 3814 ) 3815 *116 (Net 3337 3816 uid 568,0 3338 3817 decl (Decl … … 3350 3829 font "Courier New,8,0" 3351 3830 ) 3352 xt " 2000,22000,30500,22800"3353 st "SIGNAL adc_data : std_logic_vector(11 DOWNTO 0)"3354 ) 3355 ) 3356 *1 05(Net3831 xt "-90000,34200,-58000,35000" 3832 st "SIGNAL adc_data : std_logic_vector(11 DOWNTO 0)" 3833 ) 3834 ) 3835 *117 (Net 3357 3836 uid 767,0 3358 3837 decl (Decl … … 3368 3847 font "Courier New,8,0" 3369 3848 ) 3370 xt " 2000,40400,33500,41200"3371 st "SIGNAL wiz_reset : std_logic := '1'"3372 ) 3373 ) 3374 *1 06(Net3849 xt "-90000,58200,-55000,59000" 3850 st "SIGNAL wiz_reset : std_logic := '1'" 3851 ) 3852 ) 3853 *118 (Net 3375 3854 uid 775,0 3376 3855 decl (Decl … … 3388 3867 font "Courier New,8,0" 3389 3868 ) 3390 xt " 2000,31600,39500,32400"3391 st "SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')"3392 ) 3393 ) 3394 *1 07(Net3869 xt "-90000,47800,-49000,48600" 3870 st "SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')" 3871 ) 3872 ) 3873 *119 (Net 3395 3874 uid 783,0 3396 3875 decl (Decl … … 3406 3885 font "Courier New,8,0" 3407 3886 ) 3408 xt " 2000,37200,33500,38000"3409 st "SIGNAL wiz_cs : std_logic := '1'"3410 ) 3411 ) 3412 *1 08(Net3887 xt "-90000,55000,-55000,55800" 3888 st "SIGNAL wiz_cs : std_logic := '1'" 3889 ) 3890 ) 3891 *120 (Net 3413 3892 uid 791,0 3414 3893 decl (Decl … … 3423 3902 font "Courier New,8,0" 3424 3903 ) 3425 xt " 2000,38800,20000,39600"3426 st "SIGNAL wiz_int : std_logic"3427 ) 3428 ) 3429 *1 09(Net3904 xt "-90000,56600,-68000,57400" 3905 st "SIGNAL wiz_int : std_logic" 3906 ) 3907 ) 3908 *121 (Net 3430 3909 uid 799,0 3431 3910 decl (Decl … … 3440 3919 font "Courier New,8,0" 3441 3920 ) 3442 xt " 2000,28400,20000,29200"3443 st "SIGNAL dac_cs : std_logic"3444 ) 3445 ) 3446 *1 10(Net3921 xt "-90000,43800,-68000,44600" 3922 st "SIGNAL dac_cs : std_logic" 3923 ) 3924 ) 3925 *122 (Net 3447 3926 uid 807,0 3448 3927 decl (Decl … … 3458 3937 font "Courier New,8,0" 3459 3938 ) 3460 xt " 2000,32400,33500,33200"3461 st "SIGNAL mosi : std_logic := '0'"3462 ) 3463 ) 3464 *1 11(Net3939 xt "-90000,48600,-55000,49400" 3940 st "SIGNAL mosi : std_logic := '0'" 3941 ) 3942 ) 3943 *123 (Net 3465 3944 uid 815,0 3466 3945 decl (Decl … … 3478 3957 font "Courier New,8,0" 3479 3958 ) 3480 xt " 2000,29200,47000,30000"3481 st "SIGNAL denable : std_logic := '0' -- default domino wave off"3482 ) 3483 ) 3484 *1 12(Net3959 xt "-90000,44600,-41500,45400" 3960 st "SIGNAL denable : std_logic := '0' -- default domino wave off" 3961 ) 3962 ) 3963 *124 (Net 3485 3964 uid 823,0 3486 3965 decl (Decl … … 3495 3974 font "Courier New,8,0" 3496 3975 ) 3497 xt " 2000,15600,20000,16400"3498 st "SIGNAL CLK_25_PS : std_logic"3499 ) 3500 ) 3501 *1 13(Net3976 xt "-90000,25400,-68000,26200" 3977 st "SIGNAL CLK_25_PS : std_logic" 3978 ) 3979 ) 3980 *125 (Net 3502 3981 uid 831,0 3503 3982 decl (Decl … … 3512 3991 font "Courier New,8,0" 3513 3992 ) 3514 xt " 2000,16400,20000,17200"3515 st "SIGNAL CLK_50 : std_logic"3516 ) 3517 ) 3518 *1 14(Net3993 xt "-90000,26200,-68000,27000" 3994 st "SIGNAL CLK_50 : std_logic" 3995 ) 3996 ) 3997 *126 (Net 3519 3998 uid 839,0 3520 3999 decl (Decl … … 3531 4010 font "Courier New,8,0" 3532 4011 ) 3533 xt " 2000,30000,39500,30800"3534 st "SIGNAL drs_channel_id : std_logic_vector(3 downto 0) := (others => '0')"3535 ) 3536 ) 3537 *1 15(Net4012 xt "-90000,45400,-49000,46200" 4013 st "SIGNAL drs_channel_id : std_logic_vector(3 downto 0) := (others => '0')" 4014 ) 4015 ) 4016 *127 (Net 3538 4017 uid 847,0 3539 4018 decl (Decl … … 3549 4028 font "Courier New,8,0" 3550 4029 ) 3551 xt " 2000,30800,33500,31600"3552 st "SIGNAL drs_dwrite : std_logic := '1'"3553 ) 3554 ) 3555 *1 16(Net4030 xt "-90000,46200,-55000,47000" 4031 st "SIGNAL drs_dwrite : std_logic := '1'" 4032 ) 4033 ) 4034 *128 (Net 3556 4035 uid 855,0 3557 4036 decl (Decl … … 3567 4046 font "Courier New,8,0" 3568 4047 ) 3569 xt " 2000,17200,33500,18000"3570 st "SIGNAL RSRLOAD : std_logic := '0'"3571 ) 3572 ) 3573 *1 17(Net4048 xt "-90000,28600,-55000,29400" 4049 st "SIGNAL RSRLOAD : std_logic := '0'" 4050 ) 4051 ) 4052 *129 (Net 3574 4053 uid 863,0 3575 4054 decl (Decl … … 3585 4064 font "Courier New,8,0" 3586 4065 ) 3587 xt " 2000,18000,33500,18800"3588 st "SIGNAL SRCLK : std_logic := '0'"3589 ) 3590 ) 3591 *1 18(Net4066 xt "-90000,29400,-55000,30200" 4067 st "SIGNAL SRCLK : std_logic := '0'" 4068 ) 4069 ) 4070 *130 (Net 3592 4071 uid 871,0 3593 4072 decl (Decl … … 3602 4081 font "Courier New,8,0" 3603 4082 ) 3604 xt " 2000,18800,20000,19600"3605 st "SIGNAL SROUT_in_0 : std_logic"3606 ) 3607 ) 3608 *1 19(Net4083 xt "-90000,31000,-68000,31800" 4084 st "SIGNAL SROUT_in_0 : std_logic" 4085 ) 4086 ) 4087 *131 (Net 3609 4088 uid 879,0 3610 4089 decl (Decl … … 3619 4098 font "Courier New,8,0" 3620 4099 ) 3621 xt " 2000,19600,20000,20400"3622 st "SIGNAL SROUT_in_1 : std_logic"3623 ) 3624 ) 3625 *1 20(Net4100 xt "-90000,31800,-68000,32600" 4101 st "SIGNAL SROUT_in_1 : std_logic" 4102 ) 4103 ) 4104 *132 (Net 3626 4105 uid 887,0 3627 4106 decl (Decl … … 3636 4115 font "Courier New,8,0" 3637 4116 ) 3638 xt " 2000,20400,20000,21200"3639 st "SIGNAL SROUT_in_2 : std_logic"3640 ) 3641 ) 3642 *1 21(Net4117 xt "-90000,32600,-68000,33400" 4118 st "SIGNAL SROUT_in_2 : std_logic" 4119 ) 4120 ) 4121 *133 (Net 3643 4122 uid 895,0 3644 4123 decl (Decl … … 3653 4132 font "Courier New,8,0" 3654 4133 ) 3655 xt "2000,21200,20000,22000" 3656 st "SIGNAL SROUT_in_3 : std_logic" 3657 ) 3658 ) 3659 *122 (Wire 4134 xt "-90000,33400,-68000,34200" 4135 st "SIGNAL SROUT_in_3 : std_logic" 4136 ) 4137 ) 4138 *134 (Net 4139 uid 1435,0 4140 decl (Decl 4141 n "SRIN_out" 4142 t "std_logic" 4143 o 34 4144 suid 40,0 4145 i "'0'" 4146 ) 4147 declText (MLText 4148 uid 1436,0 4149 va (VaSet 4150 font "Courier New,8,0" 4151 ) 4152 xt "-90000,30200,-55000,31000" 4153 st "SIGNAL SRIN_out : std_logic := '0'" 4154 ) 4155 ) 4156 *135 (Net 4157 uid 1443,0 4158 decl (Decl 4159 n "amber" 4160 t "std_logic" 4161 o 35 4162 suid 41,0 4163 ) 4164 declText (MLText 4165 uid 1444,0 4166 va (VaSet 4167 font "Courier New,8,0" 4168 ) 4169 xt "-90000,39800,-68000,40600" 4170 st "SIGNAL amber : std_logic" 4171 ) 4172 ) 4173 *136 (Net 4174 uid 1451,0 4175 decl (Decl 4176 n "red" 4177 t "std_logic" 4178 o 36 4179 suid 42,0 4180 ) 4181 declText (MLText 4182 uid 1452,0 4183 va (VaSet 4184 font "Courier New,8,0" 4185 ) 4186 xt "-90000,50200,-68000,51000" 4187 st "SIGNAL red : std_logic" 4188 ) 4189 ) 4190 *137 (Net 4191 uid 1459,0 4192 decl (Decl 4193 n "green" 4194 t "std_logic" 4195 o 37 4196 suid 43,0 4197 ) 4198 declText (MLText 4199 uid 1460,0 4200 va (VaSet 4201 font "Courier New,8,0" 4202 ) 4203 xt "-90000,47000,-68000,47800" 4204 st "SIGNAL green : std_logic" 4205 ) 4206 ) 4207 *138 (Net 4208 uid 1467,0 4209 decl (Decl 4210 n "counter_result" 4211 t "std_logic_vector" 4212 b "(11 DOWNTO 0)" 4213 o 38 4214 suid 44,0 4215 ) 4216 declText (MLText 4217 uid 1468,0 4218 va (VaSet 4219 font "Courier New,8,0" 4220 ) 4221 xt "-90000,42200,-58000,43000" 4222 st "SIGNAL counter_result : std_logic_vector(11 DOWNTO 0)" 4223 ) 4224 ) 4225 *139 (Net 4226 uid 1475,0 4227 decl (Decl 4228 n "alarm_refclk_too_low" 4229 t "std_logic" 4230 posAdd 0 4231 o 39 4232 suid 45,0 4233 ) 4234 declText (MLText 4235 uid 1476,0 4236 va (VaSet 4237 font "Courier New,8,0" 4238 ) 4239 xt "-90000,39000,-68000,39800" 4240 st "SIGNAL alarm_refclk_too_low : std_logic" 4241 ) 4242 ) 4243 *140 (Net 4244 uid 1483,0 4245 decl (Decl 4246 n "alarm_refclk_too_high" 4247 t "std_logic" 4248 o 40 4249 suid 46,0 4250 ) 4251 declText (MLText 4252 uid 1484,0 4253 va (VaSet 4254 font "Courier New,8,0" 4255 ) 4256 xt "-90000,38200,-68000,39000" 4257 st "SIGNAL alarm_refclk_too_high : std_logic" 4258 ) 4259 ) 4260 *141 (HdlText 4261 uid 1491,0 4262 optionalChildren [ 4263 *142 (EmbeddedText 4264 uid 1497,0 4265 commentText (CommentText 4266 uid 1498,0 4267 ps "CenterOffsetStrategy" 4268 shape (Rectangle 4269 uid 1499,0 4270 va (VaSet 4271 vasetType 1 4272 fg "65535,65535,65535" 4273 lineColor "0,0,32768" 4274 lineWidth 2 4275 ) 4276 xt "27000,72000,41000,77000" 4277 ) 4278 oxt "0,0,18000,5000" 4279 text (MLText 4280 uid 1500,0 4281 va (VaSet 4282 ) 4283 xt "27200,72200,39400,77200" 4284 st " 4285 4286 D_T_in(1 downto 0) <= \"00\"; 4287 plllock_in(3 downto 0) <= \"1111\"; 4288 SROUT_in_0 <= '1'; 4289 SROUT_in_1 <= '0'; 4290 SROUT_in_2 <= '1'; 4291 SROUT_in_3 <= '0'; 4292 4293 " 4294 tm "HdlTextMgr" 4295 wrapOption 3 4296 visibleHeight 5000 4297 visibleWidth 14000 4298 ) 4299 ) 4300 ) 4301 ] 4302 shape (Rectangle 4303 uid 1492,0 4304 va (VaSet 4305 vasetType 1 4306 fg "65535,65535,37120" 4307 lineColor "0,0,32768" 4308 lineWidth 2 4309 ) 4310 xt "27000,69000,35000,72000" 4311 ) 4312 oxt "0,0,8000,10000" 4313 ttg (MlTextGroup 4314 uid 1493,0 4315 ps "CenterOffsetStrategy" 4316 stg "VerticalLayoutStrategy" 4317 textVec [ 4318 *143 (Text 4319 uid 1494,0 4320 va (VaSet 4321 font "Arial,8,1" 4322 ) 4323 xt "28150,69000,35250,70000" 4324 st "eb_mainTB_adc1" 4325 blo "28150,69800" 4326 tm "HdlTextNameMgr" 4327 ) 4328 *144 (Text 4329 uid 1495,0 4330 va (VaSet 4331 font "Arial,8,1" 4332 ) 4333 xt "28150,70000,28950,71000" 4334 st "3" 4335 blo "28150,70800" 4336 tm "HdlTextNumberMgr" 4337 ) 4338 ] 4339 ) 4340 viewicon (ZoomableIcon 4341 uid 1496,0 4342 sl 0 4343 va (VaSet 4344 vasetType 1 4345 fg "49152,49152,49152" 4346 ) 4347 xt "27250,70250,28750,71750" 4348 iconName "TextFile.png" 4349 iconMaskName "TextFile.msk" 4350 ftype 21 4351 ) 4352 viewiconposition 0 4353 ) 4354 *145 (Net 4355 uid 1501,0 4356 decl (Decl 4357 n "D_T_in" 4358 t "std_logic_vector" 4359 b "(1 DOWNTO 0)" 4360 o 41 4361 suid 47,0 4362 ) 4363 declText (MLText 4364 uid 1502,0 4365 va (VaSet 4366 font "Courier New,8,0" 4367 ) 4368 xt "-90000,27000,-58500,27800" 4369 st "SIGNAL D_T_in : std_logic_vector(1 DOWNTO 0)" 4370 ) 4371 ) 4372 *146 (SaComponent 4373 uid 1509,0 4374 optionalChildren [ 4375 *147 (CptPort 4376 uid 1519,0 4377 ps "OnEdgeStrategy" 4378 shape (Triangle 4379 uid 1520,0 4380 ro 90 4381 va (VaSet 4382 vasetType 1 4383 fg "0,65535,0" 4384 ) 4385 xt "66000,78625,66750,79375" 4386 ) 4387 tg (CPTG 4388 uid 1521,0 4389 ps "CptPortTextPlaceStrategy" 4390 stg "RightVerticalLayoutStrategy" 4391 f (Text 4392 uid 1522,0 4393 va (VaSet 4394 ) 4395 xt "63700,78500,65000,79500" 4396 st "clk" 4397 ju 2 4398 blo "65000,79300" 4399 ) 4400 ) 4401 thePort (LogicalPort 4402 m 1 4403 decl (Decl 4404 n "clk" 4405 t "STD_LOGIC" 4406 o 1 4407 i "'0'" 4408 ) 4409 ) 4410 ) 4411 *148 (CptPort 4412 uid 1523,0 4413 ps "OnEdgeStrategy" 4414 shape (Triangle 4415 uid 1524,0 4416 ro 90 4417 va (VaSet 4418 vasetType 1 4419 fg "0,65535,0" 4420 ) 4421 xt "66000,79625,66750,80375" 4422 ) 4423 tg (CPTG 4424 uid 1525,0 4425 ps "CptPortTextPlaceStrategy" 4426 stg "RightVerticalLayoutStrategy" 4427 f (Text 4428 uid 1526,0 4429 va (VaSet 4430 ) 4431 xt "63700,79500,65000,80500" 4432 st "rst" 4433 ju 2 4434 blo "65000,80300" 4435 ) 4436 ) 4437 thePort (LogicalPort 4438 m 1 4439 decl (Decl 4440 n "rst" 4441 t "STD_LOGIC" 4442 o 2 4443 i "'0'" 4444 ) 4445 ) 4446 ) 4447 ] 4448 shape (Rectangle 4449 uid 1510,0 4450 va (VaSet 4451 vasetType 1 4452 fg "0,49152,49152" 4453 lineColor "0,0,50000" 4454 lineWidth 2 4455 ) 4456 xt "55000,77000,66000,82000" 4457 ) 4458 oxt "0,0,8000,10000" 4459 ttg (MlTextGroup 4460 uid 1511,0 4461 ps "CenterOffsetStrategy" 4462 stg "VerticalLayoutStrategy" 4463 textVec [ 4464 *149 (Text 4465 uid 1512,0 4466 va (VaSet 4467 font "Arial,8,1" 4468 ) 4469 xt "56150,78000,63850,79000" 4470 st "FACT_FAD_TB_lib" 4471 blo "56150,78800" 4472 tm "BdLibraryNameMgr" 4473 ) 4474 *150 (Text 4475 uid 1513,0 4476 va (VaSet 4477 font "Arial,8,1" 4478 ) 4479 xt "56150,79000,62850,80000" 4480 st "clock_generator" 4481 blo "56150,79800" 4482 tm "CptNameMgr" 4483 ) 4484 *151 (Text 4485 uid 1514,0 4486 va (VaSet 4487 font "Arial,8,1" 4488 ) 4489 xt "56150,80000,63150,81000" 4490 st "I_mainTB_clock1" 4491 blo "56150,80800" 4492 tm "InstanceNameMgr" 4493 ) 4494 ] 4495 ) 4496 ga (GenericAssociation 4497 uid 1515,0 4498 ps "EdgeToEdgeStrategy" 4499 matrix (Matrix 4500 uid 1516,0 4501 text (MLText 4502 uid 1517,0 4503 va (VaSet 4504 font "Courier New,8,0" 4505 ) 4506 xt "55000,82400,73000,84000" 4507 st "clock_period = 1 us ( time ) 4508 reset_time = 1 us ( time ) " 4509 ) 4510 header "" 4511 ) 4512 elements [ 4513 (GiElement 4514 name "clock_period" 4515 type "time" 4516 value "1 us" 4517 ) 4518 (GiElement 4519 name "reset_time" 4520 type "time" 4521 value "1 us" 4522 ) 4523 ] 4524 ) 4525 viewicon (ZoomableIcon 4526 uid 1518,0 4527 sl 0 4528 va (VaSet 4529 vasetType 1 4530 fg "49152,49152,49152" 4531 ) 4532 xt "55250,80250,56750,81750" 4533 iconName "VhdlFileViewIcon.png" 4534 iconMaskName "VhdlFileViewIcon.msk" 4535 ftype 10 4536 ) 4537 ordering 1 4538 viewiconposition 0 4539 portVis (PortSigDisplay 4540 ) 4541 archFileType "UNKNOWN" 4542 ) 4543 *152 (Net 4544 uid 1559,0 4545 decl (Decl 4546 n "plllock_in" 4547 t "std_logic_vector" 4548 b "(3 DOWNTO 0)" 4549 eolc "-- high level, if dominowave is running and DRS PLL locked" 4550 o 43 4551 suid 49,0 4552 ) 4553 declText (MLText 4554 uid 1560,0 4555 va (VaSet 4556 font "Courier New,8,0" 4557 ) 4558 xt "-90000,49400,-29000,50200" 4559 st "SIGNAL plllock_in : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked" 4560 ) 4561 ) 4562 *153 (Net 4563 uid 1682,0 4564 lang 2 4565 decl (Decl 4566 n "ADC_CLK" 4567 t "std_logic" 4568 o 44 4569 suid 50,0 4570 ) 4571 declText (MLText 4572 uid 1683,0 4573 va (VaSet 4574 font "Courier New,8,0" 4575 ) 4576 xt "-90000,24600,-68000,25400" 4577 st "SIGNAL ADC_CLK : std_logic" 4578 ) 4579 ) 4580 *154 (Net 4581 uid 2001,0 4582 decl (Decl 4583 n "REF_CLK" 4584 t "STD_LOGIC" 4585 o 42 4586 suid 51,0 4587 i "'0'" 4588 ) 4589 declText (MLText 4590 uid 2002,0 4591 va (VaSet 4592 font "Courier New,8,0" 4593 ) 4594 xt "-90000,27800,-55000,28600" 4595 st "SIGNAL REF_CLK : STD_LOGIC := '0'" 4596 ) 4597 ) 4598 *155 (Wire 3660 4599 uid 286,0 3661 4600 shape (OrthoPolyLine … … 3670 4609 ] 3671 4610 ) 3672 start & 484611 start &59 3673 4612 end &27 3674 4613 sat 32 … … 3691 4630 ) 3692 4631 ) 3693 on & 533694 ) 3695 *1 23(Wire4632 on &64 4633 ) 4634 *156 (Wire 3696 4635 uid 318,0 3697 4636 shape (OrthoPolyLine … … 3708 4647 ) 3709 4648 start &19 3710 end & 554649 end &66 3711 4650 sat 32 3712 4651 eat 32 … … 3729 4668 ) 3730 4669 ) 3731 on & 623732 ) 3733 *1 24(Wire4670 on &74 4671 ) 4672 *157 (Wire 3734 4673 uid 324,0 3735 4674 shape (OrthoPolyLine … … 3746 4685 ) 3747 4686 start &20 3748 end & 564687 end &67 3749 4688 sat 32 3750 4689 eat 32 … … 3767 4706 ) 3768 4707 ) 3769 on & 633770 ) 3771 *1 25(Wire4708 on &75 4709 ) 4710 *158 (Wire 3772 4711 uid 330,0 3773 4712 shape (OrthoPolyLine … … 3783 4722 ) 3784 4723 start &23 3785 end & 574724 end &68 3786 4725 sat 32 3787 4726 eat 32 … … 3803 4742 ) 3804 4743 ) 3805 on & 643806 ) 3807 *1 26(Wire4744 on &76 4745 ) 4746 *159 (Wire 3808 4747 uid 336,0 3809 4748 shape (OrthoPolyLine … … 3819 4758 ) 3820 4759 start &22 3821 end & 584760 end &69 3822 4761 sat 32 3823 4762 eat 32 … … 3839 4778 ) 3840 4779 ) 3841 on & 653842 ) 3843 *1 27(Wire4780 on &77 4781 ) 4782 *160 (Wire 3844 4783 uid 374,0 3845 4784 shape (OrthoPolyLine … … 3858 4797 ) 3859 4798 start &41 3860 end & 694799 end &81 3861 4800 sat 32 3862 4801 eat 32 … … 3879 4818 ) 3880 4819 ) 3881 on & 733882 ) 3883 *1 28(Wire4820 on &85 4821 ) 4822 *161 (Wire 3884 4823 uid 380,0 3885 4824 shape (OrthoPolyLine … … 3895 4834 ) 3896 4835 start &38 3897 end & 674836 end &79 3898 4837 sat 32 3899 4838 eat 32 … … 3915 4854 ) 3916 4855 ) 3917 on & 743918 ) 3919 *1 29(Wire4856 on &86 4857 ) 4858 *162 (Wire 3920 4859 uid 386,0 3921 4860 shape (OrthoPolyLine … … 3931 4870 ) 3932 4871 start &39 3933 end & 684872 end &80 3934 4873 sat 32 3935 4874 eat 32 … … 3951 4890 ) 3952 4891 ) 3953 on & 753954 ) 3955 *1 30(Wire4892 on &87 4893 ) 4894 *163 (Wire 3956 4895 uid 426,0 3957 4896 shape (OrthoPolyLine … … 3966 4905 ] 3967 4906 ) 3968 start & 774907 start &89 3969 4908 end &15 3970 4909 sat 32 … … 3986 4925 ) 3987 4926 ) 3988 on & 813989 ) 3990 *1 31(Wire4927 on &93 4928 ) 4929 *164 (Wire 3991 4930 uid 442,0 3992 4931 shape (OrthoPolyLine … … 4005 4944 ) 4006 4945 start &17 4007 end & 824946 end &94 4008 4947 sat 32 4009 4948 eat 2 … … 4026 4965 ) 4027 4966 ) 4028 on & 864029 ) 4030 *1 32(Wire4967 on &98 4968 ) 4969 *165 (Wire 4031 4970 uid 450,0 4032 4971 shape (OrthoPolyLine … … 4045 4984 ) 4046 4985 start &18 4047 end & 824986 end &94 4048 4987 sat 32 4049 4988 eat 2 … … 4066 5005 ) 4067 5006 ) 4068 on & 874069 ) 4070 *1 33(Wire5007 on &99 5008 ) 5009 *166 (Wire 4071 5010 uid 530,0 4072 5011 shape (OrthoPolyLine … … 4085 5024 ) 4086 5025 start &28 4087 end & 965026 end &108 4088 5027 sat 32 4089 5028 eat 2 … … 4106 5045 ) 4107 5046 ) 4108 on &1 004109 ) 4110 *1 34(Wire5047 on &112 5048 ) 5049 *167 (Wire 4111 5050 uid 538,0 4112 5051 shape (OrthoPolyLine … … 4125 5064 ) 4126 5065 start &29 4127 end & 965066 end &108 4128 5067 sat 32 4129 5068 eat 2 … … 4146 5085 ) 4147 5086 ) 4148 on &1 014149 ) 4150 *1 35(Wire5087 on &113 5088 ) 5089 *168 (Wire 4151 5090 uid 546,0 4152 5091 shape (OrthoPolyLine … … 4164 5103 ) 4165 5104 start &16 4166 end & 965105 end &108 4167 5106 sat 32 4168 5107 eat 1 … … 4184 5123 ) 4185 5124 ) 4186 on &1 024187 ) 4188 *1 36(Wire5125 on &114 5126 ) 5127 *169 (Wire 4189 5128 uid 554,0 4190 5129 shape (OrthoPolyLine … … 4199 5138 ] 4200 5139 ) 4201 start & 964202 end & 925140 start &108 5141 end &104 4203 5142 sat 2 4204 5143 eat 32 … … 4219 5158 ) 4220 5159 ) 4221 on &1 024222 ) 4223 *1 37(Wire5160 on &114 5161 ) 5162 *170 (Wire 4224 5163 uid 562,0 4225 5164 shape (OrthoPolyLine … … 4234 5173 ] 4235 5174 ) 4236 start & 914237 end & 965175 start &103 5176 end &108 4238 5177 sat 32 4239 5178 eat 1 … … 4254 5193 ) 4255 5194 ) 4256 on &1 034257 ) 4258 *1 38(Wire5195 on &115 5196 ) 5197 *171 (Wire 4259 5198 uid 570,0 4260 5199 shape (OrthoPolyLine … … 4270 5209 ] 4271 5210 ) 4272 start & 904273 end & 965211 start &102 5212 end &108 4274 5213 sat 32 4275 5214 eat 1 … … 4291 5230 ) 4292 5231 ) 4293 on &1 044294 ) 4295 *1 39(Wire5232 on &116 5233 ) 5234 *172 (Wire 4296 5235 uid 578,0 4297 5236 shape (OrthoPolyLine … … 4300 5239 vasetType 3 4301 5240 ) 4302 xt "2 5000,53000,29250,53000"5241 xt "24000,53000,29250,53000" 4303 5242 pts [ 4304 5243 "29250,53000" 4305 "2 5000,53000"4306 ] 4307 ) 4308 start & 895244 "24000,53000" 5245 ] 5246 ) 5247 start &101 4309 5248 sat 32 4310 5249 eat 16 … … 4319 5258 va (VaSet 4320 5259 ) 4321 xt "2 6250,52000,27550,53000"4322 st " clk"4323 blo "2 6250,52800"5260 xt "25000,52000,29000,53000" 5261 st "ADC_CLK" 5262 blo "25000,52800" 4324 5263 tm "WireNameMgr" 4325 5264 ) 4326 5265 ) 4327 on & 534328 ) 4329 *1 40(Wire5266 on &153 5267 ) 5268 *173 (Wire 4330 5269 uid 769,0 4331 5270 shape (OrthoPolyLine … … 4360 5299 ) 4361 5300 ) 4362 on &1 054363 ) 4364 *1 41(Wire5301 on &117 5302 ) 5303 *174 (Wire 4365 5304 uid 777,0 4366 5305 shape (OrthoPolyLine … … 4397 5336 ) 4398 5337 ) 4399 on &1 064400 ) 4401 *1 42(Wire5338 on &118 5339 ) 5340 *175 (Wire 4402 5341 uid 785,0 4403 5342 shape (OrthoPolyLine … … 4432 5371 ) 4433 5372 ) 4434 on &1 074435 ) 4436 *1 43(Wire5373 on &119 5374 ) 5375 *176 (Wire 4437 5376 uid 793,0 4438 5377 shape (OrthoPolyLine … … 4441 5380 vasetType 3 4442 5381 ) 4443 xt "109750,27000,1 16000,27000"5382 xt "109750,27000,122250,27000" 4444 5383 pts [ 4445 "1 16000,27000"5384 "122250,27000" 4446 5385 "109750,27000" 4447 5386 ] 4448 5387 ) 5388 start &70 4449 5389 end &24 4450 sat 16 5390 ss 0 5391 sat 32 4451 5392 eat 32 4452 5393 st 0 … … 4467 5408 ) 4468 5409 ) 4469 on &1 084470 ) 4471 *1 44(Wire5410 on &120 5411 ) 5412 *177 (Wire 4472 5413 uid 801,0 4473 5414 shape (OrthoPolyLine … … 4502 5443 ) 4503 5444 ) 4504 on &1 094505 ) 4506 *1 45(Wire5445 on &121 5446 ) 5447 *178 (Wire 4507 5448 uid 809,0 4508 5449 shape (OrthoPolyLine … … 4537 5478 ) 4538 5479 ) 4539 on &1 104540 ) 4541 *1 46(Wire5480 on &122 5481 ) 5482 *179 (Wire 4542 5483 uid 817,0 4543 5484 shape (OrthoPolyLine … … 4572 5513 ) 4573 5514 ) 4574 on &1 114575 ) 4576 *1 47(Wire5515 on &123 5516 ) 5517 *180 (Wire 4577 5518 uid 825,0 4578 5519 shape (OrthoPolyLine … … 4607 5548 ) 4608 5549 ) 4609 on &1 124610 ) 4611 *1 48(Wire5550 on &124 5551 ) 5552 *181 (Wire 4612 5553 uid 833,0 4613 5554 shape (OrthoPolyLine … … 4642 5583 ) 4643 5584 ) 4644 on &1 134645 ) 4646 *1 49(Wire5585 on &125 5586 ) 5587 *182 (Wire 4647 5588 uid 841,0 4648 5589 shape (OrthoPolyLine … … 4679 5620 ) 4680 5621 ) 4681 on &1 144682 ) 4683 *1 50(Wire5622 on &126 5623 ) 5624 *183 (Wire 4684 5625 uid 849,0 4685 5626 shape (OrthoPolyLine … … 4714 5655 ) 4715 5656 ) 4716 on &1 154717 ) 4718 *1 51(Wire5657 on &127 5658 ) 5659 *184 (Wire 4719 5660 uid 857,0 4720 5661 shape (OrthoPolyLine … … 4749 5690 ) 4750 5691 ) 4751 on &1 164752 ) 4753 *1 52(Wire5692 on &128 5693 ) 5694 *185 (Wire 4754 5695 uid 865,0 4755 5696 shape (OrthoPolyLine … … 4784 5725 ) 4785 5726 ) 4786 on &1 174787 ) 4788 *1 53(Wire5727 on &129 5728 ) 5729 *186 (Wire 4789 5730 uid 873,0 4790 5731 shape (OrthoPolyLine … … 4819 5760 ) 4820 5761 ) 4821 on &1 184822 ) 4823 *1 54(Wire5762 on &130 5763 ) 5764 *187 (Wire 4824 5765 uid 881,0 4825 5766 shape (OrthoPolyLine … … 4854 5795 ) 4855 5796 ) 4856 on &1 194857 ) 4858 *1 55(Wire5797 on &131 5798 ) 5799 *188 (Wire 4859 5800 uid 889,0 4860 5801 shape (OrthoPolyLine … … 4889 5830 ) 4890 5831 ) 4891 on &1 204892 ) 4893 *1 56(Wire5832 on &132 5833 ) 5834 *189 (Wire 4894 5835 uid 897,0 4895 5836 shape (OrthoPolyLine … … 4924 5865 ) 4925 5866 ) 4926 on &121 5867 on &133 5868 ) 5869 *190 (Wire 5870 uid 1437,0 5871 shape (OrthoPolyLine 5872 uid 1438,0 5873 va (VaSet 5874 vasetType 3 5875 ) 5876 xt "73000,72000,80250,72000" 5877 pts [ 5878 "80250,72000" 5879 "73000,72000" 5880 ] 5881 ) 5882 start &53 5883 sat 32 5884 eat 16 5885 st 0 5886 sf 1 5887 si 0 5888 tg (WTG 5889 uid 1441,0 5890 ps "ConnStartEndStrategy" 5891 stg "STSignalDisplayStrategy" 5892 f (Text 5893 uid 1442,0 5894 va (VaSet 5895 ) 5896 xt "76000,72000,79700,73000" 5897 st "SRIN_out" 5898 blo "76000,72800" 5899 tm "WireNameMgr" 5900 ) 5901 ) 5902 on &134 5903 ) 5904 *191 (Wire 5905 uid 1445,0 5906 shape (OrthoPolyLine 5907 uid 1446,0 5908 va (VaSet 5909 vasetType 3 5910 ) 5911 xt "109750,80000,115000,80000" 5912 pts [ 5913 "109750,80000" 5914 "115000,80000" 5915 ] 5916 ) 5917 start &46 5918 sat 32 5919 eat 16 5920 st 0 5921 sf 1 5922 si 0 5923 tg (WTG 5924 uid 1449,0 5925 ps "ConnStartEndStrategy" 5926 stg "STSignalDisplayStrategy" 5927 f (Text 5928 uid 1450,0 5929 va (VaSet 5930 ) 5931 xt "111000,79000,113500,80000" 5932 st "amber" 5933 blo "111000,79800" 5934 tm "WireNameMgr" 5935 ) 5936 ) 5937 on &135 5938 ) 5939 *192 (Wire 5940 uid 1453,0 5941 shape (OrthoPolyLine 5942 uid 1454,0 5943 va (VaSet 5944 vasetType 3 5945 ) 5946 xt "109750,79000,114000,79000" 5947 pts [ 5948 "109750,79000" 5949 "114000,79000" 5950 ] 5951 ) 5952 start &52 5953 sat 32 5954 eat 16 5955 st 0 5956 sf 1 5957 si 0 5958 tg (WTG 5959 uid 1457,0 5960 ps "ConnStartEndStrategy" 5961 stg "STSignalDisplayStrategy" 5962 f (Text 5963 uid 1458,0 5964 va (VaSet 5965 ) 5966 xt "111000,78000,112500,79000" 5967 st "red" 5968 blo "111000,78800" 5969 tm "WireNameMgr" 5970 ) 5971 ) 5972 on &136 5973 ) 5974 *193 (Wire 5975 uid 1461,0 5976 shape (OrthoPolyLine 5977 uid 1462,0 5978 va (VaSet 5979 vasetType 3 5980 ) 5981 xt "109750,78000,114000,78000" 5982 pts [ 5983 "109750,78000" 5984 "114000,78000" 5985 ] 5986 ) 5987 start &50 5988 sat 32 5989 eat 16 5990 st 0 5991 sf 1 5992 si 0 5993 tg (WTG 5994 uid 1465,0 5995 ps "ConnStartEndStrategy" 5996 stg "STSignalDisplayStrategy" 5997 f (Text 5998 uid 1466,0 5999 va (VaSet 6000 ) 6001 xt "111000,77000,113400,78000" 6002 st "green" 6003 blo "111000,77800" 6004 tm "WireNameMgr" 6005 ) 6006 ) 6007 on &137 6008 ) 6009 *194 (Wire 6010 uid 1469,0 6011 shape (OrthoPolyLine 6012 uid 1470,0 6013 va (VaSet 6014 vasetType 3 6015 lineWidth 2 6016 ) 6017 xt "109750,77000,121000,77000" 6018 pts [ 6019 "109750,77000" 6020 "121000,77000" 6021 ] 6022 ) 6023 start &47 6024 sat 32 6025 eat 16 6026 sty 1 6027 st 0 6028 sf 1 6029 si 0 6030 tg (WTG 6031 uid 1473,0 6032 ps "ConnStartEndStrategy" 6033 stg "STSignalDisplayStrategy" 6034 f (Text 6035 uid 1474,0 6036 va (VaSet 6037 ) 6038 xt "111000,76000,119600,77000" 6039 st "counter_result : (11:0)" 6040 blo "111000,76800" 6041 tm "WireNameMgr" 6042 ) 6043 ) 6044 on &138 6045 ) 6046 *195 (Wire 6047 uid 1477,0 6048 shape (OrthoPolyLine 6049 uid 1478,0 6050 va (VaSet 6051 vasetType 3 6052 ) 6053 xt "109750,75000,120000,75000" 6054 pts [ 6055 "109750,75000" 6056 "120000,75000" 6057 ] 6058 ) 6059 start &45 6060 sat 32 6061 eat 16 6062 st 0 6063 sf 1 6064 si 0 6065 tg (WTG 6066 uid 1481,0 6067 ps "ConnStartEndStrategy" 6068 stg "STSignalDisplayStrategy" 6069 f (Text 6070 uid 1482,0 6071 va (VaSet 6072 ) 6073 xt "111000,74000,119200,75000" 6074 st "alarm_refclk_too_low" 6075 blo "111000,74800" 6076 tm "WireNameMgr" 6077 ) 6078 ) 6079 on &139 6080 ) 6081 *196 (Wire 6082 uid 1485,0 6083 shape (OrthoPolyLine 6084 uid 1486,0 6085 va (VaSet 6086 vasetType 3 6087 ) 6088 xt "109750,74000,121000,74000" 6089 pts [ 6090 "109750,74000" 6091 "121000,74000" 6092 ] 6093 ) 6094 start &44 6095 sat 32 6096 eat 16 6097 st 0 6098 sf 1 6099 si 0 6100 tg (WTG 6101 uid 1489,0 6102 ps "ConnStartEndStrategy" 6103 stg "STSignalDisplayStrategy" 6104 f (Text 6105 uid 1490,0 6106 va (VaSet 6107 ) 6108 xt "111000,73000,119600,74000" 6109 st "alarm_refclk_too_high" 6110 blo "111000,73800" 6111 tm "WireNameMgr" 6112 ) 6113 ) 6114 on &140 6115 ) 6116 *197 (Wire 6117 uid 1503,0 6118 shape (OrthoPolyLine 6119 uid 1504,0 6120 va (VaSet 6121 vasetType 3 6122 lineWidth 2 6123 ) 6124 xt "73000,75000,80250,75000" 6125 pts [ 6126 "73000,75000" 6127 "80250,75000" 6128 ] 6129 ) 6130 end &48 6131 sat 16 6132 eat 32 6133 sty 1 6134 st 0 6135 sf 1 6136 si 0 6137 tg (WTG 6138 uid 1507,0 6139 ps "ConnStartEndStrategy" 6140 stg "STSignalDisplayStrategy" 6141 f (Text 6142 uid 1508,0 6143 va (VaSet 6144 ) 6145 xt "74000,74000,79500,75000" 6146 st "D_T_in : (1:0)" 6147 blo "74000,74800" 6148 tm "WireNameMgr" 6149 ) 6150 ) 6151 on &145 6152 ) 6153 *198 (Wire 6154 uid 1529,0 6155 shape (OrthoPolyLine 6156 uid 1530,0 6157 va (VaSet 6158 vasetType 3 6159 ) 6160 xt "66750,76000,80250,79000" 6161 pts [ 6162 "66750,79000" 6163 "70000,79000" 6164 "70000,76000" 6165 "80250,76000" 6166 ] 6167 ) 6168 start &147 6169 end &49 6170 sat 32 6171 eat 32 6172 st 0 6173 sf 1 6174 si 0 6175 tg (WTG 6176 uid 1531,0 6177 ps "ConnStartEndStrategy" 6178 stg "STSignalDisplayStrategy" 6179 f (Text 6180 uid 1532,0 6181 va (VaSet 6182 ) 6183 xt "68750,78000,72650,79000" 6184 st "REF_CLK" 6185 blo "68750,78800" 6186 tm "WireNameMgr" 6187 ) 6188 ) 6189 on &154 6190 ) 6191 *199 (Wire 6192 uid 1533,0 6193 shape (OrthoPolyLine 6194 uid 1534,0 6195 va (VaSet 6196 vasetType 3 6197 ) 6198 xt "35000,70000,45000,70000" 6199 pts [ 6200 "35000,70000" 6201 "45000,70000" 6202 ] 6203 ) 6204 start &141 6205 sat 2 6206 eat 16 6207 st 0 6208 sf 1 6209 si 0 6210 tg (WTG 6211 uid 1539,0 6212 ps "ConnStartEndStrategy" 6213 stg "STSignalDisplayStrategy" 6214 f (Text 6215 uid 1540,0 6216 va (VaSet 6217 ) 6218 xt "37000,69000,42500,70000" 6219 st "D_T_in : (1:0)" 6220 blo "37000,69800" 6221 tm "WireNameMgr" 6222 ) 6223 ) 6224 on &145 6225 ) 6226 *200 (Wire 6227 uid 1561,0 6228 shape (OrthoPolyLine 6229 uid 1562,0 6230 va (VaSet 6231 vasetType 3 6232 lineWidth 2 6233 ) 6234 xt "72000,77000,80250,77000" 6235 pts [ 6236 "72000,77000" 6237 "80250,77000" 6238 ] 6239 ) 6240 end &51 6241 sat 16 6242 eat 32 6243 sty 1 6244 st 0 6245 sf 1 6246 si 0 6247 tg (WTG 6248 uid 1565,0 6249 ps "ConnStartEndStrategy" 6250 stg "STSignalDisplayStrategy" 6251 f (Text 6252 uid 1566,0 6253 va (VaSet 6254 ) 6255 xt "73000,76000,79100,77000" 6256 st "plllock_in : (3:0)" 6257 blo "73000,76800" 6258 tm "WireNameMgr" 6259 ) 6260 ) 6261 on &152 6262 ) 6263 *201 (Wire 6264 uid 1567,0 6265 shape (OrthoPolyLine 6266 uid 1568,0 6267 va (VaSet 6268 vasetType 3 6269 ) 6270 xt "35000,71000,45000,71000" 6271 pts [ 6272 "35000,71000" 6273 "45000,71000" 6274 ] 6275 ) 6276 start &141 6277 sat 2 6278 eat 16 6279 st 0 6280 sf 1 6281 si 0 6282 tg (WTG 6283 uid 1573,0 6284 ps "ConnStartEndStrategy" 6285 stg "STSignalDisplayStrategy" 6286 f (Text 6287 uid 1574,0 6288 va (VaSet 6289 ) 6290 xt "37000,70000,43100,71000" 6291 st "plllock_in : (3:0)" 6292 blo "37000,70800" 6293 tm "WireNameMgr" 6294 ) 6295 ) 6296 on &152 6297 ) 6298 *202 (Wire 6299 uid 1684,0 6300 shape (OrthoPolyLine 6301 uid 1685,0 6302 va (VaSet 6303 vasetType 3 6304 ) 6305 xt "70000,24000,80250,24000" 6306 pts [ 6307 "80250,24000" 6308 "70000,24000" 6309 ] 6310 ) 6311 start &54 6312 sat 32 6313 eat 16 6314 st 0 6315 sf 1 6316 si 0 6317 tg (WTG 6318 uid 1688,0 6319 ps "ConnStartEndStrategy" 6320 stg "STSignalDisplayStrategy" 6321 f (Text 6322 uid 1689,0 6323 va (VaSet 6324 ) 6325 xt "71000,23000,75000,24000" 6326 st "ADC_CLK" 6327 blo "71000,23800" 6328 tm "WireNameMgr" 6329 ) 6330 ) 6331 on &153 4927 6332 ) 4928 6333 ] … … 4938 6343 color "26368,26368,26368" 4939 6344 ) 4940 packageList * 157(PackageList6345 packageList *203 (PackageList 4941 6346 uid 41,0 4942 6347 stg "VerticalLayoutStrategy" 4943 6348 textVec [ 4944 * 158(Text6349 *204 (Text 4945 6350 uid 42,0 4946 6351 va (VaSet 4947 6352 font "arial,8,1" 4948 6353 ) 4949 xt " 0,0,5400,1000"6354 xt "-87000,0,-81600,1000" 4950 6355 st "Package List" 4951 blo " 0,800"4952 ) 4953 * 159(MLText6356 blo "-87000,800" 6357 ) 6358 *205 (MLText 4954 6359 uid 43,0 4955 6360 va (VaSet 4956 6361 ) 4957 xt " 0,1000,14500,11000"6362 xt "-87000,1000,-72500,11000" 4958 6363 st "LIBRARY ieee; 4959 6364 USE ieee.std_logic_1164.all; … … 4974 6379 stg "VerticalLayoutStrategy" 4975 6380 textVec [ 4976 * 160(Text6381 *206 (Text 4977 6382 uid 45,0 4978 6383 va (VaSet … … 4984 6389 blo "20000,800" 4985 6390 ) 4986 * 161(Text6391 *207 (Text 4987 6392 uid 46,0 4988 6393 va (VaSet … … 4994 6399 blo "20000,1800" 4995 6400 ) 4996 * 162(MLText6401 *208 (MLText 4997 6402 uid 47,0 4998 6403 va (VaSet … … 5004 6409 tm "BdCompilerDirectivesTextMgr" 5005 6410 ) 5006 * 163(Text6411 *209 (Text 5007 6412 uid 48,0 5008 6413 va (VaSet … … 5014 6419 blo "20000,4800" 5015 6420 ) 5016 * 164(MLText6421 *210 (MLText 5017 6422 uid 49,0 5018 6423 va (VaSet … … 5022 6427 tm "BdCompilerDirectivesTextMgr" 5023 6428 ) 5024 * 165(Text6429 *211 (Text 5025 6430 uid 50,0 5026 6431 va (VaSet … … 5032 6437 blo "20000,5800" 5033 6438 ) 5034 * 166(MLText6439 *212 (MLText 5035 6440 uid 51,0 5036 6441 va (VaSet … … 5044 6449 ) 5045 6450 windowSize "0,22,1281,1024" 5046 viewArea "691 21,10359,152940,73480"5047 cachedDiagramExtent " 0,0,146000,98000"6451 viewArea "69170,4172,136013,56147" 6452 cachedDiagramExtent "-92000,0,146000,98000" 5048 6453 pageSetupInfo (PageSetupInfo 5049 6454 ptrCmd "" … … 5056 6461 ) 5057 6462 hasePageBreakOrigin 1 5058 pageBreakOrigin " 0,0"5059 lastUid 1311,06463 pageBreakOrigin "-146000,0" 6464 lastUid 2112,0 5060 6465 defaultCommentText (CommentText 5061 6466 shape (Rectangle … … 5119 6524 stg "VerticalLayoutStrategy" 5120 6525 textVec [ 5121 * 167(Text6526 *213 (Text 5122 6527 va (VaSet 5123 6528 font "Arial,8,1" … … 5128 6533 tm "BdLibraryNameMgr" 5129 6534 ) 5130 * 168(Text6535 *214 (Text 5131 6536 va (VaSet 5132 6537 font "Arial,8,1" … … 5137 6542 tm "BlkNameMgr" 5138 6543 ) 5139 * 169(Text6544 *215 (Text 5140 6545 va (VaSet 5141 6546 font "Arial,8,1" … … 5188 6593 stg "VerticalLayoutStrategy" 5189 6594 textVec [ 5190 * 170(Text6595 *216 (Text 5191 6596 va (VaSet 5192 6597 font "Arial,8,1" … … 5196 6601 blo "550,4300" 5197 6602 ) 5198 * 171(Text6603 *217 (Text 5199 6604 va (VaSet 5200 6605 font "Arial,8,1" … … 5204 6609 blo "550,5300" 5205 6610 ) 5206 * 172(Text6611 *218 (Text 5207 6612 va (VaSet 5208 6613 font "Arial,8,1" … … 5253 6658 stg "VerticalLayoutStrategy" 5254 6659 textVec [ 5255 * 173(Text6660 *219 (Text 5256 6661 va (VaSet 5257 6662 font "Arial,8,1" … … 5262 6667 tm "BdLibraryNameMgr" 5263 6668 ) 5264 * 174(Text6669 *220 (Text 5265 6670 va (VaSet 5266 6671 font "Arial,8,1" … … 5271 6676 tm "CptNameMgr" 5272 6677 ) 5273 * 175(Text6678 *221 (Text 5274 6679 va (VaSet 5275 6680 font "Arial,8,1" … … 5325 6730 stg "VerticalLayoutStrategy" 5326 6731 textVec [ 5327 * 176(Text6732 *222 (Text 5328 6733 va (VaSet 5329 6734 font "Arial,8,1" … … 5333 6738 blo "500,4300" 5334 6739 ) 5335 * 177(Text6740 *223 (Text 5336 6741 va (VaSet 5337 6742 font "Arial,8,1" … … 5341 6746 blo "500,5300" 5342 6747 ) 5343 * 178(Text6748 *224 (Text 5344 6749 va (VaSet 5345 6750 font "Arial,8,1" … … 5386 6791 stg "VerticalLayoutStrategy" 5387 6792 textVec [ 5388 * 179(Text6793 *225 (Text 5389 6794 va (VaSet 5390 6795 font "Arial,8,1" … … 5394 6799 blo "50,4300" 5395 6800 ) 5396 * 180(Text6801 *226 (Text 5397 6802 va (VaSet 5398 6803 font "Arial,8,1" … … 5402 6807 blo "50,5300" 5403 6808 ) 5404 * 181(Text6809 *227 (Text 5405 6810 va (VaSet 5406 6811 font "Arial,8,1" … … 5443 6848 stg "VerticalLayoutStrategy" 5444 6849 textVec [ 5445 * 182(Text6850 *228 (Text 5446 6851 va (VaSet 5447 6852 font "Arial,8,1" … … 5452 6857 tm "HdlTextNameMgr" 5453 6858 ) 5454 * 183(Text6859 *229 (Text 5455 6860 va (VaSet 5456 6861 font "Arial,8,1" … … 5855 7260 stg "VerticalLayoutStrategy" 5856 7261 textVec [ 5857 * 184(Text7262 *230 (Text 5858 7263 va (VaSet 5859 7264 font "Arial,8,1" … … 5863 7268 blo "14100,20800" 5864 7269 ) 5865 * 185(MLText7270 *231 (MLText 5866 7271 va (VaSet 5867 7272 ) … … 5915 7320 stg "VerticalLayoutStrategy" 5916 7321 textVec [ 5917 * 186(Text7322 *232 (Text 5918 7323 va (VaSet 5919 7324 font "Arial,8,1" … … 5923 7328 blo "14100,20800" 5924 7329 ) 5925 * 187(MLText7330 *233 (MLText 5926 7331 va (VaSet 5927 7332 ) … … 6004 7409 font "Arial,8,1" 6005 7410 ) 6006 xt " 0,12600,5400,13600"7411 xt "-92000,21600,-86600,22600" 6007 7412 st "Declarations" 6008 blo " 0,13400"7413 blo "-92000,22400" 6009 7414 ) 6010 7415 portLabel (Text … … 6013 7418 font "Arial,8,1" 6014 7419 ) 6015 xt " 0,13600,2700,14600"7420 xt "-92000,22600,-89300,23600" 6016 7421 st "Ports:" 6017 blo " 0,14400"7422 blo "-92000,23400" 6018 7423 ) 6019 7424 preUserLabel (Text … … 6023 7428 font "Arial,8,1" 6024 7429 ) 6025 xt " 0,12600,3800,13600"7430 xt "-92000,21600,-88200,22600" 6026 7431 st "Pre User:" 6027 blo " 0,13400"7432 blo "-92000,22400" 6028 7433 ) 6029 7434 preUserText (MLText … … 6033 7438 font "Courier New,8,0" 6034 7439 ) 6035 xt " 0,12600,0,12600"7440 xt "-92000,21600,-92000,21600" 6036 7441 tm "BdDeclarativeTextMgr" 6037 7442 ) … … 6041 7446 font "Arial,8,1" 6042 7447 ) 6043 xt " 0,14600,7100,15600"7448 xt "-92000,23600,-84900,24600" 6044 7449 st "Diagram Signals:" 6045 blo " 0,15400"7450 blo "-92000,24400" 6046 7451 ) 6047 7452 postUserLabel (Text … … 6051 7456 font "Arial,8,1" 6052 7457 ) 6053 xt " 0,12600,4700,13600"7458 xt "-92000,21600,-87300,22600" 6054 7459 st "Post User:" 6055 blo " 0,13400"7460 blo "-92000,22400" 6056 7461 ) 6057 7462 postUserText (MLText … … 6061 7466 font "Courier New,8,0" 6062 7467 ) 6063 xt " 0,12600,0,12600"7468 xt "-92000,21600,-92000,21600" 6064 7469 tm "BdDeclarativeTextMgr" 6065 7470 ) … … 6067 7472 commonDM (CommonDM 6068 7473 ldm (LogicalDM 6069 suid 39,07474 suid 51,0 6070 7475 usingSuid 1 6071 emptyRow * 188(LEmptyRow7476 emptyRow *234 (LEmptyRow 6072 7477 ) 6073 7478 uid 54,0 6074 7479 optionalChildren [ 6075 * 189(RefLabelRowHdr6076 ) 6077 * 190(TitleRowHdr6078 ) 6079 * 191(FilterRowHdr6080 ) 6081 * 192(RefLabelColHdr7480 *235 (RefLabelRowHdr 7481 ) 7482 *236 (TitleRowHdr 7483 ) 7484 *237 (FilterRowHdr 7485 ) 7486 *238 (RefLabelColHdr 6082 7487 tm "RefLabelColHdrMgr" 6083 7488 ) 6084 * 193(RowExpandColHdr7489 *239 (RowExpandColHdr 6085 7490 tm "RowExpandColHdrMgr" 6086 7491 ) 6087 * 194(GroupColHdr7492 *240 (GroupColHdr 6088 7493 tm "GroupColHdrMgr" 6089 7494 ) 6090 * 195(NameColHdr7495 *241 (NameColHdr 6091 7496 tm "BlockDiagramNameColHdrMgr" 6092 7497 ) 6093 * 196(ModeColHdr7498 *242 (ModeColHdr 6094 7499 tm "BlockDiagramModeColHdrMgr" 6095 7500 ) 6096 * 197(TypeColHdr7501 *243 (TypeColHdr 6097 7502 tm "BlockDiagramTypeColHdrMgr" 6098 7503 ) 6099 * 198(BoundsColHdr7504 *244 (BoundsColHdr 6100 7505 tm "BlockDiagramBoundsColHdrMgr" 6101 7506 ) 6102 * 199(InitColHdr7507 *245 (InitColHdr 6103 7508 tm "BlockDiagramInitColHdrMgr" 6104 7509 ) 6105 *2 00(EolColHdr7510 *246 (EolColHdr 6106 7511 tm "BlockDiagramEolColHdrMgr" 6107 7512 ) 6108 *2 01(LeafLogPort7513 *247 (LeafLogPort 6109 7514 port (LogicalPort 6110 7515 m 4 … … 6120 7525 uid 340,0 6121 7526 ) 6122 *2 02(LeafLogPort7527 *248 (LeafLogPort 6123 7528 port (LogicalPort 6124 7529 m 4 … … 6133 7538 uid 342,0 6134 7539 ) 6135 *2 03(LeafLogPort7540 *249 (LeafLogPort 6136 7541 port (LogicalPort 6137 7542 m 4 … … 6146 7551 uid 344,0 6147 7552 ) 6148 *2 04(LeafLogPort7553 *250 (LeafLogPort 6149 7554 port (LogicalPort 6150 7555 m 4 … … 6159 7564 uid 346,0 6160 7565 ) 6161 *2 05(LeafLogPort7566 *251 (LeafLogPort 6162 7567 port (LogicalPort 6163 7568 m 4 … … 6172 7577 uid 348,0 6173 7578 ) 6174 *2 06(LeafLogPort7579 *252 (LeafLogPort 6175 7580 port (LogicalPort 6176 7581 m 4 … … 6185 7590 uid 404,0 6186 7591 ) 6187 *2 07(LeafLogPort7592 *253 (LeafLogPort 6188 7593 port (LogicalPort 6189 7594 m 4 … … 6197 7602 uid 406,0 6198 7603 ) 6199 *2 08(LeafLogPort7604 *254 (LeafLogPort 6200 7605 port (LogicalPort 6201 7606 m 4 … … 6211 7616 uid 408,0 6212 7617 ) 6213 *2 09(LeafLogPort7618 *255 (LeafLogPort 6214 7619 port (LogicalPort 6215 7620 m 4 … … 6225 7630 uid 456,0 6226 7631 ) 6227 *2 10(LeafLogPort7632 *256 (LeafLogPort 6228 7633 port (LogicalPort 6229 7634 m 4 … … 6240 7645 uid 458,0 6241 7646 ) 6242 *2 11(LeafLogPort7647 *257 (LeafLogPort 6243 7648 port (LogicalPort 6244 7649 m 4 … … 6253 7658 uid 460,0 6254 7659 ) 6255 *2 12(LeafLogPort7660 *258 (LeafLogPort 6256 7661 port (LogicalPort 6257 7662 m 4 … … 6266 7671 uid 584,0 6267 7672 ) 6268 *2 13(LeafLogPort7673 *259 (LeafLogPort 6269 7674 port (LogicalPort 6270 7675 m 4 … … 6278 7683 uid 586,0 6279 7684 ) 6280 *2 14(LeafLogPort7685 *260 (LeafLogPort 6281 7686 port (LogicalPort 6282 7687 m 4 … … 6292 7697 uid 588,0 6293 7698 ) 6294 *2 15(LeafLogPort7699 *261 (LeafLogPort 6295 7700 port (LogicalPort 6296 7701 m 4 … … 6306 7711 uid 590,0 6307 7712 ) 6308 *2 16(LeafLogPort7713 *262 (LeafLogPort 6309 7714 port (LogicalPort 6310 7715 m 4 … … 6321 7726 uid 592,0 6322 7727 ) 6323 *2 17(LeafLogPort7728 *263 (LeafLogPort 6324 7729 port (LogicalPort 6325 7730 m 4 … … 6334 7739 uid 903,0 6335 7740 ) 6336 *2 18(LeafLogPort7741 *264 (LeafLogPort 6337 7742 port (LogicalPort 6338 7743 m 4 … … 6349 7754 uid 905,0 6350 7755 ) 6351 *2 19(LeafLogPort7756 *265 (LeafLogPort 6352 7757 port (LogicalPort 6353 7758 m 4 … … 6362 7767 uid 907,0 6363 7768 ) 6364 *2 20(LeafLogPort7769 *266 (LeafLogPort 6365 7770 port (LogicalPort 6366 7771 m 4 … … 6374 7779 uid 909,0 6375 7780 ) 6376 *2 21(LeafLogPort7781 *267 (LeafLogPort 6377 7782 port (LogicalPort 6378 7783 m 4 … … 6386 7791 uid 911,0 6387 7792 ) 6388 *2 22(LeafLogPort7793 *268 (LeafLogPort 6389 7794 port (LogicalPort 6390 7795 m 4 … … 6399 7804 uid 913,0 6400 7805 ) 6401 *2 23(LeafLogPort7806 *269 (LeafLogPort 6402 7807 port (LogicalPort 6403 7808 m 4 … … 6414 7819 uid 915,0 6415 7820 ) 6416 *2 24(LeafLogPort7821 *270 (LeafLogPort 6417 7822 port (LogicalPort 6418 7823 m 4 … … 6426 7831 uid 917,0 6427 7832 ) 6428 *2 25(LeafLogPort7833 *271 (LeafLogPort 6429 7834 port (LogicalPort 6430 7835 m 4 … … 6438 7843 uid 919,0 6439 7844 ) 6440 *2 26(LeafLogPort7845 *272 (LeafLogPort 6441 7846 port (LogicalPort 6442 7847 m 4 … … 6452 7857 uid 921,0 6453 7858 ) 6454 *2 27(LeafLogPort7859 *273 (LeafLogPort 6455 7860 port (LogicalPort 6456 7861 m 4 … … 6465 7870 uid 923,0 6466 7871 ) 6467 *2 28(LeafLogPort7872 *274 (LeafLogPort 6468 7873 port (LogicalPort 6469 7874 m 4 … … 6478 7883 uid 925,0 6479 7884 ) 6480 *2 29(LeafLogPort7885 *275 (LeafLogPort 6481 7886 port (LogicalPort 6482 7887 m 4 … … 6491 7896 uid 927,0 6492 7897 ) 6493 *2 30(LeafLogPort7898 *276 (LeafLogPort 6494 7899 port (LogicalPort 6495 7900 m 4 … … 6503 7908 uid 929,0 6504 7909 ) 6505 *2 31(LeafLogPort7910 *277 (LeafLogPort 6506 7911 port (LogicalPort 6507 7912 m 4 … … 6515 7920 uid 931,0 6516 7921 ) 6517 *2 32(LeafLogPort7922 *278 (LeafLogPort 6518 7923 port (LogicalPort 6519 7924 m 4 … … 6527 7932 uid 933,0 6528 7933 ) 6529 *2 33(LeafLogPort7934 *279 (LeafLogPort 6530 7935 port (LogicalPort 6531 7936 m 4 … … 6538 7943 ) 6539 7944 uid 935,0 7945 ) 7946 *280 (LeafLogPort 7947 port (LogicalPort 7948 m 4 7949 decl (Decl 7950 n "SRIN_out" 7951 t "std_logic" 7952 o 34 7953 suid 40,0 7954 i "'0'" 7955 ) 7956 ) 7957 uid 1541,0 7958 ) 7959 *281 (LeafLogPort 7960 port (LogicalPort 7961 m 4 7962 decl (Decl 7963 n "amber" 7964 t "std_logic" 7965 o 35 7966 suid 41,0 7967 ) 7968 ) 7969 uid 1543,0 7970 ) 7971 *282 (LeafLogPort 7972 port (LogicalPort 7973 m 4 7974 decl (Decl 7975 n "red" 7976 t "std_logic" 7977 o 36 7978 suid 42,0 7979 ) 7980 ) 7981 uid 1545,0 7982 ) 7983 *283 (LeafLogPort 7984 port (LogicalPort 7985 m 4 7986 decl (Decl 7987 n "green" 7988 t "std_logic" 7989 o 37 7990 suid 43,0 7991 ) 7992 ) 7993 uid 1547,0 7994 ) 7995 *284 (LeafLogPort 7996 port (LogicalPort 7997 m 4 7998 decl (Decl 7999 n "counter_result" 8000 t "std_logic_vector" 8001 b "(11 DOWNTO 0)" 8002 o 38 8003 suid 44,0 8004 ) 8005 ) 8006 uid 1549,0 8007 ) 8008 *285 (LeafLogPort 8009 port (LogicalPort 8010 m 4 8011 decl (Decl 8012 n "alarm_refclk_too_low" 8013 t "std_logic" 8014 posAdd 0 8015 o 39 8016 suid 45,0 8017 ) 8018 ) 8019 uid 1551,0 8020 ) 8021 *286 (LeafLogPort 8022 port (LogicalPort 8023 m 4 8024 decl (Decl 8025 n "alarm_refclk_too_high" 8026 t "std_logic" 8027 o 40 8028 suid 46,0 8029 ) 8030 ) 8031 uid 1553,0 8032 ) 8033 *287 (LeafLogPort 8034 port (LogicalPort 8035 m 4 8036 decl (Decl 8037 n "D_T_in" 8038 t "std_logic_vector" 8039 b "(1 DOWNTO 0)" 8040 o 41 8041 suid 47,0 8042 ) 8043 ) 8044 uid 1555,0 8045 ) 8046 *288 (LeafLogPort 8047 port (LogicalPort 8048 m 4 8049 decl (Decl 8050 n "plllock_in" 8051 t "std_logic_vector" 8052 b "(3 DOWNTO 0)" 8053 eolc "-- high level, if dominowave is running and DRS PLL locked" 8054 o 43 8055 suid 49,0 8056 ) 8057 ) 8058 uid 1575,0 8059 ) 8060 *289 (LeafLogPort 8061 port (LogicalPort 8062 lang 2 8063 m 4 8064 decl (Decl 8065 n "ADC_CLK" 8066 t "std_logic" 8067 o 44 8068 suid 50,0 8069 ) 8070 ) 8071 uid 1690,0 8072 ) 8073 *290 (LeafLogPort 8074 port (LogicalPort 8075 m 4 8076 decl (Decl 8077 n "REF_CLK" 8078 t "STD_LOGIC" 8079 o 42 8080 suid 51,0 8081 i "'0'" 8082 ) 8083 ) 8084 uid 2003,0 6540 8085 ) 6541 8086 ] … … 6546 8091 uid 67,0 6547 8092 optionalChildren [ 6548 *2 34(Sheet8093 *291 (Sheet 6549 8094 sheetRow (SheetRow 6550 8095 headerVa (MVa … … 6563 8108 font "Tahoma,10,0" 6564 8109 ) 6565 emptyMRCItem *2 35(MRCItem6566 litem & 1886567 pos 338110 emptyMRCItem *292 (MRCItem 8111 litem &234 8112 pos 44 6568 8113 dimension 20 6569 8114 ) 6570 8115 uid 69,0 6571 8116 optionalChildren [ 6572 *2 36(MRCItem6573 litem & 1898117 *293 (MRCItem 8118 litem &235 6574 8119 pos 0 6575 8120 dimension 20 6576 8121 uid 70,0 6577 8122 ) 6578 *2 37(MRCItem6579 litem & 1908123 *294 (MRCItem 8124 litem &236 6580 8125 pos 1 6581 8126 dimension 23 6582 8127 uid 71,0 6583 8128 ) 6584 *2 38(MRCItem6585 litem & 1918129 *295 (MRCItem 8130 litem &237 6586 8131 pos 2 6587 8132 hidden 1 … … 6589 8134 uid 72,0 6590 8135 ) 6591 *2 39(MRCItem6592 litem &2 018136 *296 (MRCItem 8137 litem &247 6593 8138 pos 0 6594 8139 dimension 20 6595 8140 uid 341,0 6596 8141 ) 6597 *2 40(MRCItem6598 litem &2 028142 *297 (MRCItem 8143 litem &248 6599 8144 pos 1 6600 8145 dimension 20 6601 8146 uid 343,0 6602 8147 ) 6603 *2 41(MRCItem6604 litem &2 038148 *298 (MRCItem 8149 litem &249 6605 8150 pos 2 6606 8151 dimension 20 6607 8152 uid 345,0 6608 8153 ) 6609 *2 42(MRCItem6610 litem &2 048154 *299 (MRCItem 8155 litem &250 6611 8156 pos 3 6612 8157 dimension 20 6613 8158 uid 347,0 6614 8159 ) 6615 * 243(MRCItem6616 litem &2 058160 *300 (MRCItem 8161 litem &251 6617 8162 pos 4 6618 8163 dimension 20 6619 8164 uid 349,0 6620 8165 ) 6621 * 244(MRCItem6622 litem &2 068166 *301 (MRCItem 8167 litem &252 6623 8168 pos 5 6624 8169 dimension 20 6625 8170 uid 405,0 6626 8171 ) 6627 * 245(MRCItem6628 litem &2 078172 *302 (MRCItem 8173 litem &253 6629 8174 pos 6 6630 8175 dimension 20 6631 8176 uid 407,0 6632 8177 ) 6633 * 246(MRCItem6634 litem &2 088178 *303 (MRCItem 8179 litem &254 6635 8180 pos 7 6636 8181 dimension 20 6637 8182 uid 409,0 6638 8183 ) 6639 * 247(MRCItem6640 litem &2 098184 *304 (MRCItem 8185 litem &255 6641 8186 pos 8 6642 8187 dimension 20 6643 8188 uid 457,0 6644 8189 ) 6645 * 248(MRCItem6646 litem &2 108190 *305 (MRCItem 8191 litem &256 6647 8192 pos 9 6648 8193 dimension 20 6649 8194 uid 459,0 6650 8195 ) 6651 * 249(MRCItem6652 litem &2 118196 *306 (MRCItem 8197 litem &257 6653 8198 pos 10 6654 8199 dimension 20 6655 8200 uid 461,0 6656 8201 ) 6657 * 250(MRCItem6658 litem &2 128202 *307 (MRCItem 8203 litem &258 6659 8204 pos 11 6660 8205 dimension 20 6661 8206 uid 585,0 6662 8207 ) 6663 * 251(MRCItem6664 litem &2 138208 *308 (MRCItem 8209 litem &259 6665 8210 pos 12 6666 8211 dimension 20 6667 8212 uid 587,0 6668 8213 ) 6669 * 252(MRCItem6670 litem &2 148214 *309 (MRCItem 8215 litem &260 6671 8216 pos 13 6672 8217 dimension 20 6673 8218 uid 589,0 6674 8219 ) 6675 * 253(MRCItem6676 litem &2 158220 *310 (MRCItem 8221 litem &261 6677 8222 pos 14 6678 8223 dimension 20 6679 8224 uid 591,0 6680 8225 ) 6681 * 254(MRCItem6682 litem &2 168226 *311 (MRCItem 8227 litem &262 6683 8228 pos 15 6684 8229 dimension 20 6685 8230 uid 593,0 6686 8231 ) 6687 * 255(MRCItem6688 litem &2 178232 *312 (MRCItem 8233 litem &263 6689 8234 pos 16 6690 8235 dimension 20 6691 8236 uid 904,0 6692 8237 ) 6693 * 256(MRCItem6694 litem &2 188238 *313 (MRCItem 8239 litem &264 6695 8240 pos 17 6696 8241 dimension 20 6697 8242 uid 906,0 6698 8243 ) 6699 * 257(MRCItem6700 litem &2 198244 *314 (MRCItem 8245 litem &265 6701 8246 pos 18 6702 8247 dimension 20 6703 8248 uid 908,0 6704 8249 ) 6705 * 258(MRCItem6706 litem &2 208250 *315 (MRCItem 8251 litem &266 6707 8252 pos 19 6708 8253 dimension 20 6709 8254 uid 910,0 6710 8255 ) 6711 * 259(MRCItem6712 litem &2 218256 *316 (MRCItem 8257 litem &267 6713 8258 pos 20 6714 8259 dimension 20 6715 8260 uid 912,0 6716 8261 ) 6717 * 260(MRCItem6718 litem &2 228262 *317 (MRCItem 8263 litem &268 6719 8264 pos 21 6720 8265 dimension 20 6721 8266 uid 914,0 6722 8267 ) 6723 * 261(MRCItem6724 litem &2 238268 *318 (MRCItem 8269 litem &269 6725 8270 pos 22 6726 8271 dimension 20 6727 8272 uid 916,0 6728 8273 ) 6729 * 262(MRCItem6730 litem &2 248274 *319 (MRCItem 8275 litem &270 6731 8276 pos 23 6732 8277 dimension 20 6733 8278 uid 918,0 6734 8279 ) 6735 * 263(MRCItem6736 litem &2 258280 *320 (MRCItem 8281 litem &271 6737 8282 pos 24 6738 8283 dimension 20 6739 8284 uid 920,0 6740 8285 ) 6741 * 264(MRCItem6742 litem &2 268286 *321 (MRCItem 8287 litem &272 6743 8288 pos 25 6744 8289 dimension 20 6745 8290 uid 922,0 6746 8291 ) 6747 * 265(MRCItem6748 litem &2 278292 *322 (MRCItem 8293 litem &273 6749 8294 pos 26 6750 8295 dimension 20 6751 8296 uid 924,0 6752 8297 ) 6753 * 266(MRCItem6754 litem &2 288298 *323 (MRCItem 8299 litem &274 6755 8300 pos 27 6756 8301 dimension 20 6757 8302 uid 926,0 6758 8303 ) 6759 * 267(MRCItem6760 litem &2 298304 *324 (MRCItem 8305 litem &275 6761 8306 pos 28 6762 8307 dimension 20 6763 8308 uid 928,0 6764 8309 ) 6765 * 268(MRCItem6766 litem &2 308310 *325 (MRCItem 8311 litem &276 6767 8312 pos 29 6768 8313 dimension 20 6769 8314 uid 930,0 6770 8315 ) 6771 * 269(MRCItem6772 litem &2 318316 *326 (MRCItem 8317 litem &277 6773 8318 pos 30 6774 8319 dimension 20 6775 8320 uid 932,0 6776 8321 ) 6777 * 270(MRCItem6778 litem &2 328322 *327 (MRCItem 8323 litem &278 6779 8324 pos 31 6780 8325 dimension 20 6781 8326 uid 934,0 6782 8327 ) 6783 * 271(MRCItem6784 litem &2 338328 *328 (MRCItem 8329 litem &279 6785 8330 pos 32 6786 8331 dimension 20 6787 8332 uid 936,0 8333 ) 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80,0 6841 8452 ) 6842 * 279(MRCItem6843 litem &2 008453 *347 (MRCItem 8454 litem &246 6844 8455 pos 7 6845 8456 dimension 80 … … 6861 8472 genericsCommonDM (CommonDM 6862 8473 ldm (LogicalDM 6863 emptyRow * 280(LEmptyRow8474 emptyRow *348 (LEmptyRow 6864 8475 ) 6865 8476 uid 83,0 6866 8477 optionalChildren [ 6867 * 281(RefLabelRowHdr6868 ) 6869 * 282(TitleRowHdr6870 ) 6871 * 283(FilterRowHdr6872 ) 6873 * 284(RefLabelColHdr8478 *349 (RefLabelRowHdr 8479 ) 8480 *350 (TitleRowHdr 8481 ) 8482 *351 (FilterRowHdr 8483 ) 8484 *352 (RefLabelColHdr 6874 8485 tm "RefLabelColHdrMgr" 6875 8486 ) 6876 * 285(RowExpandColHdr8487 *353 (RowExpandColHdr 6877 8488 tm "RowExpandColHdrMgr" 6878 8489 ) 6879 * 286(GroupColHdr8490 *354 (GroupColHdr 6880 8491 tm "GroupColHdrMgr" 6881 8492 ) 6882 * 287(NameColHdr8493 *355 (NameColHdr 6883 8494 tm "GenericNameColHdrMgr" 6884 8495 ) 6885 * 288(TypeColHdr8496 *356 (TypeColHdr 6886 8497 tm "GenericTypeColHdrMgr" 6887 8498 ) 6888 * 289(InitColHdr8499 *357 (InitColHdr 6889 8500 tm "GenericValueColHdrMgr" 6890 8501 ) 6891 * 290(PragmaColHdr8502 *358 (PragmaColHdr 6892 8503 tm "GenericPragmaColHdrMgr" 6893 8504 ) 6894 * 291(EolColHdr8505 *359 (EolColHdr 6895 8506 tm "GenericEolColHdrMgr" 6896 8507 ) … … 6902 8513 uid 95,0 6903 8514 optionalChildren [ 6904 * 292(Sheet8515 *360 (Sheet 6905 8516 sheetRow (SheetRow 6906 8517 headerVa (MVa … … 6919 8530 font "Tahoma,10,0" 6920 8531 ) 6921 emptyMRCItem * 293(MRCItem6922 litem & 2808532 emptyMRCItem *361 (MRCItem 8533 litem &348 6923 8534 pos 0 6924 8535 dimension 20 … … 6926 8537 uid 97,0 6927 8538 optionalChildren [ 6928 * 294(MRCItem6929 litem & 2818539 *362 (MRCItem 8540 litem &349 6930 8541 pos 0 6931 8542 dimension 20 6932 8543 uid 98,0 6933 8544 ) 6934 * 295(MRCItem6935 litem & 2828545 *363 (MRCItem 8546 litem &350 6936 8547 pos 1 6937 8548 dimension 23 6938 8549 uid 99,0 6939 8550 ) 6940 * 296(MRCItem6941 litem & 2838551 *364 (MRCItem 8552 litem &351 6942 8553 pos 2 6943 8554 hidden 1 … … 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-
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/fad_main_tb/struct.bd.bak
r9912 r10180 118 118 uid 508,0 119 119 ) 120 (Instance 121 name "I_mainTB_clock1" 122 duLibraryName "FACT_FAD_TB_lib" 123 duName "clock_generator" 124 elements [ 125 (GiElement 126 name "clock_period" 127 type "time" 128 value "1 us" 129 ) 130 (GiElement 131 name "reset_time" 132 type "time" 133 value "1 us" 134 ) 135 ] 136 mwi 0 137 uid 1509,0 138 ) 120 139 ] 121 140 embeddedInstances [ … … 127 146 name "eb_mainTB_adc" 128 147 number "2" 148 ) 149 (EmbeddedInstance 150 name "eb_mainTB_adc1" 151 number "3" 129 152 ) 130 153 ] … … 143 166 (vvPair 144 167 variable "HDLDir" 145 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hdl"168 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl" 146 169 ) 147 170 (vvPair 148 171 variable "HDSDir" 149 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds"172 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds" 150 173 ) 151 174 (vvPair 152 175 variable "SideDataDesignDir" 153 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.info"176 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.info" 154 177 ) 155 178 (vvPair 156 179 variable "SideDataUserDir" 157 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.user"180 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.user" 158 181 ) 159 182 (vvPair 160 183 variable "SourceDir" 161 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds"184 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds" 162 185 ) 163 186 (vvPair … … 171 194 (vvPair 172 195 variable "config" 173 value "%(unit)_ config"196 value "%(unit)_%(view)_config" 174 197 ) 175 198 (vvPair 176 199 variable "d" 177 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb"200 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb" 178 201 ) 179 202 (vvPair 180 203 variable "d_logical" 181 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb"204 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb" 182 205 ) 183 206 (vvPair 184 207 variable "date" 185 value "25.0 6.2010"208 value "25.02.2011" 186 209 ) 187 210 (vvPair … … 223 246 (vvPair 224 247 variable "host" 225 value "E EPC8"248 value "E5B-LABOR6" 226 249 ) 227 250 (vvPair … … 234 257 ) 235 258 (vvPair 259 variable "library_downstream_HdsLintPlugin" 260 value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/designcheck" 261 ) 262 (vvPair 263 variable "library_downstream_ISEPARInvoke" 264 value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise" 265 ) 266 (vvPair 267 variable "library_downstream_ImpactInvoke" 268 value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise" 269 ) 270 (vvPair 236 271 variable "library_downstream_ModelSimCompiler" 237 272 value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/work" 238 273 ) 239 274 (vvPair 275 variable "library_downstream_XSTDataPrep" 276 value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise" 277 ) 278 (vvPair 240 279 variable "mm" 241 value "0 6"280 value "02" 242 281 ) 243 282 (vvPair … … 247 286 (vvPair 248 287 variable "month" 249 value " Jun"288 value "Feb" 250 289 ) 251 290 (vvPair 252 291 variable "month_long" 253 value " Juni"292 value "Februar" 254 293 ) 255 294 (vvPair 256 295 variable "p" 257 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"296 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd" 258 297 ) 259 298 (vvPair 260 299 variable "p_logical" 261 value " D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"300 value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd" 262 301 ) 263 302 (vvPair … … 283 322 (vvPair 284 323 variable "task_ModelSimPath" 285 value " $HDS_HOME/../Modeltech/win32"324 value "C:\\modeltech_6.6a\\win32" 286 325 ) 287 326 (vvPair … … 291 330 (vvPair 292 331 variable "task_PrecisionRTLPath" 293 value " $HDS_HOME/../Precision/Mgc_home/bin"332 value "<TBD>" 294 333 ) 295 334 (vvPair … … 315 354 (vvPair 316 355 variable "time" 317 value " 08:17:47"356 value "13:44:06" 318 357 ) 319 358 (vvPair … … 323 362 (vvPair 324 363 variable "user" 325 value " Benjamin Krumm"364 value "dneise" 326 365 ) 327 366 (vvPair … … 335 374 (vvPair 336 375 variable "year" 337 value "201 0"376 value "2011" 338 377 ) 339 378 (vvPair 340 379 variable "yy" 341 value "1 0"380 value "11" 342 381 ) 343 382 ] … … 367 406 bg "0,0,32768" 368 407 ) 369 xt "109200,97000,1 22200,98000"408 xt "109200,97000,118800,98000" 370 409 st " 371 410 by %user on %dd %month %year … … 706 745 n "wiz_reset" 707 746 t "std_logic" 708 o 28747 o 39 709 748 suid 2,0 710 749 i "'1'" … … 745 784 b "(7 DOWNTO 0)" 746 785 posAdd 0 747 o 21786 o 31 748 787 suid 7,0 749 788 i "(OTHERS => '0')" … … 782 821 preAdd 0 783 822 posAdd 0 784 o 1 0823 o 13 785 824 suid 18,0 786 825 ) … … 817 856 n "adc_oeb" 818 857 t "std_logic" 819 o 16858 o 21 820 859 suid 21,0 821 860 i "'1'" … … 852 891 n "board_id" 853 892 t "std_logic_vector" 854 b "(3 downto 0)" 855 preAdd 0 856 posAdd 0 857 o 8 893 b "(3 DOWNTO 0)" 894 o 9 858 895 suid 24,0 859 896 ) … … 889 926 n "crate_id" 890 927 t "std_logic_vector" 891 b "(1 downto0)"892 o 9928 b "(1 DOWNTO 0)" 929 o 10 893 930 suid 25,0 894 931 ) … … 927 964 t "std_logic_vector" 928 965 b "(9 DOWNTO 0)" 929 o 25966 o 36 930 967 suid 26,0 931 968 ) … … 964 1001 t "std_logic_vector" 965 1002 b "(15 DOWNTO 0)" 966 o 311003 o 42 967 1004 suid 27,0 968 1005 ) … … 1000 1037 n "wiz_cs" 1001 1038 t "std_logic" 1002 o 261039 o 37 1003 1040 suid 28,0 1004 1041 i "'1'" … … 1037 1074 n "wiz_wr" 1038 1075 t "std_logic" 1039 o 291076 o 40 1040 1077 suid 29,0 1041 1078 i "'1'" … … 1074 1111 n "wiz_rd" 1075 1112 t "std_logic" 1076 o 271113 o 38 1077 1114 suid 30,0 1078 1115 i "'1'" … … 1110 1147 n "wiz_int" 1111 1148 t "std_logic" 1112 o 1 11149 o 14 1113 1150 suid 31,0 1114 1151 ) … … 1145 1182 n "CLK_25_PS" 1146 1183 t "std_logic" 1147 o 1 21184 o 16 1148 1185 suid 35,0 1149 1186 ) … … 1180 1217 n "CLK_50" 1181 1218 t "std_logic" 1182 o 13 1219 preAdd 0 1220 posAdd 0 1221 o 17 1183 1222 suid 37,0 1184 1223 ) … … 1249 1288 t "std_logic_vector" 1250 1289 b "(3 DOWNTO 0)" 1251 o 71290 o 8 1252 1291 suid 40,0 1253 1292 ) … … 1283 1322 n "adc_data_array" 1284 1323 t "adc_data_array_type" 1285 o 61324 o 7 1286 1325 suid 41,0 1287 1326 ) … … 1319 1358 t "std_logic_vector" 1320 1359 b "(3 downto 0)" 1321 o 191360 o 28 1322 1361 suid 48,0 1323 1362 i "(others => '0')" … … 1355 1394 n "drs_dwrite" 1356 1395 t "std_logic" 1357 o 2 01396 o 29 1358 1397 suid 49,0 1359 1398 i "'1'" … … 1390 1429 n "SROUT_in_0" 1391 1430 t "std_logic" 1392 o 21431 o 3 1393 1432 suid 52,0 1394 1433 ) … … 1424 1463 n "SROUT_in_1" 1425 1464 t "std_logic" 1426 o 31465 o 4 1427 1466 suid 53,0 1428 1467 ) … … 1458 1497 n "SROUT_in_2" 1459 1498 t "std_logic" 1460 o 41499 o 5 1461 1500 suid 54,0 1462 1501 ) … … 1492 1531 n "SROUT_in_3" 1493 1532 t "std_logic" 1494 o 51533 o 6 1495 1534 suid 55,0 1496 1535 ) … … 1527 1566 n "RSRLOAD" 1528 1567 t "std_logic" 1529 o 1 41568 o 18 1530 1569 suid 56,0 1531 1570 i "'0'" … … 1563 1602 n "SRCLK" 1564 1603 t "std_logic" 1565 o 1 51604 o 19 1566 1605 suid 57,0 1567 1606 i "'0'" … … 1600 1639 n "sclk" 1601 1640 t "std_logic" 1602 o 231641 o 34 1603 1642 suid 62,0 1604 1643 ) … … 1638 1677 preAdd 0 1639 1678 posAdd 0 1640 o 301679 o 41 1641 1680 suid 63,0 1642 1681 ) … … 1674 1713 n "dac_cs" 1675 1714 t "std_logic" 1676 o 171715 o 26 1677 1716 suid 64,0 1678 1717 ) … … 1711 1750 t "std_logic_vector" 1712 1751 b "(3 DOWNTO 0)" 1713 o 241752 o 35 1714 1753 suid 65,0 1715 1754 ) … … 1747 1786 n "mosi" 1748 1787 t "std_logic" 1749 o 221788 o 32 1750 1789 suid 66,0 1751 1790 i "'0'" … … 1786 1825 eolc "-- default domino wave off" 1787 1826 posAdd 0 1788 o 181827 o 27 1789 1828 suid 67,0 1790 1829 i "'0'" 1830 ) 1831 ) 1832 ) 1833 *44 (CptPort 1834 uid 1395,0 1835 ps "OnEdgeStrategy" 1836 shape (Triangle 1837 uid 1396,0 1838 ro 90 1839 va (VaSet 1840 vasetType 1 1841 fg "0,65535,0" 1842 ) 1843 xt "109000,73625,109750,74375" 1844 ) 1845 tg (CPTG 1846 uid 1397,0 1847 ps "CptPortTextPlaceStrategy" 1848 stg "RightVerticalLayoutStrategy" 1849 f (Text 1850 uid 1398,0 1851 va (VaSet 1852 ) 1853 xt "99400,73500,108000,74500" 1854 st "alarm_refclk_too_high" 1855 ju 2 1856 blo "108000,74300" 1857 ) 1858 ) 1859 thePort (LogicalPort 1860 m 1 1861 decl (Decl 1862 n "alarm_refclk_too_high" 1863 t "std_logic" 1864 o 22 1865 suid 95,0 1866 ) 1867 ) 1868 ) 1869 *45 (CptPort 1870 uid 1399,0 1871 ps "OnEdgeStrategy" 1872 shape (Triangle 1873 uid 1400,0 1874 ro 90 1875 va (VaSet 1876 vasetType 1 1877 fg "0,65535,0" 1878 ) 1879 xt "109000,74625,109750,75375" 1880 ) 1881 tg (CPTG 1882 uid 1401,0 1883 ps "CptPortTextPlaceStrategy" 1884 stg "RightVerticalLayoutStrategy" 1885 f (Text 1886 uid 1402,0 1887 va (VaSet 1888 ) 1889 xt "99800,74500,108000,75500" 1890 st "alarm_refclk_too_low" 1891 ju 2 1892 blo "108000,75300" 1893 ) 1894 ) 1895 thePort (LogicalPort 1896 m 1 1897 decl (Decl 1898 n "alarm_refclk_too_low" 1899 t "std_logic" 1900 posAdd 0 1901 o 23 1902 suid 96,0 1903 ) 1904 ) 1905 ) 1906 *46 (CptPort 1907 uid 1403,0 1908 ps "OnEdgeStrategy" 1909 shape (Triangle 1910 uid 1404,0 1911 ro 90 1912 va (VaSet 1913 vasetType 1 1914 fg "0,65535,0" 1915 ) 1916 xt "109000,79625,109750,80375" 1917 ) 1918 tg (CPTG 1919 uid 1405,0 1920 ps "CptPortTextPlaceStrategy" 1921 stg "RightVerticalLayoutStrategy" 1922 f (Text 1923 uid 1406,0 1924 va (VaSet 1925 ) 1926 xt "105500,79500,108000,80500" 1927 st "amber" 1928 ju 2 1929 blo "108000,80300" 1930 ) 1931 ) 1932 thePort (LogicalPort 1933 m 1 1934 decl (Decl 1935 n "amber" 1936 t "std_logic" 1937 o 24 1938 suid 87,0 1939 ) 1940 ) 1941 ) 1942 *47 (CptPort 1943 uid 1407,0 1944 ps "OnEdgeStrategy" 1945 shape (Triangle 1946 uid 1408,0 1947 ro 90 1948 va (VaSet 1949 vasetType 1 1950 fg "0,65535,0" 1951 ) 1952 xt "109000,76625,109750,77375" 1953 ) 1954 tg (CPTG 1955 uid 1409,0 1956 ps "CptPortTextPlaceStrategy" 1957 stg "RightVerticalLayoutStrategy" 1958 f (Text 1959 uid 1410,0 1960 va (VaSet 1961 ) 1962 xt "99400,76500,108000,77500" 1963 st "counter_result : (11:0)" 1964 ju 2 1965 blo "108000,77300" 1966 ) 1967 ) 1968 thePort (LogicalPort 1969 m 1 1970 decl (Decl 1971 n "counter_result" 1972 t "std_logic_vector" 1973 b "(11 DOWNTO 0)" 1974 o 25 1975 suid 94,0 1976 ) 1977 ) 1978 ) 1979 *48 (CptPort 1980 uid 1411,0 1981 ps "OnEdgeStrategy" 1982 shape (Triangle 1983 uid 1412,0 1984 ro 90 1985 va (VaSet 1986 vasetType 1 1987 fg "0,65535,0" 1988 ) 1989 xt "80250,74625,81000,75375" 1990 ) 1991 tg (CPTG 1992 uid 1413,0 1993 ps "CptPortTextPlaceStrategy" 1994 stg "VerticalLayoutStrategy" 1995 f (Text 1996 uid 1414,0 1997 va (VaSet 1998 ) 1999 xt "82000,74500,87500,75500" 2000 st "D_T_in : (1:0)" 2001 blo "82000,75300" 2002 ) 2003 ) 2004 thePort (LogicalPort 2005 decl (Decl 2006 n "D_T_in" 2007 t "std_logic_vector" 2008 b "(1 DOWNTO 0)" 2009 o 2 2010 suid 91,0 2011 ) 2012 ) 2013 ) 2014 *49 (CptPort 2015 uid 1415,0 2016 ps "OnEdgeStrategy" 2017 shape (Triangle 2018 uid 1416,0 2019 ro 90 2020 va (VaSet 2021 vasetType 1 2022 fg "0,65535,0" 2023 ) 2024 xt "80250,75625,81000,76375" 2025 ) 2026 tg (CPTG 2027 uid 1417,0 2028 ps "CptPortTextPlaceStrategy" 2029 stg "VerticalLayoutStrategy" 2030 f (Text 2031 uid 1418,0 2032 va (VaSet 2033 ) 2034 xt "82000,75500,87100,76500" 2035 st "drs_refclk_in" 2036 blo "82000,76300" 2037 ) 2038 ) 2039 thePort (LogicalPort 2040 decl (Decl 2041 n "drs_refclk_in" 2042 t "std_logic" 2043 eolc "-- used to check if DRS REFCLK exsists, if not DENABLE inhibit" 2044 o 11 2045 suid 92,0 2046 ) 2047 ) 2048 ) 2049 *50 (CptPort 2050 uid 1419,0 2051 ps "OnEdgeStrategy" 2052 shape (Triangle 2053 uid 1420,0 2054 ro 90 2055 va (VaSet 2056 vasetType 1 2057 fg "0,65535,0" 2058 ) 2059 xt "109000,77625,109750,78375" 2060 ) 2061 tg (CPTG 2062 uid 1421,0 2063 ps "CptPortTextPlaceStrategy" 2064 stg "RightVerticalLayoutStrategy" 2065 f (Text 2066 uid 1422,0 2067 va (VaSet 2068 ) 2069 xt "105600,77500,108000,78500" 2070 st "green" 2071 ju 2 2072 blo "108000,78300" 2073 ) 2074 ) 2075 thePort (LogicalPort 2076 m 1 2077 decl (Decl 2078 n "green" 2079 t "std_logic" 2080 o 30 2081 suid 86,0 2082 ) 2083 ) 2084 ) 2085 *51 (CptPort 2086 uid 1423,0 2087 ps "OnEdgeStrategy" 2088 shape (Triangle 2089 uid 1424,0 2090 ro 90 2091 va (VaSet 2092 vasetType 1 2093 fg "0,65535,0" 2094 ) 2095 xt "80250,76625,81000,77375" 2096 ) 2097 tg (CPTG 2098 uid 1425,0 2099 ps "CptPortTextPlaceStrategy" 2100 stg "VerticalLayoutStrategy" 2101 f (Text 2102 uid 1426,0 2103 va (VaSet 2104 ) 2105 xt "82000,76500,88100,77500" 2106 st "plllock_in : (3:0)" 2107 blo "82000,77300" 2108 ) 2109 ) 2110 thePort (LogicalPort 2111 decl (Decl 2112 n "plllock_in" 2113 t "std_logic_vector" 2114 b "(3 DOWNTO 0)" 2115 eolc "-- high level, if dominowave is running and DRS PLL locked" 2116 o 12 2117 suid 93,0 2118 ) 2119 ) 2120 ) 2121 *52 (CptPort 2122 uid 1427,0 2123 ps "OnEdgeStrategy" 2124 shape (Triangle 2125 uid 1428,0 2126 ro 90 2127 va (VaSet 2128 vasetType 1 2129 fg "0,65535,0" 2130 ) 2131 xt "109000,78625,109750,79375" 2132 ) 2133 tg (CPTG 2134 uid 1429,0 2135 ps "CptPortTextPlaceStrategy" 2136 stg "RightVerticalLayoutStrategy" 2137 f (Text 2138 uid 1430,0 2139 va (VaSet 2140 ) 2141 xt "106500,78500,108000,79500" 2142 st "red" 2143 ju 2 2144 blo "108000,79300" 2145 ) 2146 ) 2147 thePort (LogicalPort 2148 m 1 2149 decl (Decl 2150 n "red" 2151 t "std_logic" 2152 o 33 2153 suid 88,0 2154 ) 2155 ) 2156 ) 2157 *53 (CptPort 2158 uid 1431,0 2159 ps "OnEdgeStrategy" 2160 shape (Triangle 2161 uid 1432,0 2162 ro 270 2163 va (VaSet 2164 vasetType 1 2165 fg "0,65535,0" 2166 ) 2167 xt "80250,71625,81000,72375" 2168 ) 2169 tg (CPTG 2170 uid 1433,0 2171 ps "CptPortTextPlaceStrategy" 2172 stg "VerticalLayoutStrategy" 2173 f (Text 2174 uid 1434,0 2175 va (VaSet 2176 ) 2177 xt "82000,71500,85700,72500" 2178 st "SRIN_out" 2179 blo "82000,72300" 2180 ) 2181 ) 2182 thePort (LogicalPort 2183 m 1 2184 decl (Decl 2185 n "SRIN_out" 2186 t "std_logic" 2187 o 20 2188 suid 85,0 2189 i "'0'" 2190 ) 2191 ) 2192 ) 2193 *54 (CptPort 2194 uid 1678,0 2195 ps "OnEdgeStrategy" 2196 shape (Triangle 2197 uid 1679,0 2198 ro 270 2199 va (VaSet 2200 vasetType 1 2201 fg "0,65535,0" 2202 ) 2203 xt "80250,23625,81000,24375" 2204 ) 2205 tg (CPTG 2206 uid 1680,0 2207 ps "CptPortTextPlaceStrategy" 2208 stg "VerticalLayoutStrategy" 2209 f (Text 2210 uid 1681,0 2211 va (VaSet 2212 ) 2213 xt "82000,23500,86000,24500" 2214 st "ADC_CLK" 2215 blo "82000,24300" 2216 ) 2217 ) 2218 thePort (LogicalPort 2219 lang 2 2220 m 1 2221 decl (Decl 2222 n "ADC_CLK" 2223 t "std_logic" 2224 o 15 2225 suid 97,0 1791 2226 ) 1792 2227 ) … … 1801 2236 lineWidth 2 1802 2237 ) 1803 xt "81000,19000,109000, 73000"2238 xt "81000,19000,109000,81000" 1804 2239 ) 1805 2240 oxt "15000,-8000,43000,46000" … … 1809 2244 stg "VerticalLayoutStrategy" 1810 2245 textVec [ 1811 * 44(Text2246 *55 (Text 1812 2247 uid 236,0 1813 2248 va (VaSet 1814 2249 font "Arial,8,1" 1815 2250 ) 1816 xt "8 1200,73000,87400,74000"2251 xt "83200,81000,89400,82000" 1817 2252 st "FACT_FAD_lib" 1818 blo "8 1200,73800"2253 blo "83200,81800" 1819 2254 tm "BdLibraryNameMgr" 1820 2255 ) 1821 * 45(Text2256 *56 (Text 1822 2257 uid 237,0 1823 2258 va (VaSet 1824 2259 font "Arial,8,1" 1825 2260 ) 1826 xt "8 1200,74000,85400,75000"2261 xt "83200,82000,87400,83000" 1827 2262 <