Changeset 10180


Ignore:
Timestamp:
02/25/11 15:56:47 (11 years ago)
Author:
neise
Message:
at least P&R runs again
Location:
firmware/FAD/FACT_FAD_20MHz_VAR_PS
Files:
78 added
26 edited

Legend:

Unmodified
Added
Removed

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD.hdp

    r10155 r10180  
    11[DesignChecker]
    22FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/designcheck
     3FACT_FAD_TB_lib = $HDS_PROJECT_DIR\FACT_FAD_TB_lib\designcheck
    34[ModelSim]
    45FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/work

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/fad_main_tb_struct.vhd

    r9912 r10180  
    22--
    33-- Created:
    4 --          by - dneise.UNKNOWN (TU-CC4900F8C7D2)
    5 --          at - 15:53:42 30.06.2010
     4--          by - dneise.UNKNOWN (E5B-LABOR6)
     5--          at - 16:10:14 25.02.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    … …  
    2020--
    2121-- Created:
    22 --          by - dneise.UNKNOWN (TU-CC4900F8C7D2)
    23 --          at - 15:53:42 30.06.2010
     22--          by - dneise.UNKNOWN (E5B-LABOR6)
     23--          at - 16:10:15 25.02.2011
    2424--
    2525-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
    … …  
    4444
    4545   -- Internal signal declarations
    46    SIGNAL CLK_25_PS      : std_logic;
    47    SIGNAL CLK_50         : std_logic;
    48    SIGNAL RSRLOAD        : std_logic                    := '0';
    49    SIGNAL SRCLK          : std_logic                    := '0';
    50    SIGNAL SROUT_in_0     : std_logic;
    51    SIGNAL SROUT_in_1     : std_logic;
    52    SIGNAL SROUT_in_2     : std_logic;
    53    SIGNAL SROUT_in_3     : std_logic;
    54    SIGNAL adc_data       : std_logic_vector(11 DOWNTO 0);
    55    SIGNAL adc_data_array : adc_data_array_type;
    56    SIGNAL adc_oeb        : std_logic;
    57    SIGNAL adc_otr        : STD_LOGIC;
    58    SIGNAL adc_otr_array  : std_logic_vector(3 DOWNTO 0);
    59    SIGNAL board_id       : std_logic_vector(3 DOWNTO 0);
    60    SIGNAL clk            : STD_LOGIC;
    61    SIGNAL crate_id       : std_logic_vector(1 DOWNTO 0);
    62    SIGNAL dac_cs         : std_logic;
    63    SIGNAL denable        : std_logic                    := '0';                -- default domino wave off
    64    SIGNAL drs_channel_id : std_logic_vector(3 DOWNTO 0) := (others => '0');
    65    SIGNAL drs_dwrite     : std_logic                    := '1';
    66    SIGNAL led            : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
    67    SIGNAL mosi           : std_logic                    := '0';
    68    SIGNAL sclk           : std_logic;
    69    SIGNAL sensor_cs      : std_logic_vector(3 DOWNTO 0);
    70    SIGNAL sio            : std_logic;
    71    SIGNAL trigger        : std_logic;
    72    SIGNAL wiz_addr       : std_logic_vector(9 DOWNTO 0);
    73    SIGNAL wiz_cs         : std_logic                    := '1';
    74    SIGNAL wiz_data       : std_logic_vector(15 DOWNTO 0);
    75    SIGNAL wiz_int        : std_logic;
    76    SIGNAL wiz_rd         : std_logic                    := '1';
    77    SIGNAL wiz_reset      : std_logic                    := '1';
    78    SIGNAL wiz_wr         : std_logic                    := '1';
     46   SIGNAL ADC_CLK               : std_logic;
     47   SIGNAL CLK_25_PS             : std_logic;
     48   SIGNAL CLK_50                : std_logic;
     49   SIGNAL D_T_in                : std_logic_vector(1 DOWNTO 0);
     50   SIGNAL REF_CLK               : STD_LOGIC                    := '0';
     51   SIGNAL RSRLOAD               : std_logic                    := '0';
     52   SIGNAL SRCLK                 : std_logic                    := '0';
     53   SIGNAL SRIN_out              : std_logic                    := '0';
     54   SIGNAL SROUT_in_0            : std_logic;
     55   SIGNAL SROUT_in_1            : std_logic;
     56   SIGNAL SROUT_in_2            : std_logic;
     57   SIGNAL SROUT_in_3            : std_logic;
     58   SIGNAL adc_data              : std_logic_vector(11 DOWNTO 0);
     59   SIGNAL adc_data_array        : adc_data_array_type;
     60   SIGNAL adc_oeb               : std_logic;
     61   SIGNAL adc_otr               : STD_LOGIC;
     62   SIGNAL adc_otr_array         : std_logic_vector(3 DOWNTO 0);
     63   SIGNAL alarm_refclk_too_high : std_logic;
     64   SIGNAL alarm_refclk_too_low  : std_logic;
     65   SIGNAL amber                 : std_logic;
     66   SIGNAL board_id              : std_logic_vector(3 DOWNTO 0);
     67   SIGNAL clk                   : STD_LOGIC;
     68   SIGNAL counter_result        : std_logic_vector(11 DOWNTO 0);
     69   SIGNAL crate_id              : std_logic_vector(1 DOWNTO 0);
     70   SIGNAL dac_cs                : std_logic;
     71   SIGNAL denable               : std_logic                    := '0';                -- default domino wave off
     72   SIGNAL drs_channel_id        : std_logic_vector(3 DOWNTO 0) := (others => '0');
     73   SIGNAL drs_dwrite            : std_logic                    := '1';
     74   SIGNAL green                 : std_logic;
     75   SIGNAL led                   : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
     76   SIGNAL mosi                  : std_logic                    := '0';
     77   SIGNAL plllock_in            : std_logic_vector(3 DOWNTO 0);                       -- high level, if dominowave is running and DRS PLL locked
     78   SIGNAL red                   : std_logic;
     79   SIGNAL sclk                  : std_logic;
     80   SIGNAL sensor_cs             : std_logic_vector(3 DOWNTO 0);
     81   SIGNAL sio                   : std_logic;
     82   SIGNAL trigger               : std_logic;
     83   SIGNAL wiz_addr              : std_logic_vector(9 DOWNTO 0);
     84   SIGNAL wiz_cs                : std_logic                    := '1';
     85   SIGNAL wiz_data              : std_logic_vector(15 DOWNTO 0);
     86   SIGNAL wiz_int               : std_logic;
     87   SIGNAL wiz_rd                : std_logic                    := '1';
     88   SIGNAL wiz_reset             : std_logic                    := '1';
     89   SIGNAL wiz_wr                : std_logic                    := '1';
    7990
    8091
    … …  
    8596   );
    8697   PORT (
    87       CLK            : IN     std_logic ;
    88       SROUT_in_0     : IN     std_logic ;
    89       SROUT_in_1     : IN     std_logic ;
    90       SROUT_in_2     : IN     std_logic ;
    91       SROUT_in_3     : IN     std_logic ;
    92       adc_data_array : IN     adc_data_array_type ;
    93       adc_otr_array  : IN     std_logic_vector (3 DOWNTO 0);
    94       board_id       : IN     std_logic_vector (3 DOWNTO 0);
    95       crate_id       : IN     std_logic_vector (1 DOWNTO 0);
    96       trigger        : IN     std_logic ;
    97       wiz_int        : IN     std_logic ;
    98       CLK_25_PS      : OUT    std_logic ;
    99       CLK_50         : OUT    std_logic ;
    100       RSRLOAD        : OUT    std_logic                     := '0';
    101       SRCLK          : OUT    std_logic                     := '0';
    102       adc_oeb        : OUT    std_logic                     := '1';
    103       dac_cs         : OUT    std_logic ;
    104       denable        : OUT    std_logic                     := '0';           -- default domino wave off
    105       drs_channel_id : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
    106       drs_dwrite     : OUT    std_logic                     := '1';
    107       led            : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
    108       mosi           : OUT    std_logic                     := '0';
    109       sclk           : OUT    std_logic ;
    110       sensor_cs      : OUT    std_logic_vector (3 DOWNTO 0);
    111       wiz_addr       : OUT    std_logic_vector (9 DOWNTO 0);
    112       wiz_cs         : OUT    std_logic                     := '1';
    113       wiz_rd         : OUT    std_logic                     := '1';
    114       wiz_reset      : OUT    std_logic                     := '1';
    115       wiz_wr         : OUT    std_logic                     := '1';
    116       sio            : INOUT  std_logic ;
    117       wiz_data       : INOUT  std_logic_vector (15 DOWNTO 0)
     98      CLK                   : IN     std_logic ;
     99      D_T_in                : IN     std_logic_vector (1 DOWNTO 0);
     100      SROUT_in_0            : IN     std_logic ;
     101      SROUT_in_1            : IN     std_logic ;
     102      SROUT_in_2            : IN     std_logic ;
     103      SROUT_in_3            : IN     std_logic ;
     104      adc_data_array        : IN     adc_data_array_type ;
     105      adc_otr_array         : IN     std_logic_vector (3 DOWNTO 0);
     106      board_id              : IN     std_logic_vector (3 DOWNTO 0);
     107      crate_id              : IN     std_logic_vector (1 DOWNTO 0);
     108      drs_refclk_in         : IN     std_logic ;                                     -- used TO check if DRS REFCLK exsists, if not DENABLE inhibit
     109      plllock_in            : IN     std_logic_vector (3 DOWNTO 0);                  -- high level, if dominowave is running and DRS PLL locked
     110      trigger               : IN     std_logic ;
     111      wiz_int               : IN     std_logic ;
     112      ADC_CLK               : OUT    std_logic ;
     113      CLK_25_PS             : OUT    std_logic ;
     114      CLK_50                : OUT    std_logic ;
     115      RSRLOAD               : OUT    std_logic                     := '0';
     116      SRCLK                 : OUT    std_logic                     := '0';
     117      SRIN_out              : OUT    std_logic                     := '0';
     118      adc_oeb               : OUT    std_logic                     := '1';
     119      alarm_refclk_too_high : OUT    std_logic ;
     120      alarm_refclk_too_low  : OUT    std_logic ;
     121      amber                 : OUT    std_logic ;
     122      counter_result        : OUT    std_logic_vector (11 DOWNTO 0);
     123      dac_cs                : OUT    std_logic ;
     124      denable               : OUT    std_logic                     := '0';           -- default domino wave off
     125      drs_channel_id        : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
     126      drs_dwrite            : OUT    std_logic                     := '1';
     127      green                 : OUT    std_logic ;
     128      led                   : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
     129      mosi                  : OUT    std_logic                     := '0';
     130      red                   : OUT    std_logic ;
     131      sclk                  : OUT    std_logic ;
     132      sensor_cs             : OUT    std_logic_vector (3 DOWNTO 0);
     133      wiz_addr              : OUT    std_logic_vector (9 DOWNTO 0);
     134      wiz_cs                : OUT    std_logic                     := '1';
     135      wiz_rd                : OUT    std_logic                     := '1';
     136      wiz_reset             : OUT    std_logic                     := '1';
     137      wiz_wr                : OUT    std_logic                     := '1';
     138      sio                   : INOUT  std_logic ;
     139      wiz_data              : INOUT  std_logic_vector (15 DOWNTO 0)
    118140   );
    119141   END COMPONENT;
    … …  
    160182   COMPONENT w5300_emulator
    161183   PORT (
     184      int  : OUT    std_logic  := '0';
    162185      addr : IN     std_logic_vector (9 DOWNTO 0);
    163186      data : INOUT  std_logic_vector (15 DOWNTO 0);
    … …  
    196219   adc_otr_array(3) <= adc_otr;
    197220
     221   -- HDL Embedded Text Block 3 eb_mainTB_adc1
     222   
     223   D_T_in(1 downto 0) <= "00";
     224   plllock_in(3 downto 0) <= "1111";
     225   SROUT_in_0 <= '1';
     226   SROUT_in_1 <= '0';
     227   SROUT_in_2 <= '1';
     228   SROUT_in_3 <= '0';
     229
    198230
    199231   -- Instance port mappings.
    … …  
    203235      )
    204236      PORT MAP (
    205          CLK            => clk,
    206          SROUT_in_0     => SROUT_in_0,
    207          SROUT_in_1     => SROUT_in_1,
    208          SROUT_in_2     => SROUT_in_2,
    209          SROUT_in_3     => SROUT_in_3,
    210          adc_data_array => adc_data_array,
    211          adc_otr_array  => adc_otr_array,
    212          board_id       => board_id,
    213          crate_id       => crate_id,
    214          trigger        => trigger,
    215          wiz_int        => wiz_int,
    216          CLK_25_PS      => CLK_25_PS,
    217          CLK_50         => CLK_50,
    218          RSRLOAD        => RSRLOAD,
    219          SRCLK          => SRCLK,
    220          adc_oeb        => adc_oeb,
    221          dac_cs         => dac_cs,
    222          denable        => denable,
    223          drs_channel_id => drs_channel_id,
    224          drs_dwrite     => drs_dwrite,
    225          led            => led,
    226          mosi           => mosi,
    227          sclk           => sclk,
    228          sensor_cs      => sensor_cs,
    229          wiz_addr       => wiz_addr,
    230          wiz_cs         => wiz_cs,
    231          wiz_rd         => wiz_rd,
    232          wiz_reset      => wiz_reset,
    233          wiz_wr         => wiz_wr,
    234          sio            => sio,
    235          wiz_data       => wiz_data
     237         CLK                   => clk,
     238         D_T_in                => D_T_in,
     239         SROUT_in_0            => SROUT_in_0,
     240         SROUT_in_1            => SROUT_in_1,
     241         SROUT_in_2            => SROUT_in_2,
     242         SROUT_in_3            => SROUT_in_3,
     243         adc_data_array        => adc_data_array,
     244         adc_otr_array         => adc_otr_array,
     245         board_id              => board_id,
     246         crate_id              => crate_id,
     247         drs_refclk_in         => REF_CLK,
     248         plllock_in            => plllock_in,
     249         trigger               => trigger,
     250         wiz_int               => wiz_int,
     251         ADC_CLK               => ADC_CLK,
     252         CLK_25_PS             => CLK_25_PS,
     253         CLK_50                => CLK_50,
     254         RSRLOAD               => RSRLOAD,
     255         SRCLK                 => SRCLK,
     256         SRIN_out              => SRIN_out,
     257         adc_oeb               => adc_oeb,
     258         alarm_refclk_too_high => alarm_refclk_too_high,
     259         alarm_refclk_too_low  => alarm_refclk_too_low,
     260         amber                 => amber,
     261         counter_result        => counter_result,
     262         dac_cs                => dac_cs,
     263         denable               => denable,
     264         drs_channel_id        => drs_channel_id,
     265         drs_dwrite            => drs_dwrite,
     266         green                 => green,
     267         led                   => led,
     268         mosi                  => mosi,
     269         red                   => red,
     270         sclk                  => sclk,
     271         sensor_cs             => sensor_cs,
     272         wiz_addr              => wiz_addr,
     273         wiz_cs                => wiz_cs,
     274         wiz_rd                => wiz_rd,
     275         wiz_reset             => wiz_reset,
     276         wiz_wr                => wiz_wr,
     277         sio                   => sio,
     278         wiz_data              => wiz_data
    236279      );
    237280   I_mainTB_adc : adc_emulator
    … …  
    240283      )
    241284      PORT MAP (
    242          clk  => clk,
     285         clk  => ADC_CLK,
    243286         data => adc_data,
    244287         otr  => adc_otr,
    … …  
    254297         rst => OPEN
    255298      );
     299   I_mainTB_clock1 : clock_generator
     300      GENERIC MAP (
     301         clock_period => 1 us,
     302         reset_time   => 1 us
     303      )
     304      PORT MAP (
     305         clk => REF_CLK,
     306         rst => OPEN
     307      );
    256308   I_mainTB_max6662 : max6662_emulator
    257309      GENERIC MAP (
    … …  
    273325   I_mainTB_w5300 : w5300_emulator
    274326      PORT MAP (
     327         int  => wiz_int,
    275328         addr => wiz_addr,
    276329         data => wiz_data,

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/w5300_emulator_beha.vhd

    r9912 r10180  
    1717ENTITY w5300_emulator IS
    1818   PORT(
     19                int : out       std_logic := '0';
    1920      addr : in     std_logic_vector (9 DOWNTO 0);
    2021      data : inout  std_logic_vector (15 DOWNTO 0);
    … …  
    7172      elsif (addr = conv_integer(W5300_S0_RX_FIFOR)) then
    7273        if (FIFOR_CNT = 0) then
    73           data_temp <= X"B000";
    74 --          FIFOR_CNT <= 1;
     74          data_temp <= X"1800";
     75          FIFOR_CNT <= 1;
    7576        elsif (FIFOR_CNT = 1) then
    76           data_temp <= X"0500";
     77          data_temp <= X"2200";
    7778          FIFOR_CNT <= 2;
    7879        elsif (FIFOR_CNT = 2) then
    79           data_temp <= X"0000";
    80         end if;
     80          data_temp <= X"A000";
     81          FIFOR_CNT <= 3;
     82
     83          elsif (FIFOR_CNT = 3) then
     84                data_temp <= X"B000";
     85          end if;
    8186      else
    8287        null;

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/.xrf/fad_main_tb_struct.xrf

    r9912 r10180  
    2525DESIGN fad_main_tb
    2626VIEW struct.bd
    27 GRAPHIC 823,0 45 0
    28 DESIGN fad_main_tb
    29 VIEW struct.bd
    30 GRAPHIC 831,0 46 0
    31 DESIGN fad_main_tb
    32 VIEW struct.bd
    33 GRAPHIC 855,0 47 0
    34 DESIGN fad_main_tb
    35 VIEW struct.bd
    36 GRAPHIC 863,0 48 0
    37 DESIGN fad_main_tb
    38 VIEW struct.bd
    39 GRAPHIC 871,0 49 0
    40 DESIGN fad_main_tb
    41 VIEW struct.bd
    42 GRAPHIC 879,0 50 0
    43 DESIGN fad_main_tb
    44 VIEW struct.bd
    45 GRAPHIC 887,0 51 0
    46 DESIGN fad_main_tb
    47 VIEW struct.bd
    48 GRAPHIC 895,0 52 0
    49 DESIGN fad_main_tb
    50 VIEW struct.bd
    51 GRAPHIC 568,0 53 0
    52 DESIGN fad_main_tb
    53 VIEW struct.bd
    54 GRAPHIC 536,0 54 0
    55 DESIGN fad_main_tb
    56 VIEW struct.bd
    57 GRAPHIC 544,0 55 0
    58 DESIGN fad_main_tb
    59 VIEW struct.bd
    60 GRAPHIC 560,0 56 0
    61 DESIGN fad_main_tb
    62 VIEW struct.bd
    63 GRAPHIC 528,0 57 0
    64 DESIGN fad_main_tb
    65 VIEW struct.bd
    66 GRAPHIC 440,0 58 0
    67 DESIGN fad_main_tb
    68 VIEW struct.bd
    69 GRAPHIC 284,0 59 0
    70 DESIGN fad_main_tb
    71 VIEW struct.bd
    72 GRAPHIC 448,0 60 0
    73 DESIGN fad_main_tb
    74 VIEW struct.bd
    75 GRAPHIC 799,0 61 0
    76 DESIGN fad_main_tb
    77 VIEW struct.bd
    78 GRAPHIC 815,0 62 0
    79 DESIGN fad_main_tb
    80 VIEW struct.bd
    81 GRAPHIC 839,0 63 0
    82 DESIGN fad_main_tb
    83 VIEW struct.bd
    84 GRAPHIC 847,0 64 0
    85 DESIGN fad_main_tb
    86 VIEW struct.bd
    87 GRAPHIC 775,0 65 0
    88 DESIGN fad_main_tb
    89 VIEW struct.bd
    90 GRAPHIC 807,0 66 0
    91 DESIGN fad_main_tb
    92 VIEW struct.bd
    93 GRAPHIC 378,0 67 0
    94 DESIGN fad_main_tb
    95 VIEW struct.bd
    96 GRAPHIC 372,0 68 0
    97 DESIGN fad_main_tb
    98 VIEW struct.bd
    99 GRAPHIC 384,0 69 0
    100 DESIGN fad_main_tb
    101 VIEW struct.bd
    102 GRAPHIC 424,0 70 0
    103 DESIGN fad_main_tb
    104 VIEW struct.bd
    105 GRAPHIC 316,0 71 0
    106 DESIGN fad_main_tb
    107 VIEW struct.bd
    108 GRAPHIC 783,0 72 0
    109 DESIGN fad_main_tb
    110 VIEW struct.bd
    111 GRAPHIC 322,0 73 0
    112 DESIGN fad_main_tb
    113 VIEW struct.bd
    114 GRAPHIC 791,0 74 0
    115 DESIGN fad_main_tb
    116 VIEW struct.bd
    117 GRAPHIC 328,0 75 0
    118 DESIGN fad_main_tb
    119 VIEW struct.bd
    120 GRAPHIC 767,0 76 0
    121 DESIGN fad_main_tb
    122 VIEW struct.bd
    123 GRAPHIC 334,0 77 0
    124 DESIGN fad_main_tb
    125 VIEW struct.bd
    126 NO_GRAPHIC 78
    127 DESIGN fad_main_tb
    128 VIEW struct.bd
    129 NO_GRAPHIC 79
     27GRAPHIC 1682,0 45 0
     28DESIGN fad_main_tb
     29VIEW struct.bd
     30GRAPHIC 823,0 46 0
     31DESIGN fad_main_tb
     32VIEW struct.bd
     33GRAPHIC 831,0 47 0
     34DESIGN fad_main_tb
     35VIEW struct.bd
     36GRAPHIC 1501,0 48 0
     37DESIGN fad_main_tb
     38VIEW struct.bd
     39GRAPHIC 2001,0 49 0
     40DESIGN fad_main_tb
     41VIEW struct.bd
     42GRAPHIC 855,0 50 0
     43DESIGN fad_main_tb
     44VIEW struct.bd
     45GRAPHIC 863,0 51 0
     46DESIGN fad_main_tb
     47VIEW struct.bd
     48GRAPHIC 1435,0 52 0
     49DESIGN fad_main_tb
     50VIEW struct.bd
     51GRAPHIC 871,0 53 0
     52DESIGN fad_main_tb
     53VIEW struct.bd
     54GRAPHIC 879,0 54 0
     55DESIGN fad_main_tb
     56VIEW struct.bd
     57GRAPHIC 887,0 55 0
     58DESIGN fad_main_tb
     59VIEW struct.bd
     60GRAPHIC 895,0 56 0
     61DESIGN fad_main_tb
     62VIEW struct.bd
     63GRAPHIC 568,0 57 0
     64DESIGN fad_main_tb
     65VIEW struct.bd
     66GRAPHIC 536,0 58 0
     67DESIGN fad_main_tb
     68VIEW struct.bd
     69GRAPHIC 544,0 59 0
     70DESIGN fad_main_tb
     71VIEW struct.bd
     72GRAPHIC 560,0 60 0
     73DESIGN fad_main_tb
     74VIEW struct.bd
     75GRAPHIC 528,0 61 0
     76DESIGN fad_main_tb
     77VIEW struct.bd
     78GRAPHIC 1483,0 62 0
     79DESIGN fad_main_tb
     80VIEW struct.bd
     81GRAPHIC 1475,0 63 0
     82DESIGN fad_main_tb
     83VIEW struct.bd
     84GRAPHIC 1443,0 64 0
     85DESIGN fad_main_tb
     86VIEW struct.bd
     87GRAPHIC 440,0 65 0
     88DESIGN fad_main_tb
     89VIEW struct.bd
     90GRAPHIC 284,0 66 0
     91DESIGN fad_main_tb
     92VIEW struct.bd
     93GRAPHIC 1467,0 67 0
     94DESIGN fad_main_tb
     95VIEW struct.bd
     96GRAPHIC 448,0 68 0
     97DESIGN fad_main_tb
     98VIEW struct.bd
     99GRAPHIC 799,0 69 0
     100DESIGN fad_main_tb
     101VIEW struct.bd
     102GRAPHIC 815,0 70 0
     103DESIGN fad_main_tb
     104VIEW struct.bd
     105GRAPHIC 839,0 71 0
     106DESIGN fad_main_tb
     107VIEW struct.bd
     108GRAPHIC 847,0 72 0
     109DESIGN fad_main_tb
     110VIEW struct.bd
     111GRAPHIC 1459,0 73 0
     112DESIGN fad_main_tb
     113VIEW struct.bd
     114GRAPHIC 775,0 74 0
     115DESIGN fad_main_tb
     116VIEW struct.bd
     117GRAPHIC 807,0 75 0
     118DESIGN fad_main_tb
     119VIEW struct.bd
     120GRAPHIC 1559,0 76 0
     121DESIGN fad_main_tb
     122VIEW struct.bd
     123GRAPHIC 1451,0 77 0
     124DESIGN fad_main_tb
     125VIEW struct.bd
     126GRAPHIC 378,0 78 0
     127DESIGN fad_main_tb
     128VIEW struct.bd
     129GRAPHIC 372,0 79 0
     130DESIGN fad_main_tb
     131VIEW struct.bd
     132GRAPHIC 384,0 80 0
     133DESIGN fad_main_tb
     134VIEW struct.bd
     135GRAPHIC 424,0 81 0
     136DESIGN fad_main_tb
     137VIEW struct.bd
     138GRAPHIC 316,0 82 0
     139DESIGN fad_main_tb
     140VIEW struct.bd
     141GRAPHIC 783,0 83 0
     142DESIGN fad_main_tb
     143VIEW struct.bd
     144GRAPHIC 322,0 84 0
     145DESIGN fad_main_tb
     146VIEW struct.bd
     147GRAPHIC 791,0 85 0
     148DESIGN fad_main_tb
     149VIEW struct.bd
     150GRAPHIC 328,0 86 0
     151DESIGN fad_main_tb
     152VIEW struct.bd
     153GRAPHIC 767,0 87 0
     154DESIGN fad_main_tb
     155VIEW struct.bd
     156GRAPHIC 334,0 88 0
     157DESIGN fad_main_tb
     158VIEW struct.bd
     159NO_GRAPHIC 89
     160DESIGN fad_main_tb
     161VIEW struct.bd
     162NO_GRAPHIC 90
    130163LIBRARY FACT_FAD_lib
    131164DESIGN @f@a@d_main
    132165VIEW struct
    133 GRAPHIC 233,0 81 0
    134 DESIGN @f@a@d_main
    135 VIEW symbol.sb
    136 GRAPHIC 14,0 82 1
    137 DESIGN @f@a@d_main
    138 VIEW symbol.sb
    139 GRAPHIC 1755,0 86 0
    140 DESIGN @f@a@d_main
    141 VIEW symbol.sb
    142 GRAPHIC 2710,0 87 0
    143 DESIGN @f@a@d_main
    144 VIEW symbol.sb
    145 GRAPHIC 2715,0 88 0
    146 DESIGN @f@a@d_main
    147 VIEW symbol.sb
    148 GRAPHIC 2720,0 89 0
    149 DESIGN @f@a@d_main
    150 VIEW symbol.sb
    151 GRAPHIC 2725,0 90 0
    152 DESIGN @f@a@d_main
    153 VIEW symbol.sb
    154 GRAPHIC 2282,0 91 0
    155 DESIGN @f@a@d_main
    156 VIEW symbol.sb
    157 GRAPHIC 1976,0 92 0
    158 DESIGN @f@a@d_main
    159 VIEW symbol.sb
    160 GRAPHIC 923,0 93 0
    161 DESIGN @f@a@d_main
    162 VIEW symbol.sb
    163 GRAPHIC 928,0 94 0
    164 DESIGN @f@a@d_main
    165 VIEW symbol.sb
    166 GRAPHIC 464,0 95 0
    167 DESIGN @f@a@d_main
    168 VIEW symbol.sb
    169 GRAPHIC 1062,0 96 0
    170 DESIGN @f@a@d_main
    171 VIEW symbol.sb
    172 GRAPHIC 1389,0 97 0
    173 DESIGN @f@a@d_main
    174 VIEW symbol.sb
    175 GRAPHIC 1725,0 98 0
    176 DESIGN @f@a@d_main
    177 VIEW symbol.sb
    178 GRAPHIC 2987,0 99 0
    179 DESIGN @f@a@d_main
    180 VIEW symbol.sb
    181 GRAPHIC 2992,0 100 0
    182 DESIGN @f@a@d_main
    183 VIEW symbol.sb
    184 GRAPHIC 833,0 101 0
    185 DESIGN @f@a@d_main
    186 VIEW symbol.sb
    187 GRAPHIC 3641,0 102 0
    188 DESIGN @f@a@d_main
    189 VIEW symbol.sb
    190 GRAPHIC 4144,0 103 0
    191 DESIGN @f@a@d_main
    192 VIEW symbol.sb
    193 GRAPHIC 2448,0 104 0
    194 DESIGN @f@a@d_main
    195 VIEW symbol.sb
    196 GRAPHIC 2453,0 105 0
    197 DESIGN @f@a@d_main
    198 VIEW symbol.sb
    199 GRAPHIC 163,0 106 0
    200 DESIGN @f@a@d_main
    201 VIEW symbol.sb
    202 GRAPHIC 4067,0 107 0
    203 DESIGN @f@a@d_main
    204 VIEW symbol.sb
    205 GRAPHIC 3631,0 108 0
    206 DESIGN @f@a@d_main
    207 VIEW symbol.sb
    208 GRAPHIC 3646,0 109 0
    209 DESIGN @f@a@d_main
    210 VIEW symbol.sb
    211 GRAPHIC 1037,0 110 0
    212 DESIGN @f@a@d_main
    213 VIEW symbol.sb
    214 GRAPHIC 1047,0 111 0
    215 DESIGN @f@a@d_main
    216 VIEW symbol.sb
    217 GRAPHIC 1057,0 112 0
    218 DESIGN @f@a@d_main
    219 VIEW symbol.sb
    220 GRAPHIC 135,0 113 0
    221 DESIGN @f@a@d_main
    222 VIEW symbol.sb
    223 GRAPHIC 1052,0 114 0
    224 DESIGN @f@a@d_main
    225 VIEW symbol.sb
    226 GRAPHIC 3636,0 115 0
    227 DESIGN @f@a@d_main
    228 VIEW symbol.sb
    229 GRAPHIC 1042,0 116 0
     166GRAPHIC 233,0 92 0
     167DESIGN @f@a@d_main
     168VIEW symbol.sb
     169GRAPHIC 14,0 93 1
     170DESIGN @f@a@d_main
     171VIEW symbol.sb
     172GRAPHIC 1755,0 97 0
     173DESIGN @f@a@d_main
     174VIEW symbol.sb
     175GRAPHIC 5328,0 98 0
     176DESIGN @f@a@d_main
     177VIEW symbol.sb
     178GRAPHIC 2710,0 99 0
     179DESIGN @f@a@d_main
     180VIEW symbol.sb
     181GRAPHIC 2715,0 100 0
     182DESIGN @f@a@d_main
     183VIEW symbol.sb
     184GRAPHIC 2720,0 101 0
     185DESIGN @f@a@d_main
     186VIEW symbol.sb
     187GRAPHIC 2725,0 102 0
     188DESIGN @f@a@d_main
     189VIEW symbol.sb
     190GRAPHIC 2282,0 103 0
     191DESIGN @f@a@d_main
     192VIEW symbol.sb
     193GRAPHIC 1976,0 104 0
     194DESIGN @f@a@d_main
     195VIEW symbol.sb
     196GRAPHIC 923,0 105 0
     197DESIGN @f@a@d_main
     198VIEW symbol.sb
     199GRAPHIC 928,0 106 0
     200DESIGN @f@a@d_main
     201VIEW symbol.sb
     202GRAPHIC 5427,0 107 0
     203DESIGN @f@a@d_main
     204VIEW symbol.sb
     205GRAPHIC 5503,0 108 0
     206DESIGN @f@a@d_main
     207VIEW symbol.sb
     208GRAPHIC 464,0 109 0
     209DESIGN @f@a@d_main
     210VIEW symbol.sb
     211GRAPHIC 1062,0 110 0
     212DESIGN @f@a@d_main
     213VIEW symbol.sb
     214GRAPHIC 6704,0 111 0
     215DESIGN @f@a@d_main
     216VIEW symbol.sb
     217GRAPHIC 1389,0 112 0
     218DESIGN @f@a@d_main
     219VIEW symbol.sb
     220GRAPHIC 1725,0 113 0
     221DESIGN @f@a@d_main
     222VIEW symbol.sb
     223GRAPHIC 2987,0 114 0
     224DESIGN @f@a@d_main
     225VIEW symbol.sb
     226GRAPHIC 2992,0 115 0
     227DESIGN @f@a@d_main
     228VIEW symbol.sb
     229GRAPHIC 4780,0 116 0
     230DESIGN @f@a@d_main
     231VIEW symbol.sb
     232GRAPHIC 833,0 117 0
     233DESIGN @f@a@d_main
     234VIEW symbol.sb
     235GRAPHIC 5634,0 118 0
     236DESIGN @f@a@d_main
     237VIEW symbol.sb
     238GRAPHIC 5639,0 119 0
     239DESIGN @f@a@d_main
     240VIEW symbol.sb
     241GRAPHIC 4911,0 120 0
     242DESIGN @f@a@d_main
     243VIEW symbol.sb
     244GRAPHIC 5629,0 121 0
     245DESIGN @f@a@d_main
     246VIEW symbol.sb
     247GRAPHIC 3641,0 122 0
     248DESIGN @f@a@d_main
     249VIEW symbol.sb
     250GRAPHIC 4144,0 123 0
     251DESIGN @f@a@d_main
     252VIEW symbol.sb
     253GRAPHIC 2448,0 124 0
     254DESIGN @f@a@d_main
     255VIEW symbol.sb
     256GRAPHIC 2453,0 125 0
     257DESIGN @f@a@d_main
     258VIEW symbol.sb
     259GRAPHIC 4906,0 126 0
     260DESIGN @f@a@d_main
     261VIEW symbol.sb
     262GRAPHIC 163,0 127 0
     263DESIGN @f@a@d_main
     264VIEW symbol.sb
     265GRAPHIC 4067,0 128 0
     266DESIGN @f@a@d_main
     267VIEW symbol.sb
     268GRAPHIC 4916,0 129 0
     269DESIGN @f@a@d_main
     270VIEW symbol.sb
     271GRAPHIC 3631,0 130 0
     272DESIGN @f@a@d_main
     273VIEW symbol.sb
     274GRAPHIC 3646,0 131 0
     275DESIGN @f@a@d_main
     276VIEW symbol.sb
     277GRAPHIC 1037,0 132 0
     278DESIGN @f@a@d_main
     279VIEW symbol.sb
     280GRAPHIC 1047,0 133 0
     281DESIGN @f@a@d_main
     282VIEW symbol.sb
     283GRAPHIC 1057,0 134 0
     284DESIGN @f@a@d_main
     285VIEW symbol.sb
     286GRAPHIC 135,0 135 0
     287DESIGN @f@a@d_main
     288VIEW symbol.sb
     289GRAPHIC 1052,0 136 0
     290DESIGN @f@a@d_main
     291VIEW symbol.sb
     292GRAPHIC 3636,0 137 0
     293DESIGN @f@a@d_main
     294VIEW symbol.sb
     295GRAPHIC 1042,0 138 0
    230296LIBRARY FACT_FAD_TB_lib
    231297DESIGN adc_emulator
    232298VIEW @behavioral
    233 GRAPHIC 508,0 119 0
     299GRAPHIC 508,0 141 0
    234300DESIGN adc_emulator
    235301VIEW symbol.sb
    236 GRAPHIC 14,0 120 1
     302GRAPHIC 14,0 142 1
    237303DESIGN adc_emulator
    238304VIEW @behavioral
    239 GRAPHIC 48,0 124 0
     305GRAPHIC 48,0 146 0
    240306DESIGN adc_emulator
    241307VIEW @behavioral
    242 GRAPHIC 53,0 125 0
     308GRAPHIC 53,0 147 0
    243309DESIGN adc_emulator
    244310VIEW @behavioral
    245 GRAPHIC 58,0 126 0
     311GRAPHIC 58,0 148 0
    246312DESIGN adc_emulator
    247313VIEW @behavioral
    248 GRAPHIC 63,0 127 0
    249 DESIGN fad_main_tb
    250 VIEW struct.bd
    251 GRAPHIC 274,0 130 0
     314GRAPHIC 63,0 149 0
     315DESIGN fad_main_tb
     316VIEW struct.bd
     317GRAPHIC 274,0 152 0
    252318DESIGN clock_generator
    253319VIEW symbol.sb
    254 GRAPHIC 14,0 131 1
     320GRAPHIC 14,0 153 1
    255321DESIGN clock_generator
    256322VIEW @behavioral
    257 GRAPHIC 48,0 136 0
     323GRAPHIC 48,0 158 0
    258324DESIGN clock_generator
    259325VIEW @behavioral
    260 GRAPHIC 53,0 137 0
    261 DESIGN fad_main_tb
    262 VIEW struct.bd
    263 GRAPHIC 362,0 140 0
     326GRAPHIC 53,0 159 0
     327DESIGN fad_main_tb
     328VIEW struct.bd
     329GRAPHIC 362,0 162 0
    264330DESIGN max6662_emulator
    265331VIEW symbol.sb
    266 GRAPHIC 14,0 141 1
     332GRAPHIC 14,0 163 1
    267333DESIGN max6662_emulator
    268334VIEW beha
    269 GRAPHIC 48,0 145 0
     335GRAPHIC 48,0 167 0
    270336DESIGN max6662_emulator
    271337VIEW beha
    272 GRAPHIC 53,0 146 0
     338GRAPHIC 53,0 168 0
    273339DESIGN max6662_emulator
    274340VIEW beha
    275 GRAPHIC 58,0 147 0
    276 DESIGN fad_main_tb
    277 VIEW struct.bd
    278 GRAPHIC 414,0 150 0
     341GRAPHIC 58,0 169 0
     342DESIGN fad_main_tb
     343VIEW struct.bd
     344GRAPHIC 414,0 172 0
    279345DESIGN trigger_generator
    280346VIEW symbol.sb
    281 GRAPHIC 14,0 151 1
     347GRAPHIC 14,0 173 1
    282348DESIGN trigger_generator
    283349VIEW beha
    284 GRAPHIC 48,0 156 0
    285 DESIGN fad_main_tb
    286 VIEW struct.bd
    287 GRAPHIC 306,0 159 0
     350GRAPHIC 48,0 178 0
     351DESIGN fad_main_tb
     352VIEW struct.bd
     353GRAPHIC 306,0 181 0
    288354DESIGN w5300_emulator
    289355VIEW beha
    290 GRAPHIC 48,0 161 0
     356GRAPHIC 163,0 183 0
    291357DESIGN w5300_emulator
    292358VIEW beha
    293 GRAPHIC 53,0 162 0
     359GRAPHIC 48,0 184 0
    294360DESIGN w5300_emulator
    295361VIEW beha
    296 GRAPHIC 58,0 163 0
     362GRAPHIC 53,0 185 0
    297363DESIGN w5300_emulator
    298364VIEW beha
    299 GRAPHIC 63,0 164 0
     365GRAPHIC 58,0 186 0
     366DESIGN w5300_emulator
     367VIEW beha
     368GRAPHIC 63,0 187 0
    300369LIBRARY FACT_FAD_TB_lib
    301370DESIGN fad_main_tb
    302371VIEW struct.bd
    303 NO_GRAPHIC 167
    304 DESIGN fad_main_tb
    305 VIEW struct.bd
    306 GRAPHIC 233,0 170 0
    307 DESIGN fad_main_tb
    308 VIEW struct.bd
    309 GRAPHIC 508,0 171 0
    310 DESIGN fad_main_tb
    311 VIEW struct.bd
    312 GRAPHIC 274,0 172 0
    313 DESIGN fad_main_tb
    314 VIEW struct.bd
    315 GRAPHIC 362,0 173 0
    316 DESIGN fad_main_tb
    317 VIEW struct.bd
    318 GRAPHIC 414,0 174 0
    319 DESIGN fad_main_tb
    320 VIEW struct.bd
    321 GRAPHIC 306,0 175 0
    322 DESIGN fad_main_tb
    323 VIEW struct.bd
    324 NO_GRAPHIC 178
    325 DESIGN fad_main_tb
    326 VIEW struct.bd
    327 GRAPHIC 430,0 181 0
    328 DESIGN fad_main_tb
    329 VIEW struct.bd
    330 NO_GRAPHIC 185
    331 DESIGN fad_main_tb
    332 VIEW struct.bd
    333 GRAPHIC 518,0 186 0
    334 DESIGN fad_main_tb
    335 VIEW struct.bd
    336 NO_GRAPHIC 196
    337 DESIGN fad_main_tb
    338 VIEW struct.bd
    339 NO_GRAPHIC 197
    340 DESIGN fad_main_tb
    341 VIEW struct.bd
    342 GRAPHIC 233,0 199 0
    343 DESIGN fad_main_tb
    344 VIEW struct.bd
    345 GRAPHIC 240,0 200 1
    346 DESIGN fad_main_tb
    347 VIEW struct.bd
    348 GRAPHIC 286,0 204 0
    349 DESIGN fad_main_tb
    350 VIEW struct.bd
    351 GRAPHIC 873,0 205 0
    352 DESIGN fad_main_tb
    353 VIEW struct.bd
    354 GRAPHIC 881,0 206 0
    355 DESIGN fad_main_tb
    356 VIEW struct.bd
    357 GRAPHIC 889,0 207 0
    358 DESIGN fad_main_tb
    359 VIEW struct.bd
    360 GRAPHIC 897,0 208 0
    361 DESIGN fad_main_tb
    362 VIEW struct.bd
    363 GRAPHIC 538,0 209 0
    364 DESIGN fad_main_tb
    365 VIEW struct.bd
    366 GRAPHIC 530,0 210 0
    367 DESIGN fad_main_tb
    368 VIEW struct.bd
    369 GRAPHIC 442,0 211 0
    370 DESIGN fad_main_tb
    371 VIEW struct.bd
    372 GRAPHIC 450,0 212 0
    373 DESIGN fad_main_tb
    374 VIEW struct.bd
    375 GRAPHIC 426,0 213 0
    376 DESIGN fad_main_tb
    377 VIEW struct.bd
    378 GRAPHIC 793,0 214 0
    379 DESIGN fad_main_tb
    380 VIEW struct.bd
    381 GRAPHIC 825,0 215 0
    382 DESIGN fad_main_tb
    383 VIEW struct.bd
    384 GRAPHIC 833,0 216 0
    385 DESIGN fad_main_tb
    386 VIEW struct.bd
    387 GRAPHIC 857,0 217 0
    388 DESIGN fad_main_tb
    389 VIEW struct.bd
    390 GRAPHIC 865,0 218 0
    391 DESIGN fad_main_tb
    392 VIEW struct.bd
    393 GRAPHIC 546,0 219 0
    394 DESIGN fad_main_tb
    395 VIEW struct.bd
    396 GRAPHIC 801,0 220 0
    397 DESIGN fad_main_tb
    398 VIEW struct.bd
    399 GRAPHIC 817,0 221 0
    400 DESIGN fad_main_tb
    401 VIEW struct.bd
    402 GRAPHIC 841,0 222 0
    403 DESIGN fad_main_tb
    404 VIEW struct.bd
    405 GRAPHIC 849,0 223 0
    406 DESIGN fad_main_tb
    407 VIEW struct.bd
    408 GRAPHIC 777,0 224 0
    409 DESIGN fad_main_tb
    410 VIEW struct.bd
    411 GRAPHIC 809,0 225 0
    412 DESIGN fad_main_tb
    413 VIEW struct.bd
    414 GRAPHIC 380,0 226 0
    415 DESIGN fad_main_tb
    416 VIEW struct.bd
    417 GRAPHIC 374,0 227 0
    418 DESIGN fad_main_tb
    419 VIEW struct.bd
    420 GRAPHIC 318,0 228 0
    421 DESIGN fad_main_tb
    422 VIEW struct.bd
    423 GRAPHIC 785,0 229 0
    424 DESIGN fad_main_tb
    425 VIEW struct.bd
    426 GRAPHIC 330,0 230 0
    427 DESIGN fad_main_tb
    428 VIEW struct.bd
    429 GRAPHIC 769,0 231 0
    430 DESIGN fad_main_tb
    431 VIEW struct.bd
    432 GRAPHIC 336,0 232 0
    433 DESIGN fad_main_tb
    434 VIEW struct.bd
    435 GRAPHIC 386,0 233 0
    436 DESIGN fad_main_tb
    437 VIEW struct.bd
    438 GRAPHIC 324,0 234 0
    439 DESIGN fad_main_tb
    440 VIEW struct.bd
    441 GRAPHIC 508,0 236 0
    442 DESIGN fad_main_tb
    443 VIEW struct.bd
    444 GRAPHIC 515,0 237 1
    445 DESIGN fad_main_tb
    446 VIEW struct.bd
    447 GRAPHIC 578,0 241 0
    448 DESIGN fad_main_tb
    449 VIEW struct.bd
    450 GRAPHIC 570,0 242 0
    451 DESIGN fad_main_tb
    452 VIEW struct.bd
    453 GRAPHIC 562,0 243 0
    454 DESIGN fad_main_tb
    455 VIEW struct.bd
    456 GRAPHIC 554,0 244 0
    457 DESIGN fad_main_tb
    458 VIEW struct.bd
    459 GRAPHIC 274,0 246 0
    460 DESIGN fad_main_tb
    461 VIEW struct.bd
    462 GRAPHIC 281,0 247 1
    463 DESIGN fad_main_tb
    464 VIEW struct.bd
    465 GRAPHIC 286,0 252 0
    466 DESIGN fad_main_tb
    467 VIEW struct.bd
    468 GRAPHIC 362,0 255 0
    469 DESIGN fad_main_tb
    470 VIEW struct.bd
    471 GRAPHIC 369,0 256 1
    472 DESIGN fad_main_tb
    473 VIEW struct.bd
    474 GRAPHIC 380,0 260 0
    475 DESIGN fad_main_tb
    476 VIEW struct.bd
    477 GRAPHIC 386,0 261 0
    478 DESIGN fad_main_tb
    479 VIEW struct.bd
    480 GRAPHIC 374,0 262 0
    481 DESIGN fad_main_tb
    482 VIEW struct.bd
    483 GRAPHIC 414,0 264 0
    484 DESIGN fad_main_tb
    485 VIEW struct.bd
    486 GRAPHIC 421,0 265 1
    487 DESIGN fad_main_tb
    488 VIEW struct.bd
    489 GRAPHIC 426,0 270 0
    490 DESIGN fad_main_tb
    491 VIEW struct.bd
    492 GRAPHIC 306,0 272 0
    493 DESIGN fad_main_tb
    494 VIEW struct.bd
    495 GRAPHIC 318,0 274 0
    496 DESIGN fad_main_tb
    497 VIEW struct.bd
    498 GRAPHIC 324,0 275 0
    499 DESIGN fad_main_tb
    500 VIEW struct.bd
    501 GRAPHIC 330,0 276 0
    502 DESIGN fad_main_tb
    503 VIEW struct.bd
    504 GRAPHIC 336,0 277 0
    505 DESIGN fad_main_tb
    506 VIEW struct.bd
    507 NO_GRAPHIC 280
     372NO_GRAPHIC 190
     373DESIGN fad_main_tb
     374VIEW struct.bd
     375GRAPHIC 233,0 193 0
     376DESIGN fad_main_tb
     377VIEW struct.bd
     378GRAPHIC 508,0 194 0
     379DESIGN fad_main_tb
     380VIEW struct.bd
     381GRAPHIC 274,0 195 0
     382DESIGN fad_main_tb
     383VIEW struct.bd
     384GRAPHIC 362,0 196 0
     385DESIGN fad_main_tb
     386VIEW struct.bd
     387GRAPHIC 414,0 197 0
     388DESIGN fad_main_tb
     389VIEW struct.bd
     390GRAPHIC 306,0 198 0
     391DESIGN fad_main_tb
     392VIEW struct.bd
     393NO_GRAPHIC 201
     394DESIGN fad_main_tb
     395VIEW struct.bd
     396GRAPHIC 430,0 204 0
     397DESIGN fad_main_tb
     398VIEW struct.bd
     399NO_GRAPHIC 208
     400DESIGN fad_main_tb
     401VIEW struct.bd
     402GRAPHIC 518,0 209 0
     403DESIGN fad_main_tb
     404VIEW struct.bd
     405NO_GRAPHIC 219
     406DESIGN fad_main_tb
     407VIEW struct.bd
     408GRAPHIC 1491,0 220 0
     409DESIGN fad_main_tb
     410VIEW struct.bd
     411NO_GRAPHIC 228
     412DESIGN fad_main_tb
     413VIEW struct.bd
     414NO_GRAPHIC 229
     415DESIGN fad_main_tb
     416VIEW struct.bd
     417GRAPHIC 233,0 231 0
     418DESIGN fad_main_tb
     419VIEW struct.bd
     420GRAPHIC 240,0 232 1
     421DESIGN fad_main_tb
     422VIEW struct.bd
     423GRAPHIC 286,0 236 0
     424DESIGN fad_main_tb
     425VIEW struct.bd
     426GRAPHIC 1503,0 237 0
     427DESIGN fad_main_tb
     428VIEW struct.bd
     429GRAPHIC 873,0 238 0
     430DESIGN fad_main_tb
     431VIEW struct.bd
     432GRAPHIC 881,0 239 0
     433DESIGN fad_main_tb
     434VIEW struct.bd
     435GRAPHIC 889,0 240 0
     436DESIGN fad_main_tb
     437VIEW struct.bd
     438GRAPHIC 897,0 241 0
     439DESIGN fad_main_tb
     440VIEW struct.bd
     441GRAPHIC 538,0 242 0
     442DESIGN fad_main_tb
     443VIEW struct.bd
     444GRAPHIC 530,0 243 0
     445DESIGN fad_main_tb
     446VIEW struct.bd
     447GRAPHIC 442,0 244 0
     448DESIGN fad_main_tb
     449VIEW struct.bd
     450GRAPHIC 450,0 245 0
     451DESIGN fad_main_tb
     452VIEW struct.bd
     453GRAPHIC 1529,0 246 0
     454DESIGN fad_main_tb
     455VIEW struct.bd
     456GRAPHIC 1561,0 247 0
     457DESIGN fad_main_tb
     458VIEW struct.bd
     459GRAPHIC 426,0 248 0
     460DESIGN fad_main_tb
     461VIEW struct.bd
     462GRAPHIC 793,0 249 0
     463DESIGN fad_main_tb
     464VIEW struct.bd
     465GRAPHIC 1684,0 250 0
     466DESIGN fad_main_tb
     467VIEW struct.bd
     468GRAPHIC 825,0 251 0
     469DESIGN fad_main_tb
     470VIEW struct.bd
     471GRAPHIC 833,0 252 0
     472DESIGN fad_main_tb
     473VIEW struct.bd
     474GRAPHIC 857,0 253 0
     475DESIGN fad_main_tb
     476VIEW struct.bd
     477GRAPHIC 865,0 254 0
     478DESIGN fad_main_tb
     479VIEW struct.bd
     480GRAPHIC 1437,0 255 0
     481DESIGN fad_main_tb
     482VIEW struct.bd
     483GRAPHIC 546,0 256 0
     484DESIGN fad_main_tb
     485VIEW struct.bd
     486GRAPHIC 1485,0 257 0
     487DESIGN fad_main_tb
     488VIEW struct.bd
     489GRAPHIC 1477,0 258 0
     490DESIGN fad_main_tb
     491VIEW struct.bd
     492GRAPHIC 1445,0 259 0
     493DESIGN fad_main_tb
     494VIEW struct.bd
     495GRAPHIC 1469,0 260 0
     496DESIGN fad_main_tb
     497VIEW struct.bd
     498GRAPHIC 801,0 261 0
     499DESIGN fad_main_tb
     500VIEW struct.bd
     501GRAPHIC 817,0 262 0
     502DESIGN fad_main_tb
     503VIEW struct.bd
     504GRAPHIC 841,0 263 0
     505DESIGN fad_main_tb
     506VIEW struct.bd
     507GRAPHIC 849,0 264 0
     508DESIGN fad_main_tb
     509VIEW struct.bd
     510GRAPHIC 1461,0 265 0
     511DESIGN fad_main_tb
     512VIEW struct.bd
     513GRAPHIC 777,0 266 0
     514DESIGN fad_main_tb
     515VIEW struct.bd
     516GRAPHIC 809,0 267 0
     517DESIGN fad_main_tb
     518VIEW struct.bd
     519GRAPHIC 1453,0 268 0
     520DESIGN fad_main_tb
     521VIEW struct.bd
     522GRAPHIC 380,0 269 0
     523DESIGN fad_main_tb
     524VIEW struct.bd
     525GRAPHIC 374,0 270 0
     526DESIGN fad_main_tb
     527VIEW struct.bd
     528GRAPHIC 318,0 271 0
     529DESIGN fad_main_tb
     530VIEW struct.bd
     531GRAPHIC 785,0 272 0
     532DESIGN fad_main_tb
     533VIEW struct.bd
     534GRAPHIC 330,0 273 0
     535DESIGN fad_main_tb
     536VIEW struct.bd
     537GRAPHIC 769,0 274 0
     538DESIGN fad_main_tb
     539VIEW struct.bd
     540GRAPHIC 336,0 275 0
     541DESIGN fad_main_tb
     542VIEW struct.bd
     543GRAPHIC 386,0 276 0
     544DESIGN fad_main_tb
     545VIEW struct.bd
     546GRAPHIC 324,0 277 0
     547DESIGN fad_main_tb
     548VIEW struct.bd
     549GRAPHIC 508,0 279 0
     550DESIGN fad_main_tb
     551VIEW struct.bd
     552GRAPHIC 515,0 280 1
     553DESIGN fad_main_tb
     554VIEW struct.bd
     555GRAPHIC 578,0 284 0
     556DESIGN fad_main_tb
     557VIEW struct.bd
     558GRAPHIC 570,0 285 0
     559DESIGN fad_main_tb
     560VIEW struct.bd
     561GRAPHIC 562,0 286 0
     562DESIGN fad_main_tb
     563VIEW struct.bd
     564GRAPHIC 554,0 287 0
     565DESIGN fad_main_tb
     566VIEW struct.bd
     567GRAPHIC 274,0 289 0
     568DESIGN fad_main_tb
     569VIEW struct.bd
     570GRAPHIC 281,0 290 1
     571DESIGN fad_main_tb
     572VIEW struct.bd
     573GRAPHIC 286,0 295 0
     574DESIGN fad_main_tb
     575VIEW struct.bd
     576GRAPHIC 1509,0 298 0
     577DESIGN fad_main_tb
     578VIEW struct.bd
     579GRAPHIC 1516,0 299 1
     580DESIGN fad_main_tb
     581VIEW struct.bd
     582GRAPHIC 1529,0 304 0
     583DESIGN fad_main_tb
     584VIEW struct.bd
     585GRAPHIC 362,0 307 0
     586DESIGN fad_main_tb
     587VIEW struct.bd
     588GRAPHIC 369,0 308 1
     589DESIGN fad_main_tb
     590VIEW struct.bd
     591GRAPHIC 380,0 312 0
     592DESIGN fad_main_tb
     593VIEW struct.bd
     594GRAPHIC 386,0 313 0
     595DESIGN fad_main_tb
     596VIEW struct.bd
     597GRAPHIC 374,0 314 0
     598DESIGN fad_main_tb
     599VIEW struct.bd
     600GRAPHIC 414,0 316 0
     601DESIGN fad_main_tb
     602VIEW struct.bd
     603GRAPHIC 421,0 317 1
     604DESIGN fad_main_tb
     605VIEW struct.bd
     606GRAPHIC 426,0 322 0
     607DESIGN fad_main_tb
     608VIEW struct.bd
     609GRAPHIC 306,0 324 0
     610DESIGN fad_main_tb
     611VIEW struct.bd
     612GRAPHIC 793,0 326 0
     613DESIGN fad_main_tb
     614VIEW struct.bd
     615GRAPHIC 318,0 327 0
     616DESIGN fad_main_tb
     617VIEW struct.bd
     618GRAPHIC 324,0 328 0
     619DESIGN fad_main_tb
     620VIEW struct.bd
     621GRAPHIC 330,0 329 0
     622DESIGN fad_main_tb
     623VIEW struct.bd
     624GRAPHIC 336,0 330 0
     625DESIGN fad_main_tb
     626VIEW struct.bd
     627NO_GRAPHIC 333

  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/fad_main_tb/struct.bd

    r9912 r10180  
    118118uid 508,0
    119119)
     120(Instance
     121name "I_mainTB_clock1"
     122duLibraryName "FACT_FAD_TB_lib"
     123duName "clock_generator"
     124elements [
     125(GiElement
     126name "clock_period"
     127type "time"
     128value "1 us"
     129)
     130(GiElement
     131name "reset_time"
     132type "time"
     133value "1 us"
     134)
     135]
     136mwi 0
     137uid 1509,0
     138)
    120139]
    121140embeddedInstances [
    … …  
    127146name "eb_mainTB_adc"
    128147number "2"
     148)
     149(EmbeddedInstance
     150name "eb_mainTB_adc1"
     151number "3"
    129152)
    130153]
    … …  
    143166(vvPair
    144167variable "HDLDir"
    145 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hdl"
     168value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
    146169)
    147170(vvPair
    148171variable "HDSDir"
    149 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds"
     172value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
    150173)
    151174(vvPair
    152175variable "SideDataDesignDir"
    153 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.info"
     176value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.info"
    154177)
    155178(vvPair
    156179variable "SideDataUserDir"
    157 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.user"
     180value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.user"
    158181)
    159182(vvPair
    160183variable "SourceDir"
    161 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds"
     184value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
    162185)
    163186(vvPair
    … …  
    171194(vvPair
    172195variable "config"
    173 value "%(unit)_config"
     196value "%(unit)_%(view)_config"
    174197)
    175198(vvPair
    176199variable "d"
    177 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb"
     200value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb"
    178201)
    179202(vvPair
    180203variable "d_logical"
    181 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb"
     204value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb"
    182205)
    183206(vvPair
    184207variable "date"
    185 value "25.06.2010"
     208value "25.02.2011"
    186209)
    187210(vvPair
    … …  
    223246(vvPair
    224247variable "host"
    225 value "EEPC8"
     248value "E5B-LABOR6"
    226249)
    227250(vvPair
    … …  
    234257)
    235258(vvPair
     259variable "library_downstream_HdsLintPlugin"
     260value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/designcheck"
     261)
     262(vvPair
     263variable "library_downstream_ISEPARInvoke"
     264value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
     265)
     266(vvPair
     267variable "library_downstream_ImpactInvoke"
     268value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
     269)
     270(vvPair
    236271variable "library_downstream_ModelSimCompiler"
    237272value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/work"
    238273)
    239274(vvPair
     275variable "library_downstream_XSTDataPrep"
     276value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
     277)
     278(vvPair
    240279variable "mm"
    241 value "06"
     280value "02"
    242281)
    243282(vvPair
    … …  
    247286(vvPair
    248287variable "month"
    249 value "Jun"
     288value "Feb"
    250289)
    251290(vvPair
    252291variable "month_long"
    253 value "Juni"
     292value "Februar"
    254293)
    255294(vvPair
    256295variable "p"
    257 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"
     296value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"
    258297)
    259298(vvPair
    260299variable "p_logical"
    261 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"
     300value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"
    262301)
    263302(vvPair
    … …  
    283322(vvPair
    284323variable "task_ModelSimPath"
    285 value "$HDS_HOME/../Modeltech/win32"
     324value "C:\\modeltech_6.6a\\win32"
    286325)
    287326(vvPair
    … …  
    291330(vvPair
    292331variable "task_PrecisionRTLPath"
    293 value "$HDS_HOME/../Precision/Mgc_home/bin"
     332value "<TBD>"
    294333)
    295334(vvPair
    … …  
    315354(vvPair
    316355variable "time"
    317 value "08:48:16"
     356value "13:51:45"
    318357)
    319358(vvPair
    … …  
    323362(vvPair
    324363variable "user"
    325 value "Benjamin Krumm"
     364value "dneise"
    326365)
    327366(vvPair
    … …  
    335374(vvPair
    336375variable "year"
    337 value "2010"
     376value "2011"
    338377)
    339378(vvPair
    340379variable "yy"
    341 value "10"
     380value "11"
    342381)
    343382]
    … …  
    367406bg "0,0,32768"
    368407)
    369 xt "109200,97000,122200,98000"
     408xt "109200,97000,118800,98000"
    370409st "
    371410by %user on %dd %month %year
    … …  
    706745n "wiz_reset"
    707746t "std_logic"
    708 o 28
     747o 39
    709748suid 2,0
    710749i "'1'"
    … …  
    745784b "(7 DOWNTO 0)"
    746785posAdd 0
    747 o 21
     786o 31
    748787suid 7,0
    749788i "(OTHERS => '0')"
    … …  
    782821preAdd 0
    783822posAdd 0
    784 o 10
     823o 13
    785824suid 18,0
    786825)
    … …  
    817856n "adc_oeb"
    818857t "std_logic"
    819 o 16
     858o 21
    820859suid 21,0
    821860i "'1'"
    … …  
    852891n "board_id"
    853892t "std_logic_vector"
    854 b "(3 downto 0)"
    855 preAdd 0
    856 posAdd 0
    857 o 8
     893b "(3 DOWNTO 0)"
     894o 9
    858895suid 24,0
    859896)
    … …  
    889926n "crate_id"
    890927t "std_logic_vector"
    891 b "(1 downto 0)"
    892 o 9
     928b "(1 DOWNTO 0)"
     929o 10
    893930suid 25,0
    894931)
    … …  
    927964t "std_logic_vector"
    928965b "(9 DOWNTO 0)"
    929 o 25
     966o 36
    930967suid 26,0
    931968)
    … …  
    9641001t "std_logic_vector"
    9651002b "(15 DOWNTO 0)"
    966 o 31
     1003o 42
    9671004suid 27,0
    9681005)
    … …  
    10001037n "wiz_cs"
    10011038t "std_logic"
    1002 o 26
     1039o 37
    10031040suid 28,0
    10041041i "'1'"
    … …  
    10371074n "wiz_wr"
    10381075t "std_logic"
    1039 o 29
     1076o 40
    10401077suid 29,0
    10411078i "'1'"
    … …  
    10741111n "wiz_rd"
    10751112t "std_logic"
    1076 o 27
     1113o 38
    10771114suid 30,0
    10781115i "'1'"
    … …  
    11101147n "wiz_int"
    11111148t "std_logic"
    1112 o 11
     1149o 14
    11131150suid 31,0
    11141151)
    … …  
    11451182n "CLK_25_PS"
    11461183t "std_logic"
    1147 o 12
     1184o 16
    11481185suid 35,0
    11491186)
    … …  
    11801217n "CLK_50"
    11811218t "std_logic"
    1182 o 13
     1219preAdd 0
     1220posAdd 0
     1221o 17
    11831222suid 37,0
    11841223)
    … …  
    12491288t "std_logic_vector"
    12501289b "(3 DOWNTO 0)"
    1251 o 7
     1290o 8
    12521291suid 40,0
    12531292)
    … …  
    12831322n "adc_data_array"
    12841323t "adc_data_array_type"
    1285 o 6
     1324o 7
    12861325suid 41,0
    12871326)
    … …  
    13191358t "std_logic_vector"
    13201359b "(3 downto 0)"
    1321 o 19
     1360o 28
    13221361suid 48,0
    13231362i "(others => '0')"
    … …  
    13551394n "drs_dwrite"
    13561395t "std_logic"
    1357 o 20
     1396o 29
    13581397suid 49,0
    13591398i "'1'"
    … …  
    13901429n "SROUT_in_0"
    13911430t "std_logic"
    1392 o 2
     1431o 3
    13931432suid 52,0
    13941433)
    … …  
    14241463n "SROUT_in_1"
    14251464t "std_logic"
    1426 o 3
     1465o 4
    14271466suid 53,0
    14281467)
    … …  
    14581497n "SROUT_in_2"
    14591498t "std_logic"
    1460 o 4
     1499o 5
    14611500suid 54,0
    14621501)
    … …  
    14921531n "SROUT_in_3"
    14931532t "std_logic"
    1494 o 5
     1533o 6
    14951534suid 55,0
    14961535)
    … …  
    15271566n "RSRLOAD"
    15281567t "std_logic"
    1529 o 14
     1568o 18
    15301569suid 56,0
    15311570i "'0'"
    … …  
    15631602n "SRCLK"
    15641603t "std_logic"
    1565 o 15
     1604o 19
    15661605suid 57,0
    15671606i "'0'"
    … …  
    16001639n "sclk"
    16011640t "std_logic"
    1602 o 23
     1641o 34
    16031642suid 62,0
    16041643)
    … …  
    16381677preAdd 0
    16391678posAdd 0
    1640 o 30
     1679o 41
    16411680suid 63,0
    16421681)
    … …  
    16741713n "dac_cs"
    16751714t "std_logic"
    1676 o 17
     1715o 26
    16771716suid 64,0
    16781717)
    … …  
    17111750t "std_logic_vector"
    17121751b "(3 DOWNTO 0)"
    1713 o 24
     1752o 35
    17141753suid 65,0
    17151754)
    … …  
    17471786n "mosi"
    17481787t "std_logic"
    1749 o 22
     1788o 32
    17501789suid 66,0
    17511790i "'0'"
    … …  
    17861825eolc "-- default domino wave off"
    17871826posAdd 0
    1788 o 18
     1827o 27
    17891828suid 67,0
    17901829i "'0'"
     1830)
     1831)
     1832)
     1833*44 (CptPort
     1834uid 1395,0
     1835ps "OnEdgeStrategy"
     1836shape (Triangle
     1837uid 1396,0
     1838ro 90
     1839va (VaSet
     1840vasetType 1
     1841fg "0,65535,0"
     1842)
     1843xt "109000,73625,109750,74375"
     1844)
     1845tg (CPTG
     1846uid 1397,0
     1847ps "CptPortTextPlaceStrategy"
     1848stg "RightVerticalLayoutStrategy"
     1849f (Text
     1850uid 1398,0
     1851va (VaSet
     1852)
     1853xt "99400,73500,108000,74500"
     1854st "alarm_refclk_too_high"
     1855ju 2
     1856blo "108000,74300"
     1857)
     1858)
     1859thePort (LogicalPort
     1860m 1
     1861decl (Decl
     1862n "alarm_refclk_too_high"
     1863t "std_logic"
     1864o 22
     1865suid 95,0
     1866)
     1867)
     1868)
     1869*45 (CptPort
     1870uid 1399,0
     1871ps "OnEdgeStrategy"
     1872shape (Triangle
     1873uid 1400,0
     1874ro 90
     1875va (VaSet
     1876vasetType 1
     1877fg "0,65535,0"
     1878)
     1879xt "109000,74625,109750,75375"
     1880)
     1881tg (CPTG
     1882uid 1401,0
     1883ps "CptPortTextPlaceStrategy"
     1884stg "RightVerticalLayoutStrategy"
     1885f (Text
     1886uid 1402,0
     1887va (VaSet
     1888)
     1889xt "99800,74500,108000,75500"
     1890st "alarm_refclk_too_low"
     1891ju 2
     1892blo "108000,75300"
     1893)
     1894)
     1895thePort (LogicalPort
     1896m 1
     1897decl (Decl
     1898n "alarm_refclk_too_low"
     1899t "std_logic"
     1900posAdd 0
     1901o 23
     1902suid 96,0
     1903)
     1904)
     1905)
     1906*46 (CptPort
     1907uid 1403,0
     1908ps "OnEdgeStrategy"
     1909shape (Triangle
     1910uid 1404,0
     1911ro 90
     1912va (VaSet
     1913vasetType 1
     1914fg "0,65535,0"
     1915)
     1916xt "109000,79625,109750,80375"
     1917)
     1918tg (CPTG
     1919uid 1405,0
     1920ps "CptPortTextPlaceStrategy"
     1921stg "RightVerticalLayoutStrategy"
     1922f (Text
     1923uid 1406,0
     1924va (VaSet
     1925)
     1926xt "105500,79500,108000,80500"
     1927st "amber"
     1928ju 2
     1929blo "108000,80300"
     1930)
     1931)
     1932thePort (LogicalPort
     1933m 1
     1934decl (Decl
     1935n "amber"
     1936t "std_logic"
     1937o 24
     1938suid 87,0
     1939)
     1940)
     1941)
     1942*47 (CptPort
     1943uid 1407,0
     1944ps "OnEdgeStrategy"
     1945shape (Triangle
     1946uid 1408,0
     1947ro 90
     1948va (VaSet
     1949vasetType 1
     1950fg "0,65535,0"
     1951)
     1952xt "109000,76625,109750,77375"
     1953)
     1954tg (CPTG
     1955uid 1409,0
     1956ps "CptPortTextPlaceStrategy"
     1957stg "RightVerticalLayoutStrategy"
     1958f (Text
     1959uid 1410,0
     1960va (VaSet
     1961)
     1962xt "99400,76500,108000,77500"
     1963st "counter_result : (11:0)"
     1964ju 2
     1965blo "108000,77300"
     1966)
     1967)
     1968thePort (LogicalPort
     1969m 1
     1970decl (Decl
     1971n "counter_result"
     1972t "std_logic_vector"
     1973b "(11 DOWNTO 0)"
     1974o 25
     1975suid 94,0
     1976)
     1977)
     1978)
     1979*48 (CptPort
     1980uid 1411,0
     1981ps "OnEdgeStrategy"
     1982shape (Triangle
     1983uid 1412,0
     1984ro 90
     1985va (VaSet
     1986vasetType 1
     1987fg "0,65535,0"
     1988)
     1989xt "80250,74625,81000,75375"
     1990)
     1991tg (CPTG
     1992uid 1413,0
     1993ps "CptPortTextPlaceStrategy"
     1994stg "VerticalLayoutStrategy"
     1995f (Text
     1996uid 1414,0
     1997va (VaSet
     1998)
     1999xt "82000,74500,87500,75500"
     2000st "D_T_in : (1:0)"
     2001blo "82000,75300"
     2002)
     2003)
     2004thePort (LogicalPort
     2005decl (Decl
     2006n "D_T_in"
     2007t "std_logic_vector"
     2008b "(1 DOWNTO 0)"
     2009o 2
     2010suid 91,0
     2011)
     2012)
     2013)
     2014*49 (CptPort
     2015uid 1415,0
     2016ps "OnEdgeStrategy"
     2017shape (Triangle
     2018uid 1416,0
     2019ro 90
     2020va (VaSet
     2021vasetType 1
     2022fg "0,65535,0"
     2023)
     2024xt "80250,75625,81000,76375"
     2025)
     2026tg (CPTG
     2027uid 1417,0
     2028ps "CptPortTextPlaceStrategy"
     2029stg "VerticalLayoutStrategy"
     2030f (Text
     2031uid 1418,0
     2032va (VaSet
     2033)
     2034xt "82000,75500,87100,76500"
     2035st "drs_refclk_in"
     2036blo "82000,76300"
     2037)
     2038)
     2039thePort (LogicalPort
     2040decl (Decl
     2041n "drs_refclk_in"
     2042t "std_logic"
     2043eolc "-- used to check if DRS REFCLK exsists, if not DENABLE inhibit"
     2044o 11
     2045suid 92,0
     2046)
     2047)
     2048)
     2049*50 (CptPort
     2050uid 1419,0
     2051ps "OnEdgeStrategy"
     2052shape (Triangle
     2053uid 1420,0
     2054ro 90
     2055va (VaSet
     2056vasetType 1
     2057fg "0,65535,0"
     2058)
     2059xt "109000,77625,109750,78375"
     2060)
     2061tg (CPTG
     2062uid 1421,0
     2063ps "CptPortTextPlaceStrategy"
     2064stg "RightVerticalLayoutStrategy"
     2065f (Text
     2066uid 1422,0
     2067va (VaSet
     2068)
     2069xt "105600,77500,108000,78500"
     2070st "green"
     2071ju 2
     2072blo "108000,78300"
     2073)
     2074)
     2075thePort (LogicalPort
     2076m 1
     2077decl (Decl
     2078n "green"
     2079t "std_logic"
     2080o 30
     2081suid 86,0
     2082)
     2083)
     2084)
     2085*51 (CptPort
     2086uid 1423,0
     2087ps "OnEdgeStrategy"
     2088shape (Triangle
     2089uid 1424,0
     2090ro 90
     2091va (VaSet
     2092vasetType 1
     2093fg "0,65535,0"
     2094)
     2095xt "80250,76625,81000,77375"
     2096)
     2097tg (CPTG
     2098uid 1425,0
     2099ps "CptPortTextPlaceStrategy"
     2100stg "VerticalLayoutStrategy"
     2101f (Text
     2102uid 1426,0
     2103va (VaSet
     2104)
     2105xt "82000,76500,88100,77500"
     2106st "plllock_in : (3:0)"
     2107blo "82000,77300"
     2108)
     2109)
     2110thePort (LogicalPort
     2111decl (Decl
     2112n "plllock_in"
     2113t "std_logic_vector"
     2114b "(3 DOWNTO 0)"
     2115eolc "-- high level, if dominowave is running and DRS PLL locked"
     2116o 12
     2117suid 93,0
     2118)
     2119)
     2120)
     2121*52 (CptPort
     2122uid 1427,0
     2123ps "OnEdgeStrategy"
     2124shape (Triangle
     2125uid 1428,0
     2126ro 90
     2127va (VaSet
     2128vasetType 1
     2129fg "0,65535,0"
     2130)
     2131xt "109000,78625,109750,79375"
     2132)
     2133tg (CPTG
     2134uid 1429,0
     2135ps "CptPortTextPlaceStrategy"
     2136stg "RightVerticalLayoutStrategy"
     2137f (Text
     2138uid 1430,0
     2139va (VaSet
     2140)
     2141xt "106500,78500,108000,79500"
     2142st "red"
     2143ju 2
     2144blo "108000,79300"
     2145)
     2146)
     2147thePort (LogicalPort
     2148m 1
     2149decl (Decl
     2150n "red"
     2151t "std_logic"
     2152o 33
     2153suid 88,0
     2154)
     2155)
     2156)
     2157*53 (CptPort
     2158uid 1431,0
     2159ps "OnEdgeStrategy"
     2160shape (Triangle
     2161uid 1432,0
     2162ro 270
     2163va (VaSet
     2164vasetType 1
     2165fg "0,65535,0"
     2166)
     2167xt "80250,71625,81000,72375"
     2168)
     2169tg (CPTG
     2170uid 1433,0
     2171ps "CptPortTextPlaceStrategy"
     2172stg "VerticalLayoutStrategy"
     2173f (Text
     2174uid 1434,0
     2175va (VaSet
     2176)
     2177xt "82000,71500,85700,72500"
     2178st "SRIN_out"
     2179blo "82000,72300"
     2180)
     2181)
     2182thePort (LogicalPort
     2183m 1
     2184decl (Decl
     2185n "SRIN_out"
     2186t "std_logic"
     2187o 20
     2188suid 85,0
     2189i "'0'"
     2190)
     2191)
     2192)
     2193*54 (CptPort
     2194uid 1678,0
     2195ps "OnEdgeStrategy"
     2196shape (Triangle
     2197uid 1679,0
     2198ro 270
     2199va (VaSet
     2200vasetType 1
     2201fg "0,65535,0"
     2202)
     2203xt "80250,23625,81000,24375"
     2204)
     2205tg (CPTG
     2206uid 1680,0
     2207ps "CptPortTextPlaceStrategy"
     2208stg "VerticalLayoutStrategy"
     2209f (Text
     2210uid 1681,0
     2211va (VaSet
     2212)
     2213xt "82000,23500,86000,24500"
     2214st "ADC_CLK"
     2215blo "82000,24300"
     2216)
     2217)
     2218thePort (LogicalPort
     2219lang 2
     2220m 1
     2221decl (Decl
     2222n "ADC_CLK"
     2223t "std_logic"
     2224o 15
     2225suid 97,0
    17912226)
    17922227)
    … …  
    18012236lineWidth 2
    18022237)
    1803 xt "81000,19000,109000,73000"
     2238xt "81000,19000,109000,81000"
    18042239)
    18052240oxt "15000,-8000,43000,46000"
    … …  
    18092244stg "VerticalLayoutStrategy"
    18102245textVec [
    1811 *44 (Text
     2246*55 (Text
    18122247uid 236,0
    18132248va (VaSet
    18142249font "Arial,8,1"
    18152250)
    1816 xt "81200,73000,87400,74000"
     2251xt "83200,81000,89400,82000"
    18172252st "FACT_FAD_lib"
    1818 blo "81200,73800"
     2253blo "83200,81800"
    18192254tm "BdLibraryNameMgr"
    18202255)
    1821 *45 (Text
     2256*56 (Text
    18222257uid 237,0
    18232258va (VaSet
    18242259font "Arial,8,1"
    18252260)
    1826 xt "81200,74000,85400,75000"
     2261xt "83200,82000,87400,83000"
    18272262st "FAD_main"
    1828 blo "81200,74800"
     2263blo "83200,82800"
    18292264tm "CptNameMgr"
    18302265)
    1831 *46 (Text
     2266*57 (Text
    18322267uid 238,0
    18332268va (VaSet
    18342269font "Arial,8,1"
    18352270)
    1836 xt "81200,75000,88000,76000"
     2271xt "83200,83000,90000,84000"
    18372272st "I_mainTB_FPGA"
    1838 blo "81200,75800"
     2273blo "83200,83800"
    18392274tm "InstanceNameMgr"
    18402275)
    … …  
    18712306fg "49152,49152,49152"
    18722307)
    1873 xt "81250,71250,82750,72750"
     2308xt "81250,79250,82750,80750"
    18742309iconName "BlockDiagram.png"
    18752310iconMaskName "BlockDiagram.msk"
    … …  
    18812316archFileType "UNKNOWN"
    18822317)
    1883 *47 (SaComponent
     2318*58 (SaComponent
    18842319uid 274,0
    18852320optionalChildren [
    1886 *48 (CptPort
     2321*59 (CptPort
    18872322uid 266,0
    18882323ps "OnEdgeStrategy"
    … …  
    19202355)
    19212356)
    1922 *49 (CptPort
     2357*60 (CptPort
    19232358uid 270,0
    19242359ps "OnEdgeStrategy"
    … …  
    19732408stg "VerticalLayoutStrategy"
    19742409textVec [
    1975 *50 (Text
     2410*61 (Text
    19762411uid 277,0
    19772412va (VaSet
    … …  
    19832418tm "BdLibraryNameMgr"
    19842419)
    1985 *51 (Text
     2420*62 (Text
    19862421uid 278,0
    19872422va (VaSet
    … …  
    19932428tm "CptNameMgr"
    19942429)
    1995 *52 (Text
     2430*63 (Text
    19962431uid 279,0
    19972432va (VaSet
    … …  
    20522487archFileType "UNKNOWN"
    20532488)
    2054 *53 (Net
     2489*64 (Net
    20552490uid 284,0
    20562491decl (Decl
    … …  
    20672502font "Courier New,8,0"
    20682503)
    2069 xt "2000,26800,20000,27600"
    2070 st "SIGNAL clk            : STD_LOGIC"
    2071 )
    2072 )
    2073 *54 (SaComponent
     2504xt "-90000,41400,-68000,42200"
     2505st "SIGNAL clk                   : STD_LOGIC"
     2506)
     2507)
     2508*65 (SaComponent
    20742509uid 306,0
    20752510optionalChildren [
    2076 *55 (CptPort
     2511*66 (CptPort
    20772512uid 290,0
    20782513ps "OnEdgeStrategy"
    … …  
    21032538n "addr"
    21042539t "std_logic_vector"
    2105 b "(9 downto 0)"
     2540b "(9 DOWNTO 0)"
    21062541preAdd 0
    21072542posAdd 0
    2108 o 1
     2543o 2
    21092544suid 1,0
    21102545)
    21112546)
    21122547)
    2113 *56 (CptPort
     2548*67 (CptPort
    21142549uid 294,0
    21152550ps "OnEdgeStrategy"
    … …  
    21412576n "data"
    21422577t "std_logic_vector"
    2143 b "(15 downto 0)"
     2578b "(15 DOWNTO 0)"
    21442579preAdd 0
    21452580posAdd 0
    2146 o 2
     2581o 3
    21472582suid 2,0
    21482583)
    21492584)
    21502585)
    2151 *57 (CptPort
     2586*68 (CptPort
    21522587uid 298,0
    21532588ps "OnEdgeStrategy"
    … …  
    21802615preAdd 0
    21812616posAdd 0
    2182 o 3
     2617o 4
    21832618suid 3,0
    21842619)
    21852620)
    21862621)
    2187 *58 (CptPort
     2622*69 (CptPort
    21882623uid 302,0
    21892624ps "OnEdgeStrategy"
    … …  
    22162651preAdd 0
    22172652posAdd 0
    2218 o 4
     2653o 5
    22192654suid 4,0
     2655)
     2656)
     2657)
     2658*70 (CptPort
     2659uid 2108,0
     2660ps "OnEdgeStrategy"
     2661shape (Triangle
     2662uid 2109,0
     2663ro 270
     2664va (VaSet
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     4069)
     4070*130 (Net
    35924071uid 871,0
    35934072decl (Decl
    … …  
    36024081font "Courier New,8,0"
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    3604 xt "2000,18800,20000,19600"
    3605 st "SIGNAL SROUT_in_0     : std_logic"
    3606 )
    3607 )
    3608 *119 (Net
     4083xt "-90000,31000,-68000,31800"
     4084st "SIGNAL SROUT_in_0            : std_logic"
     4085)
     4086)
     4087*131 (Net
    36094088uid 879,0
    36104089decl (Decl
    … …  
    36194098font "Courier New,8,0"
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    3621 xt "2000,19600,20000,20400"
    3622 st "SIGNAL SROUT_in_1     : std_logic"
    3623 )
    3624 )
    3625 *120 (Net
     4100xt "-90000,31800,-68000,32600"
     4101st "SIGNAL SROUT_in_1            : std_logic"
     4102)
     4103)
     4104*132 (Net
    36264105uid 887,0
    36274106decl (Decl
    … …  
    36364115font "Courier New,8,0"
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    3638 xt "2000,20400,20000,21200"
    3639 st "SIGNAL SROUT_in_2     : std_logic"
    3640 )
    3641 )
    3642 *121 (Net
     4117xt "-90000,32600,-68000,33400"
     4118st "SIGNAL SROUT_in_2            : std_logic"
     4119)
     4120)
     4121*133 (Net
    36434122uid 895,0
    36444123decl (Decl
    … …  
    36534132font "Courier New,8,0"
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    3655 xt "2000,21200,20000,22000"
    3656 st "SIGNAL SROUT_in_3     : std_logic"
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    3658 )
    3659 *122 (Wire
     4134xt "-90000,33400,-68000,34200"
     4135st "SIGNAL SROUT_in_3            : std_logic"
     4136)
     4137)
     4138*134 (Net
     4139uid 1435,0
     4140decl (Decl
     4141n "SRIN_out"
     4142t "std_logic"
     4143o 34
     4144suid 40,0
     4145i "'0'"
     4146)
     4147declText (MLText
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     4149va (VaSet
     4150font "Courier New,8,0"
     4151)
     4152xt "-90000,30200,-55000,31000"
     4153st "SIGNAL SRIN_out              : std_logic                    := '0'"
     4154)
     4155)
     4156*135 (Net
     4157uid 1443,0
     4158decl (Decl
     4159n "amber"
     4160t "std_logic"
     4161o 35
     4162suid 41,0
     4163)
     4164declText (MLText
     4165uid 1444,0
     4166va (VaSet
     4167font "Courier New,8,0"
     4168)
     4169xt "-90000,39800,-68000,40600"
     4170st "SIGNAL amber                 : std_logic"
     4171)
     4172)
     4173*136 (Net
     4174uid 1451,0
     4175decl (Decl
     4176n "red"
     4177t "std_logic"
     4178o 36
     4179suid 42,0
     4180)
     4181declText (MLText
     4182uid 1452,0
     4183va (VaSet
     4184font "Courier New,8,0"
     4185)
     4186xt "-90000,50200,-68000,51000"
     4187st "SIGNAL red                   : std_logic"
     4188)
     4189)
     4190*137 (Net
     4191uid 1459,0
     4192decl (Decl
     4193n "green"
     4194t "std_logic"
     4195o 37
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     4197)
     4198declText (MLText
     4199uid 1460,0
     4200va (VaSet
     4201font "Courier New,8,0"
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     4203xt "-90000,47000,-68000,47800"
     4204st "SIGNAL green                 : std_logic"
     4205)
     4206)
     4207*138 (Net
     4208uid 1467,0
     4209decl (Decl
     4210n "counter_result"
     4211t "std_logic_vector"
     4212b "(11 DOWNTO 0)"
     4213o 38
     4214suid 44,0
     4215)
     4216declText (MLText
     4217uid 1468,0
     4218va (VaSet
     4219font "Courier New,8,0"
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     4221xt "-90000,42200,-58000,43000"
     4222st "SIGNAL counter_result        : std_logic_vector(11 DOWNTO 0)"
     4223)
     4224)
     4225*139 (Net
     4226uid 1475,0
     4227decl (Decl
     4228n "alarm_refclk_too_low"
     4229t "std_logic"
     4230posAdd 0
     4231o 39
     4232suid 45,0
     4233)
     4234declText (MLText
     4235uid 1476,0
     4236va (VaSet
     4237font "Courier New,8,0"
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     4239xt "-90000,39000,-68000,39800"
     4240st "SIGNAL alarm_refclk_too_low  : std_logic"
     4241)
     4242)
     4243*140 (Net
     4244uid 1483,0
     4245decl (Decl
     4246n "alarm_refclk_too_high"
     4247t "std_logic"
     4248o 40
     4249suid 46,0
     4250)
     4251declText (MLText
     4252uid 1484,0
     4253va (VaSet
     4254font "Courier New,8,0"
     4255)
     4256xt "-90000,38200,-68000,39000"
     4257st "SIGNAL alarm_refclk_too_high : std_logic"
     4258)
     4259)
     4260*141 (HdlText
     4261uid 1491,0
     4262optionalChildren [
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     4270va (VaSet
     4271vasetType 1
     4272fg "65535,65535,65535"
     4273lineColor "0,0,32768"
     4274lineWidth 2
     4275)
     4276xt "27000,72000,41000,77000"
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     4278oxt "0,0,18000,5000"
     4279text (MLText
     4280uid 1500,0
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     4282)
     4283xt "27200,72200,39400,77200"
     4284st "
     4285
     4286D_T_in(1 downto 0) <= \"00\";
     4287plllock_in(3 downto 0) <= \"1111\";
     4288SROUT_in_0 <= '1';
     4289SROUT_in_1 <= '0';
     4290SROUT_in_2 <= '1';
     4291SROUT_in_3 <= '0';
     4292
     4293"
     4294tm "HdlTextMgr"
     4295wrapOption 3
     4296visibleHeight 5000
     4297visibleWidth 14000
     4298)
     4299)
     4300)
     4301]
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     4308lineWidth 2
     4309)
     4310xt "27000,69000,35000,72000"
     4311)
     4312oxt "0,0,8000,10000"
     4313ttg (MlTextGroup
     4314uid 1493,0
     4315ps "CenterOffsetStrategy"
     4316stg "VerticalLayoutStrategy"
     4317textVec [
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     4320va (VaSet
     4321font "Arial,8,1"
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     4323xt "28150,69000,35250,70000"
     4324st "eb_mainTB_adc1"
     4325blo "28150,69800"
     4326tm "HdlTextNameMgr"
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     4328*144 (Text
     4329uid 1495,0
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     4333xt "28150,70000,28950,71000"
     4334st "3"
     4335blo "28150,70800"
     4336tm "HdlTextNumberMgr"
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     4338]
     4339)
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     4342sl 0
     4343va (VaSet
     4344vasetType 1
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     4347xt "27250,70250,28750,71750"
     4348iconName "TextFile.png"
     4349iconMaskName "TextFile.msk"
     4350ftype 21
     4351)
     4352viewiconposition 0
     4353)
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     4356decl (Decl
     4357n "D_T_in"
     4358t "std_logic_vector"
     4359b "(1 DOWNTO 0)"
     4360o 41
     4361suid 47,0
     4362)
     4363declText (MLText
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     4365va (VaSet
     4366font "Courier New,8,0"
     4367)
     4368xt "-90000,27000,-58500,27800"
     4369st "SIGNAL D_T_in                : std_logic_vector(1 DOWNTO 0)"
     4370)
     4371)
     4372*146 (SaComponent
     4373uid 1509,0
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     4379uid 1520,0
     4380ro 90
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     4382vasetType 1
     4383fg "0,65535,0"
     4384)
     4385xt "66000,78625,66750,79375"
     4386)
     4387tg (CPTG
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     4389ps "CptPortTextPlaceStrategy"
     4390stg "RightVerticalLayoutStrategy"
     4391f (Text
     4392uid 1522,0
     4393va (VaSet
     4394)
     4395xt "63700,78500,65000,79500"
     4396st "clk"
     4397ju 2
     4398blo "65000,79300"
     4399)
     4400)
     4401thePort (LogicalPort
     4402m 1
     4403decl (Decl
     4404n "clk"
     4405t "STD_LOGIC"
     4406o 1
     4407i "'0'"
     4408)
     4409)
     4410)
     4411*148 (CptPort
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     4413ps "OnEdgeStrategy"
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     4418vasetType 1
     4419fg "0,65535,0"
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     4421xt "66000,79625,66750,80375"
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     4423tg (CPTG
     4424uid 1525,0
     4425ps "CptPortTextPlaceStrategy"
     4426stg "RightVerticalLayoutStrategy"
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     4428uid 1526,0
     4429va (VaSet
     4430)
     4431xt "63700,79500,65000,80500"
     4432st "rst"
     4433ju 2
     4434blo "65000,80300"
     4435)
     4436)
     4437thePort (LogicalPort
     4438m 1
     4439decl (Decl
     4440n "rst"
     4441t "STD_LOGIC"
     4442o 2
     4443i "'0'"
     4444)
     4445)
     4446)
     4447]
     4448shape (Rectangle
     4449uid 1510,0
     4450va (VaSet
     4451vasetType 1
     4452fg "0,49152,49152"
     4453lineColor "0,0,50000"
     4454lineWidth 2
     4455)
     4456xt "55000,77000,66000,82000"
     4457)
     4458oxt "0,0,8000,10000"
     4459ttg (MlTextGroup
     4460uid 1511,0
     4461ps "CenterOffsetStrategy"
     4462stg "VerticalLayoutStrategy"
     4463textVec [
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     4469xt "56150,78000,63850,79000"
     4470st "FACT_FAD_TB_lib"
     4471blo "56150,78800"
     4472tm "BdLibraryNameMgr"
     4473)
     4474*150 (Text
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     4477font "Arial,8,1"
     4478)
     4479xt "56150,79000,62850,80000"
     4480st "clock_generator"
     4481blo "56150,79800"
     4482tm "CptNameMgr"
     4483)
     4484*151 (Text
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     4490st "I_mainTB_clock1"
     4491blo "56150,80800"
     4492tm "InstanceNameMgr"
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     4494]
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     4507st "clock_period = 1 us    ( time ) 
     4508reset_time   = 1 us    ( time )  "
     4509)
     4510header ""
     4511)
     4512elements [
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     4514name "clock_period"
     4515type "time"
     4516value "1 us"
     4517)
     4518(GiElement
     4519name "reset_time"
     4520type "time"
     4521value "1 us"
     4522)
     4523]
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     4540)
     4541archFileType "UNKNOWN"
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     4543*152 (Net
     4544uid 1559,0
     4545decl (Decl
     4546n "plllock_in"
     4547t "std_logic_vector"
     4548b "(3 DOWNTO 0)"
     4549eolc "-- high level, if dominowave is running and DRS PLL locked"
     4550o 43
     4551suid 49,0
     4552)
     4553declText (MLText
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     4555va (VaSet
     4556font "Courier New,8,0"
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     4558xt "-90000,49400,-29000,50200"
     4559st "SIGNAL plllock_in            : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked"
     4560)
     4561)
     4562*153 (Net
     4563uid 1682,0
     4564lang 2
     4565decl (Decl
     4566n "ADC_CLK"
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     4569suid 50,0
     4570)
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     4577st "SIGNAL ADC_CLK               : std_logic"
     4578)
     4579)
     4580*154 (Net
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     4582decl (Decl
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     4586suid 51,0
     4587i "'0'"
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     4596)
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    … …  
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    … …  
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    … …  
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     5161)
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    … …  
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    … …  
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     5233)
     5234*172 (Wire
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    … …  
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     5262blo "25000,52800"
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    … …  
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    … …  
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    … …  
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    … …  
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    … …  
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    48555796)
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     5798)
     5799*188 (Wire
    48595800uid 889,0
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    … …  
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     5833)
     5834*189 (Wire
    48945835uid 897,0
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    … …  
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     5867on &133
     5868)
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     5870uid 1437,0
     5871shape (OrthoPolyLine
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     5873va (VaSet
     5874vasetType 3
     5875)
     5876xt "73000,72000,80250,72000"
     5877pts [
     5878"80250,72000"
     5879"73000,72000"
     5880]
     5881)
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     5884eat 16
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     5888tg (WTG
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     5890ps "ConnStartEndStrategy"
     5891stg "STSignalDisplayStrategy"
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     5894va (VaSet
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     5896xt "76000,72000,79700,73000"
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     5899tm "WireNameMgr"
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     5901)
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     5903)
     5904*191 (Wire
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     5907uid 1446,0
     5908va (VaSet
     5909vasetType 3
     5910)
     5911xt "109750,80000,115000,80000"
     5912pts [
     5913"109750,80000"
     5914"115000,80000"
     5915]
     5916)
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     5919eat 16
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     5921sf 1
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     5925ps "ConnStartEndStrategy"
     5926stg "STSignalDisplayStrategy"
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     5931xt "111000,79000,113500,80000"
     5932st "amber"
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     5934tm "WireNameMgr"
     5935)
     5936)
     5937on &135
     5938)
     5939*192 (Wire
     5940uid 1453,0
     5941shape (OrthoPolyLine
     5942uid 1454,0
     5943va (VaSet
     5944vasetType 3
     5945)
     5946xt "109750,79000,114000,79000"
     5947pts [
     5948"109750,79000"
     5949"114000,79000"
     5950]
     5951)
     5952start &52
     5953sat 32
     5954eat 16
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     5956sf 1
     5957si 0
     5958tg (WTG
     5959uid 1457,0
     5960ps "ConnStartEndStrategy"
     5961stg "STSignalDisplayStrategy"
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     5963uid 1458,0
     5964va (VaSet
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     5966xt "111000,78000,112500,79000"
     5967st "red"
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     5969tm "WireNameMgr"
     5970)
     5971)
     5972on &136
     5973)
     5974*193 (Wire
     5975uid 1461,0
     5976shape (OrthoPolyLine
     5977uid 1462,0
     5978va (VaSet
     5979vasetType 3
     5980)
     5981xt "109750,78000,114000,78000"
     5982pts [
     5983"109750,78000"
     5984"114000,78000"
     5985]
     5986)
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     5988sat 32
     5989eat 16
     5990st 0
     5991sf 1
     5992si 0
     5993tg (WTG
     5994uid 1465,0
     5995ps "ConnStartEndStrategy"
     5996stg "STSignalDisplayStrategy"
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     5998uid 1466,0
     5999va (VaSet
     6000)
     6001xt "111000,77000,113400,78000"
     6002st "green"
     6003blo "111000,77800"
     6004tm "WireNameMgr"
     6005)
     6006)
     6007on &137
     6008)
     6009*194 (Wire
     6010uid 1469,0
     6011shape (OrthoPolyLine
     6012uid 1470,0
     6013va (VaSet
     6014vasetType 3
     6015lineWidth 2
     6016)
     6017xt "109750,77000,121000,77000"
     6018pts [
     6019"109750,77000"
     6020"121000,77000"
     6021]
     6022)
     6023start &47
     6024sat 32
     6025eat 16
     6026sty 1
     6027st 0
     6028sf 1
     6029si 0
     6030tg (WTG
     6031uid 1473,0
     6032ps "ConnStartEndStrategy"
     6033stg "STSignalDisplayStrategy"
     6034f (Text
     6035uid 1474,0
     6036va (VaSet
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     6038xt "111000,76000,119600,77000"
     6039st "counter_result : (11:0)"
     6040blo "111000,76800"
     6041tm "WireNameMgr"
     6042)
     6043)
     6044on &138
     6045)
     6046*195 (Wire
     6047uid 1477,0
     6048shape (OrthoPolyLine
     6049uid 1478,0
     6050va (VaSet
     6051vasetType 3
     6052)
     6053xt "109750,75000,120000,75000"
     6054pts [
     6055"109750,75000"
     6056"120000,75000"
     6057]
     6058)
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     6060sat 32
     6061eat 16
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     6063sf 1
     6064si 0
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     6066uid 1481,0
     6067ps "ConnStartEndStrategy"
     6068stg "STSignalDisplayStrategy"
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     6070uid 1482,0
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     6074st "alarm_refclk_too_low"
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     6076tm "WireNameMgr"
     6077)
     6078)
     6079on &139
     6080)
     6081*196 (Wire
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     6084uid 1486,0
     6085va (VaSet
     6086vasetType 3
     6087)
     6088xt "109750,74000,121000,74000"
     6089pts [
     6090"109750,74000"
     6091"121000,74000"
     6092]
     6093)
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     6095sat 32
     6096eat 16
     6097st 0
     6098sf 1
     6099si 0
     6100tg (WTG
     6101uid 1489,0
     6102ps "ConnStartEndStrategy"
     6103stg "STSignalDisplayStrategy"
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     6105uid 1490,0
     6106va (VaSet
     6107)
     6108xt "111000,73000,119600,74000"
     6109st "alarm_refclk_too_high"
     6110blo "111000,73800"
     6111tm "WireNameMgr"
     6112)
     6113)
     6114on &140
     6115)
     6116*197 (Wire
     6117uid 1503,0
     6118shape (OrthoPolyLine
     6119uid 1504,0
     6120va (VaSet
     6121vasetType 3
     6122lineWidth 2
     6123)
     6124xt "73000,75000,80250,75000"
     6125pts [
     6126"73000,75000"
     6127"80250,75000"
     6128]
     6129)
     6130end &48
     6131sat 16
     6132eat 32
     6133sty 1
     6134st 0
     6135sf 1
     6136si 0
     6137tg (WTG
     6138uid 1507,0
     6139ps "ConnStartEndStrategy"
     6140stg "STSignalDisplayStrategy"
     6141f (Text
     6142uid 1508,0
     6143va (VaSet
     6144)
     6145xt "74000,74000,79500,75000"
     6146st "D_T_in : (1:0)"
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     6148tm "WireNameMgr"
     6149)
     6150)
     6151on &145
     6152)
     6153*198 (Wire
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     6155shape (OrthoPolyLine
     6156uid 1530,0
     6157va (VaSet
     6158vasetType 3
     6159)
     6160xt "66750,76000,80250,79000"
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     6162"66750,79000"
     6163"70000,79000"
     6164"70000,76000"
     6165"80250,76000"
     6166]
     6167)
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     6169end &49
     6170sat 32
     6171eat 32
     6172st 0
     6173sf 1
     6174si 0
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     6176uid 1531,0
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     6178stg "STSignalDisplayStrategy"
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     6180uid 1532,0
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     6186tm "WireNameMgr"
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     6188)
     6189on &154
     6190)
     6191*199 (Wire
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     6193shape (OrthoPolyLine
     6194uid 1534,0
     6195va (VaSet
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     6197)
     6198xt "35000,70000,45000,70000"
     6199pts [
     6200"35000,70000"
     6201"45000,70000"
     6202]
     6203)
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     6205sat 2
     6206eat 16
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     6208sf 1
     6209si 0
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     6211uid 1539,0
     6212ps "ConnStartEndStrategy"
     6213stg "STSignalDisplayStrategy"
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     6215uid 1540,0
     6216va (VaSet
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     6219st "D_T_in : (1:0)"
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     6221tm "WireNameMgr"
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     6223)
     6224on &145
     6225)
     6226*200 (Wire
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     6228shape (OrthoPolyLine
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     6230va (VaSet
     6231vasetType 3
     6232lineWidth 2
     6233)
     6234xt "72000,77000,80250,77000"
     6235pts [
     6236"72000,77000"
     6237"80250,77000"
     6238]
     6239)
     6240end &51
     6241sat 16
     6242eat 32
     6243sty 1
     6244st 0
     6245sf 1
     6246si 0
     6247tg (WTG
     6248uid 1565,0
     6249ps "ConnStartEndStrategy"
     6250stg "STSignalDisplayStrategy"
     6251f (Text
     6252uid 1566,0
     6253va (VaSet
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     6255xt "73000,76000,79100,77000"
     6256st "plllock_in : (3:0)"
     6257blo "73000,76800"
     6258tm "WireNameMgr"
     6259)
     6260)
     6261on &152
     6262)
     6263*201 (Wire
     6264uid 1567,0
     6265shape (OrthoPolyLine
     6266uid 1568,0
     6267va (VaSet
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     6269)
     6270xt "35000,71000,45000,71000"
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     6272"35000,71000"
     6273"45000,71000"
     6274]
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     6280sf 1
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     6283uid 1573,0
     6284ps "ConnStartEndStrategy"
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     6287uid 1574,0
     6288va (VaSet
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     6293tm "WireNameMgr"
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     6295)
     6296on &152
     6297)
     6298*202 (Wire
     6299uid 1684,0
     6300shape (OrthoPolyLine
     6301uid 1685,0
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     6303vasetType 3
     6304)
     6305xt "70000,24000,80250,24000"
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     6307"80250,24000"
     6308"70000,24000"
     6309]
     6310)
     6311start &54
     6312sat 32
     6313eat 16
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     6315sf 1
     6316si 0
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     6318uid 1688,0
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     6320stg "STSignalDisplayStrategy"
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     6322uid 1689,0
     6323va (VaSet
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     6325xt "71000,23000,75000,24000"
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     6328tm "WireNameMgr"
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     6330)
     6331on &153
    49276332)
    49286333]
    … …  
    49386343color "26368,26368,26368"
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    4940 packageList *157 (PackageList
     6345packageList *203 (PackageList
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     6356blo "-87000,800"
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     6358*205 (MLText
    49546359uid 43,0
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    49776382uid 45,0
    49786383va (VaSet
    … …  
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    66598204pos 11
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    66658210pos 12
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    66718216pos 13
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     8221litem &261
    66778222pos 14
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    66798224uid 591,0
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    6681 *254 (MRCItem
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     8227litem &262
    66838228pos 15
    66848229dimension 20
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    6687 *255 (MRCItem
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     8232*312 (MRCItem
     8233litem &263
    66898234pos 16
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    66928237)
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    66958240pos 17
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    66988243)
    6699 *257 (MRCItem
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     8244*314 (MRCItem
     8245litem &265
    67018246pos 18
    67028247dimension 20
    67038248uid 908,0
    67048249)
    6705 *258 (MRCItem
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     8250*315 (MRCItem
     8251litem &266
    67078252pos 19
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    67098254uid 910,0
    67108255)
    6711 *259 (MRCItem
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     8256*316 (MRCItem
     8257litem &267
    67138258pos 20
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    67158260uid 912,0
    67168261)
    6717 *260 (MRCItem
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    67198264pos 21
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    67258270pos 22
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    67288273)
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    67318276pos 23
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    67348279)
    6735 *263 (MRCItem
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    67378282pos 24
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    67408285)
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     8286*321 (MRCItem
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    67438288pos 25
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    67498294pos 26
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    67558300pos 27
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    67618306pos 28
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    67648309)
    6765 *268 (MRCItem
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     8311litem &276
    67678312pos 29
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    67708315)
    6771 *269 (MRCItem
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    67738318pos 30
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    67768321)
    6777 *270 (MRCItem
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     8322*327 (MRCItem
     8323litem &278
    67798324pos 31
    67808325dimension 20
    67818326uid 934,0
    67828327)
    6783 *271 (MRCItem
    6784 litem &233
     8328*328 (MRCItem
     8329litem &279
    67858330pos 32
    67868331dimension 20
    67878332uid 936,0
     8333)
     8334*329 (MRCItem
     8335litem &280
     8336pos 33
     8337dimension 20
     8338uid 1542,0
     8339)
     8340*330 (MRCItem
     8341litem &281
     8342pos 34
     8343dimension 20
     8344uid 1544,0
     8345)
     8346*331 (MRCItem
     8347litem &282
     8348pos 35
     8349dimension 20
     8350uid 1546,0
     8351)
     8352*332 (MRCItem
     8353litem &283
     8354pos 36
     8355dimension 20
     8356uid 1548,0
     8357)
     8358*333 (MRCItem
     8359litem &284
     8360pos 37
     8361dimension 20
     8362uid 1550,0
     8363)
     8364*334 (MRCItem
     8365litem &285
     8366pos 38
     8367dimension 20
     8368uid 1552,0
     8369)
     8370*335 (MRCItem
     8371litem &286
     8372pos 39
     8373dimension 20
     8374uid 1554,0
     8375)
     8376*336 (MRCItem
     8377litem &287
     8378pos 40
     8379dimension 20
     8380uid 1556,0
     8381)
     8382*337 (MRCItem
     8383litem &288
     8384pos 41
     8385dimension 20
     8386uid 1576,0
     8387)
     8388*338 (MRCItem
     8389litem &289
     8390pos 42
     8391dimension 20
     8392uid 1691,0
     8393)
     8394*339 (MRCItem
     8395litem &290
     8396pos 43
     8397dimension 20
     8398uid 2004,0
    67888399)
    67898400]
    … …  
    67988409uid 73,0
    67998410optionalChildren [
    6800 *272 (MRCItem
    6801 litem &192
     8411*340 (MRCItem
     8412litem &238
    68028413pos 0
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    68048415uid 74,0
    68058416)
    6806 *273 (MRCItem
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     8417*341 (MRCItem
     8418litem &240
    68088419pos 1
    68098420dimension 50
    68108421uid 75,0
    68118422)
    6812 *274 (MRCItem
    6813 litem &195
     8423*342 (MRCItem
     8424litem &241
    68148425pos 2
    68158426dimension 100
    68168427uid 76,0
    68178428)
    6818 *275 (MRCItem
    6819 litem &196
     8429*343 (MRCItem
     8430litem &242
    68208431pos 3
    68218432dimension 50
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    68238434)
    6824 *276 (MRCItem
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     8435*344 (MRCItem
     8436litem &243
    68268437pos 4
    68278438dimension 100
    68288439uid 78,0
    68298440)
    6830 *277 (MRCItem
    6831 litem &198
     8441*345 (MRCItem
     8442litem &244
    68328443pos 5
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    68348445uid 79,0
    68358446)
    6836 *278 (MRCItem
    6837 litem &199
     8447*346 (MRCItem
     8448litem &245
    68388449pos 6
    68398450dimension 50
    68408451uid 80,0
    68418452)
    6842 *279 (MRCItem
    6843 litem &200
     8453*347 (MRCItem
     8454litem &246
    68448455pos 7
    68458456dimension 80
    … …  
    68618472genericsCommonDM (CommonDM
    68628473ldm (LogicalDM
    6863 emptyRow *280 (LEmptyRow
     8474emptyRow *348 (LEmptyRow
    68648475)
    68658476uid 83,0
    68668477optionalChildren [
    6867 *281 (RefLabelRowHdr
    6868 )
    6869 *282 (TitleRowHdr
    6870 )
    6871 *283 (FilterRowHdr
    6872 )
    6873 *284 (RefLabelColHdr
     8478*349 (RefLabelRowHdr
     8479)
     8480*350 (TitleRowHdr
     8481)
     8482*351 (FilterRowHdr
     8483)
     8484*352 (RefLabelColHdr
    68748485tm "RefLabelColHdrMgr"
    68758486)
    6876 *285 (RowExpandColHdr
     8487*353 (RowExpandColHdr
    68778488tm "RowExpandColHdrMgr"
    68788489)
    6879 *286 (GroupColHdr
     8490*354 (GroupColHdr
    68808491tm "GroupColHdrMgr"
    68818492)
    6882 *287 (NameColHdr
     8493*355 (NameColHdr
    68838494tm "GenericNameColHdrMgr"
    68848495)
    6885 *288 (TypeColHdr
     8496*356 (TypeColHdr
    68868497tm "GenericTypeColHdrMgr"
    68878498)
    6888 *289 (InitColHdr
     8499*357 (InitColHdr
    68898500tm "GenericValueColHdrMgr"
    68908501)
    6891 *290 (PragmaColHdr
     8502*358 (PragmaColHdr
    68928503tm "GenericPragmaColHdrMgr"
    68938504)
    6894 *291 (EolColHdr
     8505*359 (EolColHdr
    68958506tm "GenericEolColHdrMgr"
    68968507)
    … …  
    69028513uid 95,0
    69038514optionalChildren [
    6904 *292 (Sheet
     8515*360 (Sheet
    69058516sheetRow (SheetRow
    69068517headerVa (MVa
    … …  
    69198530font "Tahoma,10,0"
    69208531)
    6921 emptyMRCItem *293 (MRCItem
    6922 litem &280
     8532emptyMRCItem *361 (MRCItem
     8533litem &348
    69238534pos 0
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    … …  
    69268537uid 97,0
    69278538optionalChildren [
    6928 *294 (MRCItem
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     8540litem &349
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    69338544)
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    69368547pos 1
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    69388549uid 99,0
    69398550)
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     8551*364 (MRCItem
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    69428553pos 2
    69438554hidden 1
    … …  
    69568567uid 101,0
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    6982 *301 (MRCItem
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    6988 *302 (MRCItem
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    69908601pos 5
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  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/fad_main_tb/struct.bd.bak

    <
    r9912 r10180  
    118118uid 508,0
    119119)
     120(Instance
     121name "I_mainTB_clock1"
     122duLibraryName "FACT_FAD_TB_lib"
     123duName "clock_generator"
     124elements [
     125(GiElement
     126name "clock_period"
     127type "time"
     128value "1 us"
     129)
     130(GiElement
     131name "reset_time"
     132type "time"
     133value "1 us"
     134)
     135]
     136mwi 0
     137uid 1509,0
     138)
    120139]
    121140embeddedInstances [
    … …  
    127146name "eb_mainTB_adc"
    128147number "2"
     148)
     149(EmbeddedInstance
     150name "eb_mainTB_adc1"
     151number "3"
    129152)
    130153]
    … …  
    143166(vvPair
    144167variable "HDLDir"
    145 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hdl"
     168value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
    146169)
    147170(vvPair
    148171variable "HDSDir"
    149 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds"
     172value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
    150173)
    151174(vvPair
    152175variable "SideDataDesignDir"
    153 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.info"
     176value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.info"
    154177)
    155178(vvPair
    156179variable "SideDataUserDir"
    157 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.user"
     180value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.user"
    158181)
    159182(vvPair
    160183variable "SourceDir"
    161 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds"
     184value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
    162185)
    163186(vvPair
    … …  
    171194(vvPair
    172195variable "config"
    173 value "%(unit)_config"
     196value "%(unit)_%(view)_config"
    174197)
    175198(vvPair
    176199variable "d"
    177 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb"
     200value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb"
    178201)
    179202(vvPair
    180203variable "d_logical"
    181 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb"
     204value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb"
    182205)
    183206(vvPair
    184207variable "date"
    185 value "25.06.2010"
     208value "25.02.2011"
    186209)
    187210(vvPair
    … …  
    223246(vvPair
    224247variable "host"
    225 value "EEPC8"
     248value "E5B-LABOR6"
    226249)
    227250(vvPair
    … …  
    234257)
    235258(vvPair
     259variable "library_downstream_HdsLintPlugin"
     260value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/designcheck"
     261)
     262(vvPair
     263variable "library_downstream_ISEPARInvoke"
     264value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
     265)
     266(vvPair
     267variable "library_downstream_ImpactInvoke"
     268value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
     269)
     270(vvPair
    236271variable "library_downstream_ModelSimCompiler"
    237272value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/work"
    238273)
    239274(vvPair
     275variable "library_downstream_XSTDataPrep"
     276value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
     277)
     278(vvPair
    240279variable "mm"
    241 value "06"
     280value "02"
    242281)
    243282(vvPair
    … …  
    247286(vvPair
    248287variable "month"
    249 value "Jun"
     288value "Feb"
    250289)
    251290(vvPair
    252291variable "month_long"
    253 value "Juni"
     292value "Februar"
    254293)
    255294(vvPair
    256295variable "p"
    257 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"
     296value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"
    258297)
    259298(vvPair
    260299variable "p_logical"
    261 value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"
     300value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"
    262301)
    263302(vvPair
    … …  
    283322(vvPair
    284323variable "task_ModelSimPath"
    285 value "$HDS_HOME/../Modeltech/win32"
     324value "C:\\modeltech_6.6a\\win32"
    286325)
    287326(vvPair
    … …  
    291330(vvPair
    292331variable "task_PrecisionRTLPath"
    293 value "$HDS_HOME/../Precision/Mgc_home/bin"
     332value "<TBD>"
    294333)
    295334(vvPair
    … …  
    315354(vvPair
    316355variable "time"
    317 value "08:17:47"
     356value "13:44:06"
    318357)
    319358(vvPair
    … …  
    323362(vvPair
    324363variable "user"
    325 value "Benjamin Krumm"
     364value "dneise"
    326365)
    327366(vvPair
    … …  
    335374(vvPair
    336375variable "year"
    337 value "2010"
     376value "2011"
    338377)
    339378(vvPair
    340379variable "yy"
    341 value "10"
     380value "11"
    342381)
    343382]
    … …  
    367406bg "0,0,32768"
    368407)
    369 xt "109200,97000,122200,98000"
     408xt "109200,97000,118800,98000"
    370409st "
    371410by %user on %dd %month %year
    … …  
    706745n "wiz_reset"
    707746t "std_logic"
    708 o 28
     747o 39
    709748suid 2,0
    710749i "'1'"
    … …  
    745784b "(7 DOWNTO 0)"
    746785posAdd 0
    747 o 21
     786o 31
    748787suid 7,0
    749788i "(OTHERS => '0')"
    … …  
    782821preAdd 0
    783822posAdd 0
    784 o 10
     823o 13
    785824suid 18,0
    786825)
    … …  
    817856n "adc_oeb"
    818857t "std_logic"
    819 o 16
     858o 21
    820859suid 21,0
    821860i "'1'"
    … …  
    852891n "board_id"
    853892t "std_logic_vector"
    854 b "(3 downto 0)"
    855 preAdd 0
    856 posAdd 0
    857 o 8
     893b "(3 DOWNTO 0)"
     894o 9
    858895suid 24,0
    859896)
    … …  
    889926n "crate_id"
    890927t "std_logic_vector"
    891 b "(1 downto 0)"
    892 o 9
     928b "(1 DOWNTO 0)"
     929o 10
    893930suid 25,0
    894931)
    … …  
    927964t "std_logic_vector"
    928965b "(9 DOWNTO 0)"
    929 o 25
     966o 36
    930967suid 26,0
    931968)
    … …  
    9641001t "std_logic_vector"
    9651002b "(15 DOWNTO 0)"
    966 o 31
     1003o 42
    9671004suid 27,0
    9681005)
    … …  
    10001037n "wiz_cs"
    10011038t "std_logic"
    1002 o 26
     1039o 37
    10031040suid 28,0
    10041041i "'1'"
    … …  
    10371074n "wiz_wr"
    10381075t "std_logic"
    1039 o 29
     1076o 40
    10401077suid 29,0
    10411078i "'1'"
    … …  
    10741111n "wiz_rd"
    10751112t "std_logic"
    1076 o 27
     1113o 38
    10771114suid 30,0
    10781115i "'1'"
    … …  
    11101147n "wiz_int"
    11111148t "std_logic"
    1112 o 11
     1149o 14
    11131150suid 31,0
    11141151)
    … …  
    11451182n "CLK_25_PS"
    11461183t "std_logic"
    1147 o 12
     1184o 16
    11481185suid 35,0
    11491186)
    … …  
    11801217n "CLK_50"
    11811218t "std_logic"
    1182 o 13
     1219preAdd 0
     1220posAdd 0
     1221o 17
    11831222suid 37,0
    11841223)
    … …  
    12491288t "std_logic_vector"
    12501289b "(3 DOWNTO 0)"
    1251 o 7
     1290o 8
    12521291suid 40,0
    12531292)
    … …  
    12831322n "adc_data_array"
    12841323t "adc_data_array_type"
    1285 o 6
     1324o 7
    12861325suid 41,0
    12871326)
    … …  
    13191358t "std_logic_vector"
    13201359b "(3 downto 0)"
    1321 o 19
     1360o 28
    13221361suid 48,0
    13231362i "(others => '0')"
    … …  
    13551394n "drs_dwrite"
    13561395t "std_logic"
    1357 o 20
     1396o 29
    13581397suid 49,0
    13591398i "'1'"
    … …  
    13901429n "SROUT_in_0"
    13911430t "std_logic"
    1392 o 2
     1431o 3
    13931432suid 52,0
    13941433)
    … …  
    14241463n "SROUT_in_1"
    14251464t "std_logic"
    1426 o 3
     1465o 4
    14271466suid 53,0
    14281467)
    … …  
    14581497n "SROUT_in_2"
    14591498t "std_logic"
    1460 o 4
     1499o 5
    14611500suid 54,0
    14621501)
    … …  
    14921531n "SROUT_in_3"
    14931532t "std_logic"
    1494 o 5
     1533o 6
    14951534suid 55,0
    14961535)
    … …  
    15271566n "RSRLOAD"
    15281567t "std_logic"
    1529 o 14
     1568o 18
    15301569suid 56,0
    15311570i "'0'"
    … …  
    15631602n "SRCLK"
    15641603t "std_logic"
    1565 o 15
     1604o 19
    15661605suid 57,0
    15671606i "'0'"
    … …  
    16001639n "sclk"
    16011640t "std_logic"
    1602 o 23
     1641o 34
    16031642suid 62,0
    16041643)
    … …  
    16381677preAdd 0
    16391678posAdd 0
    1640 o 30
     1679o 41
    16411680suid 63,0
    16421681)
    … …  
    16741713n "dac_cs"
    16751714t "std_logic"
    1676 o 17
     1715o 26
    16771716suid 64,0
    16781717)
    … …  
    17111750t "std_logic_vector"
    17121751b "(3 DOWNTO 0)"
    1713 o 24
     1752o 35
    17141753suid 65,0
    17151754)
    … …  
    17471786n "mosi"
    17481787t "std_logic"
    1749 o 22
     1788o 32
    17501789suid 66,0
    17511790i "'0'"
    … …  
    17861825eolc "-- default domino wave off"
    17871826posAdd 0
    1788 o 18
     1827o 27
    17891828suid 67,0
    17901829i "'0'"
     1830)
     1831)
     1832)
     1833*44 (CptPort
     1834uid 1395,0
     1835ps "OnEdgeStrategy"
     1836shape (Triangle
     1837uid 1396,0
     1838ro 90
     1839va (VaSet
     1840vasetType 1
     1841fg "0,65535,0"
     1842)
     1843xt "109000,73625,109750,74375"
     1844)
     1845tg (CPTG
     1846uid 1397,0
     1847ps "CptPortTextPlaceStrategy"
     1848stg "RightVerticalLayoutStrategy"
     1849f (Text
     1850uid 1398,0
     1851va (VaSet
     1852)
     1853xt "99400,73500,108000,74500"
     1854st "alarm_refclk_too_high"
     1855ju 2
     1856blo "108000,74300"
     1857)
     1858)
     1859thePort (LogicalPort
     1860m 1
     1861decl (Decl
     1862n "alarm_refclk_too_high"
     1863t "std_logic"
     1864o 22
     1865suid 95,0
     1866)
     1867)
     1868)
     1869*45 (CptPort
     1870uid 1399,0
     1871ps "OnEdgeStrategy"
     1872shape (Triangle
     1873uid 1400,0
     1874ro 90
     1875va (VaSet
     1876vasetType 1
     1877fg "0,65535,0"
     1878)
     1879xt "109000,74625,109750,75375"
     1880)
     1881tg (CPTG
     1882uid 1401,0
     1883ps "CptPortTextPlaceStrategy"
     1884stg "RightVerticalLayoutStrategy"
     1885f (Text
     1886uid 1402,0
     1887va (VaSet
     1888)
     1889xt "99800,74500,108000,75500"
     1890st "alarm_refclk_too_low"
     1891ju 2
     1892blo "108000,75300"
     1893)
     1894)
     1895thePort (LogicalPort
     1896m 1
     1897decl (Decl
     1898n "alarm_refclk_too_low"
     1899t "std_logic"
     1900posAdd 0
     1901o 23
     1902suid 96,0
     1903)
     1904)
     1905)
     1906*46 (CptPort
     1907uid 1403,0
     1908ps "OnEdgeStrategy"
     1909shape (Triangle
     1910uid 1404,0
     1911ro 90
     1912va (VaSet
     1913vasetType 1
     1914fg "0,65535,0"
     1915)
     1916xt "109000,79625,109750,80375"
     1917)
     1918tg (CPTG
     1919uid 1405,0
     1920ps "CptPortTextPlaceStrategy"
     1921stg "RightVerticalLayoutStrategy"
     1922f (Text
     1923uid 1406,0
     1924va (VaSet
     1925)
     1926xt "105500,79500,108000,80500"
     1927st "amber"
     1928ju 2
     1929blo "108000,80300"
     1930)
     1931)
     1932thePort (LogicalPort
     1933m 1
     1934decl (Decl
     1935n "amber"
     1936t "std_logic"
     1937o 24
     1938suid 87,0
     1939)
     1940)
     1941)
     1942*47 (CptPort
     1943uid 1407,0
     1944ps "OnEdgeStrategy"
     1945shape (Triangle
     1946uid 1408,0
     1947ro 90
     1948va (VaSet
     1949vasetType 1
     1950fg "0,65535,0"
     1951)
     1952xt "109000,76625,109750,77375"
     1953)
     1954tg (CPTG
     1955uid 1409,0
     1956ps "CptPortTextPlaceStrategy"
     1957stg "RightVerticalLayoutStrategy"
     1958f (Text
     1959uid 1410,0
     1960va (VaSet
     1961)
     1962xt "99400,76500,108000,77500"
     1963st "counter_result : (11:0)"
     1964ju 2
     1965blo "108000,77300"
     1966)
     1967)
     1968thePort (LogicalPort
     1969m 1
     1970decl (Decl
     1971n "counter_result"
     1972t "std_logic_vector"
     1973b "(11 DOWNTO 0)"
     1974o 25
     1975suid 94,0
     1976)
     1977)
     1978)
     1979*48 (CptPort
     1980uid 1411,0
     1981ps "OnEdgeStrategy"
     1982shape (Triangle
     1983uid 1412,0
     1984ro 90
     1985va (VaSet
     1986vasetType 1
     1987fg "0,65535,0"
     1988)
     1989xt "80250,74625,81000,75375"
     1990)
     1991tg (CPTG
     1992uid 1413,0
     1993ps "CptPortTextPlaceStrategy"
     1994stg "VerticalLayoutStrategy"
     1995f (Text
     1996uid 1414,0
     1997va (VaSet
     1998)
     1999xt "82000,74500,87500,75500"
     2000st "D_T_in : (1:0)"
     2001blo "82000,75300"
     2002)
     2003)
     2004thePort (LogicalPort
     2005decl (Decl
     2006n "D_T_in"
     2007t "std_logic_vector"
     2008b "(1 DOWNTO 0)"
     2009o 2
     2010suid 91,0
     2011)
     2012)
     2013)
     2014*49 (CptPort
     2015uid 1415,0
     2016ps "OnEdgeStrategy"
     2017shape (Triangle
     2018uid 1416,0
     2019ro 90
     2020va (VaSet
     2021vasetType 1
     2022fg "0,65535,0"
     2023)
     2024xt "80250,75625,81000,76375"
     2025)
     2026tg (CPTG
     2027uid 1417,0
     2028ps "CptPortTextPlaceStrategy"
     2029stg "VerticalLayoutStrategy"
     2030f (Text
     2031uid 1418,0
     2032va (VaSet
     2033)
     2034xt "82000,75500,87100,76500"
     2035st "drs_refclk_in"
     2036blo "82000,76300"
     2037)
     2038)
     2039thePort (LogicalPort
     2040decl (Decl
     2041n "drs_refclk_in"
     2042t "std_logic"
     2043eolc "-- used to check if DRS REFCLK exsists, if not DENABLE inhibit"
     2044o 11
     2045suid 92,0
     2046)
     2047)
     2048)
     2049*50 (CptPort
     2050uid 1419,0
     2051ps "OnEdgeStrategy"
     2052shape (Triangle
     2053uid 1420,0
     2054ro 90
     2055va (VaSet
     2056vasetType 1
     2057fg "0,65535,0"
     2058)
     2059xt "109000,77625,109750,78375"
     2060)
     2061tg (CPTG
     2062uid 1421,0
     2063ps "CptPortTextPlaceStrategy"
     2064stg "RightVerticalLayoutStrategy"
     2065f (Text
     2066uid 1422,0
     2067va (VaSet
     2068)
     2069xt "105600,77500,108000,78500"
     2070st "green"
     2071ju 2
     2072blo "108000,78300"
     2073)
     2074)
     2075thePort (LogicalPort
     2076m 1
     2077decl (Decl
     2078n "green"
     2079t "std_logic"
     2080o 30
     2081suid 86,0
     2082)
     2083)
     2084)
     2085*51 (CptPort
     2086uid 1423,0
     2087ps "OnEdgeStrategy"
     2088shape (Triangle
     2089uid 1424,0
     2090ro 90
     2091va (VaSet
     2092vasetType 1
     2093fg "0,65535,0"
     2094)
     2095xt "80250,76625,81000,77375"
     2096)
     2097tg (CPTG
     2098uid 1425,0
     2099ps "CptPortTextPlaceStrategy"
     2100stg "VerticalLayoutStrategy"
     2101f (Text
     2102uid 1426,0
     2103va (VaSet
     2104)
     2105xt "82000,76500,88100,77500"
     2106st "plllock_in : (3:0)"
     2107blo "82000,77300"
     2108)
     2109)
     2110thePort (LogicalPort
     2111decl (Decl
     2112n "plllock_in"
     2113t "std_logic_vector"
     2114b "(3 DOWNTO 0)"
     2115eolc "-- high level, if dominowave is running and DRS PLL locked"
     2116o 12
     2117suid 93,0
     2118)
     2119)
     2120)
     2121*52 (CptPort
     2122uid 1427,0
     2123ps "OnEdgeStrategy"
     2124shape (Triangle
     2125uid 1428,0
     2126ro 90
     2127va (VaSet
     2128vasetType 1
     2129fg "0,65535,0"
     2130)
     2131xt "109000,78625,109750,79375"
     2132)
     2133tg (CPTG
     2134uid 1429,0
     2135ps "CptPortTextPlaceStrategy"
     2136stg "RightVerticalLayoutStrategy"
     2137f (Text
     2138uid 1430,0
     2139va (VaSet
     2140)
     2141xt "106500,78500,108000,79500"
     2142st "red"
     2143ju 2
     2144blo "108000,79300"
     2145)
     2146)
     2147thePort (LogicalPort
     2148m 1
     2149decl (Decl
     2150n "red"
     2151t "std_logic"
     2152o 33
     2153suid 88,0
     2154)
     2155)
     2156)
     2157*53 (CptPort
     2158uid 1431,0
     2159ps "OnEdgeStrategy"
     2160shape (Triangle
     2161uid 1432,0
     2162ro 270
     2163va (VaSet
     2164vasetType 1
     2165fg "0,65535,0"
     2166)
     2167xt "80250,71625,81000,72375"
     2168)
     2169tg (CPTG
     2170uid 1433,0
     2171ps "CptPortTextPlaceStrategy"
     2172stg "VerticalLayoutStrategy"
     2173f (Text
     2174uid 1434,0
     2175va (VaSet
     2176)
     2177xt "82000,71500,85700,72500"
     2178st "SRIN_out"
     2179blo "82000,72300"
     2180)
     2181)
     2182thePort (LogicalPort
     2183m 1
     2184decl (Decl
     2185n "SRIN_out"
     2186t "std_logic"
     2187o 20
     2188suid 85,0
     2189i "'0'"
     2190)
     2191)
     2192)
     2193*54 (CptPort
     2194uid 1678,0
     2195ps "OnEdgeStrategy"
     2196shape (Triangle
     2197uid 1679,0
     2198ro 270
     2199va (VaSet
     2200vasetType 1
     2201fg "0,65535,0"
     2202)
     2203xt "80250,23625,81000,24375"
     2204)
     2205tg (CPTG
     2206uid 1680,0
     2207ps "CptPortTextPlaceStrategy"
     2208stg "VerticalLayoutStrategy"
     2209f (Text
     2210uid 1681,0
     2211va (VaSet
     2212)
     2213xt "82000,23500,86000,24500"
     2214st "ADC_CLK"
     2215blo "82000,24300"
     2216)
     2217)
     2218thePort (LogicalPort
     2219lang 2
     2220m 1
     2221decl (Decl
     2222n "ADC_CLK"
     2223t "std_logic"
     2224o 15
     2225suid 97,0
    17912226)
    17922227)
    … …  
    18012236lineWidth 2
    18022237)
    1803 xt "81000,19000,109000,73000"
     2238xt "81000,19000,109000,81000"
    18042239)
    18052240oxt "15000,-8000,43000,46000"
    … …  
    18092244stg "VerticalLayoutStrategy"
    18102245textVec [
    1811 *44 (Text
     2246*55 (Text
    18122247uid 236,0
    18132248va (VaSet
    18142249font "Arial,8,1"
    18152250)
    1816 xt "81200,73000,87400,74000"
     2251xt "83200,81000,89400,82000"
    18172252st "FACT_FAD_lib"
    1818 blo "81200,73800"
     2253blo "83200,81800"
    18192254tm "BdLibraryNameMgr"
    18202255)
    1821 *45 (Text
     2256*56 (Text
    18222257uid 237,0
    18232258va (VaSet
    18242259font "Arial,8,1"
    18252260)
    1826 xt "81200,74000,85400,75000"
     2261xt "83200,82000,87400,83000"
    18272262