Index: firmware/FTM/FTM_central_control.vhd =================================================================== --- firmware/FTM/FTM_central_control.vhd (revision 10227) +++ firmware/FTM/FTM_central_control.vhd (revision 10227) @@ -0,0 +1,131 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: Q. Weitzel +-- +-- Create Date: 15:56:13 02/28/2011 +-- Design Name: +-- Module Name: FTM_central_control - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Central FSM for FTM firmware +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library ftm_definitions; +USE ftm_definitions.ftm_array_types.all; +USE ftm_definitions.ftm_constants.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FTM_central_control is + port( + clk : IN std_logic; + new_config : IN std_logic; + config_started : OUT std_logic := '0'; + config_started_ack : IN std_logic; + config_start_eth : OUT std_logic := '0'; + config_started_eth : IN std_logic; + config_ready_eth : IN std_logic; + config_start_ftu : OUT std_logic := '0'; + config_started_ftu : IN std_logic ; + config_ready_ftu : IN std_logic ; + ping_ftu_start : IN std_logic; + ping_ftu_started : OUT std_logic := '0'; + ping_ftu_ready : OUT std_logic := '0'; + ping_ftu_start_ftu : OUT std_logic := '0'; + ping_ftu_started_ftu : IN std_logic; + ping_ftu_ready_ftu : IN std_logic + ); +end FTM_central_control; + +architecture Behavioral of FTM_central_control is + + type state_central_proc_type is (CP_INIT, CP_CONFIG_START, CP_CONFIG, CP_CONFIG_01, + CP_CONFIG_FTU, CP_CONFIG_FTU_01, + CP_IDLE, CP_PING); + signal state_central_proc : state_central_proc_type := CP_INIT; + +begin + + central_proc : process (clk) + begin + if rising_edge (clk) then + case state_central_proc is + + when CP_INIT => + state_central_proc <= CP_CONFIG; + + when CP_CONFIG_START => + if (config_started_ack = '1') then + config_started <= '0'; + state_central_proc <= CP_CONFIG; + end if; + + when CP_CONFIG => + config_start_eth <= '1'; + if (config_started_eth = '1') then + config_start_eth <= '0'; + state_central_proc <= CP_CONFIG_01; + end if; + + when CP_CONFIG_01 => + if (config_ready_eth = '1') then + state_central_proc <= CP_CONFIG_FTU; + end if; + + when CP_CONFIG_FTU => + config_start_ftu <= '1'; + if (config_started_ftu = '1') then + config_start_ftu <= '0'; + state_central_proc <= CP_CONFIG_FTU_01; + end if; + + when CP_CONFIG_FTU_01 => + if (config_ready_ftu = '1') then + state_central_proc <= CP_IDLE; + end if; + + when CP_IDLE => + if (new_config = '1') then + config_started <= '1'; + state_central_proc <= CP_CONFIG_START; + + elsif (ping_ftu_start = '1') then + ping_ftu_start_ftu <= '1'; + if (ping_ftu_started_ftu = '1') then + ping_ftu_start_ftu <= '0'; + ping_ftu_started <= '1'; + ping_ftu_ready <= '0'; + state_central_proc <= CP_PING; + end if; + + end if; + + when CP_PING => + if (ping_ftu_ready_ftu = '1') then + if (ping_ftu_start = '0') then + ping_ftu_started <= '0'; + ping_ftu_ready <= '1'; + state_central_proc <= CP_IDLE; + end if; + end if; + + end case; + end if; + end process central_proc; + +end Behavioral; Index: firmware/FTM/FTM_top.vhd =================================================================== --- firmware/FTM/FTM_top.vhd (revision 10225) +++ firmware/FTM/FTM_top.vhd (revision 10227) @@ -25,8 +25,12 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL; +library ftm_definitions; +USE ftm_definitions.ftm_array_types.all; +USE ftm_definitions.ftm_constants.all; + ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; +library UNISIM; +use UNISIM.VComponents.all; @@ -44,22 +48,23 @@ -- W5300 address bus - W_A : out STD_LOGIC_VECTOR(9 downto 1); -- there is NO net W_A0 because + W_A : out STD_LOGIC_VECTOR(9 downto 0); -- there is no real net W_A0 because -- the W5300 is operated in the - -- 16-bit mode + -- 16-bit mode + -- -> W_A<0> assigned to unconnected pin -- W5300 control signals -- the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17 -- W_CS is also routed to testpoint JP7 - W_CS : out STD_LOGIC; -- W5300 chip select + W_CS : out STD_LOGIC := '1'; -- W5300 chip select W_INT : IN STD_LOGIC; -- interrupt - W_RD : out STD_LOGIC; -- read - W_WR : out STD_LOGIC; -- write - W_RES : out STD_LOGIC; -- reset W5300 chip + W_RD : out STD_LOGIC := '1'; -- read + W_WR : out STD_LOGIC := '1'; -- write + W_RES : out STD_LOGIC := '1'; -- reset W5300 chip -- W5300 buffer ready indicator - W_BRDY : in STD_LOGIC_VECTOR(3 downto 0); + -- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0); -- testpoints (T18) associated with the W5300 on IO-bank 1 - W_T : inout STD_LOGIC_VECTOR(3 downto 0); + -- W_T : inout STD_LOGIC_VECTOR(3 downto 0); @@ -69,5 +74,5 @@ -- on IO-Bank 1 ------------------------------------------------------------------------------- - S_CLK : out STD_LOGIC; -- SPI clock + -- S_CLK : out STD_LOGIC; -- SPI clock -- EEPROM @@ -77,6 +82,6 @@ -- temperature sensors U45, U46, U48 and U49 - SIO : inout STD_LOGIC; -- serial IO - TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select + -- SIO : inout STD_LOGIC; -- serial IO + -- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select @@ -84,8 +89,8 @@ -- on IO-Bank 2 ------------------------------------------------------------------------------- - Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0 - Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1 - Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2 - Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3 + -- Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0 + -- Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1 + -- Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2 + -- Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3 @@ -93,16 +98,16 @@ ------------------------------------------------------------------------------ -- on IO-Bank 3 - ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input - Veto : in STD_LOGIC; -- trigger veto input - NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs + -- ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input + -- Veto : in STD_LOGIC; -- trigger veto input + -- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs -- on IO-Bank 0 -- alternative external clock input for FPGA - NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available + -- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available -- LEDs on IO-Banks 0 and 3 ------------------------------------------------------------------------------- - LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red + LED_red : out STD_LOGIC_VECTOR(3 downto 0); -- red LED_ye : out STD_LOGIC_VECTOR(1 downto 0); -- yellow LED_gn : out STD_LOGIC_VECTOR(1 downto 0); -- green @@ -112,10 +117,10 @@ -- on IO-Bank 3 ------------------------------------------------------------------------------- - CLK_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface serial clock - LE_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface latch enable - DATA_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface data + -- CLK_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface serial clock + -- LE_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface latch enable + -- DATA_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface data - SYNC_Clk_Cond : out STD_LOGIC; -- global clock synchronization - LD_Clk_Cond : in STD_LOGIC; -- lock detect, should be checked for + -- SYNC_Clk_Cond : out STD_LOGIC; -- global clock synchronization + -- LD_Clk_Cond : in STD_LOGIC; -- lock detect, should be checked for @@ -137,22 +142,22 @@ Bus1_RxD_3 : in STD_LOGIC; -- crate 3 - Bus1_TxD_3 : out STD_LOGIC; + Bus1_TxD_3 : out STD_LOGIC -- Bus 2: Trigger-ID to FAD boards - Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable - Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable - - Bus2_RxD_0 : in STD_LOGIC; -- crate 0 - Bus2_TxD_0 : out STD_LOGIC; - - Bus2_RxD_1 : in STD_LOGIC; -- crate 1 - Bus2_TxD_1 : out STD_LOGIC; - - Bus2_RxD_2 : in STD_LOGIC; -- crate 2 - Bus2_TxD_2 : out STD_LOGIC; - - Bus2_RxD_3 : in STD_LOGIC; -- crate 3 - Bus2_TxD_3 : out STD_LOGIC; + -- Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable + -- Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable + + -- Bus2_RxD_0 : in STD_LOGIC; -- crate 0 + -- Bus2_TxD_0 : out STD_LOGIC; + + -- Bus2_RxD_1 : in STD_LOGIC; -- crate 1 + -- Bus2_TxD_1 : out STD_LOGIC; + + -- Bus2_RxD_2 : in STD_LOGIC; -- crate 2 + -- Bus2_TxD_2 : out STD_LOGIC; + + -- Bus2_RxD_3 : in STD_LOGIC; -- crate 3 + -- Bus2_TxD_3 : out STD_LOGIC; @@ -172,8 +177,8 @@ -- on IO-Bank 3 ------------------------------------------------------------------------------- - Crate_Res0 : out STD_LOGIC; - Crate_Res1 : out STD_LOGIC; - Crate_Res2 : out STD_LOGIC; - Crate_Res3 : out STD_LOGIC; + -- Crate_Res0 : out STD_LOGIC; + -- Crate_Res1 : out STD_LOGIC; + -- Crate_Res2 : out STD_LOGIC; + -- Crate_Res3 : out STD_LOGIC; @@ -181,8 +186,8 @@ -- on IO-Bank 3 ------------------------------------------------------------------------------- - Busy0 : in STD_LOGIC; - Busy1 : in STD_LOGIC; - Busy2 : in STD_LOGIC; - Busy3 : in STD_LOGIC; + -- Busy0 : in STD_LOGIC; + -- Busy1 : in STD_LOGIC; + -- Busy2 : in STD_LOGIC; + -- Busy3 : in STD_LOGIC; @@ -207,13 +212,13 @@ -- LVDS output at the FPGA followed by LVDS to NIM conversion stage ------------------------------------------------------------------------------- - RES_p : out STD_LOGIC; -- RES+ Reset - RES_n : out STD_LOGIC; -- RES- IO-Bank 0 - - TRG_p : out STD_LOGIC; -- TRG+ Trigger - TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0 - - TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker - TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2 - TIM_Sel : out STD_LOGIC; -- Time Marker selector on IO-Bank 2 + -- RES_p : out STD_LOGIC; -- RES+ Reset + -- RES_n : out STD_LOGIC; -- RES- IO-Bank 0 + + -- TRG_p : out STD_LOGIC; -- TRG+ Trigger + -- TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0 + + -- TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker + -- TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2 + -- TIM_Sel : out STD_LOGIC; -- Time Marker selector on IO-Bank 2 -- CLD_FPGA : in STD_LOGIC; -- DRS-Clock feedback into FPGA @@ -225,23 +230,23 @@ -- to connector J13 -- for light pulsar in the mirror dish - Cal_0_p : out STD_LOGIC; - Cal_0_n : out STD_LOGIC; - Cal_1_p : out STD_LOGIC; - Cal_1_n : out STD_LOGIC; - Cal_2_p : out STD_LOGIC; - Cal_2_n : out STD_LOGIC; - Cal_3_p : out STD_LOGIC; - Cal_3_n : out STD_LOGIC; + -- Cal_0_p : out STD_LOGIC; + -- Cal_0_n : out STD_LOGIC; + -- Cal_1_p : out STD_LOGIC; + -- Cal_1_n : out STD_LOGIC; + -- Cal_2_p : out STD_LOGIC; + -- Cal_2_n : out STD_LOGIC; + -- Cal_3_p : out STD_LOGIC; + -- Cal_3_n : out STD_LOGIC; -- to connector J12 -- for light pulsar inside shutter - Cal_4_p : out STD_LOGIC; - Cal_4_n : out STD_LOGIC; - Cal_5_p : out STD_LOGIC; - Cal_5_n : out STD_LOGIC; - Cal_6_p : out STD_LOGIC; - Cal_6_n : out STD_LOGIC; - Cal_7_p : out STD_LOGIC; - Cal_7_n : out STD_LOGIC + -- Cal_4_p : out STD_LOGIC; + -- Cal_4_n : out STD_LOGIC; + -- Cal_5_p : out STD_LOGIC; + -- Cal_5_n : out STD_LOGIC; + -- Cal_6_p : out STD_LOGIC; + -- Cal_6_n : out STD_LOGIC; + -- Cal_7_p : out STD_LOGIC; + -- Cal_7_n : out STD_LOGIC @@ -262,5 +267,387 @@ architecture Behavioral of FTM_top is + signal cc_R0_sig : std_logic_vector(31 DOWNTO 0); + signal cc_R1_sig : std_logic_vector(31 DOWNTO 0); + signal cc_R11_sig : std_logic_vector(31 DOWNTO 0); + signal cc_R13_sig : std_logic_vector(31 DOWNTO 0); + signal cc_R14_sig : std_logic_vector(31 DOWNTO 0); + signal cc_R15_sig : std_logic_vector(31 DOWNTO 0); + signal cc_R8_sig : std_logic_vector(31 DOWNTO 0); + signal cc_R9_sig : std_logic_vector(31 DOWNTO 0); + signal coin_n_c_sig : std_logic_vector(15 DOWNTO 0); + signal coin_n_p_sig : std_logic_vector(15 DOWNTO 0); + signal dead_time_sig : std_logic_vector(15 DOWNTO 0); + signal ftu_active_cr0_sig : std_logic_vector(15 DOWNTO 0); + signal ftu_active_cr1_sig : std_logic_vector(15 DOWNTO 0); + signal ftu_active_cr2_sig : std_logic_vector(15 DOWNTO 0); + signal ftu_active_cr3_sig : std_logic_vector(15 DOWNTO 0); + signal general_settings_sig : std_logic_vector(15 DOWNTO 0); + signal lp1_amplitude_sig : std_logic_vector(15 DOWNTO 0); + signal lp1_delay_sig : std_logic_vector(15 DOWNTO 0); + signal lp2_amplitude_sig : std_logic_vector(15 DOWNTO 0); + signal lp2_delay_sig : std_logic_vector(15 DOWNTO 0); + signal lp_pt_freq_sig : std_logic_vector(15 DOWNTO 0); + signal lp_pt_ratio_sig : std_logic_vector(15 DOWNTO 0); + signal timemarker_delay_sig : std_logic_vector(15 DOWNTO 0); + signal trigger_delay_sig : std_logic_vector(15 DOWNTO 0); + signal sd_addr_ftu_sig : std_logic_vector(11 DOWNTO 0); + signal sd_busy_sig : std_logic; + signal sd_data_out_ftu_sig : std_logic_vector(15 DOWNTO 0) := (others => '0'); + signal sd_read_ftu_sig : std_logic; + signal sd_ready_sig : std_logic; + signal sd_started_ftu_sig : std_logic := '0'; + signal new_config_sig : std_logic := '0'; + signal config_started_sig : std_logic := '0'; + signal config_start_eth_sig : std_logic := '0'; + signal config_started_eth_sig : std_logic := '0'; + signal config_ready_eth_sig : std_logic := '0'; + signal config_started_ack_sig : std_logic := '0'; + signal ping_ftu_start_sig : std_logic := '0'; + signal ping_ftu_started_sig : std_logic := '0'; + signal ping_ftu_ready_sig : std_logic := '0'; + signal config_start_ftu_sig : std_logic := '0'; + signal config_started_ftu_sig : std_logic := '0'; + signal config_ready_ftu_sig : std_logic := '0'; + signal rates_ftu_start_sig : std_logic := '0'; + signal rates_ftu_started_sig : std_logic := '0'; + signal rates_ftu_ready_sig : std_logic := '0'; + signal fl_busy_sig : std_logic; + signal fl_ready_sig : std_logic; + signal fl_write_sig : std_logic := '0'; + signal fl_started_ftu_sig : std_logic := '0'; + signal fl_addr_sig : std_logic_vector(11 DOWNTO 0) := (others => '0'); + signal fl_data_sig : std_logic_vector(15 DOWNTO 0) := (others => '0'); + signal ping_ftu_start_ftu_sig : std_logic := '0'; + signal ping_ftu_started1_sig : std_logic := '0'; + signal ping_ftu_ready1_sig : std_logic := '0'; + signal dd_addr_ftu_sig : std_logic_vector(11 DOWNTO 0); + signal dd_busy_sig : std_logic; + signal dd_data_in_ftu_sig : std_logic_vector(15 DOWNTO 0); + signal dd_ready_sig : std_logic; + signal dd_started_ftu_sig : std_logic := '0'; + signal dd_write_ftu_sig : std_logic; + signal coin_win_c_sig : std_logic_vector(15 DOWNTO 0) := (others => '0'); + signal coin_win_p_sig : std_logic_vector(15 DOWNTO 0) := (others => '0'); + + signal clk_buf_sig : std_logic; + signal clk_1M_sig : STD_LOGIC; -- generated from 50M clock by divider + signal clk_50M_sig : STD_LOGIC; -- generated by internal DCM + signal clk_250M_sig : STD_LOGIC; -- generated by internal DCM + signal clk_250M_ps_sig : STD_LOGIC; -- generated by internal DCM + signal clk_ready_sig : STD_LOGIC := '0'; -- set high by FTM_clk_gen when DCMs have locked + + signal reset_sig : STD_LOGIC := '0'; -- initialize to 0 on power-up + + signal led_sig : std_logic_vector(7 downto 0) := (others => '0'); + + component FTM_clk_gen + port( + clk : IN STD_LOGIC; + rst : IN STD_LOGIC; + clk_1 : OUT STD_LOGIC; + clk_50 : OUT STD_LOGIC; + clk_250 : OUT STD_LOGIC; + clk_250_ps : OUT STD_LOGIC; + ready : OUT STD_LOGIC + ); + end component; + + component FTM_central_control + port( + clk : IN std_logic ; + new_config : IN std_logic ; + config_started : OUT std_logic := '0'; + config_started_ack : IN std_logic ; + config_start_eth : OUT std_logic := '0'; + config_started_eth : IN std_logic ; + config_ready_eth : IN std_logic ; + config_start_ftu : OUT std_logic := '0'; + config_started_ftu : IN std_logic ; + config_ready_ftu : IN std_logic ; + ping_ftu_start : IN std_logic ; + ping_ftu_started : OUT std_logic := '0'; + ping_ftu_ready : OUT std_logic := '0'; + ping_ftu_start_ftu : OUT std_logic := '0'; + ping_ftu_started_ftu : IN std_logic ; + ping_ftu_ready_ftu : IN std_logic + ); + end component; + + component FTM_ftu_control + port( + clk_50MHz : in std_logic; + rx_en : out STD_LOGIC; + tx_en : out STD_LOGIC; + rx_d_0 : in STD_LOGIC; + tx_d_0 : out STD_LOGIC; + rx_d_1 : in STD_LOGIC; + tx_d_1 : out STD_LOGIC; + rx_d_2 : in STD_LOGIC; + tx_d_2 : out STD_LOGIC; + rx_d_3 : in STD_LOGIC; + tx_d_3 : out STD_LOGIC; + new_config : in std_logic; + ping_all : in std_logic; + read_rates : in std_logic; + read_rates_started : out std_logic := '0'; + read_rates_done : out std_logic := '0'; + new_config_started : out std_logic := '0'; + new_config_done : out std_logic := '0'; + ping_all_started : out std_logic := '0'; + ping_all_done : out std_logic := '0'; + ftu_active_cr0 : in std_logic_vector (15 downto 0); + ftu_active_cr1 : in std_logic_vector (15 downto 0); + ftu_active_cr2 : in std_logic_vector (15 downto 0); + ftu_active_cr3 : in std_logic_vector (15 downto 0); + static_RAM_busy : in std_logic; + static_RAM_started : in std_logic; + static_RAM_ready : in std_logic; + data_static_RAM : in std_logic_vector(15 downto 0) := (others => '0'); + read_static_RAM : out std_logic := '0'; + addr_static_RAM : out std_logic_vector(11 downto 0) := (others => '0'); + dynamic_RAM_busy : in std_logic; + dynamic_RAM_started : in std_logic; + dynamic_RAM_ready : in std_logic; + data_dynamic_RAM : out std_logic_vector(15 downto 0) := (others => '0'); + write_dynamic_RAM : out std_logic := '0'; + addr_dynamic_RAM : out std_logic_vector(11 downto 0) := (others => '0'); + FTUlist_RAM_busy : in std_logic; + FTUlist_RAM_started : in std_logic; + FTUlist_RAM_ready : in std_logic; + data_FTUlist_RAM : out std_logic_vector(15 downto 0) := (others => '0'); + write_FTUlist_RAM : out std_logic := '0'; + addr_FTUlist_RAM : out std_logic_vector(11 downto 0) := (others => '0') + ); + end component; + + component ethernet_modul + port( + wiz_reset : OUT std_logic := '1'; + wiz_addr : OUT std_logic_vector (9 DOWNTO 0); + wiz_data : INOUT std_logic_vector (15 DOWNTO 0); + wiz_cs : OUT std_logic := '1'; + wiz_wr : OUT std_logic := '1'; + wiz_rd : OUT std_logic := '1'; + wiz_int : IN std_logic ; + clk : IN std_logic ; + sd_ready : OUT std_logic ; + sd_busy : OUT std_logic ; + led : OUT std_logic_vector (7 DOWNTO 0); + sd_read_ftu : IN std_logic ; + sd_started_ftu : OUT std_logic := '0'; + cc_R0 : OUT std_logic_vector (31 DOWNTO 0); + cc_R1 : OUT std_logic_vector (31 DOWNTO 0); + cc_R11 : OUT std_logic_vector (31 DOWNTO 0); + cc_R13 : OUT std_logic_vector (31 DOWNTO 0); + cc_R14 : OUT std_logic_vector (31 DOWNTO 0); + cc_R15 : OUT std_logic_vector (31 DOWNTO 0); + cc_R8 : OUT std_logic_vector (31 DOWNTO 0); + cc_R9 : OUT std_logic_vector (31 DOWNTO 0); + coin_n_c : OUT std_logic_vector (15 DOWNTO 0); + coin_n_p : OUT std_logic_vector (15 DOWNTO 0); + dead_time : OUT std_logic_vector (15 DOWNTO 0); + general_settings : OUT std_logic_vector (15 DOWNTO 0); + lp1_amplitude : OUT std_logic_vector (15 DOWNTO 0); + lp1_delay : OUT std_logic_vector (15 DOWNTO 0); + lp2_amplitude : OUT std_logic_vector (15 DOWNTO 0); + lp2_delay : OUT std_logic_vector (15 DOWNTO 0); + lp_pt_freq : OUT std_logic_vector (15 DOWNTO 0); + lp_pt_ratio : OUT std_logic_vector (15 DOWNTO 0); + timemarker_delay : OUT std_logic_vector (15 DOWNTO 0); + trigger_delay : OUT std_logic_vector (15 DOWNTO 0); + sd_addr_ftu : IN std_logic_vector (11 DOWNTO 0); + sd_data_out_ftu : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0); + ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0); + ftu_active_cr2 : OUT std_logic_vector (15 DOWNTO 0); + ftu_active_cr3 : OUT std_logic_vector (15 DOWNTO 0); + new_config : OUT std_logic := '0'; + config_started : IN std_logic ; + config_start_eth : IN std_logic ; + config_started_eth : OUT std_logic := '0'; + config_ready_eth : OUT std_logic := '0'; + config_started_ack : OUT std_logic := '0'; + fl_busy : OUT std_logic ; + fl_ready : OUT std_logic ; + fl_write_ftu : IN std_logic ; + fl_started_ftu : OUT std_logic := '0'; + fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0); + fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0) := (others => '0'); + ping_ftu_start : OUT std_logic := '0'; + ping_ftu_started : IN std_logic ; + ping_ftu_ready : IN std_logic ; + dd_write_ftu : IN std_logic ; + dd_started_ftu : OUT std_logic := '0'; + dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0); + dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0); + dd_busy : OUT std_logic ; + dd_ready : OUT std_logic ; + coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0') + ); + end component; + begin + + -- IBUFG: Single-ended global clock input buffer + -- Spartan-3A + -- Xilinx HDL Language Template, version 11.4 + + IBUFG_inst : IBUFG + generic map ( + IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, + -- "0"-"16" + IOSTANDARD => "DEFAULT") + port map ( + O => clk_buf_sig, -- Clock buffer output + I => clk -- Clock buffer input (connect directly to top-level port) + ); + + Inst_FTM_clk_gen : FTM_clk_gen + port map( + clk => clk_buf_sig, + rst => reset_sig, + clk_1 => clk_1M_sig, + clk_50 => clk_50M_sig, + clk_250 => clk_250M_sig, + clk_250_ps => clk_250M_ps_sig, + ready => clk_ready_sig + ); + + Inst_FTM_central_control : FTM_central_control + port map( + clk => clk_50M_sig, + new_config => new_config_sig, + config_started => config_started_sig, + config_started_ack => config_started_ack_sig, + config_start_eth => config_start_eth_sig, + config_started_eth => config_started_eth_sig, + config_ready_eth => config_ready_eth_sig, + config_start_ftu => config_start_ftu_sig, + config_started_ftu => config_started_ftu_sig, + config_ready_ftu => config_ready_ftu_sig, + ping_ftu_start => ping_ftu_start_sig, + ping_ftu_started => ping_ftu_started_sig, + ping_ftu_ready => ping_ftu_ready_sig, + ping_ftu_start_ftu => ping_ftu_start_ftu_sig, + ping_ftu_started_ftu => ping_ftu_started1_sig, + ping_ftu_ready_ftu => ping_ftu_ready1_sig + ); + + Inst_FTM_ftu_control : FTM_ftu_control + port map( + clk_50MHz => clk_50M_sig, + rx_en => Bus1_Rx_En, + tx_en => Bus1_Tx_En, + rx_d_0 => Bus1_RxD_0, + tx_d_0 => Bus1_TxD_0, + rx_d_1 => Bus1_RxD_1, + tx_d_1 => Bus1_TxD_1, + rx_d_2 => Bus1_RxD_2, + tx_d_2 => Bus1_TxD_2, + rx_d_3 => Bus1_RxD_3, + tx_d_3 => Bus1_TxD_3, + new_config => config_start_ftu_sig, + ping_all => ping_ftu_start_ftu_sig, + read_rates => rates_ftu_start_sig, + read_rates_started => rates_ftu_started_sig, + read_rates_done => rates_ftu_ready_sig, + new_config_started => config_started_ftu_sig, + new_config_done => config_ready_ftu_sig, + ping_all_started => ping_ftu_started1_sig, + ping_all_done => ping_ftu_ready1_sig, + ftu_active_cr0 => ftu_active_cr0_sig, + ftu_active_cr1 => ftu_active_cr1_sig, + ftu_active_cr2 => ftu_active_cr2_sig, + ftu_active_cr3 => ftu_active_cr3_sig, + static_RAM_busy => sd_busy_sig, + static_RAM_started => sd_started_ftu_sig, + static_RAM_ready => sd_ready_sig, + data_static_RAM => sd_data_out_ftu_sig, + read_static_RAM => sd_read_ftu_sig, + addr_static_RAM => sd_addr_ftu_sig, + dynamic_RAM_busy => dd_busy_sig, + dynamic_RAM_started => dd_started_ftu_sig, + dynamic_RAM_ready => dd_ready_sig, + data_dynamic_RAM => dd_data_in_ftu_sig, + write_dynamic_RAM => dd_write_ftu_sig, + addr_dynamic_RAM => dd_addr_ftu_sig, + FTUlist_RAM_busy => fl_busy_sig, + FTUlist_RAM_started => fl_started_ftu_sig, + FTUlist_RAM_ready => fl_ready_sig, + data_FTUlist_RAM => fl_data_sig, + write_FTUlist_RAM => fl_write_sig, + addr_FTUlist_RAM => fl_addr_sig + ); + + Inst_ethernet_modul : ethernet_modul + port map( + wiz_reset => W_RES, + wiz_addr => W_A, + wiz_data => W_D, + wiz_cs => W_CS, + wiz_wr => W_WR, + wiz_rd => W_RD, + wiz_int => W_INT, + clk => clk_50M_sig, + sd_ready => sd_ready_sig, + sd_busy => sd_busy_sig, + led => led_sig, + sd_read_ftu => sd_read_ftu_sig, + sd_started_ftu => sd_started_ftu_sig, + cc_R0 => cc_R0_sig, + cc_R1 => cc_R1_sig, + cc_R11 => cc_R11_sig, + cc_R13 => cc_R13_sig, + cc_R14 => cc_R14_sig, + cc_R15 => cc_R15_sig, + cc_R8 => cc_R8_sig, + cc_R9 => cc_R9_sig, + coin_n_c => coin_n_c_sig, + coin_n_p => coin_n_p_sig, + dead_time => dead_time_sig, + general_settings => general_settings_sig, + lp1_amplitude => lp1_amplitude_sig, + lp1_delay => lp1_delay_sig, + lp2_amplitude => lp2_amplitude_sig, + lp2_delay => lp2_delay_sig, + lp_pt_freq => lp_pt_freq_sig, + lp_pt_ratio => lp_pt_ratio_sig, + timemarker_delay => timemarker_delay_sig, + trigger_delay => trigger_delay_sig, + sd_addr_ftu => sd_addr_ftu_sig, + sd_data_out_ftu => sd_data_out_ftu_sig, + ftu_active_cr0 => ftu_active_cr0_sig, + ftu_active_cr1 => ftu_active_cr1_sig, + ftu_active_cr2 => ftu_active_cr2_sig, + ftu_active_cr3 => ftu_active_cr3_sig, + new_config => new_config_sig, + config_started => config_started_sig, + config_start_eth => config_start_eth_sig, + config_started_eth => config_started_eth_sig, + config_ready_eth => config_ready_eth_sig, + config_started_ack => config_started_ack_sig, + fl_busy => fl_busy_sig, + fl_ready => fl_ready_sig, + fl_write_ftu => fl_write_sig, + fl_started_ftu => fl_started_ftu_sig, + fl_addr_ftu => fl_addr_sig, + fl_data_in_ftu => fl_data_sig, + ping_ftu_start => ping_ftu_start_sig, + ping_ftu_started => ping_ftu_started_sig, + ping_ftu_ready => ping_ftu_ready_sig, + dd_write_ftu => dd_write_ftu_sig, + dd_started_ftu => dd_started_ftu_sig, + dd_data_in_ftu => dd_data_in_ftu_sig, + dd_addr_ftu => dd_addr_ftu_sig, + dd_busy => dd_busy_sig, + dd_ready => dd_ready_sig, + coin_win_c => coin_win_c_sig, + coin_win_p => coin_win_p_sig + ); + + LED_red <= led_sig(3 downto 0); + LED_ye <= led_sig(5 downto 4); + LED_gn <= led_sig(7 downto 6); end Behavioral; Index: firmware/FTM/FTM_top_tb.vhd =================================================================== --- firmware/FTM/FTM_top_tb.vhd (revision 10225) +++ firmware/FTM/FTM_top_tb.vhd (revision 10227) @@ -53,7 +53,8 @@ -- W5300 address bus - W_A : out STD_LOGIC_VECTOR(9 downto 1); -- there is NO net W_A0 because + W_A : out STD_LOGIC_VECTOR(9 downto 0); -- there is no real net W_A0 because -- the W5300 is operated in the - -- 16-bit mode + -- 16-bit mode + -- -> W_A<0> assigned to unconnected pin -- W5300 control signals @@ -67,8 +68,8 @@ -- W5300 buffer ready indicator - W_BRDY : in STD_LOGIC_VECTOR(3 downto 0); + -- W_BRDY : in STD_LOGIC_VECTOR(3 downto 0); -- testpoints (T18) associated with the W5300 - W_T : inout STD_LOGIC_VECTOR(3 downto 0); + -- W_T : inout STD_LOGIC_VECTOR(3 downto 0); @@ -77,5 +78,5 @@ -- temperature sensors U45, U46, U48 and U49 (all MAX6662) ------------------------------------------------------------------------------- - S_CLK : out STD_LOGIC; -- SPI clock + -- S_CLK : out STD_LOGIC; -- SPI clock -- EEPROM @@ -85,24 +86,24 @@ -- temperature sensors U45, U46, U48 and U49 - SIO : inout STD_LOGIC; -- serial IO - TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select + -- SIO : inout STD_LOGIC; -- serial IO + -- TS_CS : out STD_LOGIC_VECTOR(3 downto 0); -- temperature sensors chip select -- Trigger primitives inputs ------------------------------------------------------------------------------- - Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0 - Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1 - Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2 - Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3 + -- Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0 + -- Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1 + -- Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2 + -- Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3 -- NIM inputs ------------------------------------------------------------------------------ - ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input - Veto : in STD_LOGIC; -- trigger veto input - NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs + -- ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input + -- Veto : in STD_LOGIC; -- trigger veto input + -- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs -- alternative external clock input for FPGA - NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available + -- NIM_In3_GCLK : in STD_LOGIC; -- input with global clock buffer available @@ -116,10 +117,10 @@ -- Clock conditioner LMK03000 ------------------------------------------------------------------------------- - CLK_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface serial clock - LE_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface latch enable - DATA_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface data + -- CLK_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface serial clock + -- LE_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface latch enable + -- DATA_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface data - SYNC_Clk_Cond : out STD_LOGIC; -- global clock synchronization - LD_Clk_Cond : in STD_LOGIC; -- lock detect, should be checked for + -- SYNC_Clk_Cond : out STD_LOGIC; -- global clock synchronization + -- LD_Clk_Cond : in STD_LOGIC; -- lock detect, should be checked for @@ -140,22 +141,22 @@ Bus1_RxD_3 : in STD_LOGIC; -- crate 3 - Bus1_TxD_3 : out STD_LOGIC; + Bus1_TxD_3 : out STD_LOGIC -- Bus 2: Trigger-ID to FAD boards - Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable - Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable - - Bus2_RxD_0 : in STD_LOGIC; -- crate 0 - Bus2_TxD_0 : out STD_LOGIC; - - Bus2_RxD_1 : in STD_LOGIC; -- crate 1 - Bus2_TxD_1 : out STD_LOGIC; - - Bus2_RxD_2 : in STD_LOGIC; -- crate 2 - Bus2_TxD_2 : out STD_LOGIC; - - Bus2_RxD_3 : in STD_LOGIC; -- crate 3 - Bus2_TxD_3 : out STD_LOGIC; + -- Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable + -- Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable + + -- Bus2_RxD_0 : in STD_LOGIC; -- crate 0 + -- Bus2_TxD_0 : out STD_LOGIC; + + -- Bus2_RxD_1 : in STD_LOGIC; -- crate 1 + -- Bus2_TxD_1 : out STD_LOGIC; + + -- Bus2_RxD_2 : in STD_LOGIC; -- crate 2 + -- Bus2_TxD_2 : out STD_LOGIC; + + -- Bus2_RxD_3 : in STD_LOGIC; -- crate 3 + -- Bus2_TxD_3 : out STD_LOGIC; @@ -174,16 +175,16 @@ -- Crate-Resets ------------------------------------------------------------------------------- - Crate_Res0 : out STD_LOGIC; - Crate_Res1 : out STD_LOGIC; - Crate_Res2 : out STD_LOGIC; - Crate_Res3 : out STD_LOGIC; + -- Crate_Res0 : out STD_LOGIC; + -- Crate_Res1 : out STD_LOGIC; + -- Crate_Res2 : out STD_LOGIC; + -- Crate_Res3 : out STD_LOGIC; -- Busy signals from the FAD boards ------------------------------------------------------------------------------- - Busy0 : in STD_LOGIC; - Busy1 : in STD_LOGIC; - Busy2 : in STD_LOGIC; - Busy3 : in STD_LOGIC; +-- Busy0 : in STD_LOGIC; +-- Busy1 : in STD_LOGIC; +-- Busy2 : in STD_LOGIC; +-- Busy3 : in STD_LOGIC; @@ -207,13 +208,13 @@ -- LVDS output at the FPGA followed by LVDS to NIM conversion stage ------------------------------------------------------------------------------- - RES_p : out STD_LOGIC; -- RES+ Reset - RES_n : out STD_LOGIC; -- RES- - - TRG_p : out STD_LOGIC; -- TRG+ Trigger - TRG_n : out STD_LOGIC; -- TRG- - - TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker - TIM_Run_n : out STD_LOGIC; -- TIM_Run- - TIM_Sel : out STD_LOGIC; -- Time Marker selector +-- RES_p : out STD_LOGIC; -- RES+ Reset +-- RES_n : out STD_LOGIC; -- RES- + +-- TRG_p : out STD_LOGIC; -- TRG+ Trigger +-- TRG_n : out STD_LOGIC; -- TRG- + +-- TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker +-- TIM_Run_n : out STD_LOGIC; -- TIM_Run- +-- TIM_Sel : out STD_LOGIC; -- Time Marker selector -- CLD_FPGA : in STD_LOGIC; -- DRS-Clock feedback into FPGA @@ -224,23 +225,23 @@ -- to connector J13 -- for light pulsar in the mirror dish - Cal_0_p : out STD_LOGIC; - Cal_0_n : out STD_LOGIC; - Cal_1_p : out STD_LOGIC; - Cal_1_n : out STD_LOGIC; - Cal_2_p : out STD_LOGIC; - Cal_2_n : out STD_LOGIC; - Cal_3_p : out STD_LOGIC; - Cal_3_n : out STD_LOGIC; +-- Cal_0_p : out STD_LOGIC; +-- Cal_0_n : out STD_LOGIC; +-- Cal_1_p : out STD_LOGIC; +-- Cal_1_n : out STD_LOGIC; +-- Cal_2_p : out STD_LOGIC; +-- Cal_2_n : out STD_LOGIC; +-- Cal_3_p : out STD_LOGIC; +-- Cal_3_n : out STD_LOGIC; -- to connector J12 -- for light pulsar inside shutter - Cal_4_p : out STD_LOGIC; - Cal_4_n : out STD_LOGIC; - Cal_5_p : out STD_LOGIC; - Cal_5_n : out STD_LOGIC; - Cal_6_p : out STD_LOGIC; - Cal_6_n : out STD_LOGIC; - Cal_7_p : out STD_LOGIC; - Cal_7_n : out STD_LOGIC +-- Cal_4_p : out STD_LOGIC; +-- Cal_4_n : out STD_LOGIC; +-- Cal_5_p : out STD_LOGIC; +-- Cal_5_n : out STD_LOGIC; +-- Cal_6_p : out STD_LOGIC; +-- Cal_6_n : out STD_LOGIC; +-- Cal_7_p : out STD_LOGIC; +-- Cal_7_n : out STD_LOGIC @@ -291,5 +292,5 @@ --Outputs - signal W_A_sig : STD_LOGIC_VECTOR(9 downto 1); + signal W_A_sig : STD_LOGIC_VECTOR(9 downto 0); signal W_CS_sig : STD_LOGIC; signal W_RD_sig : STD_LOGIC; @@ -361,25 +362,25 @@ W_WR => W_WR_sig, W_RES => W_RES_sig, - W_BRDY => W_BRDY_sig, - W_T => W_T_sig, - S_CLK => S_CLK_sig, - SIO => SIO_sig, - TS_CS => TS_CS_sig, - Trig_Prim_A => Trig_Prim_A_sig, - Trig_Prim_B => Trig_Prim_B_sig, - Trig_Prim_C => Trig_Prim_C_sig, - Trig_Prim_D => Trig_Prim_D_sig, - ext_Trig => ext_Trig_sig, - Veto => Veto_sig, - NIM_In => NIM_In_sig, - NIM_In3_GCLK => NIM_In3_GCLK_sig, +-- W_BRDY => W_BRDY_sig, +-- W_T => W_T_sig, +-- S_CLK => S_CLK_sig, +-- SIO => SIO_sig, +-- TS_CS => TS_CS_sig, +-- Trig_Prim_A => Trig_Prim_A_sig, +-- Trig_Prim_B => Trig_Prim_B_sig, +-- Trig_Prim_C => Trig_Prim_C_sig, +-- Trig_Prim_D => Trig_Prim_D_sig, +-- ext_Trig => ext_Trig_sig, +-- Veto => Veto_sig, +-- NIM_In => NIM_In_sig, +-- NIM_In3_GCLK => NIM_In3_GCLK_sig, LED_red => LED_red_sig, LED_ye => LED_ye_sig, LED_gn => LED_gn_sig, - CLK_Clk_Cond => CLK_Clk_Cond_sig, - LE_Clk_Cond => LE_Clk_Cond_sig, - DATA_Clk_Cond => DATA_Clk_Cond_sig, - SYNC_Clk_Cond => SYNC_Clk_Cond_sig, - LD_Clk_Cond => LD_Clk_Cond_sig, +-- CLK_Clk_Cond => CLK_Clk_Cond_sig, +-- LE_Clk_Cond => LE_Clk_Cond_sig, +-- DATA_Clk_Cond => DATA_Clk_Cond_sig, +-- SYNC_Clk_Cond => SYNC_Clk_Cond_sig, +-- LD_Clk_Cond => LD_Clk_Cond_sig, Bus1_Tx_En => Bus1_Tx_En_sig, Bus1_Rx_En => Bus1_Rx_En_sig, @@ -391,46 +392,46 @@ Bus1_TxD_2 => Bus1_TxD_2_sig, Bus1_RxD_3 => Bus1_RxD_3_sig, - Bus1_TxD_3 => Bus1_TxD_3_sig, - Bus2_Tx_En => Bus2_Tx_En_sig, - Bus2_Rx_En => Bus2_Rx_En_sig, - Bus2_RxD_0 => Bus2_RxD_0_sig, - Bus2_TxD_0 => Bus2_TxD_0_sig, - Bus2_RxD_1 => Bus2_RxD_1_sig, - Bus2_TxD_1 => Bus2_TxD_1_sig, - Bus2_RxD_2 => Bus2_RxD_2_sig, - Bus2_TxD_2 => Bus2_TxD_2_sig, - Bus2_RxD_3 => Bus2_RxD_3_sig, - Bus2_TxD_3 => Bus2_TxD_3_sig, - Crate_Res0 => Crate_Res0_sig, - Crate_Res1 => Crate_Res1_sig, - Crate_Res2 => Crate_Res2_sig, - Crate_Res3 => Crate_Res3_sig, - Busy0 => Busy0_sig, - Busy1 => Busy1_sig, - Busy2 => Busy2_sig, - Busy3 => Busy3_sig, - RES_p => RES_p_sig, - RES_n => RES_n_sig, - TRG_p => TRG_p_sig, - TRG_n => TRG_n_sig, - TIM_Run_p => TIM_Run_p_sig, - TIM_Run_n => TIM_Run_n_sig, - TIM_Sel => TIM_Sel_sig, - Cal_0_p => Cal_0_p_sig, - Cal_0_n => Cal_0_n_sig, - Cal_1_p => Cal_1_p_sig, - Cal_1_n => Cal_1_n_sig, - Cal_2_p => Cal_2_p_sig, - Cal_2_n => Cal_2_n_sig, - Cal_3_p => Cal_3_p_sig, - Cal_3_n => Cal_3_n_sig, - Cal_4_p => Cal_4_p_sig, - Cal_4_n => Cal_4_n_sig, - Cal_5_p => Cal_5_p_sig, - Cal_5_n => Cal_5_n_sig, - Cal_6_p => Cal_6_p_sig, - Cal_6_n => Cal_6_n_sig, - Cal_7_p => Cal_7_p_sig, - Cal_7_n => Cal_7_n_sig + Bus1_TxD_3 => Bus1_TxD_3_sig +-- Bus2_Tx_En => Bus2_Tx_En_sig, +-- Bus2_Rx_En => Bus2_Rx_En_sig, +-- Bus2_RxD_0 => Bus2_RxD_0_sig, +-- Bus2_TxD_0 => Bus2_TxD_0_sig, +-- Bus2_RxD_1 => Bus2_RxD_1_sig, +-- Bus2_TxD_1 => Bus2_TxD_1_sig, +-- Bus2_RxD_2 => Bus2_RxD_2_sig, +-- Bus2_TxD_2 => Bus2_TxD_2_sig, +-- Bus2_RxD_3 => Bus2_RxD_3_sig, +-- Bus2_TxD_3 => Bus2_TxD_3_sig, +-- Crate_Res0 => Crate_Res0_sig, +-- Crate_Res1 => Crate_Res1_sig, +-- Crate_Res2 => Crate_Res2_sig, +-- Crate_Res3 => Crate_Res3_sig, +-- Busy0 => Busy0_sig, +-- Busy1 => Busy1_sig, +-- Busy2 => Busy2_sig, +-- Busy3 => Busy3_sig, +-- RES_p => RES_p_sig, +-- RES_n => RES_n_sig, +-- TRG_p => TRG_p_sig, +-- TRG_n => TRG_n_sig, +-- TIM_Run_p => TIM_Run_p_sig, +-- TIM_Run_n => TIM_Run_n_sig, +-- TIM_Sel => TIM_Sel_sig, +-- Cal_0_p => Cal_0_p_sig, +-- Cal_0_n => Cal_0_n_sig, +-- Cal_1_p => Cal_1_p_sig, +-- Cal_1_n => Cal_1_n_sig, +-- Cal_2_p => Cal_2_p_sig, +-- Cal_2_n => Cal_2_n_sig, +-- Cal_3_p => Cal_3_p_sig, +-- Cal_3_n => Cal_3_n_sig, +-- Cal_4_p => Cal_4_p_sig, +-- Cal_4_n => Cal_4_n_sig, +-- Cal_5_p => Cal_5_p_sig, +-- Cal_5_n => Cal_5_n_sig, +-- Cal_6_p => Cal_6_p_sig, +-- Cal_6_n => Cal_6_n_sig, +-- Cal_7_p => Cal_7_p_sig, +-- Cal_7_n => Cal_7_n_sig ); Index: firmware/FTM/clock/FTM_clk_gen.vhd =================================================================== --- firmware/FTM/clock/FTM_clk_gen.vhd (revision 10227) +++ firmware/FTM/clock/FTM_clk_gen.vhd (revision 10227) @@ -0,0 +1,156 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: Q. Weitzel +-- +-- Create Date: February 28, 2011 +-- Design Name: +-- Module Name: FTM_clk_gen - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: interface to different DCMs and clk dividers for FMU board +-- add here more DCMs if needed +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FTM_clk_gen is + Port ( + clk : IN STD_LOGIC; + rst : IN STD_LOGIC; + clk_1 : OUT STD_LOGIC; + clk_50 : OUT STD_LOGIC; + clk_250 : OUT STD_LOGIC; + clk_250_ps : OUT STD_LOGIC; + ready : OUT STD_LOGIC + ); +end FTM_clk_gen; + +architecture Behavioral of FTM_clk_gen is + + component FTM_dcm_40M_to_50M + port( + CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + LOCKED_OUT : out std_logic + ); + end component; + + component FTM_dcm_40M_to_250M + port( + CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKFX180_OUT : out std_logic; + LOCKED_OUT : out std_logic + ); + end component; + + component Clock_Divider + port( + clock_in : IN STD_LOGIC; + clock_out : OUT STD_LOGIC + ); + end component; + + signal clk_1M_sig : std_logic; + signal clk_50M_sig : std_logic; + signal clk_250M_sig : std_logic; + signal clk_250M_ps_sig : std_logic; + + signal dcm1_locked : std_logic; + signal dcm2_locked : std_logic; + +begin + + Inst_FTM_dcm_40M_to_50M : FTM_dcm_40M_to_50M + port map( + CLKIN_IN => clk, + RST_IN => rst, + CLKFX_OUT => clk_50M_sig, + LOCKED_OUT => dcm1_locked + ); + + Inst_FTM_dcm_40M_to_250M : FTM_dcm_40M_to_250M + port map( + CLKIN_IN => clk, + RST_IN => rst, + CLKFX_OUT => clk_250M_sig, + CLKFX180_OUT => clk_250M_ps_sig, + LOCKED_OUT => dcm2_locked + ); + + Inst_Clock_Divider : Clock_Divider + port map ( + clock_in => clk_50M_sig, + clock_out => clk_1M_sig + ); + + clk_1 <= clk_1M_sig; + clk_50 <= clk_50M_sig; + clk_250 <= clk_250M_sig; + clk_250_ps <= clk_250M_ps_sig; + + ready <= dcm1_locked and dcm2_locked; + +end Behavioral; + +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library ftm_definitions; +USE ftm_definitions.ftm_array_types.all; +USE ftm_definitions.ftm_constants.all; + +entity Clock_Divider is + generic( + divider : integer := INT_CLK_FREQUENCY_1 / LOW_FREQUENCY + ); + port( + clock_in : in std_logic; + clock_out : out std_logic := '0' + ); +end entity Clock_Divider; + +architecture RTL of Clock_Divider is + +begin + + process (clock_in) + variable Z: integer range 0 to divider - 1; + begin + if rising_edge(clock_in) then + if (Z < divider - 1) then + Z := Z + 1; + else + Z := 0; + end if; + if (Z = 0) then + clock_out <= '1'; + end if; + if (Z = divider / 2) then + clock_out <= '0'; + end if; + end if; + end process; + +end architecture RTL; Index: firmware/FTM/clock/FTM_dcm_40M_to_250M.vhd =================================================================== --- firmware/FTM/clock/FTM_dcm_40M_to_250M.vhd (revision 10227) +++ firmware/FTM/clock/FTM_dcm_40M_to_250M.vhd (revision 10227) @@ -0,0 +1,89 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 11.5 +-- \ \ Application : xaw2vhdl +-- / / Filename : FTM_dcm_40M_to_250M.vhd +-- /___/ /\ Timestamp : 03/02/2011 11:02:39 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st /ihp/home01/qweitzel/FPGA/trac-ISDC.svn/firmware/FTM/clock/FTM_dcm_40M_to_250M.xaw /ihp/home01/qweitzel/FPGA/trac-ISDC.svn/firmware/FTM/clock/FTM_dcm_40M_to_250M +--Design Name: FTM_dcm_40M_to_250M +--Device: xc3sd3400a-4fg676 +-- +-- Module FTM_dcm_40M_to_250M +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST +-- Period Jitter (unit interval) for block DCM_SP_INST = 0.20 UI +-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.79 ns + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity FTM_dcm_40M_to_250M is + port ( CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKFX180_OUT : out std_logic; + LOCKED_OUT : out std_logic); +end FTM_dcm_40M_to_250M; + +architecture BEHAVIORAL of FTM_dcm_40M_to_250M is + signal CLKFX_BUF : std_logic; + signal CLKFX180_BUF : std_logic; + signal GND_BIT : std_logic; +begin + GND_BIT <= '0'; + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + CLKFX180_BUFG_INST : BUFG + port map (I=>CLKFX180_BUF, + O=>CLKFX180_OUT); + + DCM_SP_INST : DCM_SP + generic map( CLK_FEEDBACK => "NONE", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 4, + CLKFX_MULTIPLY => 25, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 25.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>GND_BIT, + CLKIN=>CLKIN_IN, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>RST_IN, + CLKDV=>open, + CLKFX=>CLKFX_BUF, + CLKFX180=>CLKFX180_BUF, + CLK0=>open, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>LOCKED_OUT, + PSDONE=>open, + STATUS=>open); + +end BEHAVIORAL; + + Index: firmware/FTM/clock/FTM_dcm_40M_to_250M.xaw =================================================================== --- firmware/FTM/clock/FTM_dcm_40M_to_250M.xaw (revision 10227) +++ firmware/FTM/clock/FTM_dcm_40M_to_250M.xaw (revision 10227) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.5e +$6dx17=(aaz$dbcj00-rs`osrlf$J]IN/upbg(OTLJ$xzc!iisotewc(N]G$oaalk.DWIZbdeV>;ARz`_373I+~f81;86>!21684+1>92;?78>>;5080517:CQS_YHFESTOL]LAEKMCZEKC820M_YU_NLO]ZEKC@DTIUZJROCO50=FZ^PTCCBV_BNHMKYQIE_N=o5NRVX\KKJ^WMIFS^YFTBJJJBYDDB;;7L\XZ^MMH\YCL[UH<<>4ASUY[JHKQVNO^RM>109BVR\XGGFRSIJ]_BNH53=FZ^PTCCBV_EFQ[CJNXOFD\<;4ASUY[JHKQVLISHV[ESLBH447L\XZ^MMH\YUMZO_SAAHIB3;?DTPRVEE@TQYAMKG[A@TWDEOIk5NW[]@HNDRN]S[IGPRVLGCZZVPD:8ER\XXHX_h6OXZ^QZJQNSGFF?7OA[H59AQCA33JF@<;5LLJ3;43=DDB8<<85LLJ0[<>EKC;R:4=;4CMI:40=DDBN]o6MCKET\@LPNLL?0OAEIB49@HN@_02IGGKV>81a8GIMAP82;SO[I139@HN@_91:TNXHH_HLPPf=DDBLS=5>POTV:?FJLNQUIYKh4CMIE\ZDRNNUBB^Zl;BNHB]YCA_COIh5LLJD[[HSK\@ZGU45LLJD[[JSS=2IGGD@>1:AOOLHXL@\BHHQMY^0;?FJLAGUBBn5LLJKM[UCUAFNn7NBDIO]PVFYSQYO:>6MCKNWW[UNF[LUXDDH[c:AOOZ@BMMHJOF74CNONMQRBL>1H^HO[EE48@FKX[Yh0HNCPSQ]JJVRc3MOXGHYPAEHVWQ753MLXSK\JQTGMG\YJGMO:>6JCL^DQATSBFJSTABJJ5:FPW@H6=2N^XTQLYBNF[FIUZLI_EB@8;E]UEISBi2LJOYA]Y^HE1>@FDZO27KLPSNWQG@?JHKBOOm6B@CJGG[JSS;2FD[>5BH[58IZPFD\O<7CK[WNPH0>HHFL;0C55@FEFQGUCe3YBJ_HQ\HHDW=>VNFAKXNX]n;QKMMVAILLN37]GAWHFWL==WZ@G_U]K>0:RQKUYWAGCXMNZFVD78TVEKC?1[_IAAE59SW@H?3YYBBNJJC29QWQ04Xeo\Ilhhz_oydaa5:Y3>5[23R:1;P:4asuy7>bdek1}i}foo"2*52<~ang=<5wc2qg7167i$>mk;993:zppxFGx::0LMv?:G81>4}T;m0<579m:011`gbb28=?;iua7482?k112<1/;9483:P7f<013=i6<==dcff>4>00l1o;44?:082V5c2>31;o4>33fa``<6?==o7{Z81;295?7=?rY8h796:6`9564cjmo1=::8d:`5`?6=8391;v*k:6c8 4b=?j1/=h48d:&2b?1b3-=9685m3g83>45=83:p(;>53d9'a?4?3-l1:45+10816>"6:3897)?<:318 42=:;1/=84:b:&22?0>3-;<695+1986=>"613><7)?n:328 6d==01/>448;%11>g=#;:037)=9:558 6>=12.857:i;%1b>0?<,=:1:n5+4487?!262:6*;b;75?!2d2h1/9=4;a:&63?d<,:0(<>5c:&2g?2c3-?96?5+5080?l52290/9k487:&55?0b32c9m7>5$4d932=#=l0=i6*91;4f?>o1>3:1(8h5769'24<1m21b:94?:%7e>21<,5$4d932=#=l0=i65`2383>!3a2>=07b<8:18'1c<0?21d>>4?:%7e>21<3f8?6=4+5g843>=h:10;6);i:658?j42290/9k487:9l63<72-?m6:94;n0a>5<#=o0<;6*91;4f?!7e2;;07b77<3f"2l31/:<49e:9l26<72-?m6:94;|`05?6=:3:1m7>5$4d932=#>80=i65rb3g94?4=83:p(;>5209j0`<72-?m6:94$7392`=7)87:5g8yv00290:w0=i:748 3>=>50;0x96`=:k16?<4;e:p6a<72;q6?k4=c:?1a?2b3ty>87>51z?0b?343-<368o4}r17>5<6s49:68o4$7:91d=z{;l1<7?t=3g91d=#>10>m6srn3094?7|ug886=4>{|l10?6=9rwe>84?:0y~j70=83;pqc<8:182xh503:1=vsr}|BCG~572l=3mom75|BCF~6zHIZpqMN Index: firmware/FTM/clock/FTM_dcm_40M_to_250M_arwz.ucf =================================================================== --- firmware/FTM/clock/FTM_dcm_40M_to_250M_arwz.ucf (revision 10227) +++ firmware/FTM/clock/FTM_dcm_40M_to_250M_arwz.ucf (revision 10227) @@ -0,0 +1,17 @@ +# Generated by Xilinx Architecture Wizard +# --- UCF Template Only --- +# Cut and paste these attributes into the project's UCF file, if desired +INST DCM_SP_INST CLK_FEEDBACK = NONE; +INST DCM_SP_INST CLKDV_DIVIDE = 2.0; +INST DCM_SP_INST CLKFX_DIVIDE = 4; +INST DCM_SP_INST CLKFX_MULTIPLY = 25; +INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; +INST DCM_SP_INST CLKIN_PERIOD = 25.000; +INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; +INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; +INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; +INST DCM_SP_INST FACTORY_JF = C080; +INST DCM_SP_INST PHASE_SHIFT = 0; +INST DCM_SP_INST STARTUP_WAIT = FALSE; Index: firmware/FTM/clock/FTM_dcm_40M_to_50M.vhd =================================================================== --- firmware/FTM/clock/FTM_dcm_40M_to_50M.vhd (revision 10227) +++ firmware/FTM/clock/FTM_dcm_40M_to_50M.vhd (revision 10227) @@ -0,0 +1,83 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 11.5 +-- \ \ Application : xaw2vhdl +-- / / Filename : FTM_dcm_40M_to_50M.vhd +-- /___/ /\ Timestamp : 03/01/2011 18:26:24 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st /ihp/home01/qweitzel/FPGA/trac-ISDC.svn/firmware/FTM/clock/FTM_dcm_40M_to_50M.xaw /ihp/home01/qweitzel/FPGA/trac-ISDC.svn/firmware/FTM/clock/FTM_dcm_40M_to_50M +--Design Name: FTM_dcm_40M_to_50M +--Device: xc3sd3400a-4fg676 +-- +-- Module FTM_dcm_40M_to_50M +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST +-- Period Jitter (unit interval) for block DCM_SP_INST = 0.04 UI +-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.86 ns + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity FTM_dcm_40M_to_50M is + port ( CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + LOCKED_OUT : out std_logic); +end FTM_dcm_40M_to_50M; + +architecture BEHAVIORAL of FTM_dcm_40M_to_50M is + signal CLKFX_BUF : std_logic; + signal GND_BIT : std_logic; +begin + GND_BIT <= '0'; + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + DCM_SP_INST : DCM_SP + generic map( CLK_FEEDBACK => "NONE", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 4, + CLKFX_MULTIPLY => 5, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 25.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>GND_BIT, + CLKIN=>CLKIN_IN, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>RST_IN, + CLKDV=>open, + CLKFX=>CLKFX_BUF, + CLKFX180=>open, + CLK0=>open, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>LOCKED_OUT, + PSDONE=>open, + STATUS=>open); + +end BEHAVIORAL; + + Index: firmware/FTM/clock/FTM_dcm_40M_to_50M.xaw =================================================================== --- firmware/FTM/clock/FTM_dcm_40M_to_50M.xaw (revision 10227) +++ firmware/FTM/clock/FTM_dcm_40M_to_50M.xaw (revision 10227) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.5e +$6ax14=(aaz$dbcj00-rs`osrlf$J]IN/upbg(OTLJ$xzc!iisotewc(N]G$oaalk.DWIZbdeV>;ARz`_42N*}gp92:?7= ?4593*=0638>0=< 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6b=>01/8?4;;%1f>04<,:l19?5+4085f>"3;3<0(9;5579'03<2;2.?47;<;%6:>f=#3b<,8:1m6*>c;6b?!2a2;1/8h4<;h11>5<#=j0<86*:e;4a?>o5i3:1(8m5759'1g<1j2.>i78m;:k57?6=,=n>80;6);l:668 0d=>k10e;<50;&6g?133-?i6;l4;h7e>5<#=j0<86*:b;4a?>o383:1(8m5759'1g<1j21d>?4?:%7`>22<3f8<6=4+5b840>=h::0;6);l:668?j43290/9n484:9l6=<72-?h6::4;n06>5<#=j0<865`2783>!3d2>>07bi78m;%3a>77<3f8h6=4+5b840>=h>10;6);l:678 0g=>k10c8>50;&6g?133-?n6;l4;n43>5<#=j0<865rb3g94?4=83:p(8j5209j0g<72-?h6::4$4g92g=h4;b:p14<728q6?n4:0:&51?303ty8=7>51z?1a?303-<>6894}|l2b?6=9rwe>=4?:0y~j77=83;pqc<=:182xh5;3:1=vsr}|BCG~4>2k9n;llk7|BCF~6zHIZpqMN Index: firmware/FTM/clock/FTM_dcm_40M_to_50M_arwz.ucf =================================================================== --- firmware/FTM/clock/FTM_dcm_40M_to_50M_arwz.ucf (revision 10227) +++ firmware/FTM/clock/FTM_dcm_40M_to_50M_arwz.ucf (revision 10227) @@ -0,0 +1,17 @@ +# Generated by Xilinx Architecture Wizard +# --- UCF Template Only --- +# Cut and paste these attributes into the project's UCF file, if desired +INST DCM_SP_INST CLK_FEEDBACK = NONE; +INST DCM_SP_INST CLKDV_DIVIDE = 2.0; +INST DCM_SP_INST CLKFX_DIVIDE = 4; +INST DCM_SP_INST CLKFX_MULTIPLY = 5; +INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; +INST DCM_SP_INST CLKIN_PERIOD = 25.000; +INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; +INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; +INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; +INST DCM_SP_INST FACTORY_JF = C080; +INST DCM_SP_INST PHASE_SHIFT = 0; +INST DCM_SP_INST STARTUP_WAIT = FALSE; Index: firmware/FTM/clock/xaw2vhdl.log =================================================================== --- firmware/FTM/clock/xaw2vhdl.log (revision 10227) +++ firmware/FTM/clock/xaw2vhdl.log (revision 10227) @@ -0,0 +1,1 @@ +xaw2vhdl: Completed successfully Index: firmware/FTM/ethernet/CRAM_4096_16b.ngc =================================================================== --- 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firmware/FTM/ethernet/CRAM_4096_16b_CRAM_4096_16b_a.vhd (revision 10227) @@ -0,0 +1,151 @@ +-- Coregen VHDL wrapper file modified by HDL Designer + +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file CRAM_4096_16b.vhd when simulating +-- the core, CRAM_4096_16b. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +-- hds interface_start +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; + +-- synthesis translate_on +-- +ENTITY CRAM_4096_16b IS + PORT( + clka : IN std_logic; + dina : IN std_logic_VECTOR (15 DOWNTO 0); + addra : IN std_logic_VECTOR (11 DOWNTO 0); + wea : IN std_logic_VECTOR (0 DOWNTO 0); + clkb : IN std_logic; + addrb : IN std_logic_VECTOR (11 DOWNTO 0); + doutb : OUT std_logic_VECTOR (15 DOWNTO 0) + ); + +-- Declarations + +END CRAM_4096_16b ; +-- hds interface_end + +ARCHITECTURE CRAM_4096_16b_a OF CRAM_4096_16b IS + +-- hds translate_off + +-- synthesis translate_off +component wrapped_CRAM_4096_16b + port ( + clka: IN std_logic; + dina: IN std_logic_VECTOR(15 downto 0); + addra: IN std_logic_VECTOR(11 downto 0); + wea: IN std_logic_VECTOR(0 downto 0); + clkb: IN std_logic; + addrb: IN std_logic_VECTOR(11 downto 0); + doutb: OUT std_logic_VECTOR(15 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_CRAM_4096_16b use entity XilinxCoreLib.blk_mem_gen_v2_8(behavioral) + generic map( + c_has_regceb => 0, + c_has_regcea => 0, + c_mem_type => 1, + c_prim_type => 1, + c_sinita_val => "0", + c_read_width_b => 16, + c_family => "spartan3", + c_read_width_a => 16, + c_disable_warn_bhv_coll => 0, + c_write_mode_b => "READ_FIRST", + c_init_file_name => "no_coe_file_loaded", + c_write_mode_a => "READ_FIRST", + c_mux_pipeline_stages => 0, + c_has_mem_output_regs_b => 0, + c_load_init_file => 0, + c_xdevicefamily => "spartan3a", + c_has_mem_output_regs_a => 0, + c_write_depth_b => 4096, + c_write_depth_a => 4096, + c_has_ssrb => 0, + c_has_mux_output_regs_b => 0, + c_has_ssra => 0, + c_has_mux_output_regs_a => 0, + c_addra_width => 12, + c_addrb_width => 12, + c_default_data => "0", + c_use_ecc => 0, + c_algorithm => 1, + c_disable_warn_bhv_range => 0, + c_write_width_b => 16, + c_write_width_a => 16, + c_read_depth_b => 4096, + c_read_depth_a => 4096, + c_byte_size => 9, + c_sim_collision_check => "ALL", + c_use_ramb16bwer_rst_bhv => 0, + c_common_clk => 0, + c_wea_width => 1, + c_has_enb => 0, + c_web_width => 1, + c_has_ena => 0, + c_sinitb_val => "0", + c_use_byte_web => 0, + c_use_byte_wea => 0, + c_use_default_data => 1); +-- synthesis translate_on + +-- hds translate_on + +BEGIN + +-- hds translate_off + +-- synthesis translate_off +U0 : wrapped_CRAM_4096_16b + port map ( + clka => clka, + dina => dina, + addra => addra, + wea => wea, + clkb => clkb, + addrb => addrb, + doutb => doutb); +-- synthesis translate_on + + +-- hds translate_on + +END CRAM_4096_16b_a; Index: firmware/FTM/ethernet/DRAM_4096_16b.ngc =================================================================== --- firmware/FTM/ethernet/DRAM_4096_16b.ngc (revision 10227) +++ firmware/FTM/ethernet/DRAM_4096_16b.ngc (revision 10227) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e +$3244g<,[o}e~g`n;"2*413&;$>"9 > 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41a287}O91:0qc=ke;296~N6091vb>ji:181M7?82we?h>50;0xL4>73td8i<4?:3yK5=67>52zJ2<5=zf:o86=4={I3;4>{i;l>1<73:1>vF>819~j6c02909wE?70:m7`>=838pD<6?;|l0a<<72;qC=5>4}o1fe?6=:rB:4=5rn2ga>5<5sA;3<6sa3da94?4|@82;7p`7}O91:0qc=je;296~N6091vb>ki:181M7?82we?k>50;0xL4>73td8j<4?:3yK5=67>52zJ2<5=zf:l86=4={I3;4>{i;o>1<73:1>vF>819~j6`02909wE?70:m7c>=838pD<6?;|l0b<<72;qC=5>4}o1ee?6=:rB:4=5rn2da>5<5sA;3<6sa3ga94?4|@82;7p`7}O91:0qc=ie;296~N6091vb>hi:181M7?82we8=>50;0xL4>73td?<<4?:3yK5=6;>7>52zJ2<5=zf=:86=4={I3;4>{i<9>1<73:1>vF>819~j1602909wE?70:m05>=838pD<6?;|l74<<72;qC=5>4}o63e?6=:rB:4=5rn52a>5<5sA;3<6sa41a94?4|@82;7p`;0e83>7}O91:0qc:?e;296~N6091vb9>i:181M7?82we8<>50;0xL4>73td?=<4?:3yK5=6:>7>52zJ2<5=zf=;86=4={I3;4>{i<8>1<73:1>vF>819~j6?a290:wE?70:m7ad=83;pD<6?;|~yEFDs=??6>6?14417xFGJr:vLM^t}AB Index: firmware/FTM/ethernet/DRAM_4096_16b_DRAM_4096_16b_a.vhd =================================================================== --- firmware/FTM/ethernet/DRAM_4096_16b_DRAM_4096_16b_a.vhd (revision 10227) +++ firmware/FTM/ethernet/DRAM_4096_16b_DRAM_4096_16b_a.vhd (revision 10227) @@ -0,0 +1,151 @@ +-- Coregen VHDL wrapper file modified by HDL Designer + +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file DRAM_4096_16b.vhd when simulating +-- the core, DRAM_4096_16b. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +-- hds interface_start +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; + +-- synthesis translate_on +-- +ENTITY DRAM_4096_16b IS + PORT( + clka : IN std_logic; + dina : IN std_logic_VECTOR (15 DOWNTO 0); + addra : IN std_logic_VECTOR (11 DOWNTO 0); + wea : IN std_logic_VECTOR (0 DOWNTO 0); + clkb : IN std_logic; + addrb : IN std_logic_VECTOR (11 DOWNTO 0); + doutb : OUT std_logic_VECTOR (15 DOWNTO 0) + ); + +-- Declarations + +END DRAM_4096_16b ; +-- hds interface_end + +ARCHITECTURE DRAM_4096_16b_a OF DRAM_4096_16b IS + +-- hds translate_off + +-- synthesis translate_off +component wrapped_DRAM_4096_16b + port ( + clka: IN std_logic; + dina: IN std_logic_VECTOR(15 downto 0); + addra: IN std_logic_VECTOR(11 downto 0); + wea: IN std_logic_VECTOR(0 downto 0); + clkb: IN std_logic; + addrb: IN std_logic_VECTOR(11 downto 0); + doutb: OUT std_logic_VECTOR(15 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_DRAM_4096_16b use entity XilinxCoreLib.blk_mem_gen_v2_8(behavioral) + generic map( + c_has_regceb => 0, + c_has_regcea => 0, + c_mem_type => 1, + c_prim_type => 1, + c_sinita_val => "0", + c_read_width_b => 16, + c_family => "spartan3", + c_read_width_a => 16, + c_disable_warn_bhv_coll => 0, + c_write_mode_b => "READ_FIRST", + c_init_file_name => "no_coe_file_loaded", + c_write_mode_a => "READ_FIRST", + c_mux_pipeline_stages => 0, + c_has_mem_output_regs_b => 0, + c_load_init_file => 0, + c_xdevicefamily => "spartan3a", + c_has_mem_output_regs_a => 0, + c_write_depth_b => 4096, + c_write_depth_a => 4096, + c_has_ssrb => 0, + c_has_mux_output_regs_b => 0, + c_has_ssra => 0, + c_has_mux_output_regs_a => 0, + c_addra_width => 12, + c_addrb_width => 12, + c_default_data => "0", + c_use_ecc => 0, + c_algorithm => 1, + c_disable_warn_bhv_range => 0, + c_write_width_b => 16, + c_write_width_a => 16, + c_read_depth_b => 4096, + c_read_depth_a => 4096, + c_byte_size => 9, + c_sim_collision_check => "ALL", + c_use_ramb16bwer_rst_bhv => 0, + c_common_clk => 0, + c_wea_width => 1, + c_has_enb => 0, + c_web_width => 1, + c_has_ena => 0, + c_sinitb_val => "0", + c_use_byte_web => 0, + c_use_byte_wea => 0, + c_use_default_data => 1); +-- synthesis translate_on + +-- hds translate_on + +BEGIN + +-- hds translate_off + +-- synthesis translate_off +U0 : wrapped_DRAM_4096_16b + port map ( + clka => clka, + dina => dina, + addra => addra, + wea => wea, + clkb => clkb, + addrb => addrb, + doutb => doutb); +-- synthesis translate_on + + +-- hds translate_on + +END DRAM_4096_16b_a; Index: firmware/FTM/ethernet/FRAM_4096_16b.ngc =================================================================== --- firmware/FTM/ethernet/FRAM_4096_16b.ngc (revision 10227) +++ firmware/FTM/ethernet/FRAM_4096_16b.ngc (revision 10227) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e +$3244g<,[o}e~g`n;"2*413&;$>"9 > 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c_init_file_name => "no_coe_file_loaded", + c_write_mode_a => "READ_FIRST", + c_mux_pipeline_stages => 0, + c_has_mem_output_regs_b => 0, + c_load_init_file => 0, + c_xdevicefamily => "spartan3a", + c_has_mem_output_regs_a => 0, + c_write_depth_b => 4096, + c_write_depth_a => 4096, + c_has_ssrb => 0, + c_has_mux_output_regs_b => 0, + c_has_ssra => 0, + c_has_mux_output_regs_a => 0, + c_addra_width => 12, + c_addrb_width => 12, + c_default_data => "0", + c_use_ecc => 0, + c_algorithm => 1, + c_disable_warn_bhv_range => 0, + c_write_width_b => 16, + c_write_width_a => 16, + c_read_depth_b => 4096, + c_read_depth_a => 4096, + c_byte_size => 9, + c_sim_collision_check => "ALL", + c_use_ramb16bwer_rst_bhv => 0, + c_common_clk => 0, + c_wea_width => 1, + c_has_enb => 0, + c_web_width => 1, + c_has_ena => 0, + c_sinitb_val => "0", + c_use_byte_web => 0, + c_use_byte_wea => 0, + c_use_default_data => 1); +-- synthesis translate_on + +-- hds translate_on + +BEGIN + +-- hds translate_off + +-- synthesis translate_off +U0 : wrapped_FRAM_4096_16b + port map ( + clka => clka, + dina => dina, + addra => addra, + wea => wea, + clkb => clkb, + addrb => addrb, + doutb => doutb); +-- synthesis translate_on + + +-- hds translate_on + +END FRAM_4096_16b_a; Index: firmware/FTM/ethernet/cram_control_beha.vhd =================================================================== --- firmware/FTM/ethernet/cram_control_beha.vhd (revision 10227) +++ firmware/FTM/ethernet/cram_control_beha.vhd (revision 10227) @@ -0,0 +1,349 @@ +-- +-- VHDL Architecture FACT_FTM_lib.cram_control.beha +-- +-- Created: +-- by - kai.UNKNOWN (E5PCXX) +-- at - 14:42:24 01.02.2011 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE IEEE.STD_LOGIC_UNSIGNED.all; +-- LIBRARY FACT_FTM_lib; +-- USE FACT_FTM_lib.ftm_array_types.all; +-- USE FACT_FTM_lib.ftm_constants.all; +library ftm_definitions; +USE ftm_definitions.ftm_array_types.all; +USE ftm_definitions.ftm_constants.all; + +ENTITY cram_control IS + PORT( + clk : IN std_logic; + led : OUT std_logic_vector (7 downto 0) := X"00"; + cram_data_in : OUT std_logic_vector (15 downto 0); + cram_data_out : IN std_logic_vector (15 downto 0); + cram_addr_in, cram_addr_out : OUT std_logic_vector (11 downto 0); + cram_we : OUT std_logic_vector (0 downto 0) := "0"; + sd_write, sd_read, sd_read_ftu : IN std_logic; + sd_busy : OUT std_logic := '1'; + sd_started, sd_started_ftu : OUT std_logic := '0'; + sd_ready : OUT std_logic := '0'; + sd_data_in : IN std_logic_vector (15 downto 0); + sd_data_out, sd_data_out_ftu : OUT std_logic_vector (15 downto 0) := (others => '0'); + sd_addr, sd_addr_ftu : IN std_logic_vector (11 downto 0); + + config_start_cc : IN std_logic; + config_started_cc : OUT std_logic := '0'; + config_ready_cc : OUT std_logic := '0'; + + -- data from config ram + general_settings : OUT std_logic_vector (15 downto 0) := (others => '0'); + lp_pt_freq : OUT std_logic_vector (15 downto 0) := (others => '0'); + lp_pt_ratio : OUT std_logic_vector (15 downto 0) := (others => '0'); + lp1_amplitude : OUT std_logic_vector (15 downto 0) := (others => '0'); + lp2_amplitude : OUT std_logic_vector (15 downto 0) := (others => '0'); + lp1_delay : OUT std_logic_vector (15 downto 0) := (others => '0'); + lp2_delay : OUT std_logic_vector (15 downto 0) := (others => '0'); + coin_n_p : OUT std_logic_vector (15 downto 0) := (others => '0'); + coin_n_c : OUT std_logic_vector (15 downto 0) := (others => '0'); + trigger_delay : OUT std_logic_vector (15 downto 0) := (others => '0'); + timemarker_delay : OUT std_logic_vector (15 downto 0) := (others => '0'); + dead_time : OUT std_logic_vector (15 downto 0) := (others => '0'); + cc_R0 : OUT std_logic_vector (31 downto 0) := (others => '0'); + cc_R1 : OUT std_logic_vector (31 downto 0) := (others => '0'); + cc_R8 : OUT std_logic_vector (31 downto 0) := (others => '0'); + cc_R9 : OUT std_logic_vector (31 downto 0) := (others => '0'); + cc_R11 : OUT std_logic_vector (31 downto 0) := (others => '0'); + cc_R13 : OUT std_logic_vector (31 downto 0) := (others => '0'); + cc_R14 : OUT std_logic_vector (31 downto 0) := (others => '0'); + cc_R15 : OUT std_logic_vector (31 downto 0) := (others => '0'); + coin_win_p : OUT std_logic_vector (15 downto 0) := (others => '0'); + coin_win_c : OUT std_logic_vector (15 downto 0) := (others => '0'); + ftu_active_cr0 : OUT std_logic_vector (15 downto 0) := (others => '0'); + ftu_active_cr1 : OUT std_logic_vector (15 downto 0) := (others => '0'); + ftu_active_cr2 : OUT std_logic_vector (15 downto 0) := (others => '0'); + ftu_active_cr3 : OUT std_logic_vector (15 downto 0) := (others => '0') + ); + +-- Declarations + +END cram_control ; + +-- +ARCHITECTURE beha OF cram_control IS + + type state_cram_proc_type is (CR_INIT, CR_INIT_01, CR_INIT_02, CR_INIT_03, + CR_CONFIG, CR_CONFIG_START, CR_CONFIG_01, + CR_IDLE, CR_WRITE_START, CR_WRITE_END, CR_READ_START, CR_READ_WAIT, CR_READ_END, + CR_DOUT_WIZ_START, CR_DOUT_WIZ_END, CR_DOUT_FTU_START, CR_DOUT_FTU_END); + signal state_cram_proc : state_cram_proc_type := CR_INIT; + signal next_state : state_cram_proc_type := CR_IDLE; + + signal local_sd_addr : std_logic_vector (11 downto 0) := X"000"; + signal local_sd_data : std_logic_vector (15 downto 0); +-- signal addr_cnt : integer range 0 to 4096 := 0; + signal addr_cnt : std_logic_vector (11 downto 0) := X"000"; + signal ftu_cnt : integer range 0 to SD_FTU_NUM := 0; + signal ftu_active_cnt : integer range 0 to SD_FTU_ACTIVE_NUM := 0; + +BEGIN + + cram_proc : process (clk) + begin + if rising_edge (clk) then + case state_cram_proc is + + when CR_INIT => + addr_cnt <= X"000"; + state_cram_proc <= CR_INIT_01; + + -- general part of static data block + when CR_INIT_01 => + if (addr_cnt < SD_BLOCK_SIZE_GENERAL) then + local_sd_addr <= addr_cnt; + local_sd_data <= sd_block_default_array (conv_integer (addr_cnt)); + addr_cnt <= addr_cnt + 1; + next_state <= CR_INIT_01; + state_cram_proc <= CR_WRITE_START; + else + addr_cnt <= X"000"; + ftu_cnt <= 0; + state_cram_proc <= CR_INIT_02; + end if; + + -- defaults for FTUs + when CR_INIT_02 => + if (ftu_cnt < SD_FTU_NUM) then + if (addr_cnt < SD_FTU_DATA_SIZE) then + local_sd_addr <= SD_FTU_BASE_ADDR + (ftu_cnt * SD_FTU_DATA_SIZE) + addr_cnt; + -- only for testing + -- local_sd_data <= sd_block_ftu_default_array (conv_integer (addr_cnt)) OR (conv_std_logic_vector (ftu_cnt, 8) & X"00"); + -- for FTM-Board + local_sd_data <= sd_block_ftu_default_array (conv_integer (addr_cnt)); + -- -- + addr_cnt <= addr_cnt + 1; + next_state <= CR_INIT_02; + state_cram_proc <= CR_WRITE_START; + else + addr_cnt <= X"000"; + ftu_cnt <= ftu_cnt + 1; + end if; + else + addr_cnt <= X"000"; + state_cram_proc <= CR_INIT_03; + end if; + + -- defaults for active FTU lists + when CR_INIT_03 => + if (ftu_active_cnt < SD_FTU_ACTIVE_NUM) then + local_sd_addr <= SD_FTU_ACTIVE_BASE_ADDR + conv_std_logic_vector (ftu_active_cnt, 12); + -- only for testing + -- local_sd_data <= conv_std_logic_vector (ftu_active_cnt, 16); + -- for FTM-Board + local_sd_data <= sd_block_activeFTUlist_default_array (ftu_active_cnt); + ftu_active_cnt <= ftu_active_cnt + 1; + next_state <= CR_INIT_03; + state_cram_proc <= CR_WRITE_START; + else + ftu_active_cnt <= 0; + state_cram_proc <= CR_CONFIG; + end if; + + + when CR_CONFIG => + if (config_start_cc = '1') then + config_ready_cc <= '0'; + config_started_cc <= '1'; + state_cram_proc <= CR_CONFIG_START; + end if; + + when CR_CONFIG_START => + if (addr_cnt < SD_BLOCK_SIZE) then + if ((addr_cnt < SD_FTU_BASE_ADDR) OR (addr_cnt >= SD_FTU_ACTIVE_BASE_ADDR)) then + local_sd_addr <= addr_cnt; + next_state <= CR_CONFIG_01; + state_cram_proc <= CR_READ_START; + elsif (addr_cnt = SD_FTU_BASE_ADDR) then + addr_cnt <= SD_FTU_ACTIVE_BASE_ADDR; + end if; + else + addr_cnt <= X"000"; + config_started_cc <= '0'; + config_ready_cc <= '1'; + state_cram_proc <= CR_IDLE; + end if; + + when CR_CONFIG_01 => + state_cram_proc <= CR_CONFIG_START; + addr_cnt <= addr_cnt + 1; + case addr_cnt is + when SD_ADDR_general_settings => + general_settings <= local_sd_data; + when SD_ADDR_led => + led <= local_sd_data (7 downto 0); + when SD_ADDR_lp_pt_freq => + lp_pt_freq <= local_sd_data; + when SD_ADDR_lp_pt_ratio => + lp_pt_ratio <= local_sd_data; + when SD_ADDR_lp1_amplitude => + lp1_amplitude <= local_sd_data; + when SD_ADDR_lp2_amplitude => + lp2_amplitude <= local_sd_data; + when SD_ADDR_lp1_delay => + lp1_delay <= local_sd_data; + when SD_ADDR_lp2_delay => + lp2_delay <= local_sd_data; + when SD_ADDR_coin_n_p => + coin_n_p <= local_sd_data; + when SD_ADDR_coin_n_c => + coin_n_c <= local_sd_data; + when SD_ADDR_trigger_delay => + trigger_delay <= local_sd_data; + when SD_ADDR_timemarker_delay => + timemarker_delay <= local_sd_data; + when SD_ADDR_dead_time => + dead_time <= local_sd_data; + when SD_ADDR_cc_R0_HI => + cc_R0 (31 downto 16) <= local_sd_data; + when SD_ADDR_cc_R0_LO => + cc_R0 (15 downto 0) <= local_sd_data; + when SD_ADDR_cc_R1_HI => + cc_R1 (31 downto 16) <= local_sd_data; + when SD_ADDR_cc_R1_LO => + cc_R1 (15 downto 0) <= local_sd_data; + when SD_ADDR_cc_R8_HI => + cc_R8 (31 downto 16) <= local_sd_data; + when SD_ADDR_cc_R8_LO => + cc_R8 (15 downto 0) <= local_sd_data; + when SD_ADDR_cc_R9_HI => + cc_R9 (31 downto 16) <= local_sd_data; + when SD_ADDR_cc_R9_LO => + cc_R9 (15 downto 0) <= local_sd_data; + when SD_ADDR_cc_R11_HI => + cc_R11 (31 downto 16) <= local_sd_data; + when SD_ADDR_cc_R11_LO => + cc_R11 (15 downto 0) <= local_sd_data; + when SD_ADDR_cc_R13_HI => + cc_R13 (31 downto 16) <= local_sd_data; + when SD_ADDR_cc_R13_LO => + cc_R13 (15 downto 0) <= local_sd_data; + when SD_ADDR_cc_R14_HI => + cc_R14 (31 downto 16) <= local_sd_data; + when SD_ADDR_cc_R14_LO => + cc_R14 (15 downto 0) <= local_sd_data; + when SD_ADDR_cc_R15_HI => + cc_R15 (31 downto 16) <= local_sd_data; + when SD_ADDR_cc_R15_LO => + cc_R15 (15 downto 0) <= local_sd_data; + when SD_ADDR_coin_win_p => + coin_win_p <= local_sd_data; + when SD_ADDR_coin_win_c => + coin_win_c <= local_sd_data; + when SD_ADDR_ftu_active_cr0 => + ftu_active_cr0 <= local_sd_data; + when SD_ADDR_ftu_active_cr1 => + ftu_active_cr1 <= local_sd_data; + when SD_ADDR_ftu_active_cr2 => + ftu_active_cr2 <= local_sd_data; + when SD_ADDR_ftu_active_cr3 => + ftu_active_cr3 <= local_sd_data; + when others => + null; + end case; + + when CR_IDLE => + sd_busy <= '0'; + + if (config_start_cc = '1') then + sd_busy <= '1'; + state_cram_proc <= CR_CONFIG; + + elsif (sd_write = '1') then + sd_busy <= '1'; + sd_started <= '1'; + sd_ready <= '0'; + local_sd_addr <= sd_addr; + local_sd_data <= sd_data_in; + next_state <= CR_IDLE; + state_cram_proc <= CR_WRITE_START; + + elsif (sd_read = '1') then + sd_busy <= '1'; + sd_started <= '1'; + sd_ready <= '0'; + local_sd_addr <= sd_addr; + next_state <= CR_DOUT_WIZ_START; + state_cram_proc <= CR_READ_START; + + elsif (sd_read_ftu = '1') then + sd_busy <= '1'; + sd_started_ftu <= '1'; + sd_ready <= '0'; + local_sd_addr <= sd_addr_ftu; + next_state <= CR_DOUT_FTU_START; + state_cram_proc <= CR_READ_START; + end if; + + + when CR_DOUT_FTU_START => + sd_data_out_ftu <= local_sd_data; + sd_ready <= '1'; + state_cram_proc <= CR_DOUT_FTU_END; + + when CR_DOUT_FTU_END => + if (sd_read_ftu <= '0') then + sd_started_ftu <= '0'; + state_cram_proc <= CR_IDLE; + end if; + + when CR_DOUT_WIZ_START => + sd_data_out <= local_sd_data; + sd_ready <= '1'; + state_cram_proc <= CR_DOUT_WIZ_END; + + when CR_DOUT_WIZ_END => + if (sd_read <= '0') then + sd_started <= '0'; + state_cram_proc <= CR_IDLE; + end if; + + + -- -- + -- write to config ram + -- -- + when CR_WRITE_START => + cram_addr_in <= local_sd_addr; + cram_data_in <= local_sd_data; + cram_we <= "1"; + state_cram_proc <= CR_WRITE_END; + + when CR_WRITE_END => + cram_we <= "0"; + sd_started <= '0'; + sd_ready <= '1'; + state_cram_proc <= next_state; + + + -- -- + -- read from config ram + -- -- + when CR_READ_START => + cram_addr_out <= local_sd_addr; + state_cram_proc <= CR_READ_WAIT; + + when CR_READ_WAIT => + state_cram_proc <= CR_READ_END; + + when CR_READ_END => + local_sd_data <= cram_data_out; + state_cram_proc <= next_state; + + + end case; + end if; -- rising edge + end process cram_proc; + +END ARCHITECTURE beha; + Index: firmware/FTM/ethernet/dram_control_beha.vhd =================================================================== --- firmware/FTM/ethernet/dram_control_beha.vhd (revision 10227) +++ firmware/FTM/ethernet/dram_control_beha.vhd (revision 10227) @@ -0,0 +1,179 @@ +-- +-- VHDL Architecture FACT_FTM_lib.dram_control.beha +-- +-- Created: +-- by - kai.UNKNOWN (E5PCXX) +-- at - 11:39:22 23.02.2011 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE IEEE.STD_LOGIC_UNSIGNED.all; +-- LIBRARY FACT_FTM_lib; +-- USE FACT_FTM_lib.ftm_array_types.all; +-- USE FACT_FTM_lib.ftm_constants.all; +library ftm_definitions; +USE ftm_definitions.ftm_array_types.all; +USE ftm_definitions.ftm_constants.all; + +ENTITY dram_control IS + PORT( + clk : IN std_logic; + dram_data_in : OUT std_logic_vector (15 DOWNTO 0); + dram_data_out : IN std_logic_vector (15 DOWNTO 0); + dram_addr_in : OUT std_logic_vector (11 DOWNTO 0); + dram_addr_out : OUT std_logic_vector (11 DOWNTO 0); + dram_we : OUT std_logic_vector (0 DOWNTO 0) := "0"; + dd_block_start : IN std_logic; + dd_block_start_ftu : IN std_logic; + dd_block_start_ack : OUT std_logic := '0'; + dd_block_start_ack_ftu : OUT std_logic := '0'; + dd_block_ready : IN std_logic; + dd_block_ready_ftu : IN std_logic; + dd_read : IN std_logic; + dd_write_ftu : IN std_logic; + dd_busy : OUT std_logic := '1'; + dd_started : OUT std_logic := '0'; + dd_started_ftu : OUT std_logic := '0'; + dd_ready : OUT std_logic := '0'; + dd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0); + dd_addr : IN std_logic_vector (11 DOWNTO 0); + dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0) + ); + +-- Declarations + +END dram_control ; + +-- +ARCHITECTURE beha OF dram_control IS + + type state_dram_proc_type is (DR_INIT, DR_CONFIG, DR_IDLE, DR_DOUT_WIZ_START, DR_DOUT_WIZ_END, DR_WRITE_START, DR_WRITE_END, + DR_READ_START, DR_READ_WAIT, DR_READ_END); + type state_dd_block_proc_type is (DD_BLOCK_IDLE, DD_BLOCK_WAIT_WIZ, DD_BLOCK_WAIT_FTU); + + + signal state_dram_proc : state_dram_proc_type := DR_INIT; + signal next_state : state_dram_proc_type := DR_IDLE; + + signal state_dd_block_proc : state_dd_block_proc_type := DD_BLOCK_IDLE; + + signal local_addr : std_logic_vector (11 downto 0) := X"000"; + signal local_data : std_logic_vector (15 downto 0); + +BEGIN + + dd_block_proc : process (clk) + begin + if rising_edge (clk) then + case state_dd_block_proc is + + when DD_BLOCK_IDLE => + if (dd_block_start = '1') then + dd_block_start_ack <= '1'; + state_dd_block_proc <= DD_BLOCK_WAIT_WIZ; + elsif (dd_block_start_ftu = '1') then + dd_block_start_ack_ftu <= '1'; + state_dd_block_proc <= DD_BLOCK_WAIT_FTU; + end if; + + when DD_BLOCK_WAIT_WIZ => + if (dd_block_ready = '1') then + dd_block_start_ack <= '0'; + state_dd_block_proc <= DD_BLOCK_IDLE; + end if; + + when DD_BLOCK_WAIT_FTU => + if (dd_block_ready_ftu = '1') then + dd_block_start_ack_ftu <= '0'; + state_dd_block_proc <= DD_BLOCK_IDLE; + end if; + + end case; + end if; + end process dd_block_proc; + + dram_proc : process (clk) + begin + if rising_edge (clk) then + case state_dram_proc is + + when DR_INIT => + state_dram_proc <= DR_CONFIG; + + when DR_CONFIG => + state_dram_proc <= DR_IDLE; + + when DR_IDLE => + dd_busy <= '0'; + + if (dd_read = '1') then + dd_busy <= '1'; + dd_started <= '1'; + dd_ready <= '0'; + local_addr <= dd_addr; + next_state <= DR_DOUT_WIZ_START; + state_dram_proc <= DR_READ_START; + + elsif (dd_write_ftu = '1') then + dd_busy <= '1'; + dd_started_ftu <= '1'; + dd_ready <= '0'; + local_addr <= dd_addr_ftu; + local_data <= dd_data_in_ftu; + next_state <= DR_IDLE; + state_dram_proc <= DR_WRITE_START; + end if; + + + + when DR_DOUT_WIZ_START => + dd_data_out <= local_data; + dd_ready <= '1'; + state_dram_proc <= DR_DOUT_WIZ_END; + + when DR_DOUT_WIZ_END => + if (dd_read <= '0') then + dd_started <= '0'; + state_dram_proc <= DR_IDLE; + end if; + + -- -- + -- write to dynamic data ram + -- -- + when DR_WRITE_START => + dram_addr_in <= local_addr; + dram_data_in <= local_data; + dram_we <= "1"; + state_dram_proc <= DR_WRITE_END; + + when DR_WRITE_END => + dram_we <= "0"; + dd_started_ftu <= '0'; + dd_ready <= '1'; + state_dram_proc <= next_state; + + -- -- + -- read from dynamic data ram + -- -- + when DR_READ_START => + dram_addr_out <= local_addr; + state_dram_proc <= DR_READ_WAIT; + + when DR_READ_WAIT => + state_dram_proc <= DR_READ_END; + + when DR_READ_END => + local_data <= dram_data_out; + state_dram_proc <= next_state; + + + end case; + end if; -- rising edge + end process dram_proc; + +END ARCHITECTURE beha; Index: firmware/FTM/ethernet/eth_config_modul_beha.vhd =================================================================== --- firmware/FTM/ethernet/eth_config_modul_beha.vhd (revision 10227) +++ firmware/FTM/ethernet/eth_config_modul_beha.vhd (revision 10227) @@ -0,0 +1,77 @@ +-- +-- VHDL Architecture FACT_FTM_lib.eth_config_modul.beha +-- +-- Created: +-- by - kai.UNKNOWN (E5PCXX) +-- at - 14:52:32 15.02.2011 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE IEEE.STD_LOGIC_UNSIGNED.all; +-- LIBRARY FACT_FTM_lib; +-- USE FACT_FTM_lib.ftm_array_types.all; +-- USE FACT_FTM_lib.ftm_constants.all; +library ftm_definitions; +USE ftm_definitions.ftm_array_types.all; +USE ftm_definitions.ftm_constants.all; + +ENTITY eth_config_modul IS + PORT( + clk : IN std_logic; + config_start_eth : IN std_logic; + config_started_eth : OUT std_logic := '0'; + config_ready_eth : OUT std_logic := '0'; + + config_start_cc : OUT std_logic := '0'; + config_started_cc : IN std_logic; + config_ready_cc : IN std_logic + ); +END ENTITY eth_config_modul; + +-- +ARCHITECTURE beha OF eth_config_modul IS + + type state_config_proc_type is (CP_IDLE, CP_CONFIG_START, CP_CONFIG_01, CP_CONFIG_END); + signal state_config_proc : state_config_proc_type := CP_IDLE; + +BEGIN + + config_proc : process (clk) + begin + if rising_edge (clk) then + case state_config_proc is + + when CP_IDLE => + if (config_start_eth = '1') then + config_ready_eth <= '0'; + config_started_eth <= '1'; + state_config_proc <= CP_CONFIG_START; + end if; + + when CP_CONFIG_START => + config_start_cc <= '1'; + if (config_started_cc = '1') then + config_start_cc <= '0'; + state_config_proc <= CP_CONFIG_01; + end if; + + when CP_CONFIG_01 => + if (config_ready_cc = '1') then + state_config_proc <= CP_CONFIG_END; + end if; + + when CP_CONFIG_END => + config_started_eth <= '0'; + config_ready_eth <= '1'; + state_config_proc <= CP_IDLE; + + + end case; + end if; + end process config_proc; + +END ARCHITECTURE beha; + Index: firmware/FTM/ethernet/ethernet_modul_beha.vhd =================================================================== --- firmware/FTM/ethernet/ethernet_modul_beha.vhd (revision 10227) +++ firmware/FTM/ethernet/ethernet_modul_beha.vhd (revision 10227) @@ -0,0 +1,565 @@ +-- VHDL Entity FACT_FTM_lib.ethernet_modul.symbol +-- +-- Created: +-- by - kai.UNKNOWN (E5PCXX) +-- at - 11:17:45 25.02.2011 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +--LIBRARY FACT_FTM_lib; +library ftm_definitions; +USE ftm_definitions.ftm_array_types.all; +USE ftm_definitions.ftm_constants.all; + +ENTITY ethernet_modul IS + PORT( + wiz_reset : OUT std_logic := '1'; + wiz_addr : OUT std_logic_vector (9 DOWNTO 0); + wiz_data : INOUT std_logic_vector (15 DOWNTO 0); + wiz_cs : OUT std_logic := '1'; + wiz_wr : OUT std_logic := '1'; + wiz_rd : OUT std_logic := '1'; + wiz_int : IN std_logic; + clk : IN std_logic; + sd_ready : OUT std_logic; + sd_busy : OUT std_logic; + led : OUT std_logic_vector (7 DOWNTO 0); + sd_read_ftu : IN std_logic; + sd_started_ftu : OUT std_logic := '0'; + cc_R0 : OUT std_logic_vector (31 DOWNTO 0); + cc_R1 : OUT std_logic_vector (31 DOWNTO 0); + cc_R11 : OUT std_logic_vector (31 DOWNTO 0); + cc_R13 : OUT std_logic_vector (31 DOWNTO 0); + cc_R14 : OUT std_logic_vector (31 DOWNTO 0); + cc_R15 : OUT std_logic_vector (31 DOWNTO 0); + cc_R8 : OUT std_logic_vector (31 DOWNTO 0); + cc_R9 : OUT std_logic_vector (31 DOWNTO 0); + coin_n_c : OUT std_logic_vector (15 DOWNTO 0); + coin_n_p : OUT std_logic_vector (15 DOWNTO 0); + dead_time : OUT std_logic_vector (15 DOWNTO 0); + -- data from config ram + general_settings : OUT std_logic_vector (15 DOWNTO 0); + lp1_amplitude : OUT std_logic_vector (15 DOWNTO 0); + lp1_delay : OUT std_logic_vector (15 DOWNTO 0); + lp2_amplitude : OUT std_logic_vector (15 DOWNTO 0); + lp2_delay : OUT std_logic_vector (15 DOWNTO 0); + lp_pt_freq : OUT std_logic_vector (15 DOWNTO 0); + lp_pt_ratio : OUT std_logic_vector (15 DOWNTO 0); + timemarker_delay : OUT std_logic_vector (15 DOWNTO 0); + trigger_delay : OUT std_logic_vector (15 DOWNTO 0); + sd_addr_ftu : IN std_logic_vector (11 DOWNTO 0); + sd_data_out_ftu : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0); + ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0); + ftu_active_cr2 : OUT std_logic_vector (15 DOWNTO 0); + ftu_active_cr3 : OUT std_logic_vector (15 DOWNTO 0); + new_config : OUT std_logic := '0'; + config_started : IN std_logic; + config_start_eth : IN std_logic; + config_started_eth : OUT std_logic := '0'; + config_ready_eth : OUT std_logic := '0'; + config_started_ack : OUT std_logic := '0'; + fl_busy : OUT std_logic; + fl_ready : OUT std_logic; + fl_write_ftu : IN std_logic; + fl_started_ftu : OUT std_logic := '0'; + fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0); + fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0) := (others => '0'); + -- + ping_ftu_start : OUT std_logic := '0'; + ping_ftu_started : IN std_logic; + ping_ftu_ready : IN std_logic; + dd_write_ftu : IN std_logic; + dd_started_ftu : OUT std_logic := '0'; + dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0); + dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0); + dd_busy : OUT std_logic; + dd_ready : OUT std_logic; + coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0') + ); + +-- Declarations + +END ethernet_modul ; + +-- +-- VHDL Architecture FACT_FTM_lib.ethernet_modul.beha +-- +-- Created: +-- by - kai.UNKNOWN (E5PCXX) +-- at - 11:17:46 25.02.2011 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) +-- +-- +-- +--LIBRARY IEEE; +--USE IEEE.STD_LOGIC_1164.all; +--USE IEEE.STD_LOGIC_ARITH.all; +--USE IEEE.STD_LOGIC_UNSIGNED.all; +--LIBRARY FACT_FTM_lib; +--USE FACT_FTM_lib.ftm_array_types.all; +--USE FACT_FTM_lib.ftm_constants.all; + +--LIBRARY FACT_FTM_lib; + +ARCHITECTURE beha OF ethernet_modul IS + + -- Architecture declarations + + -- Internal signal declarations + SIGNAL busy : std_logic := '1'; + SIGNAL cram_data_out : std_logic_vector(15 DOWNTO 0); + SIGNAL cram_data_in : std_logic_vector(15 DOWNTO 0); + SIGNAL cram_we : std_logic_vector(0 DOWNTO 0) := "0"; + SIGNAL sd_write : std_logic := '0'; + SIGNAL sd_read : std_logic; + SIGNAL led1 : std_logic_vector(7 DOWNTO 0) := (others => '0'); + SIGNAL sd_started : std_logic; + SIGNAL sd_addr : std_logic_vector(11 DOWNTO 0); + SIGNAL cram_addr_out : std_logic_vector(11 DOWNTO 0); + SIGNAL cram_addr_in : std_logic_vector(11 DOWNTO 0); + SIGNAL sd_data_in : std_logic_vector(15 DOWNTO 0) := (others => '0'); + SIGNAL sd_data_out : std_logic_vector(15 DOWNTO 0); + SIGNAL config_ready_cc : std_logic := '0'; + SIGNAL config_started_cc : std_logic := '0'; + SIGNAL config_start_cc : std_logic; + SIGNAL fl_started : std_logic; + SIGNAL fl_read : std_logic := '0'; + -- + SIGNAL fl_addr : std_logic_vector(11 DOWNTO 0); + SIGNAL fl_data_out : std_logic_vector(15 DOWNTO 0); + SIGNAL fram_addr_out : std_logic_vector(11 DOWNTO 0); + SIGNAL doutb : std_logic_VECTOR(15 DOWNTO 0); + SIGNAL fram_we : std_logic_vector(0 DOWNTO 0) := "0"; + SIGNAL fram_addr_in : std_logic_vector(11 DOWNTO 0); + SIGNAL fram_data_in : std_logic_vector(15 DOWNTO 0); + SIGNAL led2 : std_logic_vector(7 DOWNTO 0) := X"00"; + SIGNAL dram_addr_out : std_logic_vector(11 DOWNTO 0); + SIGNAL doutb1 : std_logic_VECTOR(15 DOWNTO 0); + SIGNAL dram_we : std_logic_vector(0 DOWNTO 0) := "0"; + SIGNAL dram_addr_in : std_logic_vector(11 DOWNTO 0); + SIGNAL dram_data_in : std_logic_vector(15 DOWNTO 0); + SIGNAL dd_read : std_logic; + SIGNAL dd_started : std_logic := '0'; + SIGNAL dd_data_out : std_logic_vector(15 DOWNTO 0) := (others => '0'); + SIGNAL dd_addr : std_logic_vector(11 DOWNTO 0); + SIGNAL dd_block_ready : std_logic := '0'; + -- + SIGNAL dd_block_start : std_logic := '0'; + SIGNAL dd_block_start_ack : std_logic; + SIGNAL dd_block_ready_ftu : std_logic; + SIGNAL dd_block_start_ack_ftu : std_logic := '0'; + SIGNAL dd_block_start_ftu : std_logic; + + -- Implicit buffer signal declarations + SIGNAL dd_busy_internal : std_logic; + SIGNAL dd_ready_internal : std_logic; + SIGNAL fl_busy_internal : std_logic; + SIGNAL fl_ready_internal : std_logic; + SIGNAL sd_busy_internal : std_logic; + SIGNAL sd_ready_internal : std_logic; + + + -- Component Declarations + COMPONENT CRAM_4096_16b + PORT ( + clka : IN std_logic ; + dina : IN std_logic_VECTOR (15 DOWNTO 0); + addra : IN std_logic_VECTOR (11 DOWNTO 0); + wea : IN std_logic_VECTOR (0 DOWNTO 0); + clkb : IN std_logic ; + addrb : IN std_logic_VECTOR (11 DOWNTO 0); + doutb : OUT std_logic_VECTOR (15 DOWNTO 0) + ); + END COMPONENT; + COMPONENT DRAM_4096_16b + PORT ( + clka : IN std_logic ; + dina : IN std_logic_VECTOR (15 DOWNTO 0); + addra : IN std_logic_VECTOR (11 DOWNTO 0); + wea : IN std_logic_VECTOR (0 DOWNTO 0); + clkb : IN std_logic ; + addrb : IN std_logic_VECTOR (11 DOWNTO 0); + doutb : OUT std_logic_VECTOR (15 DOWNTO 0) + ); + END COMPONENT; + COMPONENT FRAM_4096_16b + PORT ( + clka : IN std_logic ; + dina : IN std_logic_VECTOR (15 DOWNTO 0); + addra : IN std_logic_VECTOR (11 DOWNTO 0); + wea : IN std_logic_VECTOR (0 DOWNTO 0); + clkb : IN std_logic ; + addrb : IN std_logic_VECTOR (11 DOWNTO 0); + doutb : OUT std_logic_VECTOR (15 DOWNTO 0) + ); + END COMPONENT; + COMPONENT cram_control + PORT ( + clk : IN std_logic ; + led : OUT std_logic_vector (7 DOWNTO 0) := X"00"; + cram_data_in : OUT std_logic_vector (15 DOWNTO 0); + cram_data_out : IN std_logic_vector (15 DOWNTO 0); + cram_addr_in : OUT std_logic_vector (11 DOWNTO 0); + cram_addr_out : OUT std_logic_vector (11 DOWNTO 0); + cram_we : OUT std_logic_vector (0 DOWNTO 0) := "0"; + sd_write : IN std_logic ; + sd_read : IN std_logic ; + sd_read_ftu : IN std_logic ; + sd_busy : OUT std_logic := '1'; + sd_started : OUT std_logic := '0'; + sd_started_ftu : OUT std_logic := '0'; + sd_ready : OUT std_logic := '0'; + sd_data_in : IN std_logic_vector (15 DOWNTO 0); + sd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + sd_data_out_ftu : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + sd_addr : IN std_logic_vector (11 DOWNTO 0); + sd_addr_ftu : IN std_logic_vector (11 DOWNTO 0); + config_start_cc : IN std_logic ; + config_started_cc : OUT std_logic := '0'; + config_ready_cc : OUT std_logic := '0'; + -- data from config ram + general_settings : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + lp_pt_freq : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + lp_pt_ratio : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + lp1_amplitude : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + lp2_amplitude : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + lp1_delay : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + lp2_delay : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + coin_n_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + coin_n_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + trigger_delay : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + timemarker_delay : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + dead_time : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + cc_R0 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0'); + cc_R1 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0'); + cc_R8 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0'); + cc_R9 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0'); + cc_R11 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0'); + cc_R13 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0'); + cc_R14 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0'); + cc_R15 : OUT std_logic_vector (31 DOWNTO 0) := (others => '0'); + coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + ftu_active_cr2 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + ftu_active_cr3 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0') + ); + END COMPONENT; + COMPONENT dram_control + PORT ( + clk : IN std_logic ; + dram_data_in : OUT std_logic_vector (15 DOWNTO 0); + dram_data_out : IN std_logic_vector (15 DOWNTO 0); + dram_addr_in : OUT std_logic_vector (11 DOWNTO 0); + dram_addr_out : OUT std_logic_vector (11 DOWNTO 0); + dram_we : OUT std_logic_vector (0 DOWNTO 0) := "0"; + dd_block_start : IN std_logic ; + dd_block_start_ftu : IN std_logic ; + dd_block_start_ack : OUT std_logic := '0'; + dd_block_start_ack_ftu : OUT std_logic := '0'; + dd_block_ready : IN std_logic ; + dd_block_ready_ftu : IN std_logic ; + dd_read : IN std_logic ; + dd_write_ftu : IN std_logic ; + dd_busy : OUT std_logic := '1'; + dd_started : OUT std_logic := '0'; + dd_started_ftu : OUT std_logic := '0'; + dd_ready : OUT std_logic := '0'; + dd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0); + dd_addr : IN std_logic_vector (11 DOWNTO 0); + dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0) + ); + END COMPONENT; + COMPONENT eth_config_modul + PORT ( + clk : IN std_logic ; + config_start_eth : IN std_logic ; + config_started_eth : OUT std_logic := '0'; + config_ready_eth : OUT std_logic := '0'; + config_start_cc : OUT std_logic := '0'; + config_started_cc : IN std_logic ; + config_ready_cc : IN std_logic + ); + END COMPONENT; + COMPONENT fram_control + PORT ( + clk : IN std_logic ; + fram_data_in : OUT std_logic_vector (15 DOWNTO 0); + fram_data_out : IN std_logic_vector (15 DOWNTO 0); + fram_addr_in : OUT std_logic_vector (11 DOWNTO 0); + fram_addr_out : OUT std_logic_vector (11 DOWNTO 0); + fram_we : OUT std_logic_vector (0 DOWNTO 0) := "0"; + fl_read : IN std_logic ; + fl_write_ftu : IN std_logic ; + fl_busy : OUT std_logic := '1'; + fl_started : OUT std_logic := '0'; + fl_started_ftu : OUT std_logic := '0'; + fl_ready : OUT std_logic := '0'; + fl_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0); + fl_addr : IN std_logic_vector (11 DOWNTO 0); + fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0) + ); + END COMPONENT; + COMPONENT w5300_modul + PORT ( + clk : IN std_logic ; + wiz_reset : OUT std_logic := '1'; + addr : OUT std_logic_vector (9 DOWNTO 0); + data : INOUT std_logic_vector (15 DOWNTO 0); + cs : OUT std_logic := '1'; + wr : OUT std_logic := '1'; + led : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); + rd : OUT std_logic := '1'; + int : IN std_logic ; + busy : OUT std_logic := '1'; + new_config : OUT std_logic := '0'; + config_started : IN std_logic ; + config_started_ack : OUT std_logic := '0'; + -- + ping_ftu_start : OUT std_logic := '0'; + ping_ftu_started : IN std_logic ; + ping_ftu_ready : IN std_logic ; + -- + sd_addr : OUT std_logic_vector (11 DOWNTO 0); + sd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + sd_data_in : IN std_logic_vector (15 DOWNTO 0); + sd_write : OUT std_logic := '0'; + sd_read : OUT std_logic := '0'; + sd_started : IN std_logic ; + sd_ready : IN std_logic ; + sd_busy : IN std_logic ; + -- + dd_block_start : OUT std_logic := '0'; + dd_block_start_ack : IN std_logic ; + dd_block_ready : OUT std_logic := '0'; + dd_addr : OUT std_logic_vector (11 DOWNTO 0); + dd_data_in : IN std_logic_vector (15 DOWNTO 0); + dd_read : OUT std_logic := '0'; + dd_started : IN std_logic ; + dd_ready : IN std_logic ; + dd_busy : IN std_logic ; + -- + fl_addr : OUT std_logic_vector (11 DOWNTO 0); + fl_data_in : IN std_logic_vector (15 DOWNTO 0); + fl_read : OUT std_logic := '0'; + fl_started : IN std_logic ; + fl_ready : IN std_logic ; + fl_busy : IN std_logic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + -- FOR ALL : CRAM_4096_16b USE ENTITY FACT_FTM_lib.CRAM_4096_16b; + -- FOR ALL : DRAM_4096_16b USE ENTITY FACT_FTM_lib.DRAM_4096_16b; + -- FOR ALL : FRAM_4096_16b USE ENTITY FACT_FTM_lib.FRAM_4096_16b; + -- FOR ALL : cram_control USE ENTITY FACT_FTM_lib.cram_control; + -- FOR ALL : dram_control USE ENTITY FACT_FTM_lib.dram_control; + -- FOR ALL : eth_config_modul USE ENTITY FACT_FTM_lib.eth_config_modul; + -- FOR ALL : fram_control USE ENTITY FACT_FTM_lib.fram_control; + -- FOR ALL : w5300_modul USE ENTITY FACT_FTM_lib.w5300_modul; + -- pragma synthesis_on + + +BEGIN + + -- ModuleWare code(v1.9) for instance 'U_3' of 'or' + led <= led1 OR led2; + + -- Instance port mappings. + U_1 : CRAM_4096_16b + PORT MAP ( + clka => clk, + dina => cram_data_in, + addra => cram_addr_in, + wea => cram_we, + clkb => clk, + addrb => cram_addr_out, + doutb => cram_data_out + ); + U_7 : DRAM_4096_16b + PORT MAP ( + clka => clk, + dina => dram_data_in, + addra => dram_addr_in, + wea => dram_we, + clkb => clk, + addrb => dram_addr_out, + doutb => doutb1 + ); + U_5 : FRAM_4096_16b + PORT MAP ( + clka => clk, + dina => fram_data_in, + addra => fram_addr_in, + wea => fram_we, + clkb => clk, + addrb => fram_addr_out, + doutb => doutb + ); + U_2 : cram_control + PORT MAP ( + clk => clk, + led => led2, + cram_data_in => cram_data_in, + cram_data_out => cram_data_out, + cram_addr_in => cram_addr_in, + cram_addr_out => cram_addr_out, + cram_we => cram_we, + sd_write => sd_write, + sd_read => sd_read, + sd_read_ftu => sd_read_ftu, + sd_busy => sd_busy_internal, + sd_started => sd_started, + sd_started_ftu => sd_started_ftu, + sd_ready => sd_ready_internal, + sd_data_in => sd_data_in, + sd_data_out => sd_data_out, + sd_data_out_ftu => sd_data_out_ftu, + sd_addr => sd_addr, + sd_addr_ftu => sd_addr_ftu, + config_start_cc => config_start_cc, + config_started_cc => config_started_cc, + config_ready_cc => config_ready_cc, + general_settings => general_settings, + lp_pt_freq => lp_pt_freq, + lp_pt_ratio => lp_pt_ratio, + lp1_amplitude => lp1_amplitude, + lp2_amplitude => lp2_amplitude, + lp1_delay => lp1_delay, + lp2_delay => lp2_delay, + coin_n_p => coin_n_p, + coin_n_c => coin_n_c, + trigger_delay => trigger_delay, + timemarker_delay => timemarker_delay, + dead_time => dead_time, + cc_R0 => cc_R0, + cc_R1 => cc_R1, + cc_R8 => cc_R8, + cc_R9 => cc_R9, + cc_R11 => cc_R11, + cc_R13 => cc_R13, + cc_R14 => cc_R14, + cc_R15 => cc_R15, + coin_win_p => coin_win_p, + coin_win_c => coin_win_c, + ftu_active_cr0 => ftu_active_cr0, + ftu_active_cr1 => ftu_active_cr1, + ftu_active_cr2 => ftu_active_cr2, + ftu_active_cr3 => ftu_active_cr3 + ); + U_8 : dram_control + PORT MAP ( + clk => clk, + dram_data_in => dram_data_in, + dram_data_out => doutb1, + dram_addr_in => dram_addr_in, + dram_addr_out => dram_addr_out, + dram_we => dram_we, + dd_block_start => dd_block_start, + dd_block_start_ftu => dd_block_start_ftu, + dd_block_start_ack => dd_block_start_ack, + dd_block_start_ack_ftu => dd_block_start_ack_ftu, + dd_block_ready => dd_block_ready, + dd_block_ready_ftu => dd_block_ready_ftu, + dd_read => dd_read, + dd_write_ftu => dd_write_ftu, + dd_busy => dd_busy_internal, + dd_started => dd_started, + dd_started_ftu => dd_started_ftu, + dd_ready => dd_ready_internal, + dd_data_out => dd_data_out, + dd_data_in_ftu => dd_data_in_ftu, + dd_addr => dd_addr, + dd_addr_ftu => dd_addr_ftu + ); + U_4 : eth_config_modul + PORT MAP ( + clk => clk, + config_start_eth => config_start_eth, + config_started_eth => config_started_eth, + config_ready_eth => config_ready_eth, + config_start_cc => config_start_cc, + config_started_cc => config_started_cc, + config_ready_cc => config_ready_cc + ); + U_6 : fram_control + PORT MAP ( + clk => clk, + fram_data_in => fram_data_in, + fram_data_out => doutb, + fram_addr_in => fram_addr_in, + fram_addr_out => fram_addr_out, + fram_we => fram_we, + fl_read => fl_read, + fl_write_ftu => fl_write_ftu, + fl_busy => fl_busy_internal, + fl_started => fl_started, + fl_started_ftu => fl_started_ftu, + fl_ready => fl_ready_internal, + fl_data_out => fl_data_out, + fl_data_in_ftu => fl_data_in_ftu, + fl_addr => fl_addr, + fl_addr_ftu => fl_addr_ftu + ); + U_0 : w5300_modul + PORT MAP ( + clk => clk, + wiz_reset => wiz_reset, + addr => wiz_addr, + data => wiz_data, + cs => wiz_cs, + wr => wiz_wr, + led => led1, + rd => wiz_rd, + int => wiz_int, + busy => busy, + new_config => new_config, + config_started => config_started, + config_started_ack => config_started_ack, + ping_ftu_start => ping_ftu_start, + ping_ftu_started => ping_ftu_started, + ping_ftu_ready => ping_ftu_ready, + sd_addr => sd_addr, + sd_data_out => sd_data_in, + sd_data_in => sd_data_out, + sd_write => sd_write, + sd_read => sd_read, + sd_started => sd_started, + sd_ready => sd_ready_internal, + sd_busy => sd_busy_internal, + dd_block_start => dd_block_start, + dd_block_start_ack => dd_block_start_ack, + dd_block_ready => dd_block_ready, + dd_addr => dd_addr, + dd_data_in => dd_data_out, + dd_read => dd_read, + dd_started => dd_started, + dd_ready => dd_ready_internal, + dd_busy => dd_busy_internal, + fl_addr => fl_addr, + fl_data_in => fl_data_out, + fl_read => fl_read, + fl_started => fl_started, + fl_ready => fl_ready_internal, + fl_busy => fl_busy_internal + ); + + -- Implicit buffered output assignments + dd_busy <= dd_busy_internal; + dd_ready <= dd_ready_internal; + fl_busy <= fl_busy_internal; + fl_ready <= fl_ready_internal; + sd_busy <= sd_busy_internal; + sd_ready <= sd_ready_internal; + +END beha; Index: firmware/FTM/ethernet/fram_control_beha.vhd =================================================================== --- firmware/FTM/ethernet/fram_control_beha.vhd (revision 10227) +++ firmware/FTM/ethernet/fram_control_beha.vhd (revision 10227) @@ -0,0 +1,138 @@ +-- +-- VHDL Architecture FACT_FTM_lib.fram_control.beha +-- +-- Created: +-- by - kai.UNKNOWN (E5PCXX) +-- at - 11:47:24 21.02.2011 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE IEEE.STD_LOGIC_UNSIGNED.all; +-- LIBRARY FACT_FTM_lib; +-- USE FACT_FTM_lib.ftm_array_types.all; +-- USE FACT_FTM_lib.ftm_constants.all; +library ftm_definitions; +USE ftm_definitions.ftm_array_types.all; +USE ftm_definitions.ftm_constants.all; + +ENTITY fram_control IS + PORT( + clk : IN std_logic; + fram_data_in : OUT std_logic_vector (15 DOWNTO 0); + fram_data_out : IN std_logic_vector (15 DOWNTO 0); + fram_addr_in : OUT std_logic_vector (11 DOWNTO 0); + fram_addr_out : OUT std_logic_vector (11 DOWNTO 0); + fram_we : OUT std_logic_vector (0 DOWNTO 0) := "0"; + fl_read : IN std_logic; + fl_write_ftu : IN std_logic; + fl_busy : OUT std_logic := '1'; + fl_started : OUT std_logic := '0'; + fl_started_ftu : OUT std_logic := '0'; + fl_ready : OUT std_logic := '0'; + fl_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0); + fl_addr : IN std_logic_vector (11 DOWNTO 0); + fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0) + ); + +-- Declarations + +END fram_control ; + +-- +ARCHITECTURE beha OF fram_control IS + + type state_fram_proc_type is (FR_INIT, FR_CONFIG, FR_IDLE, FR_DOUT_WIZ_START, FR_DOUT_WIZ_END, FR_WRITE_START, FR_WRITE_END, + FR_READ_START, FR_READ_WAIT, FR_READ_END); + + signal state_fram_proc : state_fram_proc_type := FR_INIT; + signal next_state : state_fram_proc_type := FR_IDLE; + + signal local_addr : std_logic_vector (11 downto 0) := X"000"; + signal local_data : std_logic_vector (15 downto 0); + +BEGIN + + fram_proc : process (clk) + begin + if rising_edge (clk) then + case state_fram_proc is + + when FR_INIT => + state_fram_proc <= FR_CONFIG; + + when FR_CONFIG => + state_fram_proc <= FR_IDLE; + + when FR_IDLE => + fl_busy <= '0'; + + if (fl_read = '1') then + fl_busy <= '1'; + fl_started <= '1'; + fl_ready <= '0'; + local_addr <= fl_addr; + next_state <= FR_DOUT_WIZ_START; + state_fram_proc <= FR_READ_START; + + elsif (fl_write_ftu = '1') then + fl_busy <= '1'; + fl_started_ftu <= '1'; + fl_ready <= '0'; + local_addr <= fl_addr_ftu; + local_data <= fl_data_in_ftu; + next_state <= FR_IDLE; + state_fram_proc <= FR_WRITE_START; + end if; + + + + when FR_DOUT_WIZ_START => + fl_data_out <= local_data; + fl_ready <= '1'; + state_fram_proc <= FR_DOUT_WIZ_END; + + when FR_DOUT_WIZ_END => + if (fl_read <= '0') then + fl_started <= '0'; + state_fram_proc <= FR_IDLE; + end if; + + -- -- + -- write to ftu-list ram + -- -- + when FR_WRITE_START => + fram_addr_in <= local_addr; + fram_data_in <= local_data; + fram_we <= "1"; + state_fram_proc <= FR_WRITE_END; + + when FR_WRITE_END => + fram_we <= "0"; + fl_started_ftu <= '0'; + fl_ready <= '1'; + state_fram_proc <= next_state; + + -- -- + -- read from ftu-list ram + -- -- + when FR_READ_START => + fram_addr_out <= local_addr; + state_fram_proc <= FR_READ_WAIT; + + when FR_READ_WAIT => + state_fram_proc <= FR_READ_END; + + when FR_READ_END => + local_data <= fram_data_out; + state_fram_proc <= next_state; + + + end case; + end if; -- rising edge + end process fram_proc; + +END ARCHITECTURE beha; Index: firmware/FTM/ethernet/w5300_modul.vhd =================================================================== --- firmware/FTM/ethernet/w5300_modul.vhd (revision 10227) +++ firmware/FTM/ethernet/w5300_modul.vhd (revision 10227) @@ -0,0 +1,939 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 11:48:48 11/10/2009 +-- Design Name: +-- Module Name: w5300_modul - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +-- hds interface_start +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.all; +USE IEEE.STD_LOGIC_ARITH.all; +USE IEEE.STD_LOGIC_UNSIGNED.all; +-- LIBRARY FACT_FTM_lib; +-- USE FACT_FTM_lib.ftm_array_types.all; +-- USE FACT_FTM_lib.ftm_constants.all; +library ftm_definitions; +USE ftm_definitions.ftm_array_types.all; +USE ftm_definitions.ftm_constants.all; + +-- -- Uncomment the following library declaration if instantiating +-- -- any Xilinx primitives in this code. + library UNISIM; + use UNISIM.VComponents.all; + +-- +ENTITY w5300_modul IS + PORT( + clk : IN std_logic; + wiz_reset : OUT std_logic := '1'; + addr : OUT std_logic_vector (9 DOWNTO 0); + data : INOUT std_logic_vector (15 DOWNTO 0); + cs : OUT std_logic := '1'; + wr : OUT std_logic := '1'; + led : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); + rd : OUT std_logic := '1'; + int : IN std_logic; + busy : OUT std_logic := '1'; + new_config : OUT std_logic := '0'; + config_started : IN std_logic; + config_started_ack : OUT std_logic := '0'; + -- + ping_ftu_start : OUT std_logic := '0'; + ping_ftu_started : IN std_logic; + ping_ftu_ready : IN std_logic; + -- + sd_addr : OUT std_logic_vector (11 DOWNTO 0); + sd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + sd_data_in : IN std_logic_vector (15 DOWNTO 0); + sd_write : OUT std_logic := '0'; + sd_read : OUT std_logic := '0'; + sd_started : IN std_logic; + sd_ready : IN std_logic; + sd_busy : IN std_logic; + -- + dd_block_start : OUT std_logic := '0'; + dd_block_start_ack : IN std_logic; + dd_block_ready : OUT std_logic := '0'; + dd_addr : OUT std_logic_vector (11 DOWNTO 0); + dd_data_in : IN std_logic_vector (15 DOWNTO 0); + dd_read : OUT std_logic := '0'; + dd_started : IN std_logic; + dd_ready : IN std_logic; + dd_busy : IN std_logic; + -- + fl_addr : OUT std_logic_vector (11 DOWNTO 0); + fl_data_in : IN std_logic_vector (15 DOWNTO 0); + fl_read : OUT std_logic := '0'; + fl_started : IN std_logic; + fl_ready : IN std_logic; + fl_busy : IN std_logic + ); + +-- Declarations + +END w5300_modul ; +-- hds interface_end + +architecture Behavioral of w5300_modul is + + type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA, + INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, + SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, + READ_DATA, WRITE_TO_SD_ADDR, READ_FROM_SD_ADDR, READ_FROM_DD_ADDR, READ_FROM_FL_ADDR); + type state_write_type is (WR_START, WR_LENGTH, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO_01); + type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04); + type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06); + type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_CMD, RD_CMD_PARSE, RD_PING, RD_WRITE_SD_ADDR, RD_READ_SD_ADDR, RD_READ_SD_BLOCK, RD_READ_DD_BLOCK, RD_WRITE_SD_BLOCK, RD_END); + type state_write_sd_type is (WRITE_SD_START, WRITE_SD_WAIT, WRITE_SD_END); + type state_read_sd_type is (READ_SD_START, READ_SD_WAIT, READ_SD_END); + type state_read_fl_type is (READ_FL_START, READ_FL_WAIT, READ_FL_END); + type state_ping_type is (PING_START, PING_WAIT, PING_WRITE_LIST); + type state_read_dd_type is (READ_DD_START, READ_DD_WAIT, READ_DD_END); + type state_read_dd_block_type is (READ_DD_BLOCK_START, READ_DD_BLOCK_WRITE, READ_DD_BLOCK_END); + + signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120"; + + signal par_addr : std_logic_vector (9 downto 0) := (others => '0'); + signal par_data : std_logic_vector (15 downto 0) := (others => '0'); + signal data_read : std_logic_vector (15 downto 0) := (others => '0'); + + signal state_init, next_state , next_state_tmp : state_init_type := RESET; + signal read_addr_state : state_init_type := RESET; + signal count : std_logic_vector (2 downto 0) := "000"; + signal state_write : state_write_type := WR_START; + signal state_interrupt_1 : state_interrupt_1_type := IR1_01; + signal state_interrupt_2 : state_interrupt_2_type := IR2_01; + signal state_read_data : state_read_data_type := RD_1; + signal next_state_read_data : state_read_data_type := RD_CMD; + signal state_write_sd : state_write_sd_type := WRITE_SD_START; + signal state_read_sd : state_read_sd_type := READ_SD_START; + signal state_read_fl : state_read_fl_type := READ_FL_START; + signal state_ping : state_ping_type := PING_START; + signal state_read_dd : state_read_dd_type := READ_DD_START; + signal state_read_dd_block : state_read_dd_block_type := READ_DD_BLOCK_START; + + + signal interrupt_ignore : std_logic := '1'; + signal int_flag : std_logic := '0'; + + signal zaehler : std_logic_vector (19 downto 0) := (others => '0'); + signal data_cnt : integer := 0; + signal socket_cnt : std_logic_vector (2 downto 0) := "000"; + + signal socket_tx_free : std_logic_vector (31 downto 0) := (others => '0'); + signal write_length_bytes : std_logic_vector (16 downto 0); + + signal socket_rx_received : std_logic_vector (31 downto 0) := (others => '0'); + signal chk_recv_cntr : integer range 0 to 10000 := 0; + + signal next_packet_data_cnt : integer range 0 to 4095 := 0; + signal rx_packets_cnt : std_logic_vector (15 downto 0); + signal new_config_flag : std_logic := '0'; + + signal local_write_length : std_logic_vector (16 downto 0); + signal local_socket_nr : std_logic_vector (2 downto 0); + + type cmd_array_type is array (0 to 4) of std_logic_vector (15 downto 0); + signal cmd_array : cmd_array_type; + + -- -- -- + signal led_int : std_logic_vector (7 downto 0) := X"00"; + signal led_cnt : integer range 0 to 2**22 := 0; + -- -- -- + + signal local_sd_addr : std_logic_vector (11 downto 0); + signal local_sd_data : std_logic_vector (15 downto 0); + + +begin + + --synthesis translate_off + RST_TIME <= X"00120"; + --synthesis translate_on + + + w5300_init_proc : process (clk, int) + begin + + if rising_edge (clk) then + + -- -- -- + led <= led_int; + -- -- -- + + -- Interrupt low + if (int = '0') and (interrupt_ignore = '0') then + case state_interrupt_1 is + when IR1_01 => + int_flag <= '1'; + busy <= '1'; + state_interrupt_1 <= IR1_02; + when IR1_02 => + state_interrupt_1 <= IR1_03; + when IR1_03 => + state_init <= INTERRUPT; + socket_cnt <= "000"; + zaehler <= X"00000"; + count <= "000"; + int_flag <= '0'; + interrupt_ignore <= '1'; + state_interrupt_1 <= IR1_04; + when others => + null; + end case; + end if; -- int = '0' + + if int_flag = '0' then + case state_init is + -- Interrupt + when INTERRUPT => + case state_interrupt_2 is + when IR2_01 => + par_addr <= W5300_IR; + state_init <= READ_REG; + next_state <= INTERRUPT; + state_interrupt_2 <= IR2_02; + when IR2_02 => + if (data_read (conv_integer(socket_cnt)) = '1') then -- Sx Interrupt + state_interrupt_2 <= IR2_03; + else + socket_cnt <= socket_cnt + 1; + if (socket_cnt = W5300_LAST_SOCKET) then + state_interrupt_2 <= IR2_06; + else + state_interrupt_2 <= IR2_02; + end if; + end if; + when IR2_03 => + par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register + state_init <= READ_REG; + next_state <= INTERRUPT; + state_interrupt_2 <= IR2_04; + when IR2_04 => + par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; + par_data <= data_read; -- clear Interrupts + state_init <= WRITE_REG; + next_state <= INTERRUPT; + state_interrupt_2 <= IR2_05; + when IR2_05 => + par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; + par_data <= X"0010"; -- CLOSE + state_init <= WRITE_REG; + next_state <= INTERRUPT; + socket_cnt <= socket_cnt + 1; + if (socket_cnt = W5300_LAST_SOCKET) then + state_interrupt_2 <= IR2_06; + else + state_interrupt_2 <= IR2_01; + end if; + + when IR2_06 => + state_interrupt_1 <= IR1_01; + state_interrupt_2 <= IR2_01; + socket_cnt <= "000"; + state_init <= RESET; + end case; + + -- reset W5300 + when RESET => + busy <= '1'; + zaehler <= zaehler + 1; + wiz_reset <= '0'; + if (zaehler >= X"00064") then -- wait 2µs + wiz_reset <= '1'; + end if; + if (zaehler = RST_TIME) then -- wait 10ms + zaehler <= X"00000"; + socket_cnt <= "000"; + count <= "000"; + interrupt_ignore <= '0'; + rd <= '1'; + wr <= '1'; + cs <= '1'; + state_write <= WR_START; + state_init <= INIT; + -- -- -- + led_int <= X"00"; + -- -- -- + end if; + + -- Init + when INIT => + par_addr <= W5300_MR; + par_data <= X"0000"; + state_init <= WRITE_REG; + next_state <= IM; + + -- Interrupt Mask + when IM => + par_addr <= W5300_IMR; + par_data <= X"00FF"; -- S0-S7 Interrupts + state_init <= WRITE_REG; + next_state <= MT; + + -- Memory Type + when MT => + par_addr <= W5300_MTYPER; + par_data <= X"00FF"; -- 64K RX, 64K TX-Buffer + state_init <= WRITE_REG; + next_state <= STX; + + -- Socket TX Memory Size + when STX => + par_data <= X"4000"; -- 64K TX for socket 0, others 0 + + par_addr <= W5300_TMS01R; + state_init <= WRITE_REG; + next_state <= STX1; + when STX1 => + par_data <= X"0000"; + par_addr <= W5300_TMS23R; + state_init <= WRITE_REG; + next_state <= STX2; + when STX2 => + par_addr <= W5300_TMS45R; + state_init <= WRITE_REG; + next_state <= STX3; + when STX3 => + par_addr <= W5300_TMS67R; + state_init <= WRITE_REG; + next_state <= SRX; + + -- Socket RX Memory Size + when SRX => + par_data <= X"4000"; -- 64K RX for socket 0, others 0 + + par_addr <= W5300_RMS01R; + state_init <= WRITE_REG; + next_state <= SRX1; + when SRX1 => + par_data <= X"0000"; + par_addr <= W5300_RMS23R; + state_init <= WRITE_REG; + next_state <= SRX2; + when SRX2 => + par_addr <= W5300_RMS45R; + state_init <= WRITE_REG; + next_state <= SRX3; + when SRX3 => + par_addr <= W5300_RMS67R; + state_init <= WRITE_REG; + next_state <= MAC; + + -- MAC + when MAC => + par_addr <= W5300_SHAR; + par_data <= MAC_ADDRESS (0); + state_init <= WRITE_REG; + next_state <= MAC1; + when MAC1 => + par_addr <= W5300_SHAR + 2; + par_data <= MAC_ADDRESS (1); + state_init <= WRITE_REG; + next_state <= MAC2; + when MAC2 => + par_addr <= W5300_SHAR + 4; + par_data <= MAC_ADDRESS (2); + state_init <= WRITE_REG; + next_state <= GW; + + -- Gateway + when GW => + par_addr <= W5300_GAR; + par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (0), 8); + par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (1), 8); + state_init <= WRITE_REG; + next_state <= GW1; + when GW1 => + par_addr <= W5300_GAR + 2; + par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (2), 8); + par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (3), 8); + state_init <= WRITE_REG; + next_state <= SNM; + + -- Subnet Mask + when SNM => + par_addr <= W5300_SUBR; + par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (0), 8); + par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (1), 8); + state_init <= WRITE_REG; + next_state <= SNM1; + when SNM1 => + par_addr <= W5300_SUBR + 2; + par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (2), 8); + par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (3), 8); + state_init <= WRITE_REG; + next_state <= IP; + -- Own IP-Address + when IP => + par_addr <= W5300_SIPR; + par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (0), 8); + par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (1), 8); + state_init <= WRITE_REG; + next_state <= IP1; + when IP1 => + par_addr <= W5300_SIPR + 2; + par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (2), 8); + par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3), 8); + state_init <= WRITE_REG; + next_state <= SI; + -- Socket Init + when SI => + par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC; + par_data <= X"0101"; -- ALIGN, TCP + state_init <= WRITE_REG; + next_state <= SI1; + -- Sx Interrupt Mask + when SI1 => + par_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC; + par_data <= X"000A"; -- TIMEOUT, DISCON + state_init <= WRITE_REG; + next_state <= SI2; + when SI2 => + par_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC; + par_data <= conv_std_logic_vector(FIRST_PORT + unsigned (socket_cnt), 16); + state_init <= WRITE_REG; + next_state <= SI3; + when SI3 => + par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; + par_data <= X"0001"; -- OPEN + state_init <= WRITE_REG; + next_state <= SI4; + when SI4 => + par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC; + state_init <= READ_REG; + next_state <= SI5; + when SI5 => + if (data_read (7 downto 0) = X"13") then -- is open? + state_init <= SI6; + else + state_init <= SI4; + end if; + when SI6 => + par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; + par_data <= X"0002"; -- LISTEN + state_init <= WRITE_REG; + socket_cnt <= socket_cnt + 1; + if (socket_cnt = W5300_LAST_SOCKET) then + socket_cnt <= "000"; + next_state <= ESTABLISH; -- All Sockets open + else + next_state <= SI; -- Next Socket + end if; + -- End Socket Init + + when ESTABLISH => + par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC; + state_init <= READ_REG; + next_state <= EST1; + when EST1 => + case data_read (7 downto 0) is + when X"17" => -- established + if (socket_cnt = W5300_LAST_SOCKET) then + socket_cnt <= "000"; + busy <= '0'; + state_init <= MAIN; + -- -- -- + led_int <= X"00"; + -- -- -- + else + socket_cnt <= socket_cnt + 1; + state_init <= ESTABLISH; + end if; + when others => + state_init <= ESTABLISH; + -- -- -- + -- Just for fun... + if (led_cnt = 1100000) then + if (led_int = X"00") then + led_int <= X"18"; + else + led_int (7 downto 4) <= led_int (6 downto 4) & '0'; + led_int (3 downto 0) <= '0' & led_int (3 downto 1); + end if; + led_cnt <= 0; + else + led_cnt <= led_cnt + 1; + end if; + -- -- -- + end case; + + when CONFIG => + new_config <= '1'; + config_started_ack <= '0'; + if (config_started = '1') then + new_config <= '0'; + config_started_ack <= '1'; + state_init <= MAIN; + end if; + + -- main "loop" + when MAIN => + if (chk_recv_cntr = 1000) then + chk_recv_cntr <= 0; + state_read_data <= RD_1; + state_init <= READ_DATA; + busy <= '1'; + else + chk_recv_cntr <= chk_recv_cntr + 1; + end if; + + + -- read data from socket 0 + when READ_DATA => + case state_read_data is + when RD_1 => + par_addr <= W5300_S0_RX_RSR; + state_init <= READ_REG; + next_state <= READ_DATA; + state_read_data <= RD_2; + when RD_2 => + socket_rx_received (31 downto 16) <= data_read; + par_addr <= W5300_S0_RX_RSR + X"2"; + state_init <= READ_REG; + next_state <= READ_DATA; + state_read_data <= RD_3; + when RD_3 => + socket_rx_received (15 downto 0) <= data_read; + state_read_data <= RD_4; + when RD_4 => + if (socket_rx_received (16 downto 0) > ('0' & X"000")) then + rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2 + state_read_data <= RD_5; + else + busy <= '0'; + state_init <= MAIN; + end if; + when RD_5 => + if (rx_packets_cnt > 0) then + rx_packets_cnt <= rx_packets_cnt - '1'; + par_addr <= W5300_S0_RX_FIFOR; + state_init <= READ_REG; + next_state <= READ_DATA; + state_read_data <= next_state_read_data; + else + state_read_data <= RD_END; + end if; + + + ------------------------- + -- command handling + ------------------------- + + -- read command (5 words) + when RD_CMD => + cmd_array (next_packet_data_cnt) <= data_read; + next_packet_data_cnt <= next_packet_data_cnt + 1; + -- look for command start + if (next_packet_data_cnt = 0) then + if (data_read /= CMD_START_DELIMITER) then + next_packet_data_cnt <= 0; + end if; + end if; + -- last command-word + if (next_packet_data_cnt = 4) then + next_packet_data_cnt <= 0; + state_read_data <= RD_CMD_PARSE; + else + state_read_data <= RD_5; + end if; + + -- process commands and parameters + when RD_CMD_PARSE => + case cmd_array (1) is + + when CMD_TLED => + led_int <= NOT led_int; + state_read_data <= RD_5; + + when CMD_WRITE => + case cmd_array (2) is + -- write to address in static data block + when PAR_WRITE_SD_ADDR => + new_config_flag <= '1'; + next_state_read_data <= RD_WRITE_SD_ADDR; + state_read_data <= RD_5; + -- write static data block + when PAR_WRITE_SD => + new_config_flag <= '1'; + next_state_read_data <= RD_WRITE_SD_BLOCK; + state_read_data <= RD_5; + when others => + state_read_data <= RD_5; + end case; -- cmd_array (2) + + when CMD_READ => + case cmd_array (2) is + -- read from address in static data block + when PAR_READ_SD_ADDR => + next_state_read_data <= RD_READ_SD_ADDR; + state_read_data <= RD_5; + -- read static data block + when PAR_READ_SD => + state_read_data <= RD_READ_SD_BLOCK; + when PAR_READ_DD => + state_read_data <= RD_READ_DD_BLOCK; + when others => + state_read_data <= RD_5; + end case; -- cmd_array (2) + + when CMD_PING => + state_ping <= PING_START; + state_read_data <= RD_PING; + + when others => + state_read_data <= RD_5; + + end case; -- cmd_array (1) + + + -- ping all FTUs and write FTU-list to ethernet + when RD_PING => + case state_ping is + when PING_START => + ping_ftu_start <= '1'; + if (ping_ftu_started = '1') then + ping_ftu_start <= '0'; + state_ping <= PING_WAIT; + end if; + when PING_WAIT => + if (ping_ftu_ready = '1') then + state_ping <= PING_WRITE_LIST; + end if; + when PING_WRITE_LIST => + state_read_data <= RD_5; + read_addr_state <= READ_FROM_FL_ADDR; + local_sd_addr <= X"000"; --start at address 0x000 + local_write_length <= "00000" & FL_BLOCK_SIZE; + next_state_read_data <= RD_CMD; + next_state <= READ_DATA; + state_init <= WRITE_DATA; + end case; + + -- read dynamic data block and write it to ethernet + when RD_READ_DD_BLOCK => + case state_read_dd_block is + when READ_DD_BLOCK_START => + dd_block_start <= '1'; + dd_block_ready <= '0'; + if (dd_block_start_ack = '1') then + dd_block_start <= '0'; + state_read_dd_block <= READ_DD_BLOCK_WRITE; + end if; + when READ_DD_BLOCK_WRITE => + read_addr_state <= READ_FROM_DD_ADDR; + local_sd_addr <= X"000"; -- start at address 0x000 + local_write_length <= "00000" & DD_BLOCK_SIZE; + state_read_dd_block <= READ_DD_BLOCK_END; + next_state <= READ_DATA; + state_init <= WRITE_DATA; + when READ_DD_BLOCK_END => + dd_block_ready <= '1'; + state_read_dd_block <= READ_DD_BLOCK_START; + state_read_data <= RD_5; + next_state_read_data <= RD_CMD; + end case; + + -- read static data block and write it to ethernet + when RD_READ_SD_BLOCK => + state_read_data <= RD_5; + read_addr_state <= READ_FROM_SD_ADDR; + local_sd_addr <= X"000"; -- start at address 0x000 + local_write_length <= "00000" & SD_BLOCK_SIZE; + next_state_read_data <= RD_CMD; + next_state <= READ_DATA; + state_init <= WRITE_DATA; + + -- read from address in static data ram and write data to ethernet + when RD_READ_SD_ADDR => + state_read_data <= RD_5; + read_addr_state <= READ_FROM_SD_ADDR; + local_sd_addr <= data_read (11 downto 0); + local_write_length <= '0' & X"0001"; -- one word will be written to ethernet + next_state_read_data <= RD_CMD; + next_state <= READ_DATA; + state_init <= WRITE_DATA; + + -- read static data block from ethernet and write it to static data ram + when RD_WRITE_SD_BLOCK => + state_read_data <= RD_5; + next_packet_data_cnt <= next_packet_data_cnt + 1; + local_sd_addr <= conv_std_logic_vector (next_packet_data_cnt, 12); + local_sd_data <= data_read; + next_state <= READ_DATA; + state_init <= WRITE_TO_SD_ADDR; + -- last word + if (next_packet_data_cnt = (SD_BLOCK_SIZE - 1)) then + next_packet_data_cnt <= 0; + next_state_read_data <= RD_CMD; + end if; + + -- write to address in static data ram + when RD_WRITE_SD_ADDR => + state_read_data <= RD_5; + next_packet_data_cnt <= next_packet_data_cnt + 1; + if (next_packet_data_cnt = 0) then + local_sd_addr <= data_read (11 downto 0); + else + local_sd_data <= data_read; + next_packet_data_cnt <= 0; + next_state_read_data <= RD_CMD; + next_state <= READ_DATA; + state_init <= WRITE_TO_SD_ADDR; + end if; + + + ------------------------- + ------------------------- + + + when RD_END => + par_addr <= W5300_S0_CR; + par_data <= X"0040"; -- RECV + state_init <= WRITE_REG; + if (new_config_flag = '1') then + new_config_flag <= '0'; + next_state <= CONFIG; + else + next_state <= MAIN; + end if; + + end case; -- state_read_data + + + -- read from ftu list ram + when READ_FROM_FL_ADDR => + case state_read_fl is + when READ_FL_START => + if (fl_busy = '0') then + fl_addr <= local_sd_addr; + fl_read <= '1'; + state_read_fl <= READ_FL_WAIT; + end if; + when READ_FL_WAIT => + if (fl_started = '1') then + state_read_fl <= READ_FL_END; + end if; + when READ_FL_END => + if (fl_ready = '1') then + local_sd_data <= fl_data_in; + fl_read <= '0'; + state_read_fl <= READ_FL_START; + state_init <= next_state; + end if; + end case; + + -- read from dynamic data block + when READ_FROM_DD_ADDR => + case state_read_dd is + when READ_DD_START => + if (dd_busy = '0') then + dd_addr <= local_sd_addr; + dd_read <= '1'; + state_read_dd <= READ_DD_WAIT; + end if; + when READ_DD_WAIT => + if (dd_started = '1') then + state_read_dd <= READ_DD_END; + end if; + when READ_DD_END => + if (dd_ready = '1') then + local_sd_data <= dd_data_in; + dd_read <= '0'; + state_read_dd <= READ_DD_START; + state_init <= next_state; + end if; + end case; + + -- read from static data block + when READ_FROM_SD_ADDR => + case state_read_sd is + when READ_SD_START => + if (sd_busy = '0') then + sd_addr <= local_sd_addr; + sd_read <= '1'; + state_read_sd <= READ_SD_WAIT; + end if; + when READ_SD_WAIT => + if (sd_started = '1') then + state_read_sd <= READ_SD_END; + end if; + when READ_SD_END => + if (sd_ready = '1') then + local_sd_data <= sd_data_in; + sd_read <= '0'; + state_read_sd <= READ_SD_START; + state_init <= next_state; + end if; + end case; + + -- write to static data block + when WRITE_TO_SD_ADDR => + case state_write_sd is + when WRITE_SD_START => + if (sd_busy = '0') then + sd_addr <= local_sd_addr; + sd_data_out <= local_sd_data; + sd_write <= '1'; + state_write_sd <= WRITE_SD_WAIT; + end if; + when WRITE_SD_WAIT => + if (sd_started = '1') then + sd_write <= '0'; + state_write_sd <= WRITE_SD_END; + end if; + when WRITE_SD_END => + if (sd_ready = '1') then + state_write_sd <= WRITE_SD_START; + state_init <= next_state; + end if; + end case; + + + + when WRITE_DATA => + case state_write is + when WR_START => + state_write <= WR_LENGTH; + when WR_LENGTH => + local_socket_nr <= "000"; + next_state_tmp <= next_state; + write_length_bytes <= local_write_length (15 downto 0) & '0'; -- shift left (*2) + data_cnt <= 0; + state_write <= WR_01; + -- Check FIFO Size + when WR_01 => + par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC; + state_init <= READ_REG; + next_state <= WRITE_DATA; + state_write <= WR_02; + when WR_02 => + socket_tx_free (31 downto 16) <= data_read; + par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2"; + state_init <= READ_REG; + next_state <= WRITE_DATA; + state_write <= WR_03; + when WR_03 => + socket_tx_free (15 downto 0) <= data_read; + state_write <= WR_04; + when WR_04 => + if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then + state_write <= WR_01; + else + state_write <= WR_FIFO; + end if; + + -- Fill FIFO + when WR_FIFO => + state_init <= read_addr_state; + next_state <= WRITE_DATA; + state_write <= WR_FIFO_01; + + when WR_FIFO_01 => + data_cnt <= data_cnt + 1; + if (data_cnt < local_write_length) then + local_sd_addr <= local_sd_addr + 1; + par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; + par_data <= local_sd_data; + state_init <= WRITE_REG; + next_state <= WRITE_DATA; + state_write <= WR_FIFO; + else + state_write <= WR_05; + end if; + + --Send FIFO + when WR_05 => + par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC; + par_data <= (0 => write_length_bytes (16), others => '0'); + state_init <= WRITE_REG; + state_write <= WR_06; + when WR_06 => + par_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2"; + par_data <= write_length_bytes (15 downto 0); + state_init <= WRITE_REG; + state_write <= WR_07; + when WR_07 => + par_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC; + par_data <= X"0020"; -- Send + state_init <= WRITE_REG; + state_write <= WR_08; + when others => + state_init <= next_state_tmp; + state_write <= WR_START; + end case; + -- End WRITE_DATA + + when READ_REG => + case count is + when "000" => + cs <= '0'; + rd <= '0'; + wr <= '1'; + data <= (others => 'Z'); -- !!!!!!!!!! + count <= "001"; + addr <= par_addr; + when "001" => + count <= "010"; + when "010" => + count <= "100"; + when "100" => + data_read <= data; + count <= "110"; + when "110" => + count <= "111"; + when "111" => + cs <= '1'; + rd <= '1'; + count <= "000"; + state_init <= next_state; + when others => + null; + end case; + + when WRITE_REG => + case count is + when "000" => + cs <= '0'; + wr <= '0'; + rd <= '1'; + addr <= par_addr; + data <= par_data; + count <= "100"; + when "100" => + count <= "101"; + when "101" => + count <= "110"; + when "110" => + cs <= '1'; + wr <= '1'; + state_init <= next_state; + count <= "000"; + when others => + null; + end case; + + when others => + null; + end case; + end if; -- int_flag = '0' + + end if; -- rising_edge (clk) + + end process w5300_init_proc; + +end Behavioral; + Index: firmware/FTM/ftm_board.ucf =================================================================== --- firmware/FTM/ftm_board.ucf (revision 10225) +++ firmware/FTM/ftm_board.ucf (revision 10227) @@ -5,6 +5,8 @@ # Pin location constraints # -# by Patrick Vogler -# 18 August 2010 +# by Patrick Vogler, 18 August 2010 +# +# modified by Q. Weitzel, 01 March 2011 +# (NET W_A<0> added and assigned to unconnected pin) ######################################################## @@ -38,7 +40,8 @@ # W5300 address bus -NET W_A<1> LOC = AA25 | IOSTANDARD=LVCMOS33; # there is NO net W_A0 because -NET W_A<2> LOC = AA24 | IOSTANDARD=LVCMOS33; # the W5300 is operated in the 16-bit mode -NET W_A<3> LOC = AA23 | IOSTANDARD=LVCMOS33; # see W5300 datasheet +NET W_A<0> LOC = U18 | IOSTANDARD=LVCMOS33; # there is no real net W_A0 because +NET W_A<1> LOC = AA25 | IOSTANDARD=LVCMOS33; # the W5300 is operated in the 16-bit mode +NET W_A<2> LOC = AA24 | IOSTANDARD=LVCMOS33; # (see W5300 datasheet) +NET W_A<3> LOC = AA23 | IOSTANDARD=LVCMOS33; # -> W_A<0> assigned to unconnected pin NET W_A<4> LOC = Y25 | IOSTANDARD=LVCMOS33; # NET W_A<5> LOC = Y24 | IOSTANDARD=LVCMOS33; # @@ -58,14 +61,14 @@ # W5300 buffer ready indicator -NET W_BRDY<0> LOC = AB26 | IOSTANDARD=LVCMOS33; # -NET W_BRDY<1> LOC = AC26 | IOSTANDARD=LVCMOS33; # -NET W_BRDY<2> LOC = AC25 | IOSTANDARD=LVCMOS33; # -NET W_BRDY<3> LOC = AD26 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<0> LOC = AB26 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<1> LOC = AC26 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<2> LOC = AC25 | IOSTANDARD=LVCMOS33; # +# NET W_BRDY<3> LOC = AD26 | IOSTANDARD=LVCMOS33; # # W5300 associated testpoints -NET W_T<0> LOC = N21 | IOSTANDARD=LVCMOS33; # -NET W_T<1> LOC = M21 | IOSTANDARD=LVCMOS33; # -NET W_T<2> LOC = K21 | IOSTANDARD=LVCMOS33; # -NET W_T<3> LOC = R19 | IOSTANDARD=LVCMOS33; # +# NET W_T<0> LOC = N21 | IOSTANDARD=LVCMOS33; # +# NET W_T<1> LOC = M21 | IOSTANDARD=LVCMOS33; # +# NET W_T<2> LOC = K21 | IOSTANDARD=LVCMOS33; # +# NET W_T<3> LOC = R19 | IOSTANDARD=LVCMOS33; # @@ -75,17 +78,17 @@ # on IO-Bank 1 ####################################################### -NET S_CLK LOC = U20 | IOSTANDARD=LVCMOS33; # SPI clock +# NET S_CLK LOC = U20 | IOSTANDARD=LVCMOS33; # SPI clock # EEPROM -NET MOSI LOC = AA22 | IOSTANDARD=LVCMOS33; # master out slave in -NET MISO LOC = V22 | IOSTANDARD=LVCMOS33; # master in slave out -NET EE_CS LOC = G22 | IOSTANDARD=LVCMOS33; # master out slave in +# NET MOSI LOC = AA22 | IOSTANDARD=LVCMOS33; # master out slave in +# NET MISO LOC = V22 | IOSTANDARD=LVCMOS33; # master in slave out +# NET EE_CS LOC = G22 | IOSTANDARD=LVCMOS33; # master out slave in # temperature sensors -NET SIO LOC = F22 | IOSTANDARD=LVCMOS33; # serial IO -NET TS_CS<0> LOC = H21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select0 -NET TS_CS<1> LOC = J21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select1 -NET TS_CS<2> LOC = C25 | IOSTANDARD=LVCMOS33; # temperature sensors chip select2 -NET TS_CS<3> LOC = C26 | IOSTANDARD=LVCMOS33; # temperature sensors chip select3 +# NET SIO LOC = F22 | IOSTANDARD=LVCMOS33; # serial IO +# NET TS_CS<0> LOC = H21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select0 +# NET TS_CS<1> LOC = J21 | IOSTANDARD=LVCMOS33; # temperature sensors chip select1 +# NET TS_CS<2> LOC = C25 | IOSTANDARD=LVCMOS33; # temperature sensors chip select2 +# NET TS_CS<3> LOC = C26 | IOSTANDARD=LVCMOS33; # temperature sensors chip select3 @@ -95,53 +98,53 @@ # crate 0 # crate A -NET Trig_Prim_A<0> LOC = AC6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<0> -NET Trig_Prim_A<1> LOC = AD6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<1> -NET Trig_Prim_A<2> LOC = AF3 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<2> -NET Trig_Prim_A<3> LOC = AE4 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<3> -NET Trig_Prim_A<4> LOC = AE6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<4> -NET Trig_Prim_A<5> LOC = AE7 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<5> -NET Trig_Prim_A<6> LOC = AE8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<6> -NET Trig_Prim_A<7> LOC = AC8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<7> -NET Trig_Prim_A<8> LOC = AC11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<8> -NET Trig_Prim_A<9> LOC = AD11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<9> +# NET Trig_Prim_A<0> LOC = AC6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<0> +# NET Trig_Prim_A<1> LOC = AD6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<1> +# NET Trig_Prim_A<2> LOC = AF3 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<2> +# NET Trig_Prim_A<3> LOC = AE4 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<3> +# NET Trig_Prim_A<4> LOC = AE6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<4> +# NET Trig_Prim_A<5> LOC = AE7 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<5> +# NET Trig_Prim_A<6> LOC = AE8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<6> +# NET Trig_Prim_A<7> LOC = AC8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<7> +# NET Trig_Prim_A<8> LOC = AC11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<8> +# NET Trig_Prim_A<9> LOC = AD11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<9> # crate 1 # crate B -NET Trig_Prim_B<0> LOC = AB16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<0> -NET Trig_Prim_B<1> LOC = AC15 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<1> -NET Trig_Prim_B<2> LOC = AC16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<2> -NET Trig_Prim_B<3> LOC = AE17 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<3> -NET Trig_Prim_B<4> LOC = AD19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<4> -NET Trig_Prim_B<5> LOC = AE19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<5> -NET Trig_Prim_B<6> LOC = AE20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<6> -NET Trig_Prim_B<7> LOC = AF20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<7> -NET Trig_Prim_B<8> LOC = AD21 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<8> -NET Trig_Prim_B<9> LOC = AE23 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<9> +# NET Trig_Prim_B<0> LOC = AB16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<0> +# NET Trig_Prim_B<1> LOC = AC15 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<1> +# NET Trig_Prim_B<2> LOC = AC16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<2> +# NET Trig_Prim_B<3> LOC = AE17 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<3> +# NET Trig_Prim_B<4> LOC = AD19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<4> +# NET Trig_Prim_B<5> LOC = AE19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<5> +# NET Trig_Prim_B<6> LOC = AE20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<6> +# NET Trig_Prim_B<7> LOC = AF20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<7> +# NET Trig_Prim_B<8> LOC = AD21 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<8> +# NET Trig_Prim_B<9> LOC = AE23 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<9> # crate 2 # crate C -NET Trig_Prim_C<0> LOC = AF23 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<0> -NET Trig_Prim_C<1> LOC = AC21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<1> -NET Trig_Prim_C<2> LOC = AE21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<2> -NET Trig_Prim_C<3> LOC = AD20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<3> -NET Trig_Prim_C<4> LOC = AC20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<4> -NET Trig_Prim_C<5> LOC = AF19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<5> -NET Trig_Prim_C<6> LOC = AC19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<6> -NET Trig_Prim_C<7> LOC = AD17 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<7> -NET Trig_Prim_C<8> LOC = AD14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<8> -NET Trig_Prim_C<9> LOC = AC14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<9> +# NET Trig_Prim_C<0> LOC = AF23 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<0> +# NET Trig_Prim_C<1> LOC = AC21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<1> +# NET Trig_Prim_C<2> LOC = AE21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<2> +# NET Trig_Prim_C<3> LOC = AD20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<3> +# NET Trig_Prim_C<4> LOC = AC20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<4> +# NET Trig_Prim_C<5> LOC = AF19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<5> +# NET Trig_Prim_C<6> LOC = AC19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<6> +# NET Trig_Prim_C<7> LOC = AD17 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<7> +# NET Trig_Prim_C<8> LOC = AD14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<8> +# NET Trig_Prim_C<9> LOC = AC14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<9> # crate 3 # crate D -NET Trig_Prim_D<0> LOC = AB12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<0> -NET Trig_Prim_D<1> LOC = AC12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<1> -NET Trig_Prim_D<2> LOC = AC9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<2> -NET Trig_Prim_D<3> LOC = AB9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<3> -NET Trig_Prim_D<4> LOC = AB7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<4> -NET Trig_Prim_D<5> LOC = AF8 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<5> -NET Trig_Prim_D<6> LOC = AF4 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<6> -NET Trig_Prim_D<7> LOC = AF5 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<7> -NET Trig_Prim_D<8> LOC = AD7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<8> -NET Trig_Prim_D<9> LOC = AE3 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<9> +# NET Trig_Prim_D<0> LOC = AB12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<0> +# NET Trig_Prim_D<1> LOC = AC12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<1> +# NET Trig_Prim_D<2> LOC = AC9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<2> +# NET Trig_Prim_D<3> LOC = AB9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<3> +# NET Trig_Prim_D<4> LOC = AB7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<4> +# NET Trig_Prim_D<5> LOC = AF8 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<5> +# NET Trig_Prim_D<6> LOC = AF4 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<6> +# NET Trig_Prim_D<7> LOC = AF5 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<7> +# NET Trig_Prim_D<8> LOC = AD7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<8> +# NET Trig_Prim_D<9> LOC = AE3 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<9> @@ -149,14 +152,14 @@ ####################################################### # on IO-Bank 3 -NET ext_Trig<1> LOC = B1 | IOSTANDARD=LVCMOS33; # -NET ext_Trig<2> LOC = B2 | IOSTANDARD=LVCMOS33; # -NET Veto LOC = E4 | IOSTANDARD=LVCMOS33; # -NET NIM_In<0> LOC = D3 | IOSTANDARD=LVCMOS33; # -NET NIM_In<1> LOC = F4 | IOSTANDARD=LVCMOS33; # -NET NIM_In<2> LOC = E3 | IOSTANDARD=LVCMOS33; # +# NET ext_Trig<1> LOC = B1 | IOSTANDARD=LVCMOS33; # +# NET ext_Trig<2> LOC = B2 | IOSTANDARD=LVCMOS33; # +# NET Veto LOC = E4 | IOSTANDARD=LVCMOS33; # +# NET NIM_In<0> LOC = D3 | IOSTANDARD=LVCMOS33; # +# NET NIM_In<1> LOC = F4 | IOSTANDARD=LVCMOS33; # +# NET NIM_In<2> LOC = E3 | IOSTANDARD=LVCMOS33; # # on IO-Bank 0 # input pin with global clock buffer available -NET NIM_In3_GCLK LOC = K14 | IOSTANDARD=LVCMOS33; +# NET NIM_In3_GCLK LOC = K14 | IOSTANDARD=LVCMOS33; @@ -182,9 +185,9 @@ # on IO-Bank 3 ####################################################### -NET CLK_Clk_Cond LOC = G4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 -NET LE_Clk_Cond LOC = F2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 -NET LD_Clk_Cond LOC = J4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 -NET DATA_Clk_Cond LOC = F3 | IOSTANDARD=LVCMOS33; # IO-Bank 3 -NET SYNC_Clk_Cond LOC = H2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET CLK_Clk_Cond LOC = G4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET LE_Clk_Cond LOC = F2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET LD_Clk_Cond LOC = J4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET DATA_Clk_Cond LOC = F3 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET SYNC_Clk_Cond LOC = H2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 @@ -214,33 +217,33 @@ # Bus 2: Trigger-ID to FAD boards -NET Bus2_Tx_En LOC = K2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -NET Bus2_Rx_En LOC = K4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_Tx_En LOC = K2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_Rx_En LOC = K4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # # crate 0 -NET Bus2_RxD_0 LOC = L4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -NET Bus2_TxD_0 LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_RxD_0 LOC = L4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_0 LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # # crate 1 -NET Bus2_RxD_1 LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -NET Bus2_TxD_1 LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_RxD_1 LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_1 LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # # crate 2 -NET Bus2_RxD_2 LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -NET Bus2_TxD_2 LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_RxD_2 LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_2 LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # # crate 3 -NET Bus2_RxD_3 LOC = U4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -NET Bus2_TxD_3 LOC = U2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_RxD_3 LOC = U4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Bus2_TxD_3 LOC = U2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # # auxiliary access -NET Aux_Rx_D LOC = W3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -NET Aux_Tx_D LOC = Y2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -NET Aux_Rx_En LOC = W4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # Rx- and Tx enable -NET Aux_Tx_En LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary Trigger-ID +# NET Aux_Rx_D LOC = W3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Aux_Tx_D LOC = Y2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Aux_Rx_En LOC = W4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # Rx- and Tx enable +# NET Aux_Tx_En LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary Trigger-ID # auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container) -NET TrID_Rx_D LOC = U6 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -NET TrID_Tx_D LOC = T7 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET TrID_Rx_D LOC = U6 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET TrID_Tx_D LOC = T7 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # @@ -248,8 +251,8 @@ # on IO-Bank 3 ####################################################### -NET Crate_Res0 LOC = M1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -NET Crate_Res1 LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -NET Crate_Res2 LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -NET Crate_Res3 LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Crate_Res0 LOC = M1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Crate_Res1 LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Crate_Res2 LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Crate_Res3 LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # @@ -257,8 +260,8 @@ # on IO-Bank 3 ####################################################### -NET Busy0 LOC = M4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -NET Busy1 LOC = P2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -NET Busy2 LOC = R4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -NET Busy3 LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy0 LOC = M4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy1 LOC = P2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy2 LOC = R4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +# NET Busy3 LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # @@ -269,14 +272,14 @@ ####################################################### # calibration -NET Cal_NIM1_p LOC = D18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM1+ -NET Cal_NIM1_n LOC = C18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM1- -NET Cal_NIM2_p LOC = B18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM2+ -NET Cal_NIM2_n LOC = A18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM2- +# NET Cal_NIM1_p LOC = D18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM1+ +# NET Cal_NIM1_n LOC = C18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM1- +# NET Cal_NIM2_p LOC = B18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM2+ +# NET Cal_NIM2_n LOC = A18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # Cal_NIM2- # auxiliarry / spare NIM outputs -NET NIM_Out0_p LOC = C17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out0+ -NET NIM_Out0_n LOC = B17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out0- -NET NIM_Out1_p LOC = D17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # NIM_Out1+ -NET NIM_Out1_n LOC = C16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out1- +# NET NIM_Out0_p LOC = C17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out0+ +# NET NIM_Out0_n LOC = B17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out0- +# NET NIM_Out1_p LOC = D17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # NIM_Out1+ +# NET NIM_Out1_n LOC = C16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out1- @@ -285,16 +288,16 @@ # conversion stage ####################################################### -NET RES_p LOC = D16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES+ Reset -NET RES_n LOC = C15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES- IO-Bank 0 - -NET TRG_p LOC = B15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG+ Trigger -NET TRG_n LOC = A15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG- IO-Bank 0 - -NET TIM_Run_p LOC = AF25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run+ Time Marker -NET TIM_Run_n LOC = AE25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run- on IO-Bank2 - -NET TIM_Sel LOC = AD22 | IOSTANDARD=LVCMOS33; # Time Marker selector IO-Bank 2 - -NET CLD_FPGA LOC = AA14 | IOSTANDARD=LVCMOS33; # DRS-Clock feedback into FPGA +# NET RES_p LOC = D16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES+ Reset +# NET RES_n LOC = C15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES- IO-Bank 0 + +# NET TRG_p LOC = B15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG+ Trigger +# NET TRG_n LOC = A15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG- IO-Bank 0 + +# NET TIM_Run_p LOC = AF25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run+ Time Marker +# NET TIM_Run_n LOC = AE25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run- on IO-Bank2 + +# NET TIM_Sel LOC = AD22 | IOSTANDARD=LVCMOS33; # Time Marker selector IO-Bank 2 + +# NET CLD_FPGA LOC = AA14 | IOSTANDARD=LVCMOS33; # DRS-Clock feedback into FPGA @@ -303,22 +306,22 @@ ####################################################### # to connector J13 -NET Cal_0_p LOC = D22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0+ -NET Cal_0_n LOC = C22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0- -NET Cal_1_p LOC = D23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1+ -NET Cal_1_n LOC = C23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1- -NET Cal_2_p LOC = B23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2+ -NET Cal_2_n LOC = A22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2- -NET Cal_3_p LOC = C21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3+ -NET Cal_3_n LOC = B21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3- +# NET Cal_0_p LOC = D22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0+ +# NET Cal_0_n LOC = C22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0- +# NET Cal_1_p LOC = D23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1+ +# NET Cal_1_n LOC = C23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1- +# NET Cal_2_p LOC = B23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2+ +# NET Cal_2_n LOC = A22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2- +# NET Cal_3_p LOC = C21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3+ +# NET Cal_3_n LOC = B21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3- # to connector J12 -NET Cal_4_p LOC = E21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4+ -NET Cal_4_n LOC = D21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4- -NET Cal_5_p LOC = D20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5+ -NET Cal_5_n LOC = C20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5- -NET Cal_6_p LOC = B20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6+ -NET Cal_6_n LOC = A20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6- -NET Cal_7_p LOC = B19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7+ -NET Cal_7_n LOC = A19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7- +# NET Cal_4_p LOC = E21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4+ +# NET Cal_4_n LOC = D21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4- +# NET Cal_5_p LOC = D20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5+ +# NET Cal_5_n LOC = C20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5- +# NET Cal_6_p LOC = B20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6+ +# NET Cal_6_n LOC = A20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6- +# NET Cal_7_p LOC = B19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7+ +# NET Cal_7_n LOC = A19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7- @@ -327,65 +330,65 @@ # Connector T7 # IO-Bank 0 -NET TP<0> LOC = B14 | IOSTANDARD=LVCMOS33; # -NET TP<1> LOC = A14 | IOSTANDARD=LVCMOS33; # -NET TP<2> LOC = C13 | IOSTANDARD=LVCMOS33; # -NET TP<3> LOC = B13 | IOSTANDARD=LVCMOS33; # +# NET TP<0> LOC = B14 | IOSTANDARD=LVCMOS33; # +# NET TP<1> LOC = A14 | IOSTANDARD=LVCMOS33; # +# NET TP<2> LOC = C13 | IOSTANDARD=LVCMOS33; # +# NET TP<3> LOC = B13 | IOSTANDARD=LVCMOS33; # # Connector T10 # IO-Bank 0 -NET TP<4> LOC = D13 | IOSTANDARD=LVCMOS33; # -NET TP<5> LOC = C12 | IOSTANDARD=LVCMOS33; # -NET TP<6> LOC = B12 | IOSTANDARD=LVCMOS33; # -NET TP<7> LOC = A12 | IOSTANDARD=LVCMOS33; # +# NET TP<4> LOC = D13 | IOSTANDARD=LVCMOS33; # +# NET TP<5> LOC = C12 | IOSTANDARD=LVCMOS33; # +# NET TP<6> LOC = B12 | IOSTANDARD=LVCMOS33; # +# NET TP<7> LOC = A12 | IOSTANDARD=LVCMOS33; # # on Connector T12 # IO-Bank 0 -NET TP<8> LOC = D11 | IOSTANDARD=LVCMOS33; # -NET TP<9> LOC = C11 | IOSTANDARD=LVCMOS33; # +# NET TP<8> LOC = D11 | IOSTANDARD=LVCMOS33; # +# NET TP<9> LOC = C11 | IOSTANDARD=LVCMOS33; # # on Connector T14 # IO-Bank 0 -NET TP<10> LOC = D10 | IOSTANDARD=LVCMOS33; # -NET TP<11> LOC = C10 | IOSTANDARD=LVCMOS33; # -NET TP<12> LOC = A10 | IOSTANDARD=LVCMOS33; # -NET TP<13> LOC = B10 | IOSTANDARD=LVCMOS33; # +# NET TP<10> LOC = D10 | IOSTANDARD=LVCMOS33; # +# NET TP<11> LOC = C10 | IOSTANDARD=LVCMOS33; # +# NET TP<12> LOC = A10 | IOSTANDARD=LVCMOS33; # +# NET TP<13> LOC = B10 | IOSTANDARD=LVCMOS33; # # on Connector T16 # IO-Bank 0 -NET TP<14> LOC = A9 | IOSTANDARD=LVCMOS33; # -NET TP<15> LOC = B9 | IOSTANDARD=LVCMOS33; # -NET TP<16> LOC = A8 | IOSTANDARD=LVCMOS33; # -NET TP<17> LOC = B8 | IOSTANDARD=LVCMOS33; # +# NET TP<14> LOC = A9 | IOSTANDARD=LVCMOS33; # +# NET TP<15> LOC = B9 | IOSTANDARD=LVCMOS33; # +# NET TP<16> LOC = A8 | IOSTANDARD=LVCMOS33; # +# NET TP<17> LOC = B8 | IOSTANDARD=LVCMOS33; # # on Connector T8 # IO-Bank 0 -NET TP<18> LOC = C8 | IOSTANDARD=LVCMOS33; # -NET TP<19> LOC = D8 | IOSTANDARD=LVCMOS33; # -NET TP<20> LOC = C6 | IOSTANDARD=LVCMOS33; # -NET TP<21> LOC = B6 | IOSTANDARD=LVCMOS33; # +# NET TP<18> LOC = C8 | IOSTANDARD=LVCMOS33; # +# NET TP<19> LOC = D8 | IOSTANDARD=LVCMOS33; # +# NET TP<20> LOC = C6 | IOSTANDARD=LVCMOS33; # +# NET TP<21> LOC = B6 | IOSTANDARD=LVCMOS33; # # on Connector T9 # IO-Bank 0 -NET TP<22> LOC = C7 | IOSTANDARD=LVCMOS33; # -NET TP<23> LOC = B7 | IOSTANDARD=LVCMOS33; # +# NET TP<22> LOC = C7 | IOSTANDARD=LVCMOS33; # +# NET TP<23> LOC = B7 | IOSTANDARD=LVCMOS33; # # on Connector T11 # IO-Bank 3 -NET TP<24> LOC = Y1 | IOSTANDARD=LVCMOS33; # -NET TP<25> LOC = AA3 | IOSTANDARD=LVCMOS33; # -NET TP<26> LOC = AA2 | IOSTANDARD=LVCMOS33; # -NET TP<27> LOC = AC1 | IOSTANDARD=LVCMOS33; # +# NET TP<24> LOC = Y1 | IOSTANDARD=LVCMOS33; # +# NET TP<25> LOC = AA3 | IOSTANDARD=LVCMOS33; # +# NET TP<26> LOC = AA2 | IOSTANDARD=LVCMOS33; # +# NET TP<27> LOC = AC1 | IOSTANDARD=LVCMOS33; # # on Connector T13 # IO-Bank 3 -NET TP<28> LOC = AB1 | IOSTANDARD=LVCMOS33; # -NET TP<29> LOC = AC3 | IOSTANDARD=LVCMOS33; # -NET TP<30> LOC = AC2 | IOSTANDARD=LVCMOS33; # -NET TP<31> LOC = AD2 | IOSTANDARD=LVCMOS33; # +# NET TP<28> LOC = AB1 | IOSTANDARD=LVCMOS33; # +# NET TP<29> LOC = AC3 | IOSTANDARD=LVCMOS33; # +# NET TP<30> LOC = AC2 | IOSTANDARD=LVCMOS33; # +# NET TP<31> LOC = AD2 | IOSTANDARD=LVCMOS33; # # on Connector T15 -NET TP<32> LOC = AD1 | IOSTANDARD=LVCMOS33; # IO-Bank 3 -NET TP_in<33> LOC = AE2 | IOSTANDARD=LVCMOS33; # input only -NET TP_in<34> LOC = AE1 | IOSTANDARD=LVCMOS33; # input only +# NET TP<32> LOC = AD1 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +# NET TP_in<33> LOC = AE2 | IOSTANDARD=LVCMOS33; # input only +# NET TP_in<34> LOC = AE1 | IOSTANDARD=LVCMOS33; # input only @@ -394,11 +397,10 @@ # all on 'input only' pins ####################################################### -NET brd_id<0> LOC = A13 | IOSTANDARD=LVCMOS33; # -NET brd_id<1> LOC = A17 | IOSTANDARD=LVCMOS33; # -NET brd_id<2> LOC = D12 | IOSTANDARD=LVCMOS33; # -NET brd_id<3> LOC = N25 | IOSTANDARD=LVCMOS33; # -NET brd_id<4> LOC = N26 | IOSTANDARD=LVCMOS33; # -NET brd_id<5> LOC = K24 | IOSTANDARD=LVCMOS33; # -NET brd_id<6> LOC = H24 | IOSTANDARD=LVCMOS33; # -NET brd_id<7> LOC = Y26 | IOSTANDARD=LVCMOS33; # - +# NET brd_id<0> LOC = A13 | IOSTANDARD=LVCMOS33; # +# NET brd_id<1> LOC = A17 | IOSTANDARD=LVCMOS33; # +# NET brd_id<2> LOC = D12 | IOSTANDARD=LVCMOS33; # +# NET brd_id<3> LOC = N25 | IOSTANDARD=LVCMOS33; # +# NET brd_id<4> LOC = N26 | IOSTANDARD=LVCMOS33; # +# NET brd_id<5> LOC = K24 | IOSTANDARD=LVCMOS33; # +# NET brd_id<6> LOC = H24 | IOSTANDARD=LVCMOS33; # +# NET brd_id<7> LOC = Y26 | IOSTANDARD=LVCMOS33; # Index: firmware/FTM/ftm_definitions.vhd =================================================================== --- firmware/FTM/ftm_definitions.vhd (revision 10225) +++ firmware/FTM/ftm_definitions.vhd (revision 10227) @@ -19,4 +19,7 @@ -- modified: Patrick Vogler, February 17 2011 -- merged with library file from Dortmund, Q. Weitzel, February 24, 2011 +-- +-- kw 25.02.: changes for HDL-Designer (use FACT_FTM.lib.ftm_...), +-- DD_BLOCK_SIZE added (set to 0x008 for first tests), SD_ADDR_coin_win_[p,c] defined ---------------------------------------------------------------------------------- @@ -53,7 +56,10 @@ use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; +-- for HDL-Designer +-- LIBRARY FACT_FTM_lib; +-- use FACT_FTM_lib.ftm_array_types.all; library ftm_definitions; use ftm_definitions.ftm_array_types.all; --- use IEEE.NUMERIC_STD.ALL; +use IEEE.NUMERIC_STD.ALL; package ftm_constants is @@ -69,4 +75,5 @@ constant INT_CLK_FREQUENCY_1 : integer := 50000000; -- 50MHz constant INT_CLK_FREQUENCY_2 : integer := 250000000; -- 250MHz + constant LOW_FREQUENCY : integer := 1000000; -- has to be smaller than INT_CLK_FREQUENCY_1 --FTM address and firmware ID @@ -77,4 +84,6 @@ constant FTU_RS485_BAUD_RATE : integer := 250000; -- bits / sec in our case constant FTU_RS485_TIMEOUT : integer := (INT_CLK_FREQUENCY_1 * 2) / 1000; -- 2ms @ 50MHz (100000 clk periods) + -- constant FTU_RS485_BAUD_RATE : integer := 10000000; -- for simulation + -- constant FTU_RS485_TIMEOUT : integer := (INT_CLK_FREQUENCY_1 * 2) / 40000; -- for simulation constant FTU_RS485_NO_OF_RETRY : integer range 0 to 2 := 2; -- in case of timeout, !!! HAS TO BE < 3 !!! constant FTU_RS485_BLOCK_WIDTH : integer := 224; -- 28 byte protocol @@ -166,5 +175,5 @@ -- FTU-list parameters - constant FL_BLOCK_SIZE : std_logic_vector := X"0F9"; -- FTU-list size -- 9 + (40 * 6) =249 + constant FL_BLOCK_SIZE : std_logic_vector := X"0F9"; -- FTU-list size -- 9 + (40 * 6) = 249 constant NO_OF_FTU_LIST_REG : integer := 6; constant FTU_LIST_RAM_OFFSET : integer := 16#009#; @@ -181,4 +190,7 @@ constant SD_FTU_ACTIVE_NUM : integer := 4; -- number of active FTU lists (cr0 to cr3) constant SD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1B4"; -- total size of static data block + + -- dynamic data block + constant DD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"008"; -- 7 + (40 * 12) = 0x1E7 --total size of dynamic data block -- addresses in static data block @@ -212,4 +224,6 @@ constant SD_ADDR_cc_R15_HI : std_logic_vector := X"01B"; constant SD_ADDR_cc_R15_LO : std_logic_vector := X"01C"; + constant SD_ADDR_coin_win_p : std_logic_vector := X"01D"; + constant SD_ADDR_coin_win_c : std_logic_vector := X"01E"; constant SD_ADDR_ftu_active_cr0 : std_logic_vector := X"1B0"; constant SD_ADDR_ftu_active_cr1 : std_logic_vector := X"1B1"; @@ -221,4 +235,5 @@ type sd_block_default_array_type is array (0 to (SD_BLOCK_SIZE_GENERAL - 1)) of std_logic_vector (15 downto 0); type sd_block_ftu_default_array_type is array (0 to (SD_FTU_DATA_SIZE - 1)) of std_logic_vector (15 downto 0); + type sd_block_activeFTUlist_default_array_type is array (0 to (NO_OF_CRATES - 1)) of std_logic_vector (15 downto 0); -- general default values @@ -272,4 +287,12 @@ X"0001" -- Prescaling board x crate y ); + + --default values for active FTU lists + constant sd_block_activeFTUlist_default_array : sd_block_activeFTUlist_default_array_type := ( + X"0001", + X"0000", + X"0000", + X"0000" + ); end ftm_constants; Index: firmware/FTM/ftu_control/FTM_ftu_control.vhd =================================================================== --- firmware/FTM/ftu_control/FTM_ftu_control.vhd (revision 10225) +++ firmware/FTM/ftu_control/FTM_ftu_control.vhd (revision 10227) @@ -69,4 +69,10 @@ ping_all_done : out std_logic := '0'; + -- active FTU lists + ftu_active_cr0 : in std_logic_vector (15 downto 0); + ftu_active_cr1 : in std_logic_vector (15 downto 0); + ftu_active_cr2 : in std_logic_vector (15 downto 0); + ftu_active_cr3 : in std_logic_vector (15 downto 0); + -- communication with static (config) RAM -- this RAM is only read by FTU_control @@ -123,10 +129,10 @@ -- global signals after multiplexer - signal rx_en_sig : std_logic; - signal tx_en_sig : std_logic; - signal rx_valid_sig : std_logic; - signal tx_busy_sig : std_logic; - signal tx_start_sig : std_logic; - signal tx_data_sig : std_logic_vector (7 DOWNTO 0); + signal rx_en_sig : std_logic := '0'; + signal tx_en_sig : std_logic := '0'; + signal rx_valid_sig : std_logic := '0'; + signal tx_busy_sig : std_logic := '0'; + signal tx_start_sig : std_logic := '0'; + signal tx_data_sig : std_logic_vector (7 DOWNTO 0) := (others => '0'); -- signals for interpreter of FTU communication @@ -190,5 +196,5 @@ -- various loop counters - signal active_FTU_list_cnt : integer range 0 to NO_OF_CRATES := 0; + --signal active_FTU_list_cnt : integer range 0 to NO_OF_CRATES := 0; signal crate_cnt : integer range 0 to NO_OF_CRATES := 0; signal FTU_cnt : integer range 0 to NO_OF_FTUS_PER_CRATE := 0; @@ -272,5 +278,4 @@ type FTM_ftu_rs485_control_StateType is (INIT, IDLE, ACTIVE_LIST, READ_CONFIG, TRANSMIT_CONFIG, PING, PING_END, FTU_LIST, RATES, - ACTIVE_LIST_1, ACTIVE_LIST_2, ACTIVE_LIST_3, READ_CONFIG_1, READ_CONFIG_2, READ_CONFIG_3, TRANSMIT_CONFIG_1, TRANSMIT_CONFIG_2, TRANSMIT_CONFIG_3, @@ -435,31 +440,38 @@ end if; - when ACTIVE_LIST => -- loop over 4 crates to get active FTU list - if (active_FTU_list_cnt < NO_OF_CRATES) then - active_FTU_list_cnt <= active_FTU_list_cnt + 1; - FTM_ftu_rs485_control_State <= ACTIVE_LIST_1; - else - active_FTU_list_cnt <= 0; - FTM_ftu_rs485_control_State <= READ_CONFIG; - end if; - - when ACTIVE_LIST_1 => - if (static_RAM_busy = '0') then - read_static_RAM <= '1'; - addr_static_RAM <= conv_std_logic_vector(STATIC_RAM_ACT_FTU_OFFSET + (active_FTU_list_cnt - 1), STATIC_RAM_ADDR_WIDTH); - FTM_ftu_rs485_control_State <= ACTIVE_LIST_2; - end if; + when ACTIVE_LIST => -- copy active FTU list from inputs to array + active_FTU_array_sig(0) <= ftu_active_cr0; + active_FTU_array_sig(1) <= ftu_active_cr1; + active_FTU_array_sig(2) <= ftu_active_cr2; + active_FTU_array_sig(3) <= ftu_active_cr3; + FTM_ftu_rs485_control_State <= READ_CONFIG; + +-- when ACTIVE_LIST => -- loop over 4 crates to get active FTU list +-- if (active_FTU_list_cnt < NO_OF_CRATES) then +-- active_FTU_list_cnt <= active_FTU_list_cnt + 1; +-- FTM_ftu_rs485_control_State <= ACTIVE_LIST_1; +-- else +-- active_FTU_list_cnt <= 0; +-- FTM_ftu_rs485_control_State <= READ_CONFIG; +-- end if; + +-- when ACTIVE_LIST_1 => +-- if (static_RAM_busy = '0') then +-- read_static_RAM <= '1'; +-- addr_static_RAM <= conv_std_logic_vector(STATIC_RAM_ACT_FTU_OFFSET + (active_FTU_list_cnt - 1), STATIC_RAM_ADDR_WIDTH); +-- FTM_ftu_rs485_control_State <= ACTIVE_LIST_2; +-- end if; - when ACTIVE_LIST_2 => - if (static_RAM_started = '1') then - FTM_ftu_rs485_control_State <= ACTIVE_LIST_3; - end if; +-- when ACTIVE_LIST_2 => +-- if (static_RAM_started = '1') then +-- FTM_ftu_rs485_control_State <= ACTIVE_LIST_3; +-- end if; - when ACTIVE_LIST_3 => - if (static_RAM_ready = '1') then - active_FTU_array_sig(active_FTU_list_cnt - 1) <= data_static_RAM; - read_static_RAM <= '0'; - FTM_ftu_rs485_control_State <= ACTIVE_LIST; - end if; +-- when ACTIVE_LIST_3 => +-- if (static_RAM_ready = '1') then +-- active_FTU_array_sig(active_FTU_list_cnt - 1) <= data_static_RAM; +-- read_static_RAM <= '0'; +-- FTM_ftu_rs485_control_State <= ACTIVE_LIST; +-- end if; when READ_CONFIG => -- read configuration of FTUs (one by one) @@ -535,7 +547,7 @@ & FTU_dac_array_RAM_sig(0)(15 downto 8) & FTU_dac_array_RAM_sig(0)(7 downto 0) & "00000000" & FIRMWARE_ID & FTM_ADDRESS - & "00" & conv_std_logic_vector(FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2) + & "00" & conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2) & FTU_RS485_START_DELIM; - FTU_brd_add_sig <= conv_std_logic_vector(FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2); + FTU_brd_add_sig <= conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2); FTU_command_sig <= "00000000"; FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_1; @@ -552,7 +564,7 @@ & FTU_enable_array_RAM_sig(0)(15 downto 8) & FTU_enable_array_RAM_sig(0)(7 downto 0) & "00000011" & FIRMWARE_ID & FTM_ADDRESS - & "00" & conv_std_logic_vector(FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2) + & "00" & conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2) & FTU_RS485_START_DELIM; - FTU_brd_add_sig <= conv_std_logic_vector(FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2); + FTU_brd_add_sig <= conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2); FTU_command_sig <= "00000011"; FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_1; @@ -567,7 +579,7 @@ & FTU_prescaling_RAM_sig(15 downto 8) & FTU_prescaling_RAM_sig(7 downto 0) & "00000110" & FIRMWARE_ID & FTM_ADDRESS - & "00" & conv_std_logic_vector(FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2) + & "00" & conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2) & FTU_RS485_START_DELIM; - FTU_brd_add_sig <= conv_std_logic_vector(FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2); + FTU_brd_add_sig <= conv_std_logic_vector((FTU_cnt - 1),4) & conv_std_logic_vector(crate_cnt,2); FTU_command_sig <= "00000110"; FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_1; @@ -735,5 +747,5 @@ write_FTUlist_RAM <= '1'; addr_FTUlist_RAM <= conv_std_logic_vector(FTU_LIST_RAM_OFFSET + - FTU_cnt * NO_OF_FTU_LIST_REG + + (FTU_cnt - 1)* NO_OF_FTU_LIST_REG + (FTU_list_reg_cnt - 1), FTU_LIST_RAM_ADDR_WIDTH); if (retry_cnt < FTU_RS485_NO_OF_RETRY) then