Index: /firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd =================================================================== --- /firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd (revision 10231) +++ /firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd (revision 10231) @@ -0,0 +1,204 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: Patrick Vogler +-- +-- Create Date: 14 February 2010 +-- Design Name: +-- Module Name: FTM Clock conditioner Interface +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Interface to the LMK03000 Clock conditioner +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- +-- modifications: February 21 2011 by Patrick Vogler +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +library ftm_definitions; +USE ftm_definitions.ftm_array_types.all; +USE ftm_definitions.ftm_constants.all; + + + +entity Clock_cond_interface is + port( + + +-- Clock +------------------------------------------------------------------------------- + clk : IN STD_LOGIC; -- 50 MHz system clock + + +-- Clock conditioner LMK03000 +------------------------------------------------------------------------------- + CLK_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface clock + LE_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface latch enable + DATA_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface data + + SYNC_Clk_Cond : out STD_LOGIC; -- clock conditioner global clock synchronization + LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect + + +-- Time Marker +------------------------------------------------------------------------------- + TIM_Sel : out STD_LOGIC; -- Time Marker selector + -- 1 = time marker from Clock conditioner + -- for DRS timing calibration + -- + -- 0 = time marker from FPGA for normal + -- operation / physics run + + + +-- FPGA intern clock conditioner configuration data +------------------------------------------------------------------------------- + cc_R0 : in std_logic_vector (31 downto 0) := (others => '0'); + cc_R1 : in std_logic_vector (31 downto 0) := (others => '0'); + cc_R8 : in std_logic_vector (31 downto 0) := (others => '0'); + cc_R9 : in std_logic_vector (31 downto 0) := (others => '0'); + cc_R11 : in std_logic_vector (31 downto 0) := (others => '0'); + cc_R13 : in std_logic_vector (31 downto 0) := (others => '0'); + cc_R14 : in std_logic_vector (31 downto 0) := (others => '0'); + cc_R15 : in std_logic_vector (31 downto 0) := (others => '0'); + + + + +-- FPGA intern control signals +------------------------------------------------------------------------------- + start_config : in STD_LOGIC; -- load new configuration into the clock + -- conditioner + + config_started : out STD_LOGIC; -- indicates that the new configuration + -- is currently loaded into the clock conditioner + + config_done : out STD_LOGIC; -- indicates that the configuration has + -- been loaded and the clock conditioners + -- PLL is locked + + timemarker_select: in STD_LOGIC -- selects time marker source + -- + -- 1 = time marker from Clock conditioner + -- for DRS timing calibration + -- + -- 0 = time marker from FPGA for normal + -- operation / physics run + + ); +end Clock_cond_interface; + + + + +architecture Behavioral of Clock_cond_interface is + + +component microwire_interface IS + PORT( + clk : IN std_logic; + clk_uwire : OUT std_logic; --- IN or OUT ? + data_uwire : OUT std_logic; + le_uwire : OUT std_logic; + clk_cond_array : IN clk_cond_array_type; + config_start : IN std_logic; + config_ready : OUT std_logic; + config_started : OUT std_logic + ); +end component; + + + + + signal clk_50M_sig : STD_LOGIC; -- system clock +-- signal start_config_sig : STD_LOGIC; + + signal config_ready_sig : STD_LOGIC; + signal clk_uwire_sig : STD_LOGIC; + + signal config_started_sig : STD_LOGIC; + + signal clk_cond_array_sig : clk_cond_array_type; + + signal cc_R0_sig : std_logic_vector (31 downto 0); + signal cc_R1_sig : std_logic_vector (31 downto 0); + signal cc_R8_sig : std_logic_vector (31 downto 0); + signal cc_R9_sig : std_logic_vector (31 downto 0); + signal cc_R11_sig : std_logic_vector (31 downto 0); + signal cc_R13_sig : std_logic_vector (31 downto 0); + signal cc_R14_sig : std_logic_vector (31 downto 0); + signal cc_R15_sig : std_logic_vector (31 downto 0); + +begin + + Inst_microwire_interface:microwire_interface + port map ( + clk => clk_50M_sig, + clk_uwire => clk_uwire_sig, + data_uwire => DATA_Clk_Cond, + le_uwire => LE_Clk_Cond, + clk_cond_array => clk_cond_array_sig, + + config_start => start_config, + -- config_start => start_config_sig, + -- config_start <= start_config_sig, + + config_ready => config_ready_sig, + config_started => config_started_sig + ); + + + config_done <= (config_ready_sig AND LD_Clk_Cond); -- indicates that the configuration + -- has been loaded and + -- the PLL is locked again + + TIM_Sel <= timemarker_select; + CLK_Clk_Cond <= clk_uwire_sig; + + clk_50M_sig <= clk; + -- start_config_sig <= start_config; + + -- start_config <= start_config_sig; + + + config_started <= config_started_sig; + + cc_R0_sig <= cc_R0; + cc_R1_sig <= cc_R1; + cc_R8_sig <= cc_R8; + cc_R9_sig <= cc_R9; + cc_R11_sig <= cc_R11; + cc_R13_sig <= cc_R13; + cc_R14_sig <= cc_R14; + cc_R15_sig <= cc_R15; + + clk_cond_array_sig(0) <= LMK03000_Reset; -- reset LKM03000 by setting + -- bit 31 of register 0 + clk_cond_array_sig(1) <= cc_R0_sig; + clk_cond_array_sig(2) <= cc_R1_sig; + clk_cond_array_sig(3) <= cc_R8_sig; + clk_cond_array_sig(4) <= cc_R9_sig; + clk_cond_array_sig(5) <= cc_R11_sig; + clk_cond_array_sig(6) <= cc_R13_sig; + clk_cond_array_sig(7) <= cc_R14_sig; + clk_cond_array_sig(8) <= cc_R15_sig; + + +end Behavioral; + + Index: /firmware/FTM/Clock_cond_interface/Clock_cond_interface_tb.vhd =================================================================== --- /firmware/FTM/Clock_cond_interface/Clock_cond_interface_tb.vhd (revision 10231) +++ /firmware/FTM/Clock_cond_interface/Clock_cond_interface_tb.vhd (revision 10231) @@ -0,0 +1,182 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: Patrick Vogler +-- +-- Create Date: 16:19:23 02/21/2011 +-- Design Name: +-- Module Name: +-- Project Name: Clock_cond_interface +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: Clock_cond_interface +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE ieee.numeric_std.ALL; + + +library ftm_definitions; +use ftm_definitions.ftm_array_types.all; +use ftm_definitions.ftm_constants.all; + + +ENTITY Clock_cond_interface_tb IS +END Clock_cond_interface_tb; + +ARCHITECTURE behavior OF Clock_cond_interface_tb IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT Clock_cond_interface + PORT( + clk : IN std_logic; + CLK_Clk_Cond : OUT std_logic; + LE_Clk_Cond : OUT std_logic; + DATA_Clk_Cond : OUT std_logic; + SYNC_Clk_Cond : OUT std_logic; + LD_Clk_Cond : IN std_logic; + TIM_Sel : OUT std_logic; + cc_R0 : IN std_logic_vector(31 downto 0); + cc_R1 : IN std_logic_vector(31 downto 0); + cc_R8 : IN std_logic_vector(31 downto 0); + cc_R9 : IN std_logic_vector(31 downto 0); + cc_R11 : IN std_logic_vector(31 downto 0); + cc_R13 : IN std_logic_vector(31 downto 0); + cc_R14 : IN std_logic_vector(31 downto 0); + cc_R15 : IN std_logic_vector(31 downto 0); + + + start_config : IN std_logic; + config_started : OUT std_logic; + config_done : OUT std_logic; + timemarker_select : IN std_logic + ); + END COMPONENT; + + + --Inputs + signal clk : std_logic := '0'; + signal LD_Clk_Cond : std_logic := '0'; + + + signal cc_R0 : std_logic_vector(31 downto 0) := x"00010100"; + signal cc_R1 : std_logic_vector(31 downto 0) := x"00010101"; + signal cc_R8 : std_logic_vector(31 downto 0) := x"10000908"; + signal cc_R9 : std_logic_vector(31 downto 0) := x"A0032A09"; + signal cc_R11 : std_logic_vector(31 downto 0) := x"0082000B"; + signal cc_R13 : std_logic_vector(31 downto 0) := x"020A000D"; + signal cc_R14 : std_logic_vector(31 downto 0) := x"0830280E"; + signal cc_R15 : std_logic_vector(31 downto 0) := x"2000960F"; + + + signal start_config : std_logic := '0'; + signal timemarker_select : std_logic := '0'; + + + + + + --Outputs + signal CLK_Clk_Cond : std_logic; + signal LE_Clk_Cond : std_logic; + signal DATA_Clk_Cond : std_logic; + signal SYNC_Clk_Cond : std_logic; + signal TIM_Sel : std_logic; + signal config_started : std_logic; + signal config_done : std_logic; + + + + -- Clock period definitions + constant clk_period : time := 20 ns; -- 50 MHz Clock + -- constant CLK_Clk_Cond_period : time := 10 ns; + + + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: Clock_cond_interface PORT MAP ( + clk => clk, + CLK_Clk_Cond => CLK_Clk_Cond, + LE_Clk_Cond => LE_Clk_Cond, + DATA_Clk_Cond => DATA_Clk_Cond, + SYNC_Clk_Cond => SYNC_Clk_Cond, + LD_Clk_Cond => LD_Clk_Cond, + TIM_Sel => TIM_Sel, + cc_R0 => cc_R0, + cc_R1 => cc_R1, + cc_R8 => cc_R8, + cc_R9 => cc_R9, + cc_R11 => cc_R11, + cc_R13 => cc_R13, + cc_R14 => cc_R14, + cc_R15 => cc_R15, + start_config => start_config, + config_started => config_started, + config_done => config_done, + timemarker_select => timemarker_select + ); + + + + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + +-- CLK_Clk_Cond_process :process +-- begin +-- CLK_Clk_Cond <= '0'; +-- wait for CLK_Clk_Cond_period/2; +-- CLK_Clk_Cond <= '1'; +-- wait for CLK_Clk_Cond_period/2; +-- end process; + + + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100 ms. + -- wait for 100 ms; + + TIM_Sel <= '0'; + + wait for clk_period*20; + + -- insert stimulus here + + start_config <= '1'; + wait for clk_period*100; + start_config <= '0'; + + wait for 180 us; + LD_Clk_Cond <= '1'; + + wait; + end process; + +END; Index: /firmware/FTM/Clock_cond_interface/microwire_clock_gen.vhd =================================================================== --- /firmware/FTM/Clock_cond_interface/microwire_clock_gen.vhd (revision 10231) +++ /firmware/FTM/Clock_cond_interface/microwire_clock_gen.vhd (revision 10231) @@ -0,0 +1,63 @@ +-- +-- VHDL Architecture FACT_FAD_lib.spi_clock_generator.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 14:49:19 01.04.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +-- modified by Patrick Vogler +-- +-- February 17 2011 +-- +-- September 16 2010 +-- +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; + + +library ftm_definitions; +USE ftm_definitions.ftm_constants.all; + + + + + +ENTITY microwire_clock_gen IS + GENERIC( + CLK_DIVIDER : integer := INT_CLK_FREQUENCY_1 / MICROWIRE_CLK_FREQUENCY --2 MHz @ 50 MHz + + ); + PORT( + clk : IN std_logic; + sclk : OUT std_logic := '0' + ); +END microwire_clock_gen; + +ARCHITECTURE beha OF microwire_clock_gen IS + +BEGIN + + spi_clk_proc: process (clk) + variable Z: integer range 0 to clk_divider - 1; + begin + if rising_edge(clk) then + if (Z < clk_divider - 1) then + Z := Z + 1; + else + Z := 0; + end if; + if (Z = 0) then + sclk <= '1'; + end if; + if (Z = clk_divider / 2) then + sclk <= '0'; + end if; + end if; + end process spi_clk_proc; + +END ARCHITECTURE beha; Index: /firmware/FTM/Clock_cond_interface/microwire_controller.vhd =================================================================== --- /firmware/FTM/Clock_cond_interface/microwire_controller.vhd (revision 10231) +++ /firmware/FTM/Clock_cond_interface/microwire_controller.vhd (revision 10231) @@ -0,0 +1,112 @@ +-- +-- VHDL Architecture FACT_FAD_lib.spi_controller.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 10:37:20 12.04.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +-- modified by Q. Weitzel +-- +------------------------------------------------------------------------------- +-- +-- modified by Patrick Vogler +-- February 17 2011 +-- September 17 2010 +-- +-- modified to be used as a Microwire interface to control the clock +-- conditioner LMK03000 on the FTM board +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; + + +library ftm_definitions; +USE ftm_definitions.ftm_array_types.all; +USE ftm_definitions.ftm_constants.all; + + + +ENTITY microwire_controller IS + PORT( + clk_uwire : IN std_logic; -- sclk + data_uwire : OUT std_logic := '0'; -- mosi + le_uwire : OUT std_logic := '1'; -- Latch Enable = chip select + + clk_cond_array : IN clk_cond_array_type; -- data to be loaded + -- into the clock conditioner + config_start : IN std_logic; + config_ready : OUT std_logic := '0'; + config_started : OUT std_logic := '0' + ); +END microwire_controller ; + + +ARCHITECTURE beha OF microwire_controller IS + + type TYPE_uWire_STATE is (IDLE, LOAD_SHIFT_REG, SHIFT); + signal uwire_state : TYPE_uWire_STATE := IDLE; + signal register_count : integer range 0 to LMK03000_REGISTER_COUNT := 0; + signal bit_count : integer range 0 to LMK03000_REGISTER_WIDTH := 0; + signal shift_reg : std_logic_vector (LMK03000_REGISTER_WIDTH - 1 downto 0) := (others => '0'); + + + +BEGIN + + uwire_write_proc: process (clk_uwire) + begin + + if falling_edge(clk_uwire) then + + case uwire_state is + + when IDLE => + + le_uwire <= '1'; + config_ready <= '1'; + config_started <= '0'; + bit_count <= 0; + register_count <= 0; + data_uwire <= '0'; + + if (config_start = '1') then + config_ready <= '0'; + uwire_state <= LOAD_SHIFT_REG; + end if; + + + when LOAD_SHIFT_REG => + bit_count <= 0; + config_started <= '1'; + shift_reg <= clk_cond_array(register_count) (LMK03000_REGISTER_WIDTH - 1 downto 0); + register_count <= register_count + 1; +-- le_uwire <= '0'; + uwire_state <= SHIFT; + + + when SHIFT => + data_uwire <= shift_reg(LMK03000_REGISTER_WIDTH - 1); + le_uwire <= '0'; + shift_reg <= shift_reg(LMK03000_REGISTER_WIDTH - 2 downto 0) & shift_reg(LMK03000_REGISTER_WIDTH - 1); + bit_count <= bit_count + 1; + if ((bit_count = LMK03000_REGISTER_WIDTH)AND(register_count = LMK03000_REGISTER_COUNT)) then + le_uwire <= '1'; + uwire_state <= IDLE; + elsif ((bit_count =LMK03000_REGISTER_WIDTH )AND(NOT(register_count = LMK03000_REGISTER_COUNT))) then + le_uwire <= '1'; + uwire_state <= LOAD_SHIFT_REG; + else + uwire_state <= SHIFT; + end if; + + end case; + end if; + + end process uwire_write_proc; + +END ARCHITECTURE beha; Index: /firmware/FTM/Clock_cond_interface/microwire_interface.vhd =================================================================== --- /firmware/FTM/Clock_cond_interface/microwire_interface.vhd (revision 10231) +++ /firmware/FTM/Clock_cond_interface/microwire_interface.vhd (revision 10231) @@ -0,0 +1,118 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: P. Vogler, Q. Weitzel +-- +-- Create Date: 07/14/2010 +-- Design Name: +-- Module Name: FTM_test3_microwire_interface - Behavioral +-- (based on FTU_test5_spi_interface - Behavioral) +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Based on VHDL Entity FACT_FAD_lib.spi_interface.symbol +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- +-- modified by Patrick Vogler, September 17 2010 +-- for use as a microwire interface to the clock conditioner LMK03000 +-- on the FTM board +-- +-- modified by Patrick Vogler, February 15 2011 +-- to be used as an FTM firmware clock conditioner interface +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library ftm_definitions; +USE ftm_definitions.ftm_array_types.all; +USE ftm_definitions.ftm_constants.all; + + + +------------------------------------------------------------------------------- +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +ENTITY microwire_interface IS + PORT( + clk : IN std_logic; -- 50MHz + clk_uwire : OUT std_logic; -- sclk + data_uwire : OUT std_logic := '0'; -- mosi + le_uwire : OUT std_logic := '1'; -- Latch Enable = chip select + clk_cond_array : IN clk_cond_array_type; -- data to be loaded + -- into the clock conditioner + config_start : IN std_logic; + config_ready : OUT std_logic := '0'; + config_started : OUT std_logic := '0' + ); +END microwire_interface; + + +ARCHITECTURE struct OF microwire_interface IS + + -- Internal signal declarations + SIGNAL clk_uwire_sig : std_logic; + + + -- Component Declarations + COMPONENT microwire_clock_gen + GENERIC ( + CLK_DIVIDER : integer := INT_CLK_FREQUENCY_1 / MICROWIRE_CLK_FREQUENCY --2 MHz @ 50 MHz + ); + PORT ( + clk : IN std_logic; + sclk : OUT std_logic := '0' + ); + END COMPONENT; + + + COMPONENT microwire_controller + PORT ( + clk_uwire : IN std_logic; -- sclk + data_uwire : OUT std_logic := '0'; -- mosi + le_uwire : OUT std_logic := '1'; -- Latch Enable = chip select + clk_cond_array : IN clk_cond_array_type; -- data to be loaded + -- into the clock conditioner + config_start : IN std_logic; + config_ready : OUT std_logic := '0'; + config_started : OUT std_logic := '0' + ); + END COMPONENT; + + + +BEGIN + + -- Instance port mappings. + Inst_microwire_clock_gen : microwire_clock_gen + GENERIC MAP ( + CLK_DIVIDER => INT_CLK_FREQUENCY_1 / MICROWIRE_CLK_FREQUENCY --2 MHz @ 50 MHz + ) + PORT MAP ( + clk => clk, + sclk => clk_uwire_sig + ); + + Inst_microwire_controller : microwire_controller + PORT MAP ( + clk_uwire => clk_uwire_sig, + data_uwire => data_uwire, + le_uwire => le_uwire, + clk_cond_array => clk_cond_array, + config_start => config_start, + config_ready => config_ready, + config_started => config_started + ); + + clk_uwire<= clk_uwire_sig; + +END struct;