Index: firmware/FTU/rs485/FTU_rs485_control.vhd
===================================================================
--- firmware/FTU/rs485/FTU_rs485_control.vhd	(revision 10237)
+++ firmware/FTU/rs485/FTU_rs485_control.vhd	(revision 10238)
@@ -74,8 +74,9 @@
   signal rx_valid_sig : std_logic;  -- initialized in FTU_rs485_interface
   signal rx_data_sig  : std_logic_vector (7 DOWNTO 0);  -- initialized in FTU_rs485_interface
-  --signal rx_busy_sig  : std_logic;  -- initialized in FTU_rs485_interface
-
-  signal block_valid_sig : std_logic;  -- initialized in FTU_rs485_receiver
-  signal data_block_sig  : std_logic_vector(RS485_BLOCK_WIDTH - 1 downto 0);  -- initialized in FTU_rs485_receiver
+  signal rx_busy_sig  : std_logic;  -- initialized in FTU_rs485_interface
+
+  signal block_valid_sig       : std_logic;  -- initialized in FTU_rs485_receiver
+  signal start_interpreter_sig : std_logic := '0';
+  signal data_block_sig        : std_logic_vector(RS485_BLOCK_WIDTH - 1 downto 0);  -- initialized in FTU_rs485_receiver
 
   signal int_new_DACs_sig        : std_logic;  -- initialized in FTU_rs485_interpreter
@@ -117,5 +118,5 @@
     port(
       rec_clk   : in  std_logic;
-      --rx_busy   : in  std_logic;
+      -- rx_busy   : in  std_logic;
       rec_din   : in  std_logic_vector(7 downto 0);
       rec_den   : in  std_logic;
@@ -156,5 +157,5 @@
       -- FPGA
       rx_data  : OUT std_logic_vector (7 DOWNTO 0);
-      --rx_busy  : OUT std_logic  := '0';
+      rx_busy  : OUT std_logic  := '0';
       rx_valid : OUT std_logic  := '0';
       tx_data  : IN  std_logic_vector (7 DOWNTO 0);
@@ -176,4 +177,5 @@
 
   crc_sig <= crc_sig_inv(0) & crc_sig_inv(1) & crc_sig_inv(2) & crc_sig_inv(3) & crc_sig_inv(4) & crc_sig_inv(5) & crc_sig_inv(6) & crc_sig_inv(7);
+  start_interpreter_sig <= block_valid_sig and (not rx_busy_sig);  -- avoid answering to early to FTM
   
   Inst_ucrc_par : ucrc_par
@@ -196,5 +198,5 @@
     port map(
       rec_clk   => main_clk,
-      --rx_busy   =>,
+      -- rx_busy   => rx_busy_sig,
       rec_din   => rx_data_sig,
       rec_den   => rx_valid_sig,
@@ -207,5 +209,5 @@
       clk                    => main_clk,
       data_block             => data_block_sig,
-      block_valid            => block_valid_sig,
+      block_valid            => start_interpreter_sig,
       brd_add                => brd_add,
       crc_error_cnt          => crc_error_cnt_sig,
@@ -233,5 +235,5 @@
       -- FPGA
       rx_data  => rx_data_sig,
-      --rx_busy  => rx_busy_sig,
+      rx_busy  => rx_busy_sig,
       rx_valid => rx_valid_sig,
       tx_data  => tx_data_sig,
Index: firmware/FTU/rs485/FTU_rs485_interface.vhd
===================================================================
--- firmware/FTU/rs485/FTU_rs485_interface.vhd	(revision 10237)
+++ firmware/FTU/rs485/FTU_rs485_interface.vhd	(revision 10238)
@@ -34,5 +34,5 @@
     -- FPGA
     rx_data  : OUT    std_logic_vector (7 DOWNTO 0);
-    --rx_busy  : OUT    std_logic  := '0';
+    rx_busy  : OUT    std_logic  := '0';
     rx_valid : OUT    std_logic  := '0';
     tx_data  : IN     std_logic_vector (7 DOWNTO 0);
@@ -122,5 +122,5 @@
   rx_en <= flow_ctrl;
   rx_data <= rx_sr;
-  --rx_busy <= '1' when (rx_bitcnt < 11) else '0';
+  rx_busy <= '1' when (rx_bitcnt < 11) else '0';
 
 END ARCHITECTURE beha;
Index: firmware/FTU/rs485/FTU_rs485_receiver.vhd
===================================================================
--- firmware/FTU/rs485/FTU_rs485_receiver.vhd	(revision 10237)
+++ firmware/FTU/rs485/FTU_rs485_receiver.vhd	(revision 10238)
@@ -27,5 +27,5 @@
   port(
     rec_clk   : in  std_logic;
-    --rx_busy   : in  std_logic;
+    -- rx_busy   : in  std_logic;
     rec_din   : in  std_logic_vector(7 downto 0);
     rec_den   : in  std_logic;