Index: firmware/FTM/ftu_control/FTM_ftu_control.vhd
===================================================================
--- firmware/FTM/ftu_control/FTM_ftu_control.vhd	(revision 10232)
+++ firmware/FTM/ftu_control/FTM_ftu_control.vhd	(revision 10256)
@@ -109,5 +109,6 @@
   -- list of active FTUs, read out from static RAM before starting to contact FTUs
   signal active_FTU_array_sig : active_FTU_array_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'));
-
+  --signal active_FTU_array_sig : active_FTU_array_type := ("0000000000000001", (others => '0'), (others => '0'), (others => '0'));
+  
   -- signals to count the number of responding FTUs (per crate and total) in case of a ping
   signal FTU_answer_array_sig : FTU_answer_array_type := (0,0,0,0);
@@ -129,10 +130,12 @@
 
   -- global signals after multiplexer
-  signal rx_en_sig    : std_logic := '0';
-  signal tx_en_sig    : std_logic := '0';
-  signal rx_valid_sig : std_logic := '0';
-  signal tx_busy_sig  : std_logic := '0';
-  signal tx_start_sig : std_logic := '0';
-  signal tx_data_sig  : std_logic_vector (7 DOWNTO 0) := (others => '0');
+  signal rx_en_sig     : std_logic := '0';
+  signal tx_en_sig     : std_logic := '0';
+  signal rx_valid_sig  : std_logic := '0';
+  signal tx_busy_sig   : std_logic := '0';
+  signal tx_start_sig  : std_logic := '0';
+  signal tx_data_sig   : std_logic_vector (7 DOWNTO 0) := (others => '0');
+  signal rx_busy_sig   : std_logic := '0';
+  signal start_int_sig : std_logic := '0';
   
   -- signals for interpreter of FTU communication
@@ -163,4 +166,5 @@
   signal rx_valid_0_sig : std_logic;  -- initialized in FTM_ftu_rs485_interface_0
   signal rx_data_0_sig  : std_logic_vector (7 DOWNTO 0);  -- initialized in FTM_ftu_rs485_interface_0
+  signal rx_busy_0_sig  : std_logic;  -- initialized in FTU_rs485_interface_0
   
   signal tx_start_1_sig : std_logic := '0';
@@ -169,5 +173,6 @@
   signal rx_valid_1_sig : std_logic;  -- initialized in FTM_ftu_rs485_interface_1
   signal rx_data_1_sig  : std_logic_vector (7 DOWNTO 0);  -- initialized in FTM_ftu_rs485_interface_1
-
+  signal rx_busy_1_sig  : std_logic;  -- initialized in FTU_rs485_interface_1
+  
   signal tx_start_2_sig : std_logic := '0';
   signal tx_data_2_sig  : std_logic_vector (7 DOWNTO 0) := (others => '0');
@@ -175,5 +180,6 @@
   signal rx_valid_2_sig : std_logic;  -- initialized in FTM_ftu_rs485_interface_2
   signal rx_data_2_sig  : std_logic_vector (7 DOWNTO 0);  -- initialized in FTM_ftu_rs485_interface_2
-
+  signal rx_busy_2_sig  : std_logic;  -- initialized in FTU_rs485_interface_2
+  
   signal tx_start_3_sig : std_logic := '0';
   signal tx_data_3_sig  : std_logic_vector (7 DOWNTO 0) := (others => '0');
@@ -181,5 +187,6 @@
   signal rx_valid_3_sig : std_logic;  -- initialized in FTM_ftu_rs485_interface_3
   signal rx_data_3_sig  : std_logic_vector (7 DOWNTO 0);  -- initialized in FTM_ftu_rs485_interface_3
-
+  signal rx_busy_3_sig  : std_logic;  -- initialized in FTU_rs485_interface_3
+  
   -- signals to control and read out CRC
   signal sel_crc_input_source_sig        : std_logic := '0';  -- 0 -> FSM, 1 -> interpreter
@@ -219,5 +226,5 @@
       -- FPGA
       rx_data  : OUT std_logic_vector (7 DOWNTO 0);
-      --rx_busy  : OUT std_logic  := '0';
+      rx_busy  : OUT std_logic  := '0';
       rx_valid : OUT std_logic  := '0';
       tx_data  : IN  std_logic_vector (7 DOWNTO 0);
@@ -277,5 +284,6 @@
 
   type FTM_ftu_rs485_control_StateType is (INIT, IDLE, ACTIVE_LIST, READ_CONFIG, TRANSMIT_CONFIG,
-                                           PING, PING_END, FTU_LIST, RATES,
+                                           PING, PING_END, FTU_LIST,
+                                           RATES, RATES_1, RATES_2, RATES_3,
                                            READ_CONFIG_1, READ_CONFIG_2, READ_CONFIG_3,
                                            TRANSMIT_CONFIG_1, TRANSMIT_CONFIG_2, TRANSMIT_CONFIG_3,
@@ -285,5 +293,5 @@
 
 begin
-
+  
   Inst_FTM_fTU_rs485_interface_0 : FTM_ftu_rs485_interface  -- crate 0
     port map(
@@ -296,5 +304,5 @@
       -- FPGA
       rx_data  => rx_data_0_sig,
-      --rx_busy  => ,
+      rx_busy  => rx_busy_0_sig,
       rx_valid => rx_valid_0_sig,
       tx_data  => tx_data_0_sig,
@@ -313,5 +321,5 @@
       -- FPGA
       rx_data  => rx_data_1_sig,
-      --rx_busy  => ,
+      rx_busy  => rx_busy_1_sig,
       rx_valid => rx_valid_1_sig,
       tx_data  => tx_data_1_sig,
@@ -330,5 +338,5 @@
       -- FPGA
       rx_data  => rx_data_2_sig,
-      --rx_busy  => ,
+      rx_busy  => rx_busy_2_sig,
       rx_valid => rx_valid_2_sig,
       tx_data  => tx_data_2_sig,
@@ -347,5 +355,5 @@
       -- FPGA
       rx_data  => rx_data_3_sig,
-      --rx_busy  => ,
+      rx_busy  => rx_busy_3_sig,
       rx_valid => rx_valid_3_sig,
       tx_data  => tx_data_3_sig,
@@ -369,5 +377,5 @@
       clk               => clk_50MHz,
       data_block        => rec_block_sig,
-      block_valid       => rec_valid_sig,
+      block_valid       => start_int_sig,
       crc               => crc_sig,
       FTU_brd_add       => FTU_brd_add_sig,
@@ -427,4 +435,5 @@
             ping_all_started   <= '1';
             read_rates_started <= '0';
+            rec_reset_sig <= '1';
             FTM_ftu_rs485_control_State <= PING;
           elsif (new_config = '0' and  ping_all = '0' and read_rates = '1') then
@@ -486,4 +495,5 @@
                 FTU_register_cnt <= 0;
                 if (active_FTU_array_sig(crate_cnt)(FTU_cnt) = '1') then
+                  rec_reset_sig <= '1';
                   FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG;
                 else
@@ -644,5 +654,5 @@
             end if;
           end if;
-            
+
         when PING =>  -- ping all FTUs
           rec_reset_sig <= '0';
@@ -679,7 +689,9 @@
         when PING_1 =>  -- wait one cycle for CRC calculation
           enable_crc_from_FSM_sig <= '0';
+          rec_reset_sig <= '1';
           FTM_ftu_rs485_control_State <= PING_2;
 
         when PING_2 =>  -- transmit byte by byte
+          rec_reset_sig <= '0';
           if (tx_busy_sig = '0') then
             if (frame_cnt < 27) then
@@ -789,4 +801,9 @@
             ping_all_done <= '1';
             sel_crate_sig <= "111";
+            FTU_answer_array_sig(0) <= 0;
+            FTU_answer_array_sig(1) <= 0;
+            FTU_answer_array_sig(2) <= 0;
+            FTU_answer_array_sig(3) <= 0;
+            no_of_FTU_answer_sig <= 0;
             FTM_ftu_rs485_control_State <= IDLE;
           end if;
@@ -818,6 +835,91 @@
           
         when RATES =>  -- read all FTU rates
-          FTM_ftu_rs485_control_State <= IDLE;
-
+          rec_reset_sig <= '0';
+          if (crate_cnt < NO_OF_CRATES) then
+            sel_crate_sig <= conv_std_logic_vector(crate_cnt, 3);
+            if (FTU_cnt < NO_OF_FTUS_PER_CRATE) then
+              FTU_cnt <= FTU_cnt + 1;
+              if (active_FTU_array_sig(crate_cnt)(FTU_cnt) = '1') then
+                enable_crc_from_FSM_sig <= '1';
+                crc_data_from_FSM_sig <= "00000000"
+                                         & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
+                                         & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
+                                         & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
+                                         & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" & "00000000"
+                                         & "00000010" & FIRMWARE_ID & FTM_ADDRESS
+                                         & "00" & conv_std_logic_vector(FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2)
+                                         & FTU_RS485_START_DELIM;
+                FTU_brd_add_sig <= conv_std_logic_vector(FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2);
+                FTU_command_sig <= "00000010";
+                FTM_ftu_rs485_control_State <= RATES_1;
+              else
+                FTM_ftu_rs485_control_State <= RATES;
+              end if;
+            else
+              crate_cnt <= crate_cnt + 1;
+              FTU_cnt <= 0;
+              FTM_ftu_rs485_control_State <= RATES;
+            end if;
+          else
+            crate_cnt <= 0;
+            read_rates_started <= '0';
+            read_rates_done <= '1';
+            sel_crate_sig <= "111";
+            FTM_ftu_rs485_control_State <= IDLE;
+          end if;
+
+        when RATES_1 =>  -- wait one cycle for CRC calculation
+          enable_crc_from_FSM_sig <= '0';
+          FTM_ftu_rs485_control_State <= RATES_2;
+
+        when RATES_2 =>  -- transmit byte by byte
+          if (tx_busy_sig = '0') then
+            if (frame_cnt < 27) then
+              frame_cnt <= frame_cnt + 1;
+              tx_data_sig <= crc_data_from_FSM_sig (7 downto 0);
+              crc_data_from_FSM_sig <= "00000000" & crc_data_from_FSM_sig ((FTU_RS485_BLOCK_WIDTH - 9) downto 8);
+              tx_start_sig <= '1';
+              FTM_ftu_rs485_control_State <= RATES_2;
+            elsif (frame_cnt = 27) then
+              frame_cnt <= frame_cnt + 1;
+              tx_data_sig <= crc_sig;
+              tx_start_sig <= '1';
+              FTM_ftu_rs485_control_State <= RATES_2;
+            else
+              frame_cnt <= 0;
+              reset_crc_from_FSM_sig <= '1';
+              FTM_ftu_rs485_control_State <= RATES_3;
+            end if;            
+          else
+            tx_start_sig <= '0';
+            FTM_ftu_rs485_control_State <= RATES_2;
+          end if;
+
+          when RATES_3 =>  -- wait for FTU answer
+          reset_crc_from_FSM_sig <= '0';
+          if (FTU_answer_ok_sig = '1') then
+            timeout_cnt <= 0;
+            sel_crc_input_source_sig <= '0';
+            FTM_ftu_rs485_control_State <= RATES;
+          else
+            if (timeout_cnt < FTU_RS485_TIMEOUT) then
+              timeout_cnt <= timeout_cnt + 1;
+              sel_crc_input_source_sig <= '1';
+              FTM_ftu_rs485_control_State <= RATES_3;
+            else
+              timeout_cnt <= 0;
+              sel_crc_input_source_sig <= '0';
+              rec_reset_sig <= '1';
+              if (retry_cnt < FTU_RS485_NO_OF_RETRY) then
+                retry_cnt <= retry_cnt + 1;
+                FTU_cnt <= FTU_cnt - 1;  -- repeat this FTU
+                FTM_ftu_rs485_control_State <= RATES;
+              else
+                FTU_cnt <= FTU_cnt;  -- move on
+                FTM_ftu_rs485_control_State <= RATES;
+              end if;
+            end if;
+          end if;
+          
       end case;
     end if;
@@ -831,4 +933,5 @@
                               rx_data_0_sig, rx_data_1_sig, rx_data_2_sig, rx_data_3_sig,
                               tx_busy_0_sig, tx_busy_1_sig, tx_busy_2_sig, tx_busy_3_sig,
+                              rx_busy_0_sig, rx_busy_1_sig, rx_busy_2_sig, rx_busy_3_sig,
                               tx_start_sig, tx_data_sig)
   begin 
@@ -840,4 +943,5 @@
         rec_data_sig <= rx_data_0_sig;
         tx_busy_sig <= tx_busy_0_sig;
+        rx_busy_sig <= rx_busy_0_sig;
         tx_start_0_sig <= tx_start_sig;
         tx_start_1_sig <= '0';
@@ -854,4 +958,5 @@
         rec_data_sig <= rx_data_1_sig;
         tx_busy_sig <= tx_busy_1_sig;
+        rx_busy_sig <= rx_busy_1_sig;
         tx_start_0_sig <= '0';
         tx_start_1_sig <= tx_start_sig;
@@ -868,4 +973,5 @@
         rec_data_sig <= rx_data_2_sig;
         tx_busy_sig <= tx_busy_2_sig;
+        rx_busy_sig <= rx_busy_2_sig;
         tx_start_0_sig <= '0';
         tx_start_1_sig <= '0';
@@ -882,4 +988,5 @@
         rec_data_sig <= rx_data_3_sig;
         tx_busy_sig <= tx_busy_3_sig;
+        rx_busy_sig <= rx_busy_3_sig;
         tx_start_0_sig <= '0';
         tx_start_1_sig <= '0';
@@ -896,4 +1003,5 @@
         rec_data_sig <= (others => '0');
         tx_busy_sig <= '0';
+        rx_busy_sig <= '0';
         tx_start_0_sig <= '0';
         tx_start_1_sig <= '0';
@@ -933,4 +1041,5 @@
 
   crc_sig <= crc_sig_inv(0) & crc_sig_inv(1) & crc_sig_inv(2) & crc_sig_inv(3) & crc_sig_inv(4) & crc_sig_inv(5) & crc_sig_inv(6) & crc_sig_inv(7);
+  start_int_sig <= rec_valid_sig and (not rx_busy_sig);  -- avoid continuing to early after FTU answer
   
 end Behavioral;
Index: firmware/FTM/ftu_control/FTM_ftu_rs485_interface.vhd
===================================================================
--- firmware/FTM/ftu_control/FTM_ftu_rs485_interface.vhd	(revision 10232)
+++ firmware/FTM/ftu_control/FTM_ftu_rs485_interface.vhd	(revision 10256)
@@ -17,5 +17,5 @@
 
 library ftm_definitions;
--- USE ftm_definitions.ftm_array_types.all;
+USE ftm_definitions.ftm_array_types.all;
 USE ftm_definitions.ftm_constants.all;
 
@@ -34,5 +34,5 @@
     -- FPGA
     rx_data  : OUT    std_logic_vector (7 DOWNTO 0);
-    --rx_busy  : OUT    std_logic  := '0';
+    rx_busy  : OUT    std_logic  := '0';
     rx_valid : OUT    std_logic  := '0';
     tx_data  : IN     std_logic_vector (7 DOWNTO 0);
@@ -122,5 +122,5 @@
   rx_en <= flow_ctrl;
   rx_data <= rx_sr;
-  --rx_busy <= '1' when (rx_bitcnt < 11) else '0';
+  rx_busy <= '1' when (rx_bitcnt < 11) else '0';
 
 END ARCHITECTURE beha;
