Index: firmware/FTM/FTM_central_control.vhd =================================================================== --- firmware/FTM/FTM_central_control.vhd (revision 10250) +++ firmware/FTM/FTM_central_control.vhd (revision 10256) @@ -35,4 +35,5 @@ port( clk : IN std_logic; + clk_scaler : IN std_logic; new_config : IN std_logic; config_started : OUT std_logic := '0'; @@ -49,5 +50,15 @@ ping_ftu_start_ftu : OUT std_logic := '0'; ping_ftu_started_ftu : IN std_logic; - ping_ftu_ready_ftu : IN std_logic + ping_ftu_ready_ftu : IN std_logic; + rates_ftu : OUT std_logic := '0'; + rates_started_ftu : IN std_logic; + rates_ready_ftu : IN std_logic; + prescaling_FTU01 : IN std_logic_vector(7 downto 0); + dd_send : OUT std_logic := '0'; + dd_send_ack : IN std_logic; + dd_send_ready : IN std_logic; + config_start_cc : out std_logic := '0'; + config_started_cc : in std_logic; + config_ready_cc : in std_logic ); end FTM_central_control; @@ -55,12 +66,19 @@ architecture Behavioral of FTM_central_control is - type state_central_proc_type is (CP_INIT, CP_CONFIG_START, CP_CONFIG, CP_CONFIG_01, - CP_CONFIG_FTU, CP_CONFIG_FTU_01, - CP_IDLE, CP_PING); + signal reset_scaler_sig : std_logic := '0'; + signal scaler_counts_sig : integer := 0; + signal scaler_period_sig : integer range 0 to 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER) := 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER); + + type state_central_proc_type is (CP_INIT, + CP_CONFIG_START, CP_CONFIG, CP_CONFIG_01, + CP_CONFIG_CC, CP_CONFIG_CC_01, + CP_CONFIG_FTU, CP_CONFIG_FTU_01, CP_CONFIG_SCALER, + CP_IDLE, CP_PING, CP_READ_RATES, CP_READ_RATES_01, + CP_SEND_START, CP_SEND_END); signal state_central_proc : state_central_proc_type := CP_INIT; begin - central_proc : process (clk) + central_proc : process (clk, prescaling_FTU01) begin if rising_edge (clk) then @@ -71,4 +89,5 @@ when CP_CONFIG_START => + reset_scaler_sig <= '1'; if (config_started_ack = '1') then config_started <= '0'; @@ -77,4 +96,5 @@ when CP_CONFIG => + reset_scaler_sig <= '1'; config_start_eth <= '1'; if (config_started_eth = '1') then @@ -85,7 +105,21 @@ when CP_CONFIG_01 => if (config_ready_eth = '1') then + state_central_proc <= CP_CONFIG_CC; + --state_central_proc <= CP_CONFIG_SCALER; + --state_central_proc <= CP_IDLE; + end if; + + when CP_CONFIG_CC => + config_start_cc <= '1'; + if (config_started_cc = '1') then + config_start_cc <= '0'; + state_central_proc <= CP_CONFIG_CC_01; + end if; + + when CP_CONFIG_CC_01 => + if (config_ready_cc = '1') then state_central_proc <= CP_CONFIG_FTU; end if; - + when CP_CONFIG_FTU => config_start_ftu <= '1'; @@ -97,13 +131,23 @@ when CP_CONFIG_FTU_01 => if (config_ready_ftu = '1') then - state_central_proc <= CP_IDLE; - end if; + state_central_proc <= CP_CONFIG_SCALER; + end if; + + when CP_CONFIG_SCALER => + --if ((conv_integer(unsigned(prescaling_FTU01))) mod 2 = 0) then + --scaler_period_sig <= ((((conv_integer(unsigned(prescaling_FTU01)) / 2)) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER)) + (LOW_FREQUENCY / (2 * SCALER_FREQ_DIVIDER))); + --else + --scaler_period_sig <= (((conv_integer(unsigned(prescaling_FTU01)) - 1) / 2) + 1) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER); + --end if; + reset_scaler_sig <= '1'; + state_central_proc <= CP_IDLE; when CP_IDLE => + reset_scaler_sig <= '0'; if (new_config = '1') then config_started <= '1'; state_central_proc <= CP_CONFIG_START; - elsif (ping_ftu_start = '1') then + --else ping_ftu_start_ftu <= '1'; if (ping_ftu_started_ftu = '1') then @@ -112,6 +156,9 @@ ping_ftu_ready <= '0'; state_central_proc <= CP_PING; - end if; - + end if; + --elsif (scaler_counts_sig = scaler_period_sig) then + -- reset_scaler_sig <= '1'; + -- rates_ftu <= '1'; + -- state_central_proc <= CP_READ_RATES; end if; @@ -125,7 +172,55 @@ end if; + when CP_READ_RATES => + reset_scaler_sig <= '0'; + if (rates_started_ftu = '1') then + rates_ftu <= '0'; + state_central_proc <= CP_READ_RATES_01; + end if; + + when CP_READ_RATES_01 => + if (rates_ready_ftu = '1') then + state_central_proc <= CP_SEND_START; + end if; + + when CP_SEND_START => + dd_send <= '1'; + if (dd_send_ack = '1') then + dd_send <= '0'; + state_central_proc <= CP_SEND_END; + end if; + + when CP_SEND_END => + if (dd_send_ready = '1') then + state_central_proc <= CP_IDLE; + end if; + end case; end if; end process central_proc; + scaler_process: process(reset_scaler_sig, clk_scaler) + begin + if reset_scaler_sig = '1' then + scaler_counts_sig <= 0; + elsif rising_edge(clk_scaler) then + if (scaler_counts_sig < scaler_period_sig) then + scaler_counts_sig <= scaler_counts_sig + 1; + else + scaler_counts_sig <= scaler_counts_sig; + end if; + end if; + end process scaler_process; + + process(reset_scaler_sig, prescaling_FTU01) + begin + if rising_edge(reset_scaler_sig) then + if ((conv_integer(unsigned(prescaling_FTU01))) mod 2 = 0) then + scaler_period_sig <= ((((conv_integer(unsigned(prescaling_FTU01)) / 2)) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER)) + (LOW_FREQUENCY / (2 * SCALER_FREQ_DIVIDER))); + else + scaler_period_sig <= (((conv_integer(unsigned(prescaling_FTU01)) - 1) / 2) + 1) * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER); + end if; + end if; + end process; + end Behavioral; Index: firmware/FTM/FTM_top.vhd =================================================================== --- firmware/FTM/FTM_top.vhd (revision 10250) +++ firmware/FTM/FTM_top.vhd (revision 10256) @@ -117,10 +117,10 @@ -- on IO-Bank 3 ------------------------------------------------------------------------------- - -- CLK_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface serial clock - -- LE_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface latch enable - -- DATA_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface data + CLK_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface serial clock + LE_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface latch enable + DATA_Clk_Cond : out STD_LOGIC; -- MICROWIRE interface data - -- SYNC_Clk_Cond : out STD_LOGIC; -- global clock synchronization - -- LD_Clk_Cond : in STD_LOGIC; -- lock detect, should be checked for + SYNC_Clk_Cond : out STD_LOGIC; -- global clock synchronization + LD_Clk_Cond : in STD_LOGIC; -- lock detect, should be checked for @@ -142,5 +142,5 @@ Bus1_RxD_3 : in STD_LOGIC; -- crate 3 - Bus1_TxD_3 : out STD_LOGIC + Bus1_TxD_3 : out STD_LOGIC; @@ -220,5 +220,5 @@ -- TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker -- TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2 - -- TIM_Sel : out STD_LOGIC; -- Time Marker selector on IO-Bank 2 + TIM_Sel : out STD_LOGIC -- Time Marker selector on IO-Bank 2 -- CLD_FPGA : in STD_LOGIC; -- DRS-Clock feedback into FPGA @@ -321,13 +321,23 @@ signal ping_ftu_started1_sig : std_logic := '0'; signal ping_ftu_ready1_sig : std_logic := '0'; - signal dd_addr_ftu_sig : std_logic_vector(11 DOWNTO 0); - signal dd_busy_sig : std_logic; - signal dd_data_in_ftu_sig : std_logic_vector(15 DOWNTO 0); - signal dd_ready_sig : std_logic; - signal dd_started_ftu_sig : std_logic := '0'; - signal dd_write_ftu_sig : std_logic; signal coin_win_c_sig : std_logic_vector(15 DOWNTO 0) := (others => '0'); signal coin_win_p_sig : std_logic_vector(15 DOWNTO 0) := (others => '0'); - + --new or changed stuff + signal dd_data_sig : std_logic_vector(15 DOWNTO 0) := (others => '0'); + signal dd_addr_sig : std_logic_vector(11 DOWNTO 0) := (others => '0'); + signal dd_block_start_sig : std_logic := '0'; + signal dd_block_start_ack_ftu_sig : std_logic := '0'; + signal dd_block_ready_sig : std_logic := '0'; + signal dd_busy_sig : std_logic; + signal dd_write_sig : std_logic := '0'; + signal dd_started_ftu_sig : std_logic := '0'; + signal dd_ready_sig : std_logic; + signal dd_send_sig : std_logic := '1'; + signal dd_send_ack_sig : std_logic := '1'; + signal dd_send_ready_sig : std_logic := '1'; + signal config_start_cc_sig : std_logic := '0'; + signal config_started_cc_sig : std_logic := '0'; + signal config_ready_cc_sig : std_logic := '0'; + signal clk_buf_sig : std_logic; signal clk_1M_sig : STD_LOGIC; -- generated from 50M clock by divider @@ -352,23 +362,58 @@ ); end component; + + component Clock_cond_interface is + port( + clk : IN STD_LOGIC; + CLK_Clk_Cond : out STD_LOGIC; + LE_Clk_Cond : out STD_LOGIC; + DATA_Clk_Cond : out STD_LOGIC; + SYNC_Clk_Cond : out STD_LOGIC; + LD_Clk_Cond : in STD_LOGIC; + TIM_Sel : out STD_LOGIC; + cc_R0 : in std_logic_vector (31 downto 0) := (others => '0'); + cc_R1 : in std_logic_vector (31 downto 0) := (others => '0'); + cc_R8 : in std_logic_vector (31 downto 0) := (others => '0'); + cc_R9 : in std_logic_vector (31 downto 0) := (others => '0'); + cc_R11 : in std_logic_vector (31 downto 0) := (others => '0'); + cc_R13 : in std_logic_vector (31 downto 0) := (others => '0'); + cc_R14 : in std_logic_vector (31 downto 0) := (others => '0'); + cc_R15 : in std_logic_vector (31 downto 0) := (others => '0'); + start_config : in STD_LOGIC; + config_started : out STD_LOGIC; + config_done : out STD_LOGIC; + timemarker_select: in STD_LOGIC + ); + end component; component FTM_central_control port( - clk : IN std_logic ; - new_config : IN std_logic ; + clk : IN std_logic; + clk_scaler : IN std_logic; + new_config : IN std_logic; config_started : OUT std_logic := '0'; - config_started_ack : IN std_logic ; + config_started_ack : IN std_logic; config_start_eth : OUT std_logic := '0'; - config_started_eth : IN std_logic ; - config_ready_eth : IN std_logic ; + config_started_eth : IN std_logic; + config_ready_eth : IN std_logic; config_start_ftu : OUT std_logic := '0'; - config_started_ftu : IN std_logic ; - config_ready_ftu : IN std_logic ; - ping_ftu_start : IN std_logic ; + config_started_ftu : IN std_logic; + config_ready_ftu : IN std_logic; + ping_ftu_start : IN std_logic; ping_ftu_started : OUT std_logic := '0'; ping_ftu_ready : OUT std_logic := '0'; ping_ftu_start_ftu : OUT std_logic := '0'; - ping_ftu_started_ftu : IN std_logic ; - ping_ftu_ready_ftu : IN std_logic + ping_ftu_started_ftu : IN std_logic; + ping_ftu_ready_ftu : IN std_logic; + rates_ftu : OUT std_logic := '0'; + rates_started_ftu : IN std_logic; + rates_ready_ftu : IN std_logic; + prescaling_FTU01 : IN std_logic_vector(7 downto 0); + dd_send : OUT std_logic := '0'; + dd_send_ack : IN std_logic; + dd_send_ready : IN std_logic; + config_start_cc : out std_logic := '0'; + config_started_cc : in std_logic; + config_ready_cc : in std_logic ); end component; @@ -484,5 +529,12 @@ dd_ready : OUT std_logic ; coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); - coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0') + coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + --new stuff + dd_block_ready_ftu : IN std_logic; + dd_block_start_ack_ftu : OUT std_logic := '0'; + dd_block_start_ftu : IN std_logic; + dd_send : IN std_logic; + dd_send_ack : OUT std_logic := '1'; + dd_send_ready : OUT std_logic := '1' ); end component; @@ -514,8 +566,32 @@ ready => clk_ready_sig ); - + + Inst_Clock_cond_interface : Clock_cond_interface + port map( + clk => clk_50M_sig, + CLK_Clk_Cond => CLK_Clk_Cond, + LE_Clk_Cond => LE_Clk_Cond, + DATA_Clk_Cond => DATA_Clk_Cond, + SYNC_Clk_Cond => SYNC_Clk_Cond, + LD_Clk_Cond => LD_Clk_Cond, + TIM_Sel => TIM_Sel, + cc_R0 => cc_R0_sig, + cc_R1 => cc_R1_sig, + cc_R8 => cc_R8_sig, + cc_R9 => cc_R9_sig, + cc_R11 => cc_R11_sig, + cc_R13 => cc_R13_sig, + cc_R14 => cc_R14_sig, + cc_R15 => cc_R15_sig, + start_config => config_start_cc_sig, + config_started => config_started_cc_sig, + config_done => config_ready_cc_sig, + timemarker_select => general_settings_sig(0) + ); + Inst_FTM_central_control : FTM_central_control port map( clk => clk_50M_sig, + clk_scaler => clk_1M_sig, new_config => new_config_sig, config_started => config_started_sig, @@ -532,5 +608,15 @@ ping_ftu_start_ftu => ping_ftu_start_ftu_sig, ping_ftu_started_ftu => ping_ftu_started1_sig, - ping_ftu_ready_ftu => ping_ftu_ready1_sig + ping_ftu_ready_ftu => ping_ftu_ready1_sig, + rates_ftu => rates_ftu_start_sig, + rates_started_ftu => rates_ftu_started_sig, + rates_ready_ftu => rates_ftu_ready_sig, + prescaling_FTU01 => "00010011", + dd_send => dd_send_sig, + dd_send_ack => dd_send_ack_sig, + dd_send_ready => dd_send_ready_sig, + config_start_cc => config_start_cc_sig, + config_started_cc => config_started_cc_sig, + config_ready_cc => config_ready_cc_sig ); @@ -570,7 +656,7 @@ dynamic_RAM_started => dd_started_ftu_sig, dynamic_RAM_ready => dd_ready_sig, - data_dynamic_RAM => dd_data_in_ftu_sig, - write_dynamic_RAM => dd_write_ftu_sig, - addr_dynamic_RAM => dd_addr_ftu_sig, + data_dynamic_RAM => dd_data_sig, + write_dynamic_RAM => dd_write_sig, + addr_dynamic_RAM => dd_addr_sig, FTUlist_RAM_busy => fl_busy_sig, FTUlist_RAM_started => fl_started_ftu_sig, @@ -637,12 +723,19 @@ ping_ftu_started => ping_ftu_started_sig, ping_ftu_ready => ping_ftu_ready_sig, - dd_write_ftu => dd_write_ftu_sig, + dd_write_ftu => dd_write_sig, dd_started_ftu => dd_started_ftu_sig, - dd_data_in_ftu => dd_data_in_ftu_sig, - dd_addr_ftu => dd_addr_ftu_sig, + dd_data_in_ftu => dd_data_sig, + dd_addr_ftu => dd_addr_sig, dd_busy => dd_busy_sig, dd_ready => dd_ready_sig, coin_win_c => coin_win_c_sig, - coin_win_p => coin_win_p_sig + coin_win_p => coin_win_p_sig, + --new stuff + dd_block_ready_ftu => dd_block_ready_sig, + dd_block_start_ack_ftu => dd_block_start_ack_ftu_sig, + dd_block_start_ftu => dd_block_start_sig, + dd_send => dd_send_sig, + dd_send_ack => dd_send_ack_sig, + dd_send_ready => dd_send_ready_sig ); @@ -654,4 +747,2 @@ - - Index: firmware/FTM/FTM_top_tb.vhd =================================================================== --- firmware/FTM/FTM_top_tb.vhd (revision 10250) +++ firmware/FTM/FTM_top_tb.vhd (revision 10256) @@ -347,5 +347,6 @@ -- Clock period definitions - constant clk_period : TIME := 25 ns; -- 40 MHZ oscillator U47 + constant clk_period : TIME := 25 ns; -- 40 MHZ oscillator U47 + constant baud_rate_period : TIME := 4 us; -- 250 kHz baud rate begin @@ -444,4 +445,104 @@ wait for clk_period/2; end process clk_proc; - + + -- Stimulus process for RS485 of crate 0 + rs485_0_proc: process + + procedure assign_rs485_0 (data: std_logic_vector(7 downto 0)) is + begin + Bus1_RxD_0_sig <= '0'; --start bit + wait for baud_rate_period; + Bus1_RxD_0_sig <= data(0); --bit 0 + wait for baud_rate_period; + Bus1_RxD_0_sig <= data(1); --bit 1 + wait for baud_rate_period; + Bus1_RxD_0_sig <= data(2); --bit 2 + wait for baud_rate_period; + Bus1_RxD_0_sig <= data(3); --bit 3 + wait for baud_rate_period; + Bus1_RxD_0_sig <= data(4); --bit 4 + wait for baud_rate_period; + Bus1_RxD_0_sig <= data(5); --bit 5 + wait for baud_rate_period; + Bus1_RxD_0_sig <= data(6); --bit 6 + wait for baud_rate_period; + Bus1_RxD_0_sig <= data(7); --bit 7 + wait for baud_rate_period; + Bus1_RxD_0_sig <= '1'; --stop bit + wait for baud_rate_period; + Bus1_RxD_0_sig <= '1'; --stop bit + wait for baud_rate_period; + end assign_rs485_0; + + begin + --------------------------------------------------------------------------- + -- time of FTU answer + --------------------------------------------------------------------------- + wait for 2ms; + --------------------------------------------------------------------------- + -- data package of FTU answer (28 byte) + --------------------------------------------------------------------------- + assign_rs485_0(X"40"); --start delimiter + wait for 0us; + assign_rs485_0(X"C0"); --FTM address + wait for 0ns; + assign_rs485_0(X"00"); --FTU address + wait for 0ns; + assign_rs485_0(X"01"); --FTM firmware ID + wait for 0ns; + assign_rs485_0(X"05"); --instruction + wait for 0us; + assign_rs485_0(X"00"); --data byte 01 + wait for 0ns; + assign_rs485_0(X"00"); --data byte 02 + wait for 0ns; + assign_rs485_0(X"00"); --data byte 03 + wait for 0ns; + assign_rs485_0(X"00"); --data byte 04 + wait for 0ns; + assign_rs485_0(X"00"); --data byte 05 + wait for 0ns; + assign_rs485_0(X"00"); --data byte 06 + wait for 0ns; + assign_rs485_0(X"00"); --data byte 07 + wait for 0ns; + assign_rs485_0(X"00"); --data byte 08 + wait for 0ns; + assign_rs485_0(X"00"); --data byte 09 + wait for 0ns; + assign_rs485_0(X"00"); --data byte 10 + wait for 0ns; + assign_rs485_0(X"00"); --data byte 11 + wait for 0ns; + assign_rs485_0(X"00"); --data byte 12 + wait for 0ns; + assign_rs485_0(X"00"); --data byte 13 + wait for 0ns; + assign_rs485_0(X"00"); --data byte 14 + wait for 0ns; + assign_rs485_0(X"00"); --data byte 15 + wait for 0ns; + assign_rs485_0(X"00"); --data byte 16 + wait for 0ns; + assign_rs485_0(X"00"); --data byte 17 + wait for 0ns; + assign_rs485_0(X"00"); --data byte 18 + wait for 0ns; + assign_rs485_0(X"00"); --data byte 19 + wait for 0ns; + assign_rs485_0(X"00"); --data byte 20 + wait for 0ns; + assign_rs485_0(X"00"); --data byte 21 + wait for 0ns; + assign_rs485_0(X"00"); --CRC error counter (not used) + wait for 0ns; + --assign_rs485_0(X"9E"); --check sum for rates + assign_rs485_0(X"A5"); --check sum for ping + --------------------------------------------------------------------------- + -- don't forget final wait! + --------------------------------------------------------------------------- + wait; + + end process rs485_0_proc; + end; Index: firmware/FTM/ethernet/cram_control_beha.vhd =================================================================== --- firmware/FTM/ethernet/cram_control_beha.vhd (revision 10250) +++ firmware/FTM/ethernet/cram_control_beha.vhd (revision 10256) @@ -8,4 +8,7 @@ -- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) -- +-- updated by Q. Weitzel, March 14, 2011 +-- + LIBRARY ieee; USE ieee.std_logic_1164.all; @@ -20,57 +23,53 @@ ENTITY cram_control IS - PORT( - clk : IN std_logic; - led : OUT std_logic_vector (7 downto 0) := X"00"; - cram_data_in : OUT std_logic_vector (15 downto 0); - cram_data_out : IN std_logic_vector (15 downto 0); - cram_addr_in, cram_addr_out : OUT std_logic_vector (11 downto 0); - cram_we : OUT std_logic_vector (0 downto 0) := "0"; - sd_write, sd_read, sd_read_ftu : IN std_logic; - sd_busy : OUT std_logic := '1'; - sd_started, sd_started_ftu : OUT std_logic := '0'; - sd_ready : OUT std_logic := '0'; - sd_data_in : IN std_logic_vector (15 downto 0); - sd_data_out, sd_data_out_ftu : OUT std_logic_vector (15 downto 0) := (others => '0'); - sd_addr, sd_addr_ftu : IN std_logic_vector (11 downto 0); + PORT( + clk : IN std_logic; + led : OUT std_logic_vector (7 downto 0) := X"00"; + cram_data_in : OUT std_logic_vector (15 downto 0) := (others => '0'); + cram_data_out : IN std_logic_vector (15 downto 0); + cram_addr_in, cram_addr_out : OUT std_logic_vector (11 downto 0) := (others => '0'); + cram_we : OUT std_logic_vector (0 downto 0) := "0"; + sd_write, sd_read, sd_read_ftu : IN std_logic; + sd_busy : OUT std_logic := '1'; + sd_started, sd_started_ftu : OUT std_logic := '0'; + sd_ready : OUT std_logic := '0'; + sd_data_in : IN std_logic_vector (15 downto 0); + sd_data_out, sd_data_out_ftu : OUT std_logic_vector (15 downto 0) := (others => '0'); + sd_addr, sd_addr_ftu : IN std_logic_vector (11 downto 0); - config_start_cc : IN std_logic; - config_started_cc : OUT std_logic := '0'; - config_ready_cc : OUT std_logic := '0'; + config_start_cc : IN std_logic; + config_started_cc : OUT std_logic := '0'; + config_ready_cc : OUT std_logic := '0'; - -- data from config ram - general_settings : OUT std_logic_vector (15 downto 0) := (others => '0'); - lp_pt_freq : OUT std_logic_vector (15 downto 0) := (others => '0'); - lp_pt_ratio : OUT std_logic_vector (15 downto 0) := (others => '0'); - lp1_amplitude : OUT std_logic_vector (15 downto 0) := (others => '0'); - lp2_amplitude : OUT std_logic_vector (15 downto 0) := (others => '0'); - lp1_delay : OUT std_logic_vector (15 downto 0) := (others => '0'); - lp2_delay : OUT std_logic_vector (15 downto 0) := (others => '0'); - coin_n_p : OUT std_logic_vector (15 downto 0) := (others => '0'); - coin_n_c : OUT std_logic_vector (15 downto 0) := (others => '0'); - trigger_delay : OUT std_logic_vector (15 downto 0) := (others => '0'); - timemarker_delay : OUT std_logic_vector (15 downto 0) := (others => '0'); - dead_time : OUT std_logic_vector (15 downto 0) := (others => '0'); - cc_R0 : OUT std_logic_vector (31 downto 0) := (others => '0'); - cc_R1 : OUT std_logic_vector (31 downto 0) := (others => '0'); - cc_R8 : OUT std_logic_vector (31 downto 0) := (others => '0'); - cc_R9 : OUT std_logic_vector (31 downto 0) := (others => '0'); - cc_R11 : OUT std_logic_vector (31 downto 0) := (others => '0'); - cc_R13 : OUT std_logic_vector (31 downto 0) := (others => '0'); - cc_R14 : OUT std_logic_vector (31 downto 0) := (others => '0'); - cc_R15 : OUT std_logic_vector (31 downto 0) := (others => '0'); - coin_win_p : OUT std_logic_vector (15 downto 0) := (others => '0'); - coin_win_c : OUT std_logic_vector (15 downto 0) := (others => '0'); - ftu_active_cr0 : OUT std_logic_vector (15 downto 0) := (others => '0'); - ftu_active_cr1 : OUT std_logic_vector (15 downto 0) := (others => '0'); - ftu_active_cr2 : OUT std_logic_vector (15 downto 0) := (others => '0'); - ftu_active_cr3 : OUT std_logic_vector (15 downto 0) := (others => '0') - ); - --- Declarations - + -- data from config ram + general_settings : OUT std_logic_vector (15 downto 0) := (others => '0'); + lp_pt_freq : OUT std_logic_vector (15 downto 0) := (others => '0'); + lp_pt_ratio : OUT std_logic_vector (15 downto 0) := (others => '0'); + lp1_amplitude : OUT std_logic_vector (15 downto 0) := (others => '0'); + lp2_amplitude : OUT std_logic_vector (15 downto 0) := (others => '0'); + lp1_delay : OUT std_logic_vector (15 downto 0) := (others => '0'); + lp2_delay : OUT std_logic_vector (15 downto 0) := (others => '0'); + coin_n_p : OUT std_logic_vector (15 downto 0) := (others => '0'); + coin_n_c : OUT std_logic_vector (15 downto 0) := (others => '0'); + trigger_delay : OUT std_logic_vector (15 downto 0) := (others => '0'); + timemarker_delay : OUT std_logic_vector (15 downto 0) := (others => '0'); + dead_time : OUT std_logic_vector (15 downto 0) := (others => '0'); + cc_R0 : OUT std_logic_vector (31 downto 0) := (others => '0'); + cc_R1 : OUT std_logic_vector (31 downto 0) := (others => '0'); + cc_R8 : OUT std_logic_vector (31 downto 0) := (others => '0'); + cc_R9 : OUT std_logic_vector (31 downto 0) := (others => '0'); + cc_R11 : OUT std_logic_vector (31 downto 0) := (others => '0'); + cc_R13 : OUT std_logic_vector (31 downto 0) := (others => '0'); + cc_R14 : OUT std_logic_vector (31 downto 0) := (others => '0'); + cc_R15 : OUT std_logic_vector (31 downto 0) := (others => '0'); + coin_win_p : OUT std_logic_vector (15 downto 0) := (others => '0'); + coin_win_c : OUT std_logic_vector (15 downto 0) := (others => '0'); + ftu_active_cr0 : OUT std_logic_vector (15 downto 0) := (others => '0'); + ftu_active_cr1 : OUT std_logic_vector (15 downto 0) := (others => '0'); + ftu_active_cr2 : OUT std_logic_vector (15 downto 0) := (others => '0'); + ftu_active_cr3 : OUT std_logic_vector (15 downto 0) := (others => '0') + ); END cram_control ; --- ARCHITECTURE beha OF cram_control IS @@ -143,5 +142,6 @@ -- local_sd_data <= conv_std_logic_vector (ftu_active_cnt, 16); -- for FTM-Board - local_sd_data <= sd_block_activeFTUlist_default_array (ftu_active_cnt); + local_sd_data <= sd_block_default_ftu_active_list (ftu_active_cnt); + -- -- ftu_active_cnt <= ftu_active_cnt + 1; next_state <= CR_INIT_03; @@ -322,8 +322,9 @@ when CR_WRITE_END => cram_we <= "0"; - sd_started <= '0'; - sd_ready <= '1'; - state_cram_proc <= next_state; - + if (sd_write = '0') then + sd_started <= '0'; + sd_ready <= '1'; + state_cram_proc <= next_state; + end if; -- -- Index: firmware/FTM/ethernet/dd_write_general_modul_beha.vhd =================================================================== --- firmware/FTM/ethernet/dd_write_general_modul_beha.vhd (revision 10256) +++ firmware/FTM/ethernet/dd_write_general_modul_beha.vhd (revision 10256) @@ -0,0 +1,150 @@ +-- +-- VHDL Architecture FACT_FTM_lib.dd_write_general_modul.beha +-- +-- Created: +-- by - kai.UNKNOWN (E5PCXX) +-- at - 11:27:33 02.03.2011 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE IEEE.STD_LOGIC_UNSIGNED.all; +-- LIBRARY FACT_FTM_lib; +-- USE FACT_FTM_lib.ftm_array_types.all; +-- USE FACT_FTM_lib.ftm_constants.all; +library ftm_definitions; +USE ftm_definitions.ftm_array_types.all; +USE ftm_definitions.ftm_constants.all; + +ENTITY dd_write_general_modul IS +PORT( + clk : IN std_logic; + dd_write_general : IN std_logic; + dd_write_general_started : OUT std_logic := '0'; + dd_write_general_ready : OUT std_logic := '0'; + dd_busy : IN std_logic; + dd_write : OUT std_logic := '0'; + dd_started : IN std_logic; + dd_ready : IN std_logic; + dd_addr : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); + dd_data : OUT std_logic_vector (15 DOWNTO 0) := (others => '0') + ); +END ENTITY dd_write_general_modul; + +-- +ARCHITECTURE beha OF dd_write_general_modul IS + + type state_write_general_proc_type is (WGP_INIT, WGP_CONFIG, WGP_IDLE, WGP_WRITE_COUNTER_01, WGP_WRITE_COUNTER_02, WGP_WRITE_COUNTER_03, + WGP_WRITE_TEMP_01, WGP_WRITE_TEMP_02, WGP_WRITE_TEMP_03, WGP_WRITE_TEMP_04, WGP_WRITE_READY, WRITE_TO_DD_ADDR); + type state_write_dd_type is (WRITE_DD_START, WRITE_DD_WAIT, WRITE_DD_END); + + signal state_write_general_proc : state_write_general_proc_type := WGP_INIT; + signal next_state_dd : state_write_general_proc_type := WGP_INIT; + signal state_write_dd : state_write_dd_type := WRITE_DD_START; + + signal local_dd_addr : std_logic_vector (11 DOWNTO 0) := (others => '0'); + signal local_dd_data : std_logic_vector (15 DOWNTO 0) := (others => '0'); + + signal on_time_counter : std_logic_vector (47 DOWNTO 0) := X"333322221111"; + signal temp_sensor_0 : std_logic_vector (15 DOWNTO 0) := X"00FF"; + signal temp_sensor_1 : std_logic_vector (15 DOWNTO 0) := X"11FF"; + signal temp_sensor_2 : std_logic_vector (15 DOWNTO 0) := X"22FF"; + signal temp_sensor_3 : std_logic_vector (15 DOWNTO 0) := X"33FF"; + +BEGIN + write_general_proc : process (clk) + begin + if rising_edge (clk) then + case state_write_general_proc is + + when WGP_INIT => + state_write_general_proc <= WGP_CONFIG; + + when WGP_CONFIG => + state_write_general_proc <= WGP_IDLE; + + when WGP_IDLE => + if (dd_write_general = '1') then + dd_write_general_started <= '1'; + dd_write_general_ready <= '0'; + state_write_general_proc <= WGP_WRITE_COUNTER_01; + end if; + + when WGP_WRITE_COUNTER_01 => + local_dd_addr <= X"000"; + local_dd_data <= on_time_counter (47 DOWNTO 32); + next_state_dd <= WGP_WRITE_COUNTER_02; + state_write_general_proc <= WRITE_TO_DD_ADDR; + + when WGP_WRITE_COUNTER_02 => + local_dd_addr <= X"001"; + local_dd_data <= on_time_counter (31 DOWNTO 16); + next_state_dd <= WGP_WRITE_COUNTER_03; + state_write_general_proc <= WRITE_TO_DD_ADDR; + + when WGP_WRITE_COUNTER_03 => + local_dd_addr <= X"002"; + local_dd_data <= on_time_counter (15 DOWNTO 0); + next_state_dd <= WGP_WRITE_TEMP_01; + state_write_general_proc <= WRITE_TO_DD_ADDR; + + when WGP_WRITE_TEMP_01 => + local_dd_addr <= X"003"; + local_dd_data <= temp_sensor_0; + next_state_dd <= WGP_WRITE_TEMP_02; + state_write_general_proc <= WRITE_TO_DD_ADDR; + + when WGP_WRITE_TEMP_02 => + local_dd_addr <= X"004"; + local_dd_data <= temp_sensor_1; + next_state_dd <= WGP_WRITE_TEMP_03; + state_write_general_proc <= WRITE_TO_DD_ADDR; + + when WGP_WRITE_TEMP_03 => + local_dd_addr <= X"005"; + local_dd_data <= temp_sensor_2; + next_state_dd <= WGP_WRITE_TEMP_04; + state_write_general_proc <= WRITE_TO_DD_ADDR; + + when WGP_WRITE_TEMP_04 => + local_dd_addr <= X"006"; + local_dd_data <= temp_sensor_3; + next_state_dd <= WGP_WRITE_READY; + state_write_general_proc <= WRITE_TO_DD_ADDR; + + when WGP_WRITE_READY => + if (dd_write_general = '0') then + dd_write_general_ready <= '1'; + state_write_general_proc <= WGP_IDLE; + end if; + + -- write to dynamic data block + when WRITE_TO_DD_ADDR => + case state_write_dd is + when WRITE_DD_START => + if (dd_busy = '0') then + dd_addr <= local_dd_addr; + dd_data <= local_dd_data; + dd_write <= '1'; + state_write_dd <= WRITE_DD_WAIT; + end if; + when WRITE_DD_WAIT => + if (dd_started = '1') then + dd_write <= '0'; + state_write_dd <= WRITE_DD_END; + end if; + when WRITE_DD_END => + if (dd_ready = '1') then + state_write_dd <= WRITE_DD_START; + state_write_general_proc <= next_state_dd; + end if; + end case; + + end case; + end if; + end process write_general_proc; + +END ARCHITECTURE beha; Index: firmware/FTM/ethernet/dram_control_beha.vhd =================================================================== --- firmware/FTM/ethernet/dram_control_beha.vhd (revision 10250) +++ firmware/FTM/ethernet/dram_control_beha.vhd (revision 10256) @@ -21,28 +21,32 @@ ENTITY dram_control IS - PORT( - clk : IN std_logic; - dram_data_in : OUT std_logic_vector (15 DOWNTO 0); - dram_data_out : IN std_logic_vector (15 DOWNTO 0); - dram_addr_in : OUT std_logic_vector (11 DOWNTO 0); - dram_addr_out : OUT std_logic_vector (11 DOWNTO 0); - dram_we : OUT std_logic_vector (0 DOWNTO 0) := "0"; - dd_block_start : IN std_logic; - dd_block_start_ftu : IN std_logic; - dd_block_start_ack : OUT std_logic := '0'; - dd_block_start_ack_ftu : OUT std_logic := '0'; - dd_block_ready : IN std_logic; - dd_block_ready_ftu : IN std_logic; - dd_read : IN std_logic; - dd_write_ftu : IN std_logic; - dd_busy : OUT std_logic := '1'; - dd_started : OUT std_logic := '0'; - dd_started_ftu : OUT std_logic := '0'; - dd_ready : OUT std_logic := '0'; - dd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); - dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0); - dd_addr : IN std_logic_vector (11 DOWNTO 0); - dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0) - ); + PORT( + clk : IN std_logic; + dram_data_in : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + dram_data_out : IN std_logic_vector (15 DOWNTO 0); + dram_addr_in : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); + dram_addr_out : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); + dram_we : OUT std_logic_vector (0 DOWNTO 0) := "0"; + dd_block_start : IN std_logic; + dd_block_start_ftu : IN std_logic; + dd_block_start_ack : OUT std_logic := '0'; + dd_block_start_ack_ftu : OUT std_logic := '0'; + dd_block_ready : IN std_logic; + dd_block_ready_ftu : IN std_logic; + dd_read : IN std_logic; + dd_write_ftu : IN std_logic; + dd_write_general : IN std_logic; + dd_busy : OUT std_logic := '1'; + dd_started : OUT std_logic := '0'; + dd_started_ftu : OUT std_logic := '0'; + dd_started_general : OUT std_logic := '0'; + dd_ready : OUT std_logic := '0'; + dd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0); + dd_data_in_general : IN std_logic_vector (15 DOWNTO 0); + dd_addr : IN std_logic_vector (11 DOWNTO 0); + dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0); + dd_addr_general : IN std_logic_vector (11 DOWNTO 0) + ); -- Declarations @@ -53,5 +57,5 @@ ARCHITECTURE beha OF dram_control IS - type state_dram_proc_type is (DR_INIT, DR_CONFIG, DR_IDLE, DR_DOUT_WIZ_START, DR_DOUT_WIZ_END, DR_WRITE_START, DR_WRITE_END, + type state_dram_proc_type is (DR_INIT, DR_CONFIG, DR_IDLE, DR_DOUT_WIZ_START, DR_DOUT_WIZ_END, DR_WRITE_START, DR_WRITE_END_FTU, DR_WRITE_END_GENERAL, DR_READ_START, DR_READ_WAIT, DR_READ_END); type state_dd_block_proc_type is (DD_BLOCK_IDLE, DD_BLOCK_WAIT_WIZ, DD_BLOCK_WAIT_FTU); @@ -60,4 +64,5 @@ signal state_dram_proc : state_dram_proc_type := DR_INIT; signal next_state : state_dram_proc_type := DR_IDLE; + signal write_end_state : state_dram_proc_type := DR_WRITE_END_FTU; signal state_dd_block_proc : state_dd_block_proc_type := DD_BLOCK_IDLE; @@ -70,30 +75,30 @@ dd_block_proc : process (clk) begin - if rising_edge (clk) then - case state_dd_block_proc is - - when DD_BLOCK_IDLE => - if (dd_block_start = '1') then - dd_block_start_ack <= '1'; - state_dd_block_proc <= DD_BLOCK_WAIT_WIZ; - elsif (dd_block_start_ftu = '1') then - dd_block_start_ack_ftu <= '1'; - state_dd_block_proc <= DD_BLOCK_WAIT_FTU; - end if; - - when DD_BLOCK_WAIT_WIZ => - if (dd_block_ready = '1') then - dd_block_start_ack <= '0'; - state_dd_block_proc <= DD_BLOCK_IDLE; - end if; - - when DD_BLOCK_WAIT_FTU => - if (dd_block_ready_ftu = '1') then - dd_block_start_ack_ftu <= '0'; - state_dd_block_proc <= DD_BLOCK_IDLE; - end if; - - end case; - end if; + if rising_edge (clk) then + case state_dd_block_proc is + + when DD_BLOCK_IDLE => + if (dd_block_start = '1') then + dd_block_start_ack <= '1'; + state_dd_block_proc <= DD_BLOCK_WAIT_WIZ; + elsif (dd_block_start_ftu = '1') then + dd_block_start_ack_ftu <= '1'; + state_dd_block_proc <= DD_BLOCK_WAIT_FTU; + end if; + + when DD_BLOCK_WAIT_WIZ => + if (dd_block_ready = '1') then + dd_block_start_ack <= '0'; + state_dd_block_proc <= DD_BLOCK_IDLE; + end if; + + when DD_BLOCK_WAIT_FTU => + if (dd_block_ready_ftu = '1') then + dd_block_start_ack_ftu <= '0'; + state_dd_block_proc <= DD_BLOCK_IDLE; + end if; + + end case; + end if; end process dd_block_proc; @@ -127,7 +132,17 @@ local_data <= dd_data_in_ftu; next_state <= DR_IDLE; + write_end_state <= DR_WRITE_END_FTU; state_dram_proc <= DR_WRITE_START; - end if; - + + elsif (dd_write_general = '1') then + dd_busy <= '1'; + dd_started_general <= '1'; + dd_ready <= '0'; + local_addr <= dd_addr_general; + local_data <= dd_data_in_general; + next_state <= DR_IDLE; + write_end_state <= DR_WRITE_END_GENERAL; + state_dram_proc <= DR_WRITE_START; + end if; @@ -150,11 +165,21 @@ dram_data_in <= local_data; dram_we <= "1"; - state_dram_proc <= DR_WRITE_END; - - when DR_WRITE_END => + state_dram_proc <= write_end_state; + + when DR_WRITE_END_FTU => dram_we <= "0"; - dd_started_ftu <= '0'; - dd_ready <= '1'; - state_dram_proc <= next_state; + if (dd_write_ftu = '0') then + dd_started_ftu <= '0'; + dd_ready <= '1'; + state_dram_proc <= next_state; + end if; + + when DR_WRITE_END_GENERAL => + dram_we <= "0"; + if (dd_write_general = '0') then + dd_started_general <= '0'; + dd_ready <= '1'; + state_dram_proc <= next_state; + end if; -- -- Index: firmware/FTM/ethernet/ethernet_modul_beha.vhd =================================================================== --- firmware/FTM/ethernet/ethernet_modul_beha.vhd (revision 10250) +++ firmware/FTM/ethernet/ethernet_modul_beha.vhd (revision 10256) @@ -3,8 +3,9 @@ -- Created: -- by - kai.UNKNOWN (E5PCXX) --- at - 11:17:45 25.02.2011 +-- at - 11:52:19 03.03.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) -- + LIBRARY ieee; USE ieee.std_logic_1164.all; @@ -16,96 +17,78 @@ ENTITY ethernet_modul IS - PORT( - wiz_reset : OUT std_logic := '1'; - wiz_addr : OUT std_logic_vector (9 DOWNTO 0); - wiz_data : INOUT std_logic_vector (15 DOWNTO 0); - wiz_cs : OUT std_logic := '1'; - wiz_wr : OUT std_logic := '1'; - wiz_rd : OUT std_logic := '1'; - wiz_int : IN std_logic; - clk : IN std_logic; - sd_ready : OUT std_logic; - sd_busy : OUT std_logic; - led : OUT std_logic_vector (7 DOWNTO 0); - sd_read_ftu : IN std_logic; - sd_started_ftu : OUT std_logic := '0'; - cc_R0 : OUT std_logic_vector (31 DOWNTO 0); - cc_R1 : OUT std_logic_vector (31 DOWNTO 0); - cc_R11 : OUT std_logic_vector (31 DOWNTO 0); - cc_R13 : OUT std_logic_vector (31 DOWNTO 0); - cc_R14 : OUT std_logic_vector (31 DOWNTO 0); - cc_R15 : OUT std_logic_vector (31 DOWNTO 0); - cc_R8 : OUT std_logic_vector (31 DOWNTO 0); - cc_R9 : OUT std_logic_vector (31 DOWNTO 0); - coin_n_c : OUT std_logic_vector (15 DOWNTO 0); - coin_n_p : OUT std_logic_vector (15 DOWNTO 0); - dead_time : OUT std_logic_vector (15 DOWNTO 0); - -- data from config ram - general_settings : OUT std_logic_vector (15 DOWNTO 0); - lp1_amplitude : OUT std_logic_vector (15 DOWNTO 0); - lp1_delay : OUT std_logic_vector (15 DOWNTO 0); - lp2_amplitude : OUT std_logic_vector (15 DOWNTO 0); - lp2_delay : OUT std_logic_vector (15 DOWNTO 0); - lp_pt_freq : OUT std_logic_vector (15 DOWNTO 0); - lp_pt_ratio : OUT std_logic_vector (15 DOWNTO 0); - timemarker_delay : OUT std_logic_vector (15 DOWNTO 0); - trigger_delay : OUT std_logic_vector (15 DOWNTO 0); - sd_addr_ftu : IN std_logic_vector (11 DOWNTO 0); - sd_data_out_ftu : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); - ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0); - ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0); - ftu_active_cr2 : OUT std_logic_vector (15 DOWNTO 0); - ftu_active_cr3 : OUT std_logic_vector (15 DOWNTO 0); - new_config : OUT std_logic := '0'; - config_started : IN std_logic; - config_start_eth : IN std_logic; - config_started_eth : OUT std_logic := '0'; - config_ready_eth : OUT std_logic := '0'; - config_started_ack : OUT std_logic := '0'; - fl_busy : OUT std_logic; - fl_ready : OUT std_logic; - fl_write_ftu : IN std_logic; - fl_started_ftu : OUT std_logic := '0'; - fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0); - fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0) := (others => '0'); - -- - ping_ftu_start : OUT std_logic := '0'; - ping_ftu_started : IN std_logic; - ping_ftu_ready : IN std_logic; - dd_write_ftu : IN std_logic; - dd_started_ftu : OUT std_logic := '0'; - dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0); - dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0); - dd_busy : OUT std_logic; - dd_ready : OUT std_logic; - coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); - coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0') - ); - --- Declarations - + PORT( + wiz_reset : OUT std_logic := '1'; + wiz_addr : OUT std_logic_vector (9 DOWNTO 0); + wiz_data : INOUT std_logic_vector (15 DOWNTO 0); + wiz_cs : OUT std_logic := '1'; + wiz_wr : OUT std_logic := '1'; + wiz_rd : OUT std_logic := '1'; + wiz_int : IN std_logic; + clk : IN std_logic; + sd_ready : OUT std_logic; + sd_busy : OUT std_logic; + led : OUT std_logic_vector (7 DOWNTO 0); + sd_read_ftu : IN std_logic; + sd_started_ftu : OUT std_logic := '0'; + cc_R0 : OUT std_logic_vector (31 DOWNTO 0); + cc_R1 : OUT std_logic_vector (31 DOWNTO 0); + cc_R11 : OUT std_logic_vector (31 DOWNTO 0); + cc_R13 : OUT std_logic_vector (31 DOWNTO 0); + cc_R14 : OUT std_logic_vector (31 DOWNTO 0); + cc_R15 : OUT std_logic_vector (31 DOWNTO 0); + cc_R8 : OUT std_logic_vector (31 DOWNTO 0); + cc_R9 : OUT std_logic_vector (31 DOWNTO 0); + coin_n_c : OUT std_logic_vector (15 DOWNTO 0); + coin_n_p : OUT std_logic_vector (15 DOWNTO 0); + dead_time : OUT std_logic_vector (15 DOWNTO 0); + -- data from config ram + general_settings : OUT std_logic_vector (15 DOWNTO 0); + lp1_amplitude : OUT std_logic_vector (15 DOWNTO 0); + lp1_delay : OUT std_logic_vector (15 DOWNTO 0); + lp2_amplitude : OUT std_logic_vector (15 DOWNTO 0); + lp2_delay : OUT std_logic_vector (15 DOWNTO 0); + lp_pt_freq : OUT std_logic_vector (15 DOWNTO 0); + lp_pt_ratio : OUT std_logic_vector (15 DOWNTO 0); + timemarker_delay : OUT std_logic_vector (15 DOWNTO 0); + trigger_delay : OUT std_logic_vector (15 DOWNTO 0); + sd_addr_ftu : IN std_logic_vector (11 DOWNTO 0); + sd_data_out_ftu : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0); + ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0); + ftu_active_cr2 : OUT std_logic_vector (15 DOWNTO 0); + ftu_active_cr3 : OUT std_logic_vector (15 DOWNTO 0); + new_config : OUT std_logic := '0'; + config_started : IN std_logic; + config_start_eth : IN std_logic; + config_started_eth : OUT std_logic := '0'; + config_ready_eth : OUT std_logic := '0'; + config_started_ack : OUT std_logic := '0'; + fl_busy : OUT std_logic; + fl_ready : OUT std_logic; + fl_write_ftu : IN std_logic; + fl_started_ftu : OUT std_logic := '0'; + fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0); + fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0) := (others => '0'); + -- + ping_ftu_start : OUT std_logic := '0'; + ping_ftu_started : IN std_logic; + ping_ftu_ready : IN std_logic; + dd_write_ftu : IN std_logic; + dd_started_ftu : OUT std_logic := '0'; + dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0); + dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0); + dd_busy : OUT std_logic; + dd_ready : OUT std_logic; + coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + dd_block_ready_ftu : IN std_logic; + dd_block_start_ack_ftu : OUT std_logic := '0'; + dd_block_start_ftu : IN std_logic; + dd_send : IN std_logic; + dd_send_ack : OUT std_logic := '1'; + dd_send_ready : OUT std_logic := '1' + ); END ethernet_modul ; --- --- VHDL Architecture FACT_FTM_lib.ethernet_modul.beha --- --- Created: --- by - kai.UNKNOWN (E5PCXX) --- at - 11:17:46 25.02.2011 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) --- --- --- ---LIBRARY IEEE; ---USE IEEE.STD_LOGIC_1164.all; ---USE IEEE.STD_LOGIC_ARITH.all; ---USE IEEE.STD_LOGIC_UNSIGNED.all; ---LIBRARY FACT_FTM_lib; ---USE FACT_FTM_lib.ftm_array_types.all; ---USE FACT_FTM_lib.ftm_constants.all; - ---LIBRARY FACT_FTM_lib; - ARCHITECTURE beha OF ethernet_modul IS @@ -113,47 +96,58 @@ -- Internal signal declarations - SIGNAL busy : std_logic := '1'; - SIGNAL cram_data_out : std_logic_vector(15 DOWNTO 0); - SIGNAL cram_data_in : std_logic_vector(15 DOWNTO 0); - SIGNAL cram_we : std_logic_vector(0 DOWNTO 0) := "0"; - SIGNAL sd_write : std_logic := '0'; - SIGNAL sd_read : std_logic; - SIGNAL led1 : std_logic_vector(7 DOWNTO 0) := (others => '0'); - SIGNAL sd_started : std_logic; - SIGNAL sd_addr : std_logic_vector(11 DOWNTO 0); - SIGNAL cram_addr_out : std_logic_vector(11 DOWNTO 0); - SIGNAL cram_addr_in : std_logic_vector(11 DOWNTO 0); - SIGNAL sd_data_in : std_logic_vector(15 DOWNTO 0) := (others => '0'); - SIGNAL sd_data_out : std_logic_vector(15 DOWNTO 0); - SIGNAL config_ready_cc : std_logic := '0'; - SIGNAL config_started_cc : std_logic := '0'; - SIGNAL config_start_cc : std_logic; - SIGNAL fl_started : std_logic; - SIGNAL fl_read : std_logic := '0'; + SIGNAL busy : std_logic := '1'; + SIGNAL cram_data_out : std_logic_vector(15 DOWNTO 0); + SIGNAL cram_data_in : std_logic_vector(15 DOWNTO 0); + SIGNAL cram_we : std_logic_vector(0 DOWNTO 0) := "0"; + SIGNAL sd_write : std_logic := '0'; + SIGNAL sd_read : std_logic; + SIGNAL led1 : std_logic_vector(7 DOWNTO 0) := (others => '0'); + SIGNAL sd_started : std_logic; + SIGNAL sd_addr : std_logic_vector(11 DOWNTO 0); + SIGNAL cram_addr_out : std_logic_vector(11 DOWNTO 0); + SIGNAL cram_addr_in : std_logic_vector(11 DOWNTO 0); + SIGNAL sd_data_in : std_logic_vector(15 DOWNTO 0) := (others => '0'); + SIGNAL sd_data_out : std_logic_vector(15 DOWNTO 0); + SIGNAL config_ready_cc : std_logic := '0'; + SIGNAL config_started_cc : std_logic := '0'; + SIGNAL config_start_cc : std_logic; + SIGNAL fl_started : std_logic; + SIGNAL fl_read : std_logic := '0'; -- - SIGNAL fl_addr : std_logic_vector(11 DOWNTO 0); - SIGNAL fl_data_out : std_logic_vector(15 DOWNTO 0); - SIGNAL fram_addr_out : std_logic_vector(11 DOWNTO 0); - SIGNAL doutb : std_logic_VECTOR(15 DOWNTO 0); - SIGNAL fram_we : std_logic_vector(0 DOWNTO 0) := "0"; - SIGNAL fram_addr_in : std_logic_vector(11 DOWNTO 0); - SIGNAL fram_data_in : std_logic_vector(15 DOWNTO 0); - SIGNAL led2 : std_logic_vector(7 DOWNTO 0) := X"00"; - SIGNAL dram_addr_out : std_logic_vector(11 DOWNTO 0); - SIGNAL doutb1 : std_logic_VECTOR(15 DOWNTO 0); - SIGNAL dram_we : std_logic_vector(0 DOWNTO 0) := "0"; - SIGNAL dram_addr_in : std_logic_vector(11 DOWNTO 0); - SIGNAL dram_data_in : std_logic_vector(15 DOWNTO 0); - SIGNAL dd_read : std_logic; - SIGNAL dd_started : std_logic := '0'; - SIGNAL dd_data_out : std_logic_vector(15 DOWNTO 0) := (others => '0'); - SIGNAL dd_addr : std_logic_vector(11 DOWNTO 0); - SIGNAL dd_block_ready : std_logic := '0'; + SIGNAL fl_addr : std_logic_vector(11 DOWNTO 0); + SIGNAL fl_data_out : std_logic_vector(15 DOWNTO 0); + SIGNAL fram_addr_out : std_logic_vector(11 DOWNTO 0); + SIGNAL doutb : std_logic_VECTOR(15 DOWNTO 0); + SIGNAL fram_we : std_logic_vector(0 DOWNTO 0) := "0"; + SIGNAL fram_addr_in : std_logic_vector(11 DOWNTO 0); + SIGNAL fram_data_in : std_logic_vector(15 DOWNTO 0); + SIGNAL dram_addr_out : std_logic_vector(11 DOWNTO 0); + SIGNAL doutb1 : std_logic_VECTOR(15 DOWNTO 0); + SIGNAL dram_we : std_logic_vector(0 DOWNTO 0) := "0"; + SIGNAL dram_addr_in : std_logic_vector(11 DOWNTO 0); + SIGNAL dram_data_in : std_logic_vector(15 DOWNTO 0); + SIGNAL dd_read : std_logic; + SIGNAL dd_started : std_logic := '0'; + SIGNAL dd_data_out : std_logic_vector(15 DOWNTO 0) := (others => '0'); + SIGNAL dd_addr : std_logic_vector(11 DOWNTO 0); + SIGNAL dd_block_ready : std_logic := '0'; -- - SIGNAL dd_block_start : std_logic := '0'; - SIGNAL dd_block_start_ack : std_logic; - SIGNAL dd_block_ready_ftu : std_logic; - SIGNAL dd_block_start_ack_ftu : std_logic := '0'; - SIGNAL dd_block_start_ftu : std_logic; + SIGNAL dd_block_start : std_logic := '0'; + SIGNAL dd_block_start_ack : std_logic; + SIGNAL dd_write_general : std_logic := '0'; + SIGNAL dd_write_general_ready : std_logic; + SIGNAL dd_write_general_started : std_logic; + SIGNAL dd_write : std_logic := '0'; + SIGNAL dd_started_general : std_logic := '0'; + SIGNAL dd_addr1 : std_logic_vector(11 DOWNTO 0) := (others => '0'); + SIGNAL dd_data : std_logic_vector(15 DOWNTO 0) := (others => '0'); + SIGNAL get_header : std_logic; + SIGNAL get_header_started : std_logic := '0'; + SIGNAL get_header_ready : std_logic := '0'; + SIGNAL led2 : std_logic_vector(7 DOWNTO 0); + SIGNAL header_board_id : std_logic_vector(63 DOWNTO 0); + SIGNAL header_firmware_id : std_logic_vector(15 DOWNTO 0); + SIGNAL header_timestamp_counter : std_logic_vector(47 DOWNTO 0); + SIGNAL header_trigger_counter : std_logic_vector(31 DOWNTO 0); -- Implicit buffer signal declarations @@ -204,8 +198,8 @@ clk : IN std_logic ; led : OUT std_logic_vector (7 DOWNTO 0) := X"00"; - cram_data_in : OUT std_logic_vector (15 DOWNTO 0); + cram_data_in : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); cram_data_out : IN std_logic_vector (15 DOWNTO 0); - cram_addr_in : OUT std_logic_vector (11 DOWNTO 0); - cram_addr_out : OUT std_logic_vector (11 DOWNTO 0); + cram_addr_in : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); + cram_addr_out : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); cram_we : OUT std_logic_vector (0 DOWNTO 0) := "0"; sd_write : IN std_logic ; @@ -253,11 +247,25 @@ ); END COMPONENT; + COMPONENT dd_write_general_modul + PORT ( + clk : IN std_logic ; + dd_write_general : IN std_logic ; + dd_write_general_started : OUT std_logic := '0'; + dd_write_general_ready : OUT std_logic := '0'; + dd_busy : IN std_logic ; + dd_write : OUT std_logic := '0'; + dd_started : IN std_logic ; + dd_ready : IN std_logic ; + dd_addr : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); + dd_data : OUT std_logic_vector (15 DOWNTO 0) := (others => '0') + ); + END COMPONENT; COMPONENT dram_control PORT ( clk : IN std_logic ; - dram_data_in : OUT std_logic_vector (15 DOWNTO 0); + dram_data_in : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); dram_data_out : IN std_logic_vector (15 DOWNTO 0); - dram_addr_in : OUT std_logic_vector (11 DOWNTO 0); - dram_addr_out : OUT std_logic_vector (11 DOWNTO 0); + dram_addr_in : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); + dram_addr_out : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); dram_we : OUT std_logic_vector (0 DOWNTO 0) := "0"; dd_block_start : IN std_logic ; @@ -269,12 +277,16 @@ dd_read : IN std_logic ; dd_write_ftu : IN std_logic ; + dd_write_general : IN std_logic ; dd_busy : OUT std_logic := '1'; dd_started : OUT std_logic := '0'; dd_started_ftu : OUT std_logic := '0'; + dd_started_general : OUT std_logic := '0'; dd_ready : OUT std_logic := '0'; dd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0); + dd_data_in_general : IN std_logic_vector (15 DOWNTO 0); dd_addr : IN std_logic_vector (11 DOWNTO 0); - dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0) + dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0); + dd_addr_general : IN std_logic_vector (11 DOWNTO 0) ); END COMPONENT; @@ -293,8 +305,8 @@ PORT ( clk : IN std_logic ; - fram_data_in : OUT std_logic_vector (15 DOWNTO 0); + fram_data_in : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); fram_data_out : IN std_logic_vector (15 DOWNTO 0); - fram_addr_in : OUT std_logic_vector (11 DOWNTO 0); - fram_addr_out : OUT std_logic_vector (11 DOWNTO 0); + fram_addr_in : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); + fram_addr_out : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); fram_we : OUT std_logic_vector (0 DOWNTO 0) := "0"; fl_read : IN std_logic ; @@ -310,49 +322,75 @@ ); END COMPONENT; + COMPONENT header_modul + PORT ( + clk : IN std_logic ; + get_header : IN std_logic ; + get_header_started : OUT std_logic := '0'; + get_header_ready : OUT std_logic := '0'; + header_board_id : OUT std_logic_vector (63 DOWNTO 0) := (others => '0'); + header_firmware_id : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + header_trigger_counter : OUT std_logic_vector (31 DOWNTO 0) := (others => '0'); + header_timestamp_counter : OUT std_logic_vector (47 DOWNTO 0) := (others => '0') + ); + END COMPONENT; COMPONENT w5300_modul PORT ( - clk : IN std_logic ; - wiz_reset : OUT std_logic := '1'; - addr : OUT std_logic_vector (9 DOWNTO 0); - data : INOUT std_logic_vector (15 DOWNTO 0); - cs : OUT std_logic := '1'; - wr : OUT std_logic := '1'; - led : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); - rd : OUT std_logic := '1'; - int : IN std_logic ; - busy : OUT std_logic := '1'; - new_config : OUT std_logic := '0'; - config_started : IN std_logic ; - config_started_ack : OUT std_logic := '0'; + clk : IN std_logic ; + wiz_reset : OUT std_logic := '1'; + addr : OUT std_logic_vector (9 DOWNTO 0); + data : INOUT std_logic_vector (15 DOWNTO 0); + cs : OUT std_logic := '1'; + wr : OUT std_logic := '1'; + led : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); + rd : OUT std_logic := '1'; + int : IN std_logic ; + busy : OUT std_logic := '1'; + new_config : OUT std_logic := '0'; + config_started : IN std_logic ; + config_started_ack : OUT std_logic := '0'; -- - ping_ftu_start : OUT std_logic := '0'; - ping_ftu_started : IN std_logic ; - ping_ftu_ready : IN std_logic ; + ping_ftu_start : OUT std_logic := '0'; + ping_ftu_started : IN std_logic ; + ping_ftu_ready : IN std_logic ; -- - sd_addr : OUT std_logic_vector (11 DOWNTO 0); - sd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); - sd_data_in : IN std_logic_vector (15 DOWNTO 0); - sd_write : OUT std_logic := '0'; - sd_read : OUT std_logic := '0'; - sd_started : IN std_logic ; - sd_ready : IN std_logic ; - sd_busy : IN std_logic ; + sd_addr : OUT std_logic_vector (11 DOWNTO 0); + sd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + sd_data_in : IN std_logic_vector (15 DOWNTO 0); + sd_write : OUT std_logic := '0'; + sd_read : OUT std_logic := '0'; + sd_started : IN std_logic ; + sd_ready : IN std_logic ; + sd_busy : IN std_logic ; -- - dd_block_start : OUT std_logic := '0'; - dd_block_start_ack : IN std_logic ; - dd_block_ready : OUT std_logic := '0'; - dd_addr : OUT std_logic_vector (11 DOWNTO 0); - dd_data_in : IN std_logic_vector (15 DOWNTO 0); - dd_read : OUT std_logic := '0'; - dd_started : IN std_logic ; - dd_ready : IN std_logic ; - dd_busy : IN std_logic ; + dd_block_start : OUT std_logic := '0'; + dd_block_start_ack : IN std_logic ; + dd_block_ready : OUT std_logic := '1'; + dd_send : IN std_logic ; + dd_send_ack : OUT std_logic := '1'; + dd_send_ready : OUT std_logic := '1'; + dd_addr : OUT std_logic_vector (11 DOWNTO 0); + dd_data_in : IN std_logic_vector (15 DOWNTO 0); + dd_read : OUT std_logic := '0'; + dd_started : IN std_logic ; + dd_ready : IN std_logic ; + dd_busy : IN std_logic ; + dd_write_general : OUT std_logic := '0'; + dd_write_general_started : IN std_logic ; + dd_write_general_ready : IN std_logic ; -- - fl_addr : OUT std_logic_vector (11 DOWNTO 0); - fl_data_in : IN std_logic_vector (15 DOWNTO 0); - fl_read : OUT std_logic := '0'; - fl_started : IN std_logic ; - fl_ready : IN std_logic ; - fl_busy : IN std_logic + fl_addr : OUT std_logic_vector (11 DOWNTO 0); + fl_data_in : IN std_logic_vector (15 DOWNTO 0); + fl_read : OUT std_logic := '0'; + fl_started : IN std_logic ; + fl_ready : IN std_logic ; + fl_busy : IN std_logic ; + -- + get_header : OUT std_logic := '0'; + get_header_started : IN std_logic ; + get_header_ready : IN std_logic ; + header_board_id : IN std_logic_vector (63 DOWNTO 0); + header_firmware_id : IN std_logic_vector (15 DOWNTO 0); + header_trigger_counter : IN std_logic_vector (31 DOWNTO 0); + header_timestamp_counter : IN std_logic_vector (47 DOWNTO 0) ); END COMPONENT; @@ -364,10 +402,11 @@ -- FOR ALL : FRAM_4096_16b USE ENTITY FACT_FTM_lib.FRAM_4096_16b; -- FOR ALL : cram_control USE ENTITY FACT_FTM_lib.cram_control; + -- FOR ALL : dd_write_general_modul USE ENTITY FACT_FTM_lib.dd_write_general_modul; -- FOR ALL : dram_control USE ENTITY FACT_FTM_lib.dram_control; -- FOR ALL : eth_config_modul USE ENTITY FACT_FTM_lib.eth_config_modul; -- FOR ALL : fram_control USE ENTITY FACT_FTM_lib.fram_control; + -- FOR ALL : header_modul USE ENTITY FACT_FTM_lib.header_modul; -- FOR ALL : w5300_modul USE ENTITY FACT_FTM_lib.w5300_modul; -- pragma synthesis_on - BEGIN @@ -458,4 +497,17 @@ ftu_active_cr3 => ftu_active_cr3 ); + U_9 : dd_write_general_modul + PORT MAP ( + clk => clk, + dd_write_general => dd_write_general, + dd_write_general_started => dd_write_general_started, + dd_write_general_ready => dd_write_general_ready, + dd_busy => dd_busy_internal, + dd_write => dd_write, + dd_started => dd_started_general, + dd_ready => dd_ready_internal, + dd_addr => dd_addr1, + dd_data => dd_data + ); U_8 : dram_control PORT MAP ( @@ -474,12 +526,16 @@ dd_read => dd_read, dd_write_ftu => dd_write_ftu, + dd_write_general => dd_write, dd_busy => dd_busy_internal, dd_started => dd_started, dd_started_ftu => dd_started_ftu, + dd_started_general => dd_started_general, dd_ready => dd_ready_internal, dd_data_out => dd_data_out, dd_data_in_ftu => dd_data_in_ftu, + dd_data_in_general => dd_data, dd_addr => dd_addr, - dd_addr_ftu => dd_addr_ftu + dd_addr_ftu => dd_addr_ftu, + dd_addr_general => dd_addr1 ); U_4 : eth_config_modul @@ -512,45 +568,69 @@ fl_addr_ftu => fl_addr_ftu ); + U_10 : header_modul + PORT MAP ( + clk => clk, + get_header => get_header, + get_header_started => get_header_started, + get_header_ready => get_header_ready, + header_board_id => header_board_id, + header_firmware_id => header_firmware_id, + header_trigger_counter => header_trigger_counter, + header_timestamp_counter => header_timestamp_counter + ); U_0 : w5300_modul PORT MAP ( - clk => clk, - wiz_reset => wiz_reset, - addr => wiz_addr, - data => wiz_data, - cs => wiz_cs, - wr => wiz_wr, - led => led1, - rd => wiz_rd, - int => wiz_int, - busy => busy, - new_config => new_config, - config_started => config_started, - config_started_ack => config_started_ack, - ping_ftu_start => ping_ftu_start, - ping_ftu_started => ping_ftu_started, - ping_ftu_ready => ping_ftu_ready, - sd_addr => sd_addr, - sd_data_out => sd_data_in, - sd_data_in => sd_data_out, - sd_write => sd_write, - sd_read => sd_read, - sd_started => sd_started, - sd_ready => sd_ready_internal, - sd_busy => sd_busy_internal, - dd_block_start => dd_block_start, - dd_block_start_ack => dd_block_start_ack, - dd_block_ready => dd_block_ready, - dd_addr => dd_addr, - dd_data_in => dd_data_out, - dd_read => dd_read, - dd_started => dd_started, - dd_ready => dd_ready_internal, - dd_busy => dd_busy_internal, - fl_addr => fl_addr, - fl_data_in => fl_data_out, - fl_read => fl_read, - fl_started => fl_started, - fl_ready => fl_ready_internal, - fl_busy => fl_busy_internal + clk => clk, + wiz_reset => wiz_reset, + addr => wiz_addr, + data => wiz_data, + cs => wiz_cs, + wr => wiz_wr, + led => led1, + rd => wiz_rd, + int => wiz_int, + busy => busy, + new_config => new_config, + config_started => config_started, + config_started_ack => config_started_ack, + ping_ftu_start => ping_ftu_start, + ping_ftu_started => ping_ftu_started, + ping_ftu_ready => ping_ftu_ready, + sd_addr => sd_addr, + sd_data_out => sd_data_in, + sd_data_in => sd_data_out, + sd_write => sd_write, + sd_read => sd_read, + sd_started => sd_started, + sd_ready => sd_ready_internal, + sd_busy => sd_busy_internal, + dd_block_start => dd_block_start, + dd_block_start_ack => dd_block_start_ack, + dd_block_ready => dd_block_ready, + dd_send => dd_send, + dd_send_ack => dd_send_ack, + dd_send_ready => dd_send_ready, + dd_addr => dd_addr, + dd_data_in => dd_data_out, + dd_read => dd_read, + dd_started => dd_started, + dd_ready => dd_ready_internal, + dd_busy => dd_busy_internal, + dd_write_general => dd_write_general, + dd_write_general_started => dd_write_general_started, + dd_write_general_ready => dd_write_general_ready, + fl_addr => fl_addr, + fl_data_in => fl_data_out, + fl_read => fl_read, + fl_started => fl_started, + fl_ready => fl_ready_internal, + fl_busy => fl_busy_internal, + get_header => get_header, + get_header_started => get_header_started, + get_header_ready => get_header_ready, + header_board_id => header_board_id, + header_firmware_id => header_firmware_id, + header_trigger_counter => header_trigger_counter, + header_timestamp_counter => header_timestamp_counter ); Index: firmware/FTM/ethernet/fram_control_beha.vhd =================================================================== --- firmware/FTM/ethernet/fram_control_beha.vhd (revision 10250) +++ firmware/FTM/ethernet/fram_control_beha.vhd (revision 10256) @@ -8,4 +8,5 @@ -- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) -- + LIBRARY ieee; USE ieee.std_logic_1164.all; @@ -20,22 +21,22 @@ ENTITY fram_control IS - PORT( - clk : IN std_logic; - fram_data_in : OUT std_logic_vector (15 DOWNTO 0); - fram_data_out : IN std_logic_vector (15 DOWNTO 0); - fram_addr_in : OUT std_logic_vector (11 DOWNTO 0); - fram_addr_out : OUT std_logic_vector (11 DOWNTO 0); - fram_we : OUT std_logic_vector (0 DOWNTO 0) := "0"; - fl_read : IN std_logic; - fl_write_ftu : IN std_logic; - fl_busy : OUT std_logic := '1'; - fl_started : OUT std_logic := '0'; - fl_started_ftu : OUT std_logic := '0'; - fl_ready : OUT std_logic := '0'; - fl_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); - fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0); - fl_addr : IN std_logic_vector (11 DOWNTO 0); - fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0) - ); + PORT( + clk : IN std_logic; + fram_data_in : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + fram_data_out : IN std_logic_vector (15 DOWNTO 0); + fram_addr_in : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); + fram_addr_out : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); + fram_we : OUT std_logic_vector (0 DOWNTO 0) := "0"; + fl_read : IN std_logic; + fl_write_ftu : IN std_logic; + fl_busy : OUT std_logic := '1'; + fl_started : OUT std_logic := '0'; + fl_started_ftu : OUT std_logic := '0'; + fl_ready : OUT std_logic := '0'; + fl_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0); + fl_addr : IN std_logic_vector (11 DOWNTO 0); + fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0) + ); -- Declarations @@ -113,7 +114,9 @@ when FR_WRITE_END => fram_we <= "0"; - fl_started_ftu <= '0'; - fl_ready <= '1'; - state_fram_proc <= next_state; + if (fl_write_ftu = '0') then + fl_started_ftu <= '0'; + fl_ready <= '1'; + state_fram_proc <= next_state; + end if; -- -- Index: firmware/FTM/ethernet/header_modul_beha.vhd =================================================================== --- firmware/FTM/ethernet/header_modul_beha.vhd (revision 10256) +++ firmware/FTM/ethernet/header_modul_beha.vhd (revision 10256) @@ -0,0 +1,79 @@ +-- +-- VHDL Architecture FACT_FTM_lib.header_modul.beha +-- +-- Created: +-- by - kai.UNKNOWN (E5PCXX) +-- at - 10:30:24 03.03.2011 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE IEEE.STD_LOGIC_UNSIGNED.all; +-- LIBRARY FACT_FTM_lib; +-- USE FACT_FTM_lib.ftm_array_types.all; +-- USE FACT_FTM_lib.ftm_constants.all; +library ftm_definitions; +USE ftm_definitions.ftm_array_types.all; +USE ftm_definitions.ftm_constants.all; + +ENTITY header_modul IS +PORT( + clk : IN std_logic; + get_header : IN std_logic; + get_header_started : OUT std_logic := '0'; + get_header_ready : OUT std_logic := '0'; + header_board_id : OUT std_logic_vector (63 DOWNTO 0) := (others => '0'); + header_firmware_id : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + header_trigger_counter : OUT std_logic_vector (31 DOWNTO 0) := (others => '0'); + header_timestamp_counter : OUT std_logic_vector (47 DOWNTO 0) := (others => '0') + ); +END ENTITY header_modul; + +-- +ARCHITECTURE beha OF header_modul IS + + type state_header_proc_type is (HP_INIT, HP_CONFIG, HP_IDLE, HP_START, HP_END); + + signal state_header_proc : state_header_proc_type := HP_INIT; + +BEGIN + header_proc : process (clk) + begin + if rising_edge (clk) then + case state_header_proc is + + when HP_INIT => + state_header_proc <= HP_CONFIG; + + when HP_CONFIG => + state_header_proc <= HP_IDLE; + + when HP_IDLE => + if (get_header = '1') then + get_header_started <= '1'; + get_header_ready <= '0'; + state_header_proc <= HP_START; + end if; + + when HP_START => + header_board_id <= to_stdlogicvector (DNA_FOR_SIM); + header_firmware_id <= X"00" & FIRMWARE_ID; + header_trigger_counter <= X"22221111"; + header_timestamp_counter <= X"333322221111"; + state_header_proc <= HP_END; + + when HP_END => + if (get_header <= '0') then + get_header_started <= '0'; + get_header_ready <= '1'; + state_header_proc <= HP_IDLE; + end if; + + end case; + end if; + end process header_proc; + +END ARCHITECTURE beha; Index: firmware/FTM/ethernet/w5300_modul.vhd =================================================================== --- firmware/FTM/ethernet/w5300_modul.vhd (revision 10250) +++ firmware/FTM/ethernet/w5300_modul.vhd (revision 10256) @@ -18,5 +18,5 @@ -- ---------------------------------------------------------------------------------- --- hds interface_start + LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; @@ -30,61 +30,72 @@ USE ftm_definitions.ftm_constants.all; --- -- Uncomment the following library declaration if instantiating --- -- any Xilinx primitives in this code. - library UNISIM; - use UNISIM.VComponents.all; - --- +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + + ENTITY w5300_modul IS - PORT( - clk : IN std_logic; - wiz_reset : OUT std_logic := '1'; - addr : OUT std_logic_vector (9 DOWNTO 0); - data : INOUT std_logic_vector (15 DOWNTO 0); - cs : OUT std_logic := '1'; - wr : OUT std_logic := '1'; - led : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); - rd : OUT std_logic := '1'; - int : IN std_logic; - busy : OUT std_logic := '1'; - new_config : OUT std_logic := '0'; - config_started : IN std_logic; - config_started_ack : OUT std_logic := '0'; - -- - ping_ftu_start : OUT std_logic := '0'; - ping_ftu_started : IN std_logic; - ping_ftu_ready : IN std_logic; - -- - sd_addr : OUT std_logic_vector (11 DOWNTO 0); - sd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); - sd_data_in : IN std_logic_vector (15 DOWNTO 0); - sd_write : OUT std_logic := '0'; - sd_read : OUT std_logic := '0'; - sd_started : IN std_logic; - sd_ready : IN std_logic; - sd_busy : IN std_logic; - -- - dd_block_start : OUT std_logic := '0'; - dd_block_start_ack : IN std_logic; - dd_block_ready : OUT std_logic := '0'; - dd_addr : OUT std_logic_vector (11 DOWNTO 0); - dd_data_in : IN std_logic_vector (15 DOWNTO 0); - dd_read : OUT std_logic := '0'; - dd_started : IN std_logic; - dd_ready : IN std_logic; - dd_busy : IN std_logic; - -- - fl_addr : OUT std_logic_vector (11 DOWNTO 0); - fl_data_in : IN std_logic_vector (15 DOWNTO 0); - fl_read : OUT std_logic := '0'; - fl_started : IN std_logic; - fl_ready : IN std_logic; - fl_busy : IN std_logic - ); - --- Declarations + PORT( + clk : IN std_logic; + wiz_reset : OUT std_logic := '1'; + addr : OUT std_logic_vector (9 DOWNTO 0); + data : INOUT std_logic_vector (15 DOWNTO 0); + cs : OUT std_logic := '1'; + wr : OUT std_logic := '1'; + led : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); + rd : OUT std_logic := '1'; + int : IN std_logic; + busy : OUT std_logic := '1'; + new_config : OUT std_logic := '0'; + config_started : IN std_logic; + config_started_ack : OUT std_logic := '0'; + -- + ping_ftu_start : OUT std_logic := '0'; + ping_ftu_started : IN std_logic; + ping_ftu_ready : IN std_logic; + -- + sd_addr : OUT std_logic_vector (11 DOWNTO 0); + sd_data_out : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + sd_data_in : IN std_logic_vector (15 DOWNTO 0); + sd_write : OUT std_logic := '0'; + sd_read : OUT std_logic := '0'; + sd_started : IN std_logic; + sd_ready : IN std_logic; + sd_busy : IN std_logic; + -- + dd_block_start : OUT std_logic := '0'; + dd_block_start_ack : IN std_logic; + dd_block_ready : OUT std_logic := '1'; + dd_send : IN std_logic; + dd_send_ack : OUT std_logic := '1'; + dd_send_ready : OUT std_logic := '1'; + dd_addr : OUT std_logic_vector (11 DOWNTO 0); + dd_data_in : IN std_logic_vector (15 DOWNTO 0); + dd_read : OUT std_logic := '0'; + dd_started : IN std_logic; + dd_ready : IN std_logic; + dd_busy : IN std_logic; + dd_write_general : OUT std_logic := '0'; + dd_write_general_started : IN std_logic; + dd_write_general_ready : IN std_logic; + -- + fl_addr : OUT std_logic_vector (11 DOWNTO 0); + fl_data_in : IN std_logic_vector (15 DOWNTO 0); + fl_read : OUT std_logic := '0'; + fl_started : IN std_logic; + fl_ready : IN std_logic; + fl_busy : IN std_logic; + -- + get_header : OUT std_logic := '0'; + get_header_started : IN std_logic; + get_header_ready : IN std_logic; + header_board_id : IN std_logic_vector (63 DOWNTO 0); + header_firmware_id : IN std_logic_vector (15 DOWNTO 0); + header_trigger_counter : IN std_logic_vector (31 DOWNTO 0); + header_timestamp_counter : IN std_logic_vector (47 DOWNTO 0) + ); END w5300_modul ; --- hds interface_end architecture Behavioral of w5300_modul is @@ -93,6 +104,7 @@ INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, - READ_DATA, WRITE_TO_SD_ADDR, READ_FROM_SD_ADDR, READ_FROM_DD_ADDR, READ_FROM_FL_ADDR); - type state_write_type is (WR_START, WR_LENGTH, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO_01); + READ_DATA, WRITE_TO_SD_ADDR, READ_FROM_SD_ADDR, READ_FROM_DD_ADDR, READ_FROM_FL_ADDR, READ_FROM_HEADER_MODUL); + type state_write_type is (WR_START, WR_LENGTH, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08, + WR_GET_HEADER, WR_GET_HEADER_WAIT, WR_FIFO_DATA, WR_FIFO_DATA_01, WR_FIFO_HEADER, WR_FIFO_HEADER_01); type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04); type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06); @@ -103,5 +115,5 @@ type state_ping_type is (PING_START, PING_WAIT, PING_WRITE_LIST); type state_read_dd_type is (READ_DD_START, READ_DD_WAIT, READ_DD_END); - type state_read_dd_block_type is (READ_DD_BLOCK_START, READ_DD_BLOCK_WRITE, READ_DD_BLOCK_END); + type state_read_dd_block_type is (READ_DD_BLOCK_START, READ_DD_BLOCK_WRITE_GENERAL, READ_DD_BLOCK_WRITE, READ_DD_BLOCK_END, READ_DD_BLOCK_INTERN); signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120"; @@ -132,4 +144,5 @@ signal zaehler : std_logic_vector (19 downto 0) := (others => '0'); signal data_cnt : integer := 0; + signal header_cnt : integer := 0; signal socket_cnt : std_logic_vector (2 downto 0) := "000"; @@ -149,4 +162,5 @@ type cmd_array_type is array (0 to 4) of std_logic_vector (15 downto 0); signal cmd_array : cmd_array_type; + signal internal_cmd : std_logic := '0'; -- -- -- @@ -199,5 +213,5 @@ if int_flag = '0' then case state_init is - -- Interrupt + -- Interrupt when INTERRUPT => case state_interrupt_2 is @@ -248,5 +262,5 @@ end case; - -- reset W5300 + -- reset W5300 when RESET => busy <= '1'; @@ -264,6 +278,33 @@ wr <= '1'; cs <= '1'; - state_write <= WR_START; - state_init <= INIT; + -- reset states + state_write <= WR_START; + state_init <= INIT; + state_read_data <= RD_1; + next_state_read_data <= RD_CMD; + state_write_sd <= WRITE_SD_START; + state_read_sd <= READ_SD_START; + state_read_fl <= READ_FL_START; + state_ping <= PING_START; + state_read_dd <= READ_DD_START; + state_read_dd_block <= READ_DD_BLOCK_START; + -- reset output signals + new_config <= '0'; + config_started_ack <= '1'; + ping_ftu_start <= '0'; + sd_write <= '0'; + sd_read <= '0'; + dd_block_start <= '0'; + dd_block_ready <= '1'; + dd_send_ack <= '1'; + dd_send_ready <= '1'; + dd_read <= '0'; + dd_write_general <= '0'; + fl_read <= '0'; + -- set internal signals + new_config_flag <= '0'; + chk_recv_cntr <= 0; + next_packet_data_cnt <= 0; + internal_cmd <= '0'; -- -- -- led_int <= X"00"; @@ -448,4 +489,8 @@ state_init <= MAIN; -- -- -- + config_started_ack <= '0'; + dd_block_ready <= '0'; + dd_send_ack <= '0'; + dd_send_ready <= '0'; led_int <= X"00"; -- -- -- @@ -481,6 +526,7 @@ end if; - -- main "loop" + -- main "loop" when MAIN => + chk_recv_cntr <= chk_recv_cntr + 1; if (chk_recv_cntr = 1000) then chk_recv_cntr <= 0; @@ -488,10 +534,18 @@ state_init <= READ_DATA; busy <= '1'; - else - chk_recv_cntr <= chk_recv_cntr + 1; + elsif (dd_send = '1') then + internal_cmd <= '1'; + dd_send_ack <= '1'; + dd_send_ready <= '0'; + -- "simulate" command read dynamic data block + cmd_array (0) <= CMD_START_DELIMITER; + cmd_array (1) <= CMD_READ; + cmd_array (2) <= PAR_READ_DD; + state_read_data <= RD_CMD_PARSE; + state_init <= READ_DATA; end if; - -- read data from socket 0 + -- read data from socket 0 when READ_DATA => case state_read_data is @@ -529,4 +583,19 @@ end if; + when RD_END => + if (internal_cmd = '0') then + par_addr <= W5300_S0_CR; + par_data <= X"0040"; -- RECV + state_init <= WRITE_REG; + else + internal_cmd <= '0'; + end if; + if (new_config_flag = '1') then + new_config_flag <= '0'; + next_state <= CONFIG; + else + next_state <= MAIN; + end if; + ------------------------- @@ -585,6 +654,7 @@ when PAR_READ_SD => state_read_data <= RD_READ_SD_BLOCK; - when PAR_READ_DD => - state_read_data <= RD_READ_DD_BLOCK; + -- read dynamic data block + when PAR_READ_DD => + state_read_data <= RD_READ_DD_BLOCK; when others => state_read_data <= RD_5; @@ -626,27 +696,50 @@ -- read dynamic data block and write it to ethernet when RD_READ_DD_BLOCK => - case state_read_dd_block is - when READ_DD_BLOCK_START => - dd_block_start <= '1'; - dd_block_ready <= '0'; - if (dd_block_start_ack = '1') then - dd_block_start <= '0'; - state_read_dd_block <= READ_DD_BLOCK_WRITE; - end if; - when READ_DD_BLOCK_WRITE => - read_addr_state <= READ_FROM_DD_ADDR; - local_sd_addr <= X"000"; -- start at address 0x000 - local_write_length <= "00000" & DD_BLOCK_SIZE; - state_read_dd_block <= READ_DD_BLOCK_END; - next_state <= READ_DATA; - state_init <= WRITE_DATA; - when READ_DD_BLOCK_END => - dd_block_ready <= '1'; - state_read_dd_block <= READ_DD_BLOCK_START; - state_read_data <= RD_5; - next_state_read_data <= RD_CMD; - end case; - - -- read static data block and write it to ethernet + case state_read_dd_block is + when READ_DD_BLOCK_START => + dd_block_start <= '1'; + dd_block_ready <= '0'; + if (dd_block_start_ack = '1') then + dd_block_start <= '0'; + state_read_dd_block <= READ_DD_BLOCK_WRITE_GENERAL; + end if; + -- write on-time counter and tempertures to dd-block + when READ_DD_BLOCK_WRITE_GENERAL => + dd_write_general <= '1'; + if (dd_write_general_started = '1') then + dd_write_general <= '0'; + state_read_dd_block <= READ_DD_BLOCK_WRITE; + end if; + -- write dd-block to ethernet when on-time counter and temperatures are ready + when READ_DD_BLOCK_WRITE => + if (dd_write_general_ready = '1') then + read_addr_state <= READ_FROM_DD_ADDR; + local_sd_addr <= X"000"; -- start at address 0x000 + local_write_length <= "00000" & DD_BLOCK_SIZE; + state_read_dd_block <= READ_DD_BLOCK_END; + next_state <= READ_DATA; + state_init <= WRITE_DATA; + end if; + when READ_DD_BLOCK_END => + dd_block_ready <= '1'; + next_state_read_data <= RD_CMD; + -- + if (internal_cmd = '1') then + state_read_dd_block <= READ_DD_BLOCK_INTERN; + else + state_read_dd_block <= READ_DD_BLOCK_START; + state_read_data <= RD_5; + end if; + when READ_DD_BLOCK_INTERN => + if (dd_send = '0') then + dd_send_ready <= '1'; + dd_send_ack <= '0'; + state_read_dd_block <= READ_DD_BLOCK_START; + state_read_data <= RD_5; + end if; + + end case; + + -- read static data block and write it to ethernet when RD_READ_SD_BLOCK => state_read_data <= RD_5; @@ -695,24 +788,38 @@ state_init <= WRITE_TO_SD_ADDR; end if; - - - ------------------------- - ------------------------- - - - when RD_END => - par_addr <= W5300_S0_CR; - par_data <= X"0040"; -- RECV - state_init <= WRITE_REG; - if (new_config_flag = '1') then - new_config_flag <= '0'; - next_state <= CONFIG; - else - next_state <= MAIN; - end if; end case; -- state_read_data + -- read from header modul + when READ_FROM_HEADER_MODUL => + state_init <= next_state; + case header_cnt is + when 0 => + local_sd_data <= header_board_id (63 DOWNTO 48); + when 1 => + local_sd_data <= header_board_id (47 DOWNTO 32); + when 2 => + local_sd_data <= header_board_id (31 DOWNTO 16); + when 3 => + local_sd_data <= header_board_id (15 DOWNTO 0); + when 4 => + local_sd_data <= header_firmware_id; + when 5 => + local_sd_data <= header_trigger_counter (31 DOWNTO 16); + when 6 => + local_sd_data <= header_trigger_counter (15 DOWNTO 0); + when 7 => + local_sd_data <= header_timestamp_counter (47 DOWNTO 32); + when 8 => + local_sd_data <= header_timestamp_counter (31 DOWNTO 16); + when 9 => + local_sd_data <= header_timestamp_counter (15 DOWNTO 0); + when 10 => + local_sd_data <= X"FFFF"; -- spare + when others => + null; + end case; + -- read from ftu list ram when READ_FROM_FL_ADDR => @@ -803,6 +910,5 @@ end case; - - + -- write to ethernet interface when WRITE_DATA => case state_write is @@ -812,8 +918,9 @@ local_socket_nr <= "000"; next_state_tmp <= next_state; - write_length_bytes <= local_write_length (15 downto 0) & '0'; -- shift left (*2) + write_length_bytes <= (FTM_HEADER_LENGTH + local_write_length (15 downto 0)) & '0'; -- shift left (*2) data_cnt <= 0; + header_cnt <= 0; state_write <= WR_01; - -- Check FIFO Size + -- Check FIFO Size when WR_01 => par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC; @@ -834,14 +941,44 @@ state_write <= WR_01; else - state_write <= WR_FIFO; - end if; - - -- Fill FIFO - when WR_FIFO => + state_write <= WR_GET_HEADER; + end if; + + -- get header data + when WR_GET_HEADER => + get_header <= '1'; + if (get_header_started = '1') then + get_header <= '0'; + state_write <= WR_GET_HEADER_WAIT; + end if; + + when WR_GET_HEADER_WAIT => + if (get_header_ready = '1') then + state_write <= WR_FIFO_HEADER; + end if; + + -- Fill FIFO + when WR_FIFO_HEADER => + state_init <= READ_FROM_HEADER_MODUL; + next_state <= WRITE_DATA; + state_write <= WR_FIFO_HEADER_01; + + when WR_FIFO_HEADER_01 => + header_cnt <= header_cnt + 1; + if (header_cnt < FTM_HEADER_LENGTH) then + par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; + par_data <= local_sd_data; + state_init <= WRITE_REG; + next_state <= WRITE_DATA; + state_write <= WR_FIFO_HEADER; + else + state_write <= WR_FIFO_DATA; + end if; + + when WR_FIFO_DATA => state_init <= read_addr_state; next_state <= WRITE_DATA; - state_write <= WR_FIFO_01; - - when WR_FIFO_01 => + state_write <= WR_FIFO_DATA_01; + + when WR_FIFO_DATA_01 => data_cnt <= data_cnt + 1; if (data_cnt < local_write_length) then @@ -851,10 +988,10 @@ state_init <= WRITE_REG; next_state <= WRITE_DATA; - state_write <= WR_FIFO; + state_write <= WR_FIFO_DATA; else state_write <= WR_05; end if; - --Send FIFO + -- Send FIFO when WR_05 => par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC; Index: firmware/FTM/ftm_board.ucf =================================================================== --- firmware/FTM/ftm_board.ucf (revision 10250) +++ firmware/FTM/ftm_board.ucf (revision 10256) @@ -185,9 +185,9 @@ # on IO-Bank 3 ####################################################### -# NET CLK_Clk_Cond LOC = G4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 -# NET LE_Clk_Cond LOC = F2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 -# NET LD_Clk_Cond LOC = J4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 -# NET DATA_Clk_Cond LOC = F3 | IOSTANDARD=LVCMOS33; # IO-Bank 3 -# NET SYNC_Clk_Cond LOC = H2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +NET CLK_Clk_Cond LOC = G4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +NET LE_Clk_Cond LOC = F2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +NET LD_Clk_Cond LOC = J4 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +NET DATA_Clk_Cond LOC = F3 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +NET SYNC_Clk_Cond LOC = H2 | IOSTANDARD=LVCMOS33; # IO-Bank 3 @@ -297,5 +297,5 @@ # NET TIM_Run_n LOC = AE25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run- on IO-Bank2 -# NET TIM_Sel LOC = AD22 | IOSTANDARD=LVCMOS33; # Time Marker selector IO-Bank 2 +NET TIM_Sel LOC = AD22 | IOSTANDARD=LVCMOS33; # Time Marker selector IO-Bank 2 # NET CLD_FPGA LOC = AA14 | IOSTANDARD=LVCMOS33; # DRS-Clock feedback into FPGA Index: firmware/FTM/ftm_definitions.vhd =================================================================== --- firmware/FTM/ftm_definitions.vhd (revision 10250) +++ firmware/FTM/ftm_definitions.vhd (revision 10256) @@ -56,9 +56,6 @@ type mac_type is array (0 to 2) of std_logic_vector (15 downto 0); - --- Temperature Sensor interface + -- Temperature Sensor interface type sensor_array_type is array (0 to 3) of integer range 0 to 2**16 - 1; - - end ftm_array_types; @@ -89,5 +86,5 @@ constant INT_CLK_FREQUENCY_2 : integer := 250000000; -- 250MHz constant LOW_FREQUENCY : integer := 1000000; -- has to be smaller than INT_CLK_FREQUENCY_1 - constant SCALER_FREQ_DIVIDER : integer := 3000; -- for simulation, should normally be 1 + constant SCALER_FREQ_DIVIDER : integer := 1; -- for simulation, should normally be 1 --FTM address and firmware ID @@ -272,20 +269,20 @@ X"000B", -- SD_ADDR_timemarker_delay -- timemarker delay X"000C", -- SD_ADDR_dead_time -- dead time - X"000D", -- SD_ADDR_cc_R0_HI -- clock conditioner R0 bits 31...16 - X"000E", -- SD_ADDR_cc_R0_LO -- clock conditioner R0 bits 15...0 - X"000F", -- SD_ADDR_cc_R1_HI -- clock conditioner R1 bits 31...16 - X"0010", -- SD_ADDR_cc_R1_LO -- clock conditioner R1 bits 15...0 - X"0011", -- SD_ADDR_cc_R8_HI -- clock conditioner R8 bits 31...16 - X"0012", -- SD_ADDR_cc_R8_LO -- clock conditioner R8 bits 15...0 - X"0013", -- SD_ADDR_cc_R9_HI -- clock conditioner R9 bits 31...16 - X"0014", -- SD_ADDR_cc_R9_LO -- clock conditioner R9 bits 15...0 - X"0015", -- SD_ADDR_cc_R11_HI -- clock conditioner R11 bits 31...16 - X"0016", -- SD_ADDR_cc_R11_LO -- clock conditioner R11 bits 15...0 - X"0017", -- SD_ADDR_cc_R13_HI -- clock conditioner R13 bits 31...16 - X"0018", -- SD_ADDR_cc_R13_LO -- clock conditioner R13 bits 15...0 - X"0019", -- SD_ADDR_cc_R14_HI -- clock conditioner R14 bits 31...16 - X"001A", -- SD_ADDR_cc_R14_LO -- clock conditioner R14 bits 15...0 - X"001B", -- SD_ADDR_cc_R15_HI -- clock conditioner R15 bits 31...16 - X"001C", -- SD_ADDR_cc_R15_LO -- clock conditioner R15 bits 15...0 + X"0003", -- SD_ADDR_cc_R0_HI -- clock conditioner R0 bits 31...16 + X"8000", -- SD_ADDR_cc_R0_LO -- clock conditioner R0 bits 15...0 + X"0001", -- SD_ADDR_cc_R1_HI -- clock conditioner R1 bits 31...16 + X"0101", -- SD_ADDR_cc_R1_LO -- clock conditioner R1 bits 15...0 + X"1000", -- SD_ADDR_cc_R8_HI -- clock conditioner R8 bits 31...16 + X"0908", -- SD_ADDR_cc_R8_LO -- clock conditioner R8 bits 15...0 + X"A003", -- SD_ADDR_cc_R9_HI -- clock conditioner R9 bits 31...16 + X"2A09", -- SD_ADDR_cc_R9_LO -- clock conditioner R9 bits 15...0 + X"0082", -- SD_ADDR_cc_R11_HI -- clock conditioner R11 bits 31...16 + X"000B", -- SD_ADDR_cc_R11_LO -- clock conditioner R11 bits 15...0 + X"020A", -- SD_ADDR_cc_R13_HI -- clock conditioner R13 bits 31...16 + X"000D", -- SD_ADDR_cc_R13_LO -- clock conditioner R13 bits 15...0 + X"0830", -- SD_ADDR_cc_R14_HI -- clock conditioner R14 bits 31...16 + X"280E", -- SD_ADDR_cc_R14_LO -- clock conditioner R14 bits 15...0 + X"1400", -- SD_ADDR_cc_R15_HI -- clock conditioner R15 bits 31...16 + X"FA0F", -- SD_ADDR_cc_R15_LO -- clock conditioner R15 bits 15...0 X"001D", -- SD_ADDR_coin_win_p -- majority coincidence window (for physics) X"001E", -- SD_ADDR_coin_win_c -- majority coincidence window (for calibration) @@ -319,12 +316,7 @@ constant width_PLC : integer := 6; -- counter width pulse duration - --- Timing counter + -- Timing counter constant tc_width : integer := 48; -- width (number of bits) of timing counter -constant zero : unsigned (tc_width - 1 downto 0) := (others => '0'); - - - - - + constant zero : unsigned (tc_width - 1 downto 0) := (others => '0'); + end ftm_constants; Index: firmware/FTM/ftu_control/FTM_ftu_control.vhd =================================================================== --- firmware/FTM/ftu_control/FTM_ftu_control.vhd (revision 10250) +++ firmware/FTM/ftu_control/FTM_ftu_control.vhd (revision 10256) @@ -109,5 +109,6 @@ -- list of active FTUs, read out from static RAM before starting to contact FTUs signal active_FTU_array_sig : active_FTU_array_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0')); - + --signal active_FTU_array_sig : active_FTU_array_type := ("0000000000000001", (others => '0'), (others => '0'), (others => '0')); + -- signals to count the number of responding FTUs (per crate and total) in case of a ping signal FTU_answer_array_sig : FTU_answer_array_type := (0,0,0,0); @@ -129,10 +130,12 @@ -- global signals after multiplexer - signal rx_en_sig : std_logic := '0'; - signal tx_en_sig : std_logic := '0'; - signal rx_valid_sig : std_logic := '0'; - signal tx_busy_sig : std_logic := '0'; - signal tx_start_sig : std_logic := '0'; - signal tx_data_sig : std_logic_vector (7 DOWNTO 0) := (others => '0'); + signal rx_en_sig : std_logic := '0'; + signal tx_en_sig : std_logic := '0'; + signal rx_valid_sig : std_logic := '0'; + signal tx_busy_sig : std_logic := '0'; + signal tx_start_sig : std_logic := '0'; + signal tx_data_sig : std_logic_vector (7 DOWNTO 0) := (others => '0'); + signal rx_busy_sig : std_logic := '0'; + signal start_int_sig : std_logic := '0'; -- signals for interpreter of FTU communication @@ -163,4 +166,5 @@ signal rx_valid_0_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_0 signal rx_data_0_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_ftu_rs485_interface_0 + signal rx_busy_0_sig : std_logic; -- initialized in FTU_rs485_interface_0 signal tx_start_1_sig : std_logic := '0'; @@ -169,5 +173,6 @@ signal rx_valid_1_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_1 signal rx_data_1_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_ftu_rs485_interface_1 - + signal rx_busy_1_sig : std_logic; -- initialized in FTU_rs485_interface_1 + signal tx_start_2_sig : std_logic := '0'; signal tx_data_2_sig : std_logic_vector (7 DOWNTO 0) := (others => '0'); @@ -175,5 +180,6 @@ signal rx_valid_2_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_2 signal rx_data_2_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_ftu_rs485_interface_2 - + signal rx_busy_2_sig : std_logic; -- initialized in FTU_rs485_interface_2 + signal tx_start_3_sig : std_logic := '0'; signal tx_data_3_sig : std_logic_vector (7 DOWNTO 0) := (others => '0'); @@ -181,5 +187,6 @@ signal rx_valid_3_sig : std_logic; -- initialized in FTM_ftu_rs485_interface_3 signal rx_data_3_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_ftu_rs485_interface_3 - + signal rx_busy_3_sig : std_logic; -- initialized in FTU_rs485_interface_3 + -- signals to control and read out CRC signal sel_crc_input_source_sig : std_logic := '0'; -- 0 -> FSM, 1 -> interpreter @@ -219,5 +226,5 @@ -- FPGA rx_data : OUT std_logic_vector (7 DOWNTO 0); - --rx_busy : OUT std_logic := '0'; + rx_busy : OUT std_logic := '0'; rx_valid : OUT std_logic := '0'; tx_data : IN std_logic_vector (7 DOWNTO 0); @@ -277,5 +284,6 @@ type FTM_ftu_rs485_control_StateType is (INIT, IDLE, ACTIVE_LIST, READ_CONFIG, TRANSMIT_CONFIG, - PING, PING_END, FTU_LIST, RATES, + PING, PING_END, FTU_LIST, + RATES, RATES_1, RATES_2, RATES_3, READ_CONFIG_1, READ_CONFIG_2, READ_CONFIG_3, TRANSMIT_CONFIG_1, TRANSMIT_CONFIG_2, TRANSMIT_CONFIG_3, @@ -285,5 +293,5 @@ begin - + Inst_FTM_fTU_rs485_interface_0 : FTM_ftu_rs485_interface -- crate 0 port map( @@ -296,5 +304,5 @@ -- FPGA rx_data => rx_data_0_sig, - --rx_busy => , + rx_busy => rx_busy_0_sig, rx_valid => rx_valid_0_sig, tx_data => tx_data_0_sig, @@ -313,5 +321,5 @@ -- FPGA rx_data => rx_data_1_sig, - --rx_busy => , + rx_busy => rx_busy_1_sig, rx_valid => rx_valid_1_sig, tx_data => tx_data_1_sig, @@ -330,5 +338,5 @@ -- FPGA rx_data => rx_data_2_sig, - --rx_busy => , + rx_busy => rx_busy_2_sig, rx_valid => rx_valid_2_sig, tx_data => tx_data_2_sig, @@ -347,5 +355,5 @@ -- FPGA rx_data => rx_data_3_sig, - --rx_busy => , + rx_busy => rx_busy_3_sig, rx_valid => rx_valid_3_sig, tx_data => tx_data_3_sig, @@ -369,5 +377,5 @@ clk => clk_50MHz, data_block => rec_block_sig, - block_valid => rec_valid_sig, + block_valid => start_int_sig, crc => crc_sig, FTU_brd_add => FTU_brd_add_sig, @@ -427,4 +435,5 @@ ping_all_started <= '1'; read_rates_started <= '0'; + rec_reset_sig <= '1'; FTM_ftu_rs485_control_State <= PING; elsif (new_config = '0' and ping_all = '0' and read_rates = '1') then @@ -486,4 +495,5 @@ FTU_register_cnt <= 0; if (active_FTU_array_sig(crate_cnt)(FTU_cnt) = '1') then + rec_reset_sig <= '1'; FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG; else @@ -644,5 +654,5 @@ end if; end if; - + when PING => -- ping all FTUs rec_reset_sig <= '0'; @@ -679,7 +689,9 @@ when PING_1 => -- wait one cycle for CRC calculation enable_crc_from_FSM_sig <= '0'; + rec_reset_sig <= '1'; FTM_ftu_rs485_control_State <= PING_2; when PING_2 => -- transmit byte by byte + rec_reset_sig <= '0'; if (tx_busy_sig = '0') then if (frame_cnt < 27) then @@ -789,4 +801,9 @@ ping_all_done <= '1'; sel_crate_sig <= "111"; + FTU_answer_array_sig(0) <= 0; + FTU_answer_array_sig(1) <= 0; + FTU_answer_array_sig(2) <= 0; + FTU_answer_array_sig(3) <= 0; + no_of_FTU_answer_sig <= 0; FTM_ftu_rs485_control_State <= IDLE; end if; @@ -818,6 +835,91 @@ when RATES => -- read all FTU rates - FTM_ftu_rs485_control_State <= IDLE; - + rec_reset_sig <= '0'; + if (crate_cnt < NO_OF_CRATES) then + sel_crate_sig <= conv_std_logic_vector(crate_cnt, 3); + if (FTU_cnt < NO_OF_FTUS_PER_CRATE) then + FTU_cnt <= FTU_cnt + 1; + if (active_FTU_array_sig(crate_cnt)(FTU_cnt) = '1') then + enable_crc_from_FSM_sig <= '1'; + crc_data_from_FSM_sig <= "00000000" + & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" + & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" + & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" + & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" & "00000000" + & "00000010" & FIRMWARE_ID & FTM_ADDRESS + & "00" & conv_std_logic_vector(FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2) + & FTU_RS485_START_DELIM; + FTU_brd_add_sig <= conv_std_logic_vector(FTU_cnt,4) & conv_std_logic_vector(crate_cnt,2); + FTU_command_sig <= "00000010"; + FTM_ftu_rs485_control_State <= RATES_1; + else + FTM_ftu_rs485_control_State <= RATES; + end if; + else + crate_cnt <= crate_cnt + 1; + FTU_cnt <= 0; + FTM_ftu_rs485_control_State <= RATES; + end if; + else + crate_cnt <= 0; + read_rates_started <= '0'; + read_rates_done <= '1'; + sel_crate_sig <= "111"; + FTM_ftu_rs485_control_State <= IDLE; + end if; + + when RATES_1 => -- wait one cycle for CRC calculation + enable_crc_from_FSM_sig <= '0'; + FTM_ftu_rs485_control_State <= RATES_2; + + when RATES_2 => -- transmit byte by byte + if (tx_busy_sig = '0') then + if (frame_cnt < 27) then + frame_cnt <= frame_cnt + 1; + tx_data_sig <= crc_data_from_FSM_sig (7 downto 0); + crc_data_from_FSM_sig <= "00000000" & crc_data_from_FSM_sig ((FTU_RS485_BLOCK_WIDTH - 9) downto 8); + tx_start_sig <= '1'; + FTM_ftu_rs485_control_State <= RATES_2; + elsif (frame_cnt = 27) then + frame_cnt <= frame_cnt + 1; + tx_data_sig <= crc_sig; + tx_start_sig <= '1'; + FTM_ftu_rs485_control_State <= RATES_2; + else + frame_cnt <= 0; + reset_crc_from_FSM_sig <= '1'; + FTM_ftu_rs485_control_State <= RATES_3; + end if; + else + tx_start_sig <= '0'; + FTM_ftu_rs485_control_State <= RATES_2; + end if; + + when RATES_3 => -- wait for FTU answer + reset_crc_from_FSM_sig <= '0'; + if (FTU_answer_ok_sig = '1') then + timeout_cnt <= 0; + sel_crc_input_source_sig <= '0'; + FTM_ftu_rs485_control_State <= RATES; + else + if (timeout_cnt < FTU_RS485_TIMEOUT) then + timeout_cnt <= timeout_cnt + 1; + sel_crc_input_source_sig <= '1'; + FTM_ftu_rs485_control_State <= RATES_3; + else + timeout_cnt <= 0; + sel_crc_input_source_sig <= '0'; + rec_reset_sig <= '1'; + if (retry_cnt < FTU_RS485_NO_OF_RETRY) then + retry_cnt <= retry_cnt + 1; + FTU_cnt <= FTU_cnt - 1; -- repeat this FTU + FTM_ftu_rs485_control_State <= RATES; + else + FTU_cnt <= FTU_cnt; -- move on + FTM_ftu_rs485_control_State <= RATES; + end if; + end if; + end if; + end case; end if; @@ -831,4 +933,5 @@ rx_data_0_sig, rx_data_1_sig, rx_data_2_sig, rx_data_3_sig, tx_busy_0_sig, tx_busy_1_sig, tx_busy_2_sig, tx_busy_3_sig, + rx_busy_0_sig, rx_busy_1_sig, rx_busy_2_sig, rx_busy_3_sig, tx_start_sig, tx_data_sig) begin @@ -840,4 +943,5 @@ rec_data_sig <= rx_data_0_sig; tx_busy_sig <= tx_busy_0_sig; + rx_busy_sig <= rx_busy_0_sig; tx_start_0_sig <= tx_start_sig; tx_start_1_sig <= '0'; @@ -854,4 +958,5 @@ rec_data_sig <= rx_data_1_sig; tx_busy_sig <= tx_busy_1_sig; + rx_busy_sig <= rx_busy_1_sig; tx_start_0_sig <= '0'; tx_start_1_sig <= tx_start_sig; @@ -868,4 +973,5 @@ rec_data_sig <= rx_data_2_sig; tx_busy_sig <= tx_busy_2_sig; + rx_busy_sig <= rx_busy_2_sig; tx_start_0_sig <= '0'; tx_start_1_sig <= '0'; @@ -882,4 +988,5 @@ rec_data_sig <= rx_data_3_sig; tx_busy_sig <= tx_busy_3_sig; + rx_busy_sig <= rx_busy_3_sig; tx_start_0_sig <= '0'; tx_start_1_sig <= '0'; @@ -896,4 +1003,5 @@ rec_data_sig <= (others => '0'); tx_busy_sig <= '0'; + rx_busy_sig <= '0'; tx_start_0_sig <= '0'; tx_start_1_sig <= '0'; @@ -933,4 +1041,5 @@ crc_sig <= crc_sig_inv(0) & crc_sig_inv(1) & crc_sig_inv(2) & crc_sig_inv(3) & crc_sig_inv(4) & crc_sig_inv(5) & crc_sig_inv(6) & crc_sig_inv(7); + start_int_sig <= rec_valid_sig and (not rx_busy_sig); -- avoid continuing to early after FTU answer end Behavioral; Index: firmware/FTM/ftu_control/FTM_ftu_rs485_interface.vhd =================================================================== --- firmware/FTM/ftu_control/FTM_ftu_rs485_interface.vhd (revision 10250) +++ firmware/FTM/ftu_control/FTM_ftu_rs485_interface.vhd (revision 10256) @@ -17,5 +17,5 @@ library ftm_definitions; --- USE ftm_definitions.ftm_array_types.all; +USE ftm_definitions.ftm_array_types.all; USE ftm_definitions.ftm_constants.all; @@ -34,5 +34,5 @@ -- FPGA rx_data : OUT std_logic_vector (7 DOWNTO 0); - --rx_busy : OUT std_logic := '0'; + rx_busy : OUT std_logic := '0'; rx_valid : OUT std_logic := '0'; tx_data : IN std_logic_vector (7 DOWNTO 0); @@ -122,5 +122,5 @@ rx_en <= flow_ctrl; rx_data <= rx_sr; - --rx_busy <= '1' when (rx_bitcnt < 11) else '0'; + rx_busy <= '1' when (rx_bitcnt < 11) else '0'; END ARCHITECTURE beha;