Changeset 10258
- Timestamp:
- 03/24/11 15:00:51 (14 years ago)
- Location:
- firmware/FTM
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd
r10250 r10258 138 138 139 139 signal cc_R0_sig : std_logic_vector (31 downto 0); 140 signal cc_R1_sig : std_logic_vector (31 downto 0); 140 signal cc_R1_sig : std_logic_vector (31 downto 0); 141 142 signal cc_R2_sig : std_logic_vector (31 downto 0); 143 signal cc_R3_sig : std_logic_vector (31 downto 0); 144 signal cc_R4_sig : std_logic_vector (31 downto 0); 145 signal cc_R5_sig : std_logic_vector (31 downto 0); 146 signal cc_R6_sig : std_logic_vector (31 downto 0); 147 signal cc_R7_sig : std_logic_vector (31 downto 0); 148 149 141 150 signal cc_R8_sig : std_logic_vector (31 downto 0); 142 151 signal cc_R9_sig : std_logic_vector (31 downto 0); -
firmware/FTM/ftm_definitions.vhd
r10257 r10258 50 50 51 51 -- data array for clock conditioner interface 52 type clk_cond_array_type is array (0 to 1 4) of std_logic_vector (31 downto 0);52 type clk_cond_array_type is array (0 to 13) of std_logic_vector (31 downto 0); 53 53 54 54 -- network array types
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