Index: firmware/FTM/clock/FTM_clk_gen_2.vhd =================================================================== --- firmware/FTM/clock/FTM_clk_gen_2.vhd (revision 10366) +++ firmware/FTM/clock/FTM_clk_gen_2.vhd (revision 10366) @@ -0,0 +1,163 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: Q. Weitzel +-- +-- Create Date: February 28, 2011 +-- Design Name: +-- Module Name: FTM_clk_gen_2 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: interface to different DCMs and clk dividers for FMU board +-- add here more DCMs if needed +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FTM_clk_gen_2 is + Port ( + clk : IN STD_LOGIC; + rst : IN STD_LOGIC; + clk_1 : OUT STD_LOGIC; + clk_50 : OUT STD_LOGIC; + clk_250 : OUT STD_LOGIC; + clk_250_ps : OUT STD_LOGIC; + ready : OUT STD_LOGIC + ); +end FTM_clk_gen_2; + +architecture Behavioral of FTM_clk_gen_2 is + + component FTM_dcm_40M_to_50M_2 + port( + CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic; + LOCKED_OUT : out std_logic + ); + end component; + + component FTM_dcm_50M_to_250M_2 + port( + CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKFX180_OUT : out std_logic; + CLK0_OUT : out std_logic; + LOCKED_OUT : out std_logic + ); + end component; + + component Clock_Divider + port( + clock_in : IN STD_LOGIC; + clock_out : OUT STD_LOGIC + ); + end component; + + signal clk_1M_sig : std_logic; + signal clk_50M_sig : std_logic; + signal clk_250M_sig : std_logic; + signal clk_250M_ps_sig : std_logic; + + signal clk_50M_int_sig : std_logic; + signal dcm1_ibufg_sig : std_logic; + + signal dcm1_locked : std_logic; + signal dcm2_locked : std_logic; + +begin + + Inst_FTM_dcm_40M_to_50M_2 : FTM_dcm_40M_to_50M_2 + port map( + CLKIN_IN => clk, + RST_IN => rst, + CLKFX_OUT => clk_50M_int_sig, + CLKIN_IBUFG_OUT => dcm1_ibufg_sig, + LOCKED_OUT => dcm1_locked + ); + + Inst_FTM_dcm_50M_to_250M_2 : FTM_dcm_50M_to_250M_2 + port map( + CLKIN_IN => clk_50M_int_sig, + RST_IN => rst, + CLKFX_OUT => clk_250M_sig, + CLKFX180_OUT => clk_250M_ps_sig, + CLK0_OUT => clk_50M_sig, + LOCKED_OUT => dcm2_locked + ); + + Inst_Clock_Divider : Clock_Divider + port map ( + clock_in => clk_50M_sig, + clock_out => clk_1M_sig + ); + + clk_1 <= clk_1M_sig; + clk_50 <= clk_50M_sig; + clk_250 <= clk_250M_sig; + clk_250_ps <= clk_250M_ps_sig; + + ready <= dcm1_locked and dcm2_locked; + +end Behavioral; + +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library ftm_definitions; +USE ftm_definitions.ftm_array_types.all; +USE ftm_definitions.ftm_constants.all; + +entity Clock_Divider is + generic( + divider : integer := INT_CLK_FREQUENCY_1 / LOW_FREQUENCY + ); + port( + clock_in : in std_logic; + clock_out : out std_logic := '0' + ); +end entity Clock_Divider; + +architecture RTL of Clock_Divider is + +begin + + process (clock_in) + variable Z: integer range 0 to divider - 1; + begin + if rising_edge(clock_in) then + if (Z < divider - 1) then + Z := Z + 1; + else + Z := 0; + end if; + if (Z = 0) then + clock_out <= '1'; + end if; + if (Z = divider / 2) then + clock_out <= '0'; + end if; + end if; + end process; + +end architecture RTL; Index: firmware/FTM/clock/FTM_dcm_40M_to_50M_2.vhd =================================================================== --- firmware/FTM/clock/FTM_dcm_40M_to_50M_2.vhd (revision 10366) +++ firmware/FTM/clock/FTM_dcm_40M_to_50M_2.vhd (revision 10366) @@ -0,0 +1,90 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 11.5 +-- \ \ Application : xaw2vhdl +-- / / Filename : FTM_dcm_40M_to_50M_2.vhd +-- /___/ /\ Timestamp : 04/12/2011 10:54:35 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st /ihp/home01/qweitzel/FPGA/trac-ISDC.svn/firmware/FTM/clock/FTM_dcm_40M_to_50M_2.xaw /ihp/home01/qweitzel/FPGA/trac-ISDC.svn/firmware/FTM/clock/FTM_dcm_40M_to_50M_2 +--Design Name: FTM_dcm_40M_to_50M_2 +--Device: xc3sd3400a-4fg676 +-- +-- Module FTM_dcm_40M_to_50M_2 +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST +-- Period Jitter (unit interval) for block DCM_SP_INST = 0.04 UI +-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.86 ns + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity FTM_dcm_40M_to_50M_2 is + port ( CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic; + LOCKED_OUT : out std_logic); +end FTM_dcm_40M_to_50M_2; + +architecture BEHAVIORAL of FTM_dcm_40M_to_50M_2 is + signal CLKFX_BUF : std_logic; + signal CLKIN_IBUFG : std_logic; + signal GND_BIT : std_logic; +begin + GND_BIT <= '0'; + CLKIN_IBUFG_OUT <= CLKIN_IBUFG; + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + CLKIN_IBUFG_INST : IBUFG + port map (I=>CLKIN_IN, + O=>CLKIN_IBUFG); + + DCM_SP_INST : DCM_SP + generic map( CLK_FEEDBACK => "NONE", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 4, + CLKFX_MULTIPLY => 5, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 25.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>GND_BIT, + CLKIN=>CLKIN_IBUFG, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>RST_IN, + CLKDV=>open, + CLKFX=>CLKFX_BUF, + CLKFX180=>open, + CLK0=>open, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>LOCKED_OUT, + PSDONE=>open, + STATUS=>open); + +end BEHAVIORAL; + + Index: firmware/FTM/clock/FTM_dcm_40M_to_50M_2.xaw =================================================================== --- firmware/FTM/clock/FTM_dcm_40M_to_50M_2.xaw (revision 10366) +++ firmware/FTM/clock/FTM_dcm_40M_to_50M_2.xaw (revision 10366) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.5e +$93x16=(aaz$dbcj00-rs`osrlf$J]IN/upbg(OTLJ$xzc!iisotewc(N]G$oaalk.DWIZbdeV>;ARz`_42N[7(i~;0<95?.167?5(?>81:86?>.4:853!oK92;=6<9;37-45663=808=?4539642=FZJB\EW?8;@PT^ZIIDPUHM^MNDHLD[FJL911J^ZTPOONZ[FJLAGUNTYK]N@N21>GU_SUDBAWPCMIJJZPFD\O:n6O]W[]LJI_XLJGT_ZG[CIKMCZEKC8:0M_YU_NLO]ZBCZVI;==5NRVX\KKJ^WMNYSN?>1:CQS_YHFESTHI\PCMI22>GU_SUDBAWPDEP\BIOWNEE[=85NRVX\KKJ^WOHTIUZJROCO57=FZ^PTCCBV_HLPPZHREl1J^ZTPOONZ[UKDL8?0M_YU_NLO]ZTB[L^T@BIFC0:8EWQ]WFDGURXNLHF\@CUXEFNNm6O\SNA\SLROn2K\VRMCKCWEP\VB9890MZTPCMI\KPRW]]U_U]Kl;@UY[CJH_]S[I55NW[]SEWRc3H]QS^WATIVLKI22IGG<6?6:AOO717=2IGG?V7;BNH6]7?8<1H@F7?5:AOOAPd3JF@H[QKIWKGA0=DDBLI96MCKGZ;?FJLNQ;3<45LLJD[[GSAn2IGGKVPBTDD[LHT\j1H@FHW_EKUMACb3JF@JUQBUMVJTI_>3JF@JUQ@UU78GIMNF8;0OAEFN^FJRLBBWKST>o5LLJKM[LDRNN;;7NBDIO]JFP@@W@DXXk5LLJKM[LDRNNUDYY64CMIJJZOIk2IGGD@PPDPJKAcEUMH^NH;5KCL]PTg=CKDUX\RGASUf8@@ULM^UJHG[\T008@CUXN[OZYH@LY^OL@@753MFGSK\JQTGMG\YJGMO>7I]\EO36?ASSQVIROAKPCNPQAFRNGG=0HRXNLTG;?@^SM[DJ@l5IABVLV\YMN<1MMA]J9:DA[VIRZJO27KGA_TLJPV>KX^HF^I:5AEUULVN2VTKEA=7]]KOOG7?UUBF11[_D@LDDA0?WUS>2XXXRGAb:QJC@^SM[DJ@;5\IOEOAf=T\HX_Y]QXAHV5?VRF\\Y:>6]VSUGN[V_IKAXDBB[\3:VLT1=SZ\O37X]J_CWEC<=R[LUIYKI\5:TJAR7e3QK\S[K]SHMM5a=_AECET VKB!2-5%US]K*;"<.NSBKJ2>^cjVCo==5Wdl]Neoiu^lxxeb`>0:ZgiZKnffx]i}foo78_5<7U<1P<79R4:cqs5;ya0wa5389k&8ki97718|vrzHIz8<6NOx18E>7<6sZ9n6:l57e8277bd4=i?10>7)99:678yV5c2>h1;i4>33f`0f<64}T;l0hi:5yT6194?7=93=p_>k57c84`?74:mi?o7?;cd58f3`=83:1?79t$e84g>"6m3=n7)?i:6d8 76=091/;94:;c63>5<6;3:175<,881>>5+12810>"6<3887)?::4f8 40=>k1/=:4;;%3;>0d<,831845+1`815>"4k3?i7)3-9:6o5+3587=>"41320(>o5469'7g<2j2.?=78j;%65>1=#<;0>;6*;3;74?!222>:0(9656:&7e?3e3->i6864$5f91==#i7?4$7a90<=#?80<>6*>0;c8 4b=6=n;:0;6)8>:6;8 35=?910e?l50;&55?1>3-<;6:>4$71935=:07d89:18'24<012.=<79?;:k53?6=,?;1;45+61844>=n>=0;6)8>:6;8 36=?910e9:50;&55?1>3-<;6:>4;n00>5<#>80<565`2983>!062>307b<;:18'24<0121d>84?:%42>2?<3f826=4+6084=>=h:?0;6)8>:6;8?j40290/:<489:9l6f<72-<:6:74$71935=#9j09>65`2e83>!062>307b8k:18'24<0i2.>j79?;:m61?6=,?;1;45+62844>=h><0;6)8>:6;8?xd4>3:1>7>50z&56?363`?;6=4+6084=>"1;3=;76a:c;29 37=?01/:>480:9~f7`=8381<7>t$70967=n=90;6)8>:6;8 35=?910c8m50;&55?1>3-<86:>4;|q01?6=:r7?<7=<;<15>0e<,8h1?:5rs7;94?7|5=:1:55+6`864>{t:l0;6?u24181g>;5n3?;7p}:6;295~;383?>7)8n:4a8yv5?290:w0=9:428 3g==91v><50;3x97`==j1/:l4:c:p72<729q/:l4:c:~j74=83;pqc<<:182xh5<3:1=vsa2483>4}zf;<1<7?t}o04>5<6std947>51z~yxFGKr9;6io8863bexFGJr:vLM^t}AB Index: firmware/FTM/clock/FTM_dcm_40M_to_50M_2_arwz.ucf =================================================================== --- firmware/FTM/clock/FTM_dcm_40M_to_50M_2_arwz.ucf (revision 10366) +++ firmware/FTM/clock/FTM_dcm_40M_to_50M_2_arwz.ucf (revision 10366) @@ -0,0 +1,17 @@ +# Generated by Xilinx Architecture Wizard +# --- UCF Template Only --- +# Cut and paste these attributes into the project's UCF file, if desired +INST DCM_SP_INST CLK_FEEDBACK = NONE; +INST DCM_SP_INST CLKDV_DIVIDE = 2.0; +INST DCM_SP_INST CLKFX_DIVIDE = 4; +INST DCM_SP_INST CLKFX_MULTIPLY = 5; +INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; +INST DCM_SP_INST CLKIN_PERIOD = 25.000; +INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; +INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; +INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; +INST DCM_SP_INST FACTORY_JF = C080; +INST DCM_SP_INST PHASE_SHIFT = 0; +INST DCM_SP_INST STARTUP_WAIT = FALSE; Index: firmware/FTM/clock/FTM_dcm_50M_to_250M_2.vhd =================================================================== --- firmware/FTM/clock/FTM_dcm_50M_to_250M_2.vhd (revision 10366) +++ firmware/FTM/clock/FTM_dcm_50M_to_250M_2.vhd (revision 10366) @@ -0,0 +1,97 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 11.5 +-- \ \ Application : xaw2vhdl +-- / / Filename : FTM_dcm_50M_to_250M_2.vhd +-- /___/ /\ Timestamp : 04/12/2011 10:57:30 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st /ihp/home01/qweitzel/FPGA/trac-ISDC.svn/firmware/FTM/clock/FTM_dcm_50M_to_250M_2.xaw /ihp/home01/qweitzel/FPGA/trac-ISDC.svn/firmware/FTM/clock/FTM_dcm_50M_to_250M_2 +--Design Name: FTM_dcm_50M_to_250M_2 +--Device: xc3sd3400a-4fg676 +-- +-- Module FTM_dcm_50M_to_250M_2 +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST +-- Period Jitter (unit interval) for block DCM_SP_INST = 0.17 UI +-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.69 ns + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity FTM_dcm_50M_to_250M_2 is + port ( CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKFX180_OUT : out std_logic; + CLK0_OUT : out std_logic; + LOCKED_OUT : out std_logic); +end FTM_dcm_50M_to_250M_2; + +architecture BEHAVIORAL of FTM_dcm_50M_to_250M_2 is + signal CLKFB_IN : std_logic; + signal CLKFX_BUF : std_logic; + signal CLKFX180_BUF : std_logic; + signal CLK0_BUF : std_logic; + signal GND_BIT : std_logic; +begin + GND_BIT <= '0'; + CLK0_OUT <= CLKFB_IN; + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + CLKFX180_BUFG_INST : BUFG + port map (I=>CLKFX180_BUF, + O=>CLKFX180_OUT); + + CLK0_BUFG_INST : BUFG + port map (I=>CLK0_BUF, + O=>CLKFB_IN); + + DCM_SP_INST : DCM_SP + generic map( CLK_FEEDBACK => "1X", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 1, + CLKFX_MULTIPLY => 5, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 20.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>CLKFB_IN, + CLKIN=>CLKIN_IN, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>RST_IN, + CLKDV=>open, + CLKFX=>CLKFX_BUF, + CLKFX180=>CLKFX180_BUF, + CLK0=>CLK0_BUF, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>LOCKED_OUT, + PSDONE=>open, + STATUS=>open); + +end BEHAVIORAL; + + Index: firmware/FTM/clock/FTM_dcm_50M_to_250M_2.xaw =================================================================== --- firmware/FTM/clock/FTM_dcm_50M_to_250M_2.xaw (revision 10366) +++ firmware/FTM/clock/FTM_dcm_50M_to_250M_2.xaw (revision 10366) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.5e +$95x11=(aaz$dbcj00-rs`osrlf$J]IN/upbg(OTLJ$xzc!iisotewc(N]G$oaalk.DWIZbdeV?;ARz`_373IZ4)ph}:7=:40/340>6)>0;0=95>1/7;?40 `J:3X0912>47&9:;?6<:00975>353<:<7L\LHVKY52=FZ^PTCCBV_BCPGDBNFNUH@F?7;@PT^ZIIDPUH@FGA_DZWAWHFD8?0M_YU_NLO]ZEKC@DTZLBZE0`8EWQ]WFDGURJLM^QTMQEOAGMTOAE>0:CQS_YHFESTHI\PC133?DTPRVEE@TQKDS]@5475:CQS_YHFEST^H]JT^NLCLE602KY[WQ@NM[\RDJNLVNM_RC@DDc8EVUHKV]BXEh4AVX\GIME]O^R\H?>6:CT^ZEKCK_MXT^J1^LLAAOS9:1J[WQLLJ]LQQVR\V^R\Hm4AVX\BIIP\PZN46OXZ^RBVQb:>7NBD2Y:8GIM5P82;96MCK826?FJLL_i0OAEKV^FJRLBB=2IGGKL7;BNHBGYNF<1H@FHW8:AOOC^609i0OAEIX0:3[GSA9;1H@FHW192\FP@@W@DXXn5LLJD[5=6XG\^27NBDFY]AQC`EKCF__S]FNSD]PLL@Sk2IGGRHJEE@BGN?2:FOHZ@UMX_NBNWPMNFF1>BT[LD:96JZTX]@]FJBWJEY^HM[INL4?AYQIE_Nm6HNCUMQ]ZLA=2LJ@^K6;G@\WJSUKLi0JHKKB@AH[GSA12LBBR[AIUQ;?CIR\VY_^l5IOTV\QKOS[h1MCXZPV@NVA4=N02CEXH\AAM32?OOS\LXTEC^ZT^VZT@eLN\]OYS[OCUD48HJELMMk0@BMDEE]LQQ51EIYY@RJ68JJHB92E37BHKDSASAg=W@HYNS^FFFU;8TLHOIZH^_l5_IOKPCKBBL11[ECYFDUJ;?UTNE]S[I<>4PSMS[UOIAZKHXDXJ5:RPGIM13YYOCCK;;QQFJ==W[@DHHHM<;SQW2>TT\VCEn6]FGDZWAWHFD?1XECICEb9PPDTS]YU\MDZ9;RVBPPU6:2YR_YKB_R[MGMTHFF_X?6Z@P59WVPC?3\YNSO[IG89VW@YE]OMX96XFEV3a?]GPW_OY_DAA1e9[MIOIP$RON->!1!QWQG&7&8*J_NGF6:ZgfZOc991Sh`QBakmqR`ttafd:<6Vkm^OjjjtQm{ybcc;4[183Y0=\83=V86o}w{18`fke3oydaa 0,30>pole;:7um4>33f`0f<6=7=0:0:??jl4b820`c63m2:6=4>:0yP0142b9k1}X:750;395?g|[=>14<473;306ae3k3;?i33-8:65;4$309<3=#?h0>7o:9:1827?6=8r.=47::;%d96`=#990<=6*>2;06?!742;?0(<:5289'50<5=2.::78<;%34>27<,82186*>9;42?!7f2=l0("3?3=?7):k:59'0=<2l2.?m7;k;%6`>20<,=o1:6*:0;74?!352"1<3;0(:<54g9'32<002.:=7j4$0d90<=#=h097);6:29j7f<72-<<6:h4$7;933=2><07d8j:18'22<0n2.=5799;:k5g?6=,?=1;k5+67842>=n>m0;6)88:6d8 30=??10e;o50;&53?1a3-<=6:84;h6a>5<#>>0i5=3:1(;957g9'2<<0>2.:h7<;;%3f>07<3f8o6=4+6684b>=h:00;6)88:6d8?j4f290/::48f:9l6`<72-<<6:h4;n0a>5<#>>0!002>l07b==:18'22<0n2.=5799;%3g>72<3f986=4+6684b>"113==7)?k:368?j14290/::470:&51?1132e>n7>5$7593c=#>00<:65`6c83>!002>l07pl=7;296?6=8r.=47<;;h75>5<#>>0i1:3:1(;957g9'2<<0>21vn>650;094?6|,?21>95f5783>!002>l0(;757798k34=83.=;79i;%4:>20<3th897>52;294~"1038?7d;9:18'22<0n2.=5799;:m56?6=,?=1;k5+68842>=z{:o1<7?t=5497f=#?90>:6s|3083>7}:5579~w70=838p1985249>62<2>2wx?:4?:3y>03<4:27847;9;|q00?6=:r7?:7=<;<16>00{<65>0d<,>:1:?5rs2`94?7|5:21:?5+71856>{t;?0;6"083<97p}=8;294~"083<97psa2483>4}zf;<1<7?t}o04>5<6std947>51zm6<<728qvb?o50;3xyk4e290:wp`=c;295~{i:m0;6