Index: firmware/FTM/FTM_central_control.vhd =================================================================== --- firmware/FTM/FTM_central_control.vhd (revision 10328) +++ firmware/FTM/FTM_central_control.vhd (revision 10366) @@ -35,4 +35,5 @@ port( clk : IN std_logic; + clk_ready : in std_logic; clk_scaler : IN std_logic; new_config : IN std_logic; @@ -60,5 +61,7 @@ config_start_cc : out std_logic := '0'; config_started_cc : in std_logic; - config_ready_cc : in std_logic + config_ready_cc : in std_logic; + config_trigger : out std_logic := '0'; + config_trigger_done : in std_logic ); end FTM_central_control; @@ -82,4 +85,5 @@ CP_CONFIG_FTU, CP_CONFIG_FTU_01, CP_CONFIG_SCALER, CP_CONFIG_SCALER_01, + CP_CONFIG_TRIGGER, CP_CONFIG_TRIGGER_01, CP_IDLE, CP_PING, CP_READ_RATES, CP_READ_RATES_01, CP_SEND_START, CP_SEND_END); @@ -94,6 +98,8 @@ when CP_INIT => - state_central_proc <= CP_CONFIG; - + if (clk_ready = '1') then + state_central_proc <= CP_CONFIG; + end if; + when CP_CONFIG_START => if (config_started_ack = '1') then @@ -154,4 +160,15 @@ wait_cnt_sig <= 0; reset_scaler_sig <= '0'; + state_central_proc <= CP_CONFIG_TRIGGER; + end if; + + when CP_CONFIG_TRIGGER => + --config trigger_manager block + config_trigger <= '1'; + state_central_proc <= CP_CONFIG_TRIGGER_01; + + when CP_CONFIG_TRIGGER_01 => + config_trigger <= '0'; + if (config_trigger_done = '1') then state_central_proc <= CP_IDLE; end if; Index: firmware/FTM/FTM_top.vhd =================================================================== --- firmware/FTM/FTM_top.vhd (revision 10328) +++ firmware/FTM/FTM_top.vhd (revision 10366) @@ -89,8 +89,8 @@ -- on IO-Bank 2 ------------------------------------------------------------------------------- - -- Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0 - -- Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1 - -- Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2 - -- Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3 + Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0 + Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1 + Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2 + Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3 @@ -98,6 +98,6 @@ ------------------------------------------------------------------------------ -- on IO-Bank 3 - -- ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input - -- Veto : in STD_LOGIC; -- trigger veto input + ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input + Veto : in STD_LOGIC; -- trigger veto input -- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs @@ -186,8 +186,8 @@ -- on IO-Bank 3 ------------------------------------------------------------------------------- - -- Busy0 : in STD_LOGIC; - -- Busy1 : in STD_LOGIC; - -- Busy2 : in STD_LOGIC; - -- Busy3 : in STD_LOGIC; + Busy0 : in STD_LOGIC; + Busy1 : in STD_LOGIC; + Busy2 : in STD_LOGIC; + Busy3 : in STD_LOGIC; @@ -215,9 +215,9 @@ -- RES_n : out STD_LOGIC; -- RES- IO-Bank 0 - -- TRG_p : out STD_LOGIC; -- TRG+ Trigger - -- TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0 - - -- TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker - -- TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2 + TRG_p : out STD_LOGIC; -- TRG+ Trigger + TRG_n : out STD_LOGIC; -- TRG- IO-Bank 0 + + TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker + TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2 TIM_Sel : out STD_LOGIC -- Time Marker selector on IO-Bank 2 @@ -336,7 +336,21 @@ signal dd_send_ack_sig : std_logic := '1'; signal dd_send_ready_sig : std_logic := '1'; + --very new stuff + SIGNAL ftu_error_send_ack_sig : std_logic := '1'; + SIGNAL ftu_error_send_ready_sig : std_logic := '1'; + SIGNAL ftu_error_calls_sig : std_logic_vector(15 DOWNTO 0) := X"0000"; + SIGNAL ftu_error_data_sig : std_logic_vector(223 DOWNTO 0) := (others => '0'); + SIGNAL ftu_error_send_sig : std_logic := '0'; + signal prescaling_FTU01_sig : std_logic_vector (15 DOWNTO 0); + signal trigger_counter_sig : std_logic_vector (31 DOWNTO 0); + signal trigger_counter_read_sig : std_logic; + signal trigger_counter_valid_sig : std_logic; + signal config_start_cc_sig : std_logic := '0'; signal config_started_cc_sig : std_logic := '0'; signal config_ready_cc_sig : std_logic := '0'; + + signal config_trigger_sig : std_logic; + signal config_trigger_done_sig : std_logic; signal clk_buf_sig : std_logic; @@ -349,7 +363,22 @@ signal reset_sig : STD_LOGIC := '0'; -- initialize to 0 on power-up + signal trigger_signal_sig : std_logic := '0'; + signal TIM_signal_sig : std_logic := '0'; + signal led_sig : std_logic_vector(7 downto 0) := (others => '0'); - component FTM_clk_gen +-- component FTM_clk_gen +-- port( +-- clk : IN STD_LOGIC; +-- rst : IN STD_LOGIC; +-- clk_1 : OUT STD_LOGIC; +-- clk_50 : OUT STD_LOGIC; +-- clk_250 : OUT STD_LOGIC; +-- clk_250_ps : OUT STD_LOGIC; +-- ready : OUT STD_LOGIC +-- ); +-- end component; + + component FTM_clk_gen_2 port( clk : IN STD_LOGIC; @@ -362,5 +391,60 @@ ); end component; - + + component trigger_manager + port( + --clocks + clk_50MHz : in std_logic; + clk_250MHz : in std_logic; + clk_250MHz_180 : in std_logic; + --trigger primitives from FTUs + trig_prim_0 : in std_logic_vector(9 downto 0); --crate 0 + trig_prim_1 : in std_logic_vector(9 downto 0); --crate 1 + trig_prim_2 : in std_logic_vector(9 downto 0); --crate 2 + trig_prim_3 : in std_logic_vector(9 downto 0); --crate 3 + --external signals + ext_trig_1 : in std_logic; + ext_trig_2 : in std_logic; + ext_veto : in std_logic; + FAD_busy_0 : in std_logic; --crate 0 + FAD_busy_1 : in std_logic; --crate 1 + FAD_busy_2 : in std_logic; --crate 2 + FAD_busy_3 : in std_logic; --crate 3 + --control signals from e.g. main control + start_run : in std_logic; --enable trigger output + stop_run : in std_logic; --disable trigger output + new_config : in std_logic; + --settings register (see FTM Firmware Specifications) + general_settings : in std_logic_vector(15 downto 0); + LP_and_PED_freq : in std_logic_vector(15 downto 0); + LP1_LP2_PED_ratio : in std_logic_vector(15 downto 0); + maj_coinc_n_phys : in std_logic_vector(15 downto 0); + maj_coinc_n_calib : in std_logic_vector(15 downto 0); + trigger_delay : in std_logic_vector(15 downto 0); + TIM_delay : in std_logic_vector(15 downto 0); + dead_time : in std_logic_vector(15 downto 0); + coinc_window_phys : in std_logic_vector(15 downto 0); + coinc_window_calib : in std_logic_vector(15 downto 0); + active_FTU_list_0 : in std_logic_vector(15 downto 0); + active_FTU_list_1 : in std_logic_vector(15 downto 0); + active_FTU_list_2 : in std_logic_vector(15 downto 0); + active_FTU_list_3 : in std_logic_vector(15 downto 0); + --control signals or information for other entities + trigger_ID_read : in std_logic; + trig_cnt_copy_read : in std_logic; + trigger_ID_ready : out std_logic; + trigger_ID : out std_logic_vector(55 downto 0); + trig_cnt_copy : out std_logic_vector(31 downto 0); --counter reading + trig_cnt_copy_valid : out std_logic; --trigger counter reading is valid + trigger_active : out std_logic; --phys triggers are enabled/active + config_done : out std_logic; + LP1_pulse : out std_logic; --send start signal to light pulser 1 + LP2_pulse : out std_logic; --send start signal to light pulser 2 + --trigger and time marker output signals to FADs + trigger_signal : out std_logic; + TIM_signal : out std_logic + ); + end component; + component Clock_cond_interface is port( @@ -390,4 +474,5 @@ port( clk : IN std_logic; + clk_ready : in std_logic; clk_scaler : IN std_logic; new_config : IN std_logic; @@ -415,5 +500,7 @@ config_start_cc : out std_logic := '0'; config_started_cc : in std_logic; - config_ready_cc : in std_logic + config_ready_cc : in std_logic; + config_trigger : out std_logic; + config_trigger_done : in std_logic ); end component; @@ -536,5 +623,15 @@ dd_send : IN std_logic; dd_send_ack : OUT std_logic := '1'; - dd_send_ready : OUT std_logic := '1' + dd_send_ready : OUT std_logic := '1'; + --very new stuff + ftu_error_calls : IN std_logic_vector (15 DOWNTO 0); + ftu_error_data : IN std_logic_vector (223 DOWNTO 0); -- (28 * 8) - 1 + ftu_error_send : IN std_logic; + ftu_error_send_ack : OUT std_logic := '1'; + ftu_error_send_ready : OUT std_logic := '1'; + prescaling_FTU01 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + trigger_counter : IN std_logic_vector (31 DOWNTO 0) := (others => '0'); + trigger_counter_read : OUT std_logic := '0'; + trigger_counter_valid : IN std_logic ); end component; @@ -542,21 +639,32 @@ begin - -- IBUFG: Single-ended global clock input buffer - -- Spartan-3A - -- Xilinx HDL Language Template, version 11.4 - - IBUFG_inst : IBUFG - generic map ( - IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, - -- "0"-"16" - IOSTANDARD => "DEFAULT") - port map ( - O => clk_buf_sig, -- Clock buffer output - I => clk -- Clock buffer input (connect directly to top-level port) - ); - - Inst_FTM_clk_gen : FTM_clk_gen +-- -- IBUFG: Single-ended global clock input buffer +-- -- Spartan-3A +-- -- Xilinx HDL Language Template, version 11.4 + +-- IBUFG_inst : IBUFG +-- generic map ( +-- IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, +-- -- "0"-"16" +-- IOSTANDARD => "DEFAULT") +-- port map ( +-- O => clk_buf_sig, -- Clock buffer output +-- I => clk -- Clock buffer input (connect directly to top-level port) +-- ); + +-- Inst_FTM_clk_gen : FTM_clk_gen +-- port map( +-- clk => clk_buf_sig, +-- rst => reset_sig, +-- clk_1 => clk_1M_sig, +-- clk_50 => clk_50M_sig, +-- clk_250 => clk_250M_sig, +-- clk_250_ps => clk_250M_ps_sig, +-- ready => clk_ready_sig +-- ); + + Inst_FTM_clk_gen_2 : FTM_clk_gen_2 port map( - clk => clk_buf_sig, + clk => clk, rst => reset_sig, clk_1 => clk_1M_sig, @@ -566,5 +674,75 @@ ready => clk_ready_sig ); - + + --differential output buffer for trigger signal + OBUFDS_LVDS_33_TRG : OBUFDS_LVDS_33 + port map( + O => TRG_p, + OB => TRG_n, + I => trigger_signal_sig + ); + + --differential output buffer for trigger signal + OBUFDS_LVDS_33_TIM : OBUFDS_LVDS_33 + port map( + O => TIM_Run_p, + OB => TIM_Run_n, + I => TIM_signal_sig + ); + + Inst_trigger_manager : trigger_manager + port map( + --clocks + clk_50MHz => clk_50M_sig, + clk_250MHz => clk_250M_sig, + clk_250MHz_180 => clk_250M_ps_sig, + --trigger primitives from FTUs + trig_prim_0 => Trig_Prim_A, --crate 0 + trig_prim_1 => Trig_Prim_B, --crate 1 + trig_prim_2 => Trig_Prim_C, --crate 2 + trig_prim_3 => Trig_Prim_D, --crate 3 + --external signals + ext_trig_1 => ext_Trig(1), + ext_trig_2 => ext_Trig(2), + ext_veto => Veto, + FAD_busy_0 => Busy0, --crate 0 + FAD_busy_1 => Busy1, --crate 1 + FAD_busy_2 => Busy2, --crate 2 + FAD_busy_3 => Busy3, --crate 3 + --control signals from e.g. main control + start_run => '1', --enable trigger output + stop_run => '0', --disable trigger output + new_config => config_trigger_sig, + --settings register (see FTM Firmware Specifications) + general_settings => general_settings_sig, + LP_and_PED_freq => lp_pt_freq_sig, + LP1_LP2_PED_ratio => lp_pt_ratio_sig, + maj_coinc_n_phys => coin_n_p_sig, + maj_coinc_n_calib => coin_n_c_sig, + trigger_delay => trigger_delay_sig, + TIM_delay => timemarker_delay_sig, + dead_time => dead_time_sig, + coinc_window_phys => coin_win_p_sig, + coinc_window_calib => coin_win_c_sig, + active_FTU_list_0 => ftu_active_cr0_sig, + active_FTU_list_1 => ftu_active_cr1_sig, + active_FTU_list_2 => ftu_active_cr2_sig, + active_FTU_list_3 => ftu_active_cr3_sig, + --control signals or information for other entities + trigger_ID_read => '0', + trig_cnt_copy_read => trigger_counter_read_sig, + trigger_ID_ready => open, + trigger_ID => open, + trig_cnt_copy => trigger_counter_sig, --counter reading + trig_cnt_copy_valid => trigger_counter_valid_sig, --trigger counter reading is valid + trigger_active => open, --phys triggers are enabled/active + config_done => config_trigger_done_sig, + LP1_pulse => open, --send start signal to light pulser 1 + LP2_pulse => open, --send start signal to light pulser 2 + --trigger and time marker output signals to FADs + trigger_signal => trigger_signal_sig, + TIM_signal => TIM_signal_sig + ); + Inst_Clock_cond_interface : Clock_cond_interface port map( @@ -593,4 +771,5 @@ port map( clk => clk_50M_sig, + clk_ready => clk_ready_sig, clk_scaler => clk_1M_sig, new_config => new_config_sig, @@ -612,5 +791,5 @@ rates_started_ftu => rates_ftu_started_sig, rates_ready_ftu => rates_ftu_ready_sig, - prescaling_FTU01 => "00010011", + prescaling_FTU01 => prescaling_FTU01_sig(7 downto 0), dd_send => dd_send_sig, dd_send_ack => dd_send_ack_sig, @@ -618,5 +797,7 @@ config_start_cc => config_start_cc_sig, config_started_cc => config_started_cc_sig, - config_ready_cc => config_ready_cc_sig + config_ready_cc => config_ready_cc_sig, + config_trigger => config_trigger_sig, + config_trigger_done => config_trigger_done_sig ); @@ -737,5 +918,15 @@ dd_send => dd_send_sig, dd_send_ack => dd_send_ack_sig, - dd_send_ready => dd_send_ready_sig + dd_send_ready => dd_send_ready_sig, + --very new stuff + ftu_error_calls => ftu_error_calls_sig, + ftu_error_data => ftu_error_data_sig, + ftu_error_send => ftu_error_send_sig, + ftu_error_send_ack => ftu_error_send_ack_sig, + ftu_error_send_ready => ftu_error_send_ready_sig, + prescaling_FTU01 => prescaling_FTU01_sig, + trigger_counter => trigger_counter_sig, + trigger_counter_read => trigger_counter_read_sig, + trigger_counter_valid => trigger_counter_valid_sig ); Index: firmware/FTM/FTM_top_tb.vhd =================================================================== --- firmware/FTM/FTM_top_tb.vhd (revision 10328) +++ firmware/FTM/FTM_top_tb.vhd (revision 10366) @@ -92,14 +92,14 @@ -- Trigger primitives inputs ------------------------------------------------------------------------------- - -- Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0 - -- Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1 - -- Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2 - -- Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3 + Trig_Prim_A : in STD_LOGIC_VECTOR(9 downto 0); -- crate 0 + Trig_Prim_B : in STD_LOGIC_VECTOR(9 downto 0); -- crate 1 + Trig_Prim_C : in STD_LOGIC_VECTOR(9 downto 0); -- crate 2 + Trig_Prim_D : in STD_LOGIC_VECTOR(9 downto 0); -- crate 3 -- NIM inputs ------------------------------------------------------------------------------ - -- ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input - -- Veto : in STD_LOGIC; -- trigger veto input + ext_Trig : in STD_LOGIC_VECTOR(2 downto 1); -- external trigger input + Veto : in STD_LOGIC; -- trigger veto input -- NIM_In : in STD_LOGIC_VECTOR(2 downto 0); -- auxiliary inputs @@ -141,5 +141,5 @@ Bus1_RxD_3 : in STD_LOGIC; -- crate 3 - Bus1_TxD_3 : out STD_LOGIC + Bus1_TxD_3 : out STD_LOGIC; @@ -183,8 +183,8 @@ -- Busy signals from the FAD boards ------------------------------------------------------------------------------- --- Busy0 : in STD_LOGIC; --- Busy1 : in STD_LOGIC; --- Busy2 : in STD_LOGIC; --- Busy3 : in STD_LOGIC; + Busy0 : in STD_LOGIC; + Busy1 : in STD_LOGIC; + Busy2 : in STD_LOGIC; + Busy3 : in STD_LOGIC; @@ -211,9 +211,9 @@ -- RES_n : out STD_LOGIC; -- RES- --- TRG_p : out STD_LOGIC; -- TRG+ Trigger --- TRG_n : out STD_LOGIC; -- TRG- - --- TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker --- TIM_Run_n : out STD_LOGIC; -- TIM_Run- + TRG_p : out STD_LOGIC; -- TRG+ Trigger + TRG_n : out STD_LOGIC; -- TRG- + + TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker + TIM_Run_n : out STD_LOGIC -- TIM_Run- -- TIM_Sel : out STD_LOGIC; -- Time Marker selector @@ -368,10 +368,10 @@ -- SIO => SIO_sig, -- TS_CS => TS_CS_sig, --- Trig_Prim_A => Trig_Prim_A_sig, --- Trig_Prim_B => Trig_Prim_B_sig, --- Trig_Prim_C => Trig_Prim_C_sig, --- Trig_Prim_D => Trig_Prim_D_sig, --- ext_Trig => ext_Trig_sig, --- Veto => Veto_sig, + Trig_Prim_A => Trig_Prim_A_sig, + Trig_Prim_B => Trig_Prim_B_sig, + Trig_Prim_C => Trig_Prim_C_sig, + Trig_Prim_D => Trig_Prim_D_sig, + ext_Trig => ext_Trig_sig, + Veto => Veto_sig, -- NIM_In => NIM_In_sig, -- NIM_In3_GCLK => NIM_In3_GCLK_sig, @@ -393,5 +393,5 @@ Bus1_TxD_2 => Bus1_TxD_2_sig, Bus1_RxD_3 => Bus1_RxD_3_sig, - Bus1_TxD_3 => Bus1_TxD_3_sig + Bus1_TxD_3 => Bus1_TxD_3_sig, -- Bus2_Tx_En => Bus2_Tx_En_sig, -- Bus2_Rx_En => Bus2_Rx_En_sig, @@ -408,14 +408,14 @@ -- Crate_Res2 => Crate_Res2_sig, -- Crate_Res3 => Crate_Res3_sig, --- Busy0 => Busy0_sig, --- Busy1 => Busy1_sig, --- Busy2 => Busy2_sig, --- Busy3 => Busy3_sig, + Busy0 => Busy0_sig, + Busy1 => Busy1_sig, + Busy2 => Busy2_sig, + Busy3 => Busy3_sig, -- RES_p => RES_p_sig, -- RES_n => RES_n_sig, --- TRG_p => TRG_p_sig, --- TRG_n => TRG_n_sig, --- TIM_Run_p => TIM_Run_p_sig, --- TIM_Run_n => TIM_Run_n_sig, + TRG_p => TRG_p_sig, + TRG_n => TRG_n_sig, + TIM_Run_p => TIM_Run_p_sig, + TIM_Run_n => TIM_Run_n_sig -- TIM_Sel => TIM_Sel_sig, -- Cal_0_p => Cal_0_p_sig, @@ -446,4 +446,56 @@ end process clk_proc; + -- Stimulus process for busy signals + busy_proc: process + begin + wait for 500us; + Busy0_sig <= '1'; + wait for 100us; + Busy0_sig <= '0'; + wait for 1ms; + Busy0_sig <= '1'; + wait for 500us; + Busy0_sig <= '0'; + wait; + end process busy_proc; + + -- Stimulus process for trigger + trigger_proc: process + begin + --------------------------------------------------------------------------- + -- FTUs not yet initialized + --------------------------------------------------------------------------- + wait for 10us; + Trig_Prim_A_sig(0) <= '1'; + wait for 100ns; + Trig_Prim_A_sig(0) <= '0'; + wait for 99us; + Trig_Prim_B_sig(0) <= '1'; + wait for 100ns; + Trig_Prim_B_sig(0) <= '0'; + wait for 1us; + Trig_Prim_B_sig(0) <= '1'; + wait for 100ns; + Trig_Prim_B_sig(0) <= '0'; + --------------------------------------------------------------------------- + -- now FTUs are initialized + --------------------------------------------------------------------------- + wait for 2200us; + Trig_Prim_A_sig(0) <= '1'; + Trig_Prim_B_sig(0) <= '1'; + wait for 100ns; + Trig_Prim_A_sig(0) <= '0'; + Trig_Prim_B_sig(0) <= '0'; + wait for 4us; + Trig_Prim_A_sig(0) <= '1'; + wait for 100ns; + Trig_Prim_A_sig(0) <= '0'; + wait for 22us; + Trig_Prim_B_sig(0) <= '1'; + wait for 100ns; + Trig_Prim_B_sig(0) <= '0'; + wait; + end process trigger_proc; + -- Stimulus process for RS485 of crate 0 rs485_0_proc: process Index: firmware/FTM/clock/FTM_clk_gen_2.vhd =================================================================== --- firmware/FTM/clock/FTM_clk_gen_2.vhd (revision 10366) +++ firmware/FTM/clock/FTM_clk_gen_2.vhd (revision 10366) @@ -0,0 +1,163 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: Q. Weitzel +-- +-- Create Date: February 28, 2011 +-- Design Name: +-- Module Name: FTM_clk_gen_2 - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: interface to different DCMs and clk dividers for FMU board +-- add here more DCMs if needed +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FTM_clk_gen_2 is + Port ( + clk : IN STD_LOGIC; + rst : IN STD_LOGIC; + clk_1 : OUT STD_LOGIC; + clk_50 : OUT STD_LOGIC; + clk_250 : OUT STD_LOGIC; + clk_250_ps : OUT STD_LOGIC; + ready : OUT STD_LOGIC + ); +end FTM_clk_gen_2; + +architecture Behavioral of FTM_clk_gen_2 is + + component FTM_dcm_40M_to_50M_2 + port( + CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic; + LOCKED_OUT : out std_logic + ); + end component; + + component FTM_dcm_50M_to_250M_2 + port( + CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKFX180_OUT : out std_logic; + CLK0_OUT : out std_logic; + LOCKED_OUT : out std_logic + ); + end component; + + component Clock_Divider + port( + clock_in : IN STD_LOGIC; + clock_out : OUT STD_LOGIC + ); + end component; + + signal clk_1M_sig : std_logic; + signal clk_50M_sig : std_logic; + signal clk_250M_sig : std_logic; + signal clk_250M_ps_sig : std_logic; + + signal clk_50M_int_sig : std_logic; + signal dcm1_ibufg_sig : std_logic; + + signal dcm1_locked : std_logic; + signal dcm2_locked : std_logic; + +begin + + Inst_FTM_dcm_40M_to_50M_2 : FTM_dcm_40M_to_50M_2 + port map( + CLKIN_IN => clk, + RST_IN => rst, + CLKFX_OUT => clk_50M_int_sig, + CLKIN_IBUFG_OUT => dcm1_ibufg_sig, + LOCKED_OUT => dcm1_locked + ); + + Inst_FTM_dcm_50M_to_250M_2 : FTM_dcm_50M_to_250M_2 + port map( + CLKIN_IN => clk_50M_int_sig, + RST_IN => rst, + CLKFX_OUT => clk_250M_sig, + CLKFX180_OUT => clk_250M_ps_sig, + CLK0_OUT => clk_50M_sig, + LOCKED_OUT => dcm2_locked + ); + + Inst_Clock_Divider : Clock_Divider + port map ( + clock_in => clk_50M_sig, + clock_out => clk_1M_sig + ); + + clk_1 <= clk_1M_sig; + clk_50 <= clk_50M_sig; + clk_250 <= clk_250M_sig; + clk_250_ps <= clk_250M_ps_sig; + + ready <= dcm1_locked and dcm2_locked; + +end Behavioral; + +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library ftm_definitions; +USE ftm_definitions.ftm_array_types.all; +USE ftm_definitions.ftm_constants.all; + +entity Clock_Divider is + generic( + divider : integer := INT_CLK_FREQUENCY_1 / LOW_FREQUENCY + ); + port( + clock_in : in std_logic; + clock_out : out std_logic := '0' + ); +end entity Clock_Divider; + +architecture RTL of Clock_Divider is + +begin + + process (clock_in) + variable Z: integer range 0 to divider - 1; + begin + if rising_edge(clock_in) then + if (Z < divider - 1) then + Z := Z + 1; + else + Z := 0; + end if; + if (Z = 0) then + clock_out <= '1'; + end if; + if (Z = divider / 2) then + clock_out <= '0'; + end if; + end if; + end process; + +end architecture RTL; Index: firmware/FTM/clock/FTM_dcm_40M_to_50M_2.vhd =================================================================== --- firmware/FTM/clock/FTM_dcm_40M_to_50M_2.vhd (revision 10366) +++ firmware/FTM/clock/FTM_dcm_40M_to_50M_2.vhd (revision 10366) @@ -0,0 +1,90 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 11.5 +-- \ \ Application : xaw2vhdl +-- / / Filename : FTM_dcm_40M_to_50M_2.vhd +-- /___/ /\ Timestamp : 04/12/2011 10:54:35 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st /ihp/home01/qweitzel/FPGA/trac-ISDC.svn/firmware/FTM/clock/FTM_dcm_40M_to_50M_2.xaw /ihp/home01/qweitzel/FPGA/trac-ISDC.svn/firmware/FTM/clock/FTM_dcm_40M_to_50M_2 +--Design Name: FTM_dcm_40M_to_50M_2 +--Device: xc3sd3400a-4fg676 +-- +-- Module FTM_dcm_40M_to_50M_2 +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST +-- Period Jitter (unit interval) for block DCM_SP_INST = 0.04 UI +-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.86 ns + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity FTM_dcm_40M_to_50M_2 is + port ( CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic; + LOCKED_OUT : out std_logic); +end FTM_dcm_40M_to_50M_2; + +architecture BEHAVIORAL of FTM_dcm_40M_to_50M_2 is + signal CLKFX_BUF : std_logic; + signal CLKIN_IBUFG : std_logic; + signal GND_BIT : std_logic; +begin + GND_BIT <= '0'; + CLKIN_IBUFG_OUT <= CLKIN_IBUFG; + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + CLKIN_IBUFG_INST : IBUFG + port map (I=>CLKIN_IN, + O=>CLKIN_IBUFG); + + DCM_SP_INST : DCM_SP + generic map( CLK_FEEDBACK => "NONE", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 4, + CLKFX_MULTIPLY => 5, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 25.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>GND_BIT, + CLKIN=>CLKIN_IBUFG, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>RST_IN, + CLKDV=>open, + CLKFX=>CLKFX_BUF, + CLKFX180=>open, + CLK0=>open, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>LOCKED_OUT, + PSDONE=>open, + STATUS=>open); + +end BEHAVIORAL; + + Index: firmware/FTM/clock/FTM_dcm_40M_to_50M_2.xaw =================================================================== --- firmware/FTM/clock/FTM_dcm_40M_to_50M_2.xaw (revision 10366) +++ firmware/FTM/clock/FTM_dcm_40M_to_50M_2.xaw (revision 10366) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.5e +$93x16=(aaz$dbcj00-rs`osrlf$J]IN/upbg(OTLJ$xzc!iisotewc(N]G$oaalk.DWIZbdeV>;ARz`_42N[7(i~;0<95?.167?5(?>81:86?>.4:853!oK92;=6<9;37-45663=808=?4539642=FZJB\EW?8;@PT^ZIIDPUHM^MNDHLD[FJL911J^ZTPOONZ[FJLAGUNTYK]N@N21>GU_SUDBAWPCMIJJZPFD\O:n6O]W[]LJI_XLJGT_ZG[CIKMCZEKC8:0M_YU_NLO]ZBCZVI;==5NRVX\KKJ^WMNYSN?>1:CQS_YHFESTHI\PCMI22>GU_SUDBAWPDEP\BIOWNEE[=85NRVX\KKJ^WOHTIUZJROCO57=FZ^PTCCBV_HLPPZHREl1J^ZTPOONZ[UKDL8?0M_YU_NLO]ZTB[L^T@BIFC0:8EWQ]WFDGURXNLHF\@CUXEFNNm6O\SNA\SLROn2K\VRMCKCWEP\VB9890MZTPCMI\KPRW]]U_U]Kl;@UY[CJH_]S[I55NW[]SEWRc3H]QS^WATIVLKI22IGG<6?6:AOO717=2IGG?V7;BNH6]7?8<1H@F7?5:AOOAPd3JF@H[QKIWKGA0=DDBLI96MCKGZ;?FJLNQ;3<45LLJD[[GSAn2IGGKVPBTDD[LHT\j1H@FHW_EKUMACb3JF@JUQBUMVJTI_>3JF@JUQ@UU78GIMNF8;0OAEFN^FJRLBBWKST>o5LLJKM[LDRNN;;7NBDIO]JFP@@W@DXXk5LLJKM[LDRNNUDYY64CMIJJZOIk2IGGD@PPDPJKAcEUMH^NH;5KCL]PTg=CKDUX\RGASUf8@@ULM^UJHG[\T008@CUXN[OZYH@LY^OL@@753MFGSK\JQTGMG\YJGMO>7I]\EO36?ASSQVIROAKPCNPQAFRNGG=0HRXNLTG;?@^SM[DJ@l5IABVLV\YMN<1MMA]J9:DA[VIRZJO27KGA_TLJPV>KX^HF^I:5AEUULVN2VTKEA=7]]KOOG7?UUBF11[_D@LDDA0?WUS>2XXXRGAb:QJC@^SM[DJ@;5\IOEOAf=T\HX_Y]QXAHV5?VRF\\Y:>6]VSUGN[V_IKAXDBB[\3:VLT1=SZ\O37X]J_CWEC<=R[LUIYKI\5:TJAR7e3QK\S[K]SHMM5a=_AECET VKB!2-5%US]K*;"<.NSBKJ2>^cjVCo==5Wdl]Neoiu^lxxeb`>0:ZgiZKnffx]i}foo78_5<7U<1P<79R4:cqs5;ya0wa5389k&8ki97718|vrzHIz8<6NOx18E>7<6sZ9n6:l57e8277bd4=i?10>7)99:678yV5c2>h1;i4>33f`0f<64}T;l0hi:5yT6194?7=93=p_>k57c84`?74:mi?o7?;cd58f3`=83:1?79t$e84g>"6m3=n7)?i:6d8 76=091/;94:;c63>5<6;3:175<,881>>5+12810>"6<3887)?::4f8 40=>k1/=:4;;%3;>0d<,831845+1`815>"4k3?i7)3-9:6o5+3587=>"41320(>o5469'7g<2j2.?=78j;%65>1=#<;0>;6*;3;74?!222>:0(9656:&7e?3e3->i6864$5f91==#i7?4$7a90<=#?80<>6*>0;c8 4b=6=n;:0;6)8>:6;8 35=?910e?l50;&55?1>3-<;6:>4$71935=:07d89:18'24<012.=<79?;:k53?6=,?;1;45+61844>=n>=0;6)8>:6;8 36=?910e9:50;&55?1>3-<;6:>4;n00>5<#>80<565`2983>!062>307b<;:18'24<0121d>84?:%42>2?<3f826=4+6084=>=h:?0;6)8>:6;8?j40290/:<489:9l6f<72-<:6:74$71935=#9j09>65`2e83>!062>307b8k:18'24<0i2.>j79?;:m61?6=,?;1;45+62844>=h><0;6)8>:6;8?xd4>3:1>7>50z&56?363`?;6=4+6084=>"1;3=;76a:c;29 37=?01/:>480:9~f7`=8381<7>t$70967=n=90;6)8>:6;8 35=?910c8m50;&55?1>3-<86:>4;|q01?6=:r7?<7=<;<15>0e<,8h1?:5rs7;94?7|5=:1:55+6`864>{t:l0;6?u24181g>;5n3?;7p}:6;295~;383?>7)8n:4a8yv5?290:w0=9:428 3g==91v><50;3x97`==j1/:l4:c:p72<729q/:l4:c:~j74=83;pqc<<:182xh5<3:1=vsa2483>4}zf;<1<7?t}o04>5<6std947>51z~yxFGKr9;6io8863bexFGJr:vLM^t}AB Index: firmware/FTM/clock/FTM_dcm_40M_to_50M_2_arwz.ucf =================================================================== --- firmware/FTM/clock/FTM_dcm_40M_to_50M_2_arwz.ucf (revision 10366) +++ firmware/FTM/clock/FTM_dcm_40M_to_50M_2_arwz.ucf (revision 10366) @@ -0,0 +1,17 @@ +# Generated by Xilinx Architecture Wizard +# --- UCF Template Only --- +# Cut and paste these attributes into the project's UCF file, if desired +INST DCM_SP_INST CLK_FEEDBACK = NONE; +INST DCM_SP_INST CLKDV_DIVIDE = 2.0; +INST DCM_SP_INST CLKFX_DIVIDE = 4; +INST DCM_SP_INST CLKFX_MULTIPLY = 5; +INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; +INST DCM_SP_INST CLKIN_PERIOD = 25.000; +INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; +INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; +INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; +INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; +INST DCM_SP_INST FACTORY_JF = C080; +INST DCM_SP_INST PHASE_SHIFT = 0; +INST DCM_SP_INST STARTUP_WAIT = FALSE; Index: firmware/FTM/clock/FTM_dcm_50M_to_250M_2.vhd =================================================================== --- firmware/FTM/clock/FTM_dcm_50M_to_250M_2.vhd (revision 10366) +++ firmware/FTM/clock/FTM_dcm_50M_to_250M_2.vhd (revision 10366) @@ -0,0 +1,97 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 11.5 +-- \ \ Application : xaw2vhdl +-- / / Filename : FTM_dcm_50M_to_250M_2.vhd +-- /___/ /\ Timestamp : 04/12/2011 10:57:30 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-st /ihp/home01/qweitzel/FPGA/trac-ISDC.svn/firmware/FTM/clock/FTM_dcm_50M_to_250M_2.xaw /ihp/home01/qweitzel/FPGA/trac-ISDC.svn/firmware/FTM/clock/FTM_dcm_50M_to_250M_2 +--Design Name: FTM_dcm_50M_to_250M_2 +--Device: xc3sd3400a-4fg676 +-- +-- Module FTM_dcm_50M_to_250M_2 +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST +-- Period Jitter (unit interval) for block DCM_SP_INST = 0.17 UI +-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.69 ns + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity FTM_dcm_50M_to_250M_2 is + port ( CLKIN_IN : in std_logic; + RST_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKFX180_OUT : out std_logic; + CLK0_OUT : out std_logic; + LOCKED_OUT : out std_logic); +end FTM_dcm_50M_to_250M_2; + +architecture BEHAVIORAL of FTM_dcm_50M_to_250M_2 is + signal CLKFB_IN : std_logic; + signal CLKFX_BUF : std_logic; + signal CLKFX180_BUF : std_logic; + signal CLK0_BUF : std_logic; + signal GND_BIT : std_logic; +begin + GND_BIT <= '0'; + CLK0_OUT <= CLKFB_IN; + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + CLKFX180_BUFG_INST : BUFG + port map (I=>CLKFX180_BUF, + O=>CLKFX180_OUT); + + CLK0_BUFG_INST : BUFG + port map (I=>CLK0_BUF, + O=>CLKFB_IN); + + DCM_SP_INST : DCM_SP + generic map( CLK_FEEDBACK => "1X", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 1, + CLKFX_MULTIPLY => 5, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 20.000, + CLKOUT_PHASE_SHIFT => "NONE", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"C080", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>CLKFB_IN, + CLKIN=>CLKIN_IN, + DSSEN=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>RST_IN, + CLKDV=>open, + CLKFX=>CLKFX_BUF, + CLKFX180=>CLKFX180_BUF, + CLK0=>CLK0_BUF, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + LOCKED=>LOCKED_OUT, + PSDONE=>open, + STATUS=>open); + +end BEHAVIORAL; + + Index: firmware/FTM/clock/FTM_dcm_50M_to_250M_2.xaw =================================================================== --- firmware/FTM/clock/FTM_dcm_50M_to_250M_2.xaw (revision 10366) +++ firmware/FTM/clock/FTM_dcm_50M_to_250M_2.xaw (revision 10366) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.5e +$95x11=(aaz$dbcj00-rs`osrlf$J]IN/upbg(OTLJ$xzc!iisotewc(N]G$oaalk.DWIZbdeV?;ARz`_373IZ4)ph}:7=:40/340>6)>0;0=95>1/7;?40 `J:3X0912>47&9:;?6<:00975>353<:<7L\LHVKY52=FZ^PTCCBV_BCPGDBNFNUH@F?7;@PT^ZIIDPUH@FGA_DZWAWHFD8?0M_YU_NLO]ZEKC@DTZLBZE0`8EWQ]WFDGURJLM^QTMQEOAGMTOAE>0:CQS_YHFESTHI\PC133?DTPRVEE@TQKDS]@5475:CQS_YHFEST^H]JT^NLCLE602KY[WQ@NM[\RDJNLVNM_RC@DDc8EVUHKV]BXEh4AVX\GIME]O^R\H?>6:CT^ZEKCK_MXT^J1^LLAAOS9:1J[WQLLJ]LQQVR\V^R\Hm4AVX\BIIP\PZN46OXZ^RBVQb:>7NBD2Y:8GIM5P82;96MCK826?FJLL_i0OAEKV^FJRLBB=2IGGKL7;BNHBGYNF<1H@FHW8:AOOC^609i0OAEIX0:3[GSA9;1H@FHW192\FP@@W@DXXn5LLJD[5=6XG\^27NBDFY]AQC`EKCF__S]FNSD]PLL@Sk2IGGRHJEE@BGN?2:FOHZ@UMX_NBNWPMNFF1>BT[LD:96JZTX]@]FJBWJEY^HM[INL4?AYQIE_Nm6HNCUMQ]ZLA=2LJ@^K6;G@\WJSUKLi0JHKKB@AH[GSA12LBBR[AIUQ;?CIR\VY_^l5IOTV\QKOS[h1MCXZPV@NVA4=N02CEXH\AAM32?OOS\LXTEC^ZT^VZT@eLN\]OYS[OCUD48HJELMMk0@BMDEE]LQQ51EIYY@RJ68JJHB92E37BHKDSASAg=W@HYNS^FFFU;8TLHOIZH^_l5_IOKPCKBBL11[ECYFDUJ;?UTNE]S[I<>4PSMS[UOIAZKHXDXJ5:RPGIM13YYOCCK;;QQFJ==W[@DHHHM<;SQW2>TT\VCEn6]FGDZWAWHFD?1XECICEb9PPDTS]YU\MDZ9;RVBPPU6:2YR_YKB_R[MGMTHFF_X?6Z@P59WVPC?3\YNSO[IG89VW@YE]OMX96XFEV3a?]GPW_OY_DAA1e9[MIOIP$RON->!1!QWQG&7&8*J_NGF6:ZgfZOc991Sh`QBakmqR`ttafd:<6Vkm^OjjjtQm{ybcc;4[183Y0=\83=V86o}w{18`fke3oydaa 0,30>pole;:7um4>33f`0f<6=7=0:0:??jl4b820`c63m2:6=4>:0yP0142b9k1}X:750;395?g|[=>14<473;306ae3k3;?i33-8:65;4$309<3=#?h0>7o:9:1827?6=8r.=47::;%d96`=#990<=6*>2;06?!742;?0(<:5289'50<5=2.::78<;%34>27<,82186*>9;42?!7f2=l0("3?3=?7):k:59'0=<2l2.?m7;k;%6`>20<,=o1:6*:0;74?!352"1<3;0(:<54g9'32<002.:=7j4$0d90<=#=h097);6:29j7f<72-<<6:h4$7;933=2><07d8j:18'22<0n2.=5799;:k5g?6=,?=1;k5+67842>=n>m0;6)88:6d8 30=??10e;o50;&53?1a3-<=6:84;h6a>5<#>>0i5=3:1(;957g9'2<<0>2.:h7<;;%3f>07<3f8o6=4+6684b>=h:00;6)88:6d8?j4f290/::48f:9l6`<72-<<6:h4;n0a>5<#>>0!002>l07b==:18'22<0n2.=5799;%3g>72<3f986=4+6684b>"113==7)?k:368?j14290/::470:&51?1132e>n7>5$7593c=#>00<:65`6c83>!002>l07pl=7;296?6=8r.=47<;;h75>5<#>>0i1:3:1(;957g9'2<<0>21vn>650;094?6|,?21>95f5783>!002>l0(;757798k34=83.=;79i;%4:>20<3th897>52;294~"1038?7d;9:18'22<0n2.=5799;:m56?6=,?=1;k5+68842>=z{:o1<7?t=5497f=#?90>:6s|3083>7}:5579~w70=838p1985249>62<2>2wx?:4?:3y>03<4:27847;9;|q00?6=:r7?:7=<;<16>00{<65>0d<,>:1:?5rs2`94?7|5:21:?5+71856>{t;?0;6"083<97p}=8;294~"083<97psa2483>4}zf;<1<7?t}o04>5<6std947>51zm6<<728qvb?o50;3xyk4e290:wp`=c;295~{i:m0;6 '0'); coin_win_c : OUT std_logic_vector (15 downto 0) := (others => '0'); + prescaling_FTU01 : OUT std_logic_vector (15 downto 0) := (others => '0'); ftu_active_cr0 : OUT std_logic_vector (15 downto 0) := (others => '0'); ftu_active_cr1 : OUT std_logic_vector (15 downto 0) := (others => '0'); @@ -162,9 +163,14 @@ when CR_CONFIG_START => if (addr_cnt < SD_BLOCK_SIZE) then - if ((addr_cnt < SD_FTU_BASE_ADDR) OR (addr_cnt >= SD_FTU_ACTIVE_BASE_ADDR)) then + if ((addr_cnt < SD_FTU_BASE_ADDR) + OR (addr_cnt = SD_ADDR_ftu_prescaling_0) + OR (addr_cnt >= SD_FTU_ACTIVE_BASE_ADDR) + ) then local_sd_addr <= addr_cnt; next_state <= CR_CONFIG_01; state_cram_proc <= CR_READ_START; elsif (addr_cnt = SD_FTU_BASE_ADDR) then + addr_cnt <= SD_ADDR_ftu_prescaling_0; + elsif (addr_cnt = (SD_ADDR_ftu_prescaling_0 + 1)) then addr_cnt <= SD_FTU_ACTIVE_BASE_ADDR; end if; @@ -242,4 +248,6 @@ when SD_ADDR_coin_win_c => coin_win_c <= local_sd_data; + when SD_ADDR_ftu_prescaling_0 => + prescaling_FTU01 <= local_sd_data; when SD_ADDR_ftu_active_cr0 => ftu_active_cr0 <= local_sd_data; Index: firmware/FTM/ethernet/ethernet_modul_beha.vhd =================================================================== --- firmware/FTM/ethernet/ethernet_modul_beha.vhd (revision 10328) +++ firmware/FTM/ethernet/ethernet_modul_beha.vhd (revision 10366) @@ -2,10 +2,9 @@ -- -- Created: --- by - kai.UNKNOWN (E5PCXX) --- at - 11:52:19 03.03.2011 +-- by - kai.users (tpkw.local.priv) +-- at - 10:39:41 04/13/11 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) -- - LIBRARY ieee; USE ieee.std_logic_1164.all; @@ -16,77 +15,87 @@ USE ftm_definitions.ftm_constants.all; + ENTITY ethernet_modul IS - PORT( - wiz_reset : OUT std_logic := '1'; - wiz_addr : OUT std_logic_vector (9 DOWNTO 0); - wiz_data : INOUT std_logic_vector (15 DOWNTO 0); - wiz_cs : OUT std_logic := '1'; - wiz_wr : OUT std_logic := '1'; - wiz_rd : OUT std_logic := '1'; - wiz_int : IN std_logic; - clk : IN std_logic; - sd_ready : OUT std_logic; - sd_busy : OUT std_logic; - led : OUT std_logic_vector (7 DOWNTO 0); - sd_read_ftu : IN std_logic; - sd_started_ftu : OUT std_logic := '0'; - cc_R0 : OUT std_logic_vector (31 DOWNTO 0); - cc_R1 : OUT std_logic_vector (31 DOWNTO 0); - cc_R11 : OUT std_logic_vector (31 DOWNTO 0); - cc_R13 : OUT std_logic_vector (31 DOWNTO 0); - cc_R14 : OUT std_logic_vector (31 DOWNTO 0); - cc_R15 : OUT std_logic_vector (31 DOWNTO 0); - cc_R8 : OUT std_logic_vector (31 DOWNTO 0); - cc_R9 : OUT std_logic_vector (31 DOWNTO 0); - coin_n_c : OUT std_logic_vector (15 DOWNTO 0); - coin_n_p : OUT std_logic_vector (15 DOWNTO 0); - dead_time : OUT std_logic_vector (15 DOWNTO 0); - -- data from config ram - general_settings : OUT std_logic_vector (15 DOWNTO 0); - lp1_amplitude : OUT std_logic_vector (15 DOWNTO 0); - lp1_delay : OUT std_logic_vector (15 DOWNTO 0); - lp2_amplitude : OUT std_logic_vector (15 DOWNTO 0); - lp2_delay : OUT std_logic_vector (15 DOWNTO 0); - lp_pt_freq : OUT std_logic_vector (15 DOWNTO 0); - lp_pt_ratio : OUT std_logic_vector (15 DOWNTO 0); - timemarker_delay : OUT std_logic_vector (15 DOWNTO 0); - trigger_delay : OUT std_logic_vector (15 DOWNTO 0); - sd_addr_ftu : IN std_logic_vector (11 DOWNTO 0); - sd_data_out_ftu : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); - ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0); - ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0); - ftu_active_cr2 : OUT std_logic_vector (15 DOWNTO 0); - ftu_active_cr3 : OUT std_logic_vector (15 DOWNTO 0); - new_config : OUT std_logic := '0'; - config_started : IN std_logic; - config_start_eth : IN std_logic; - config_started_eth : OUT std_logic := '0'; - config_ready_eth : OUT std_logic := '0'; - config_started_ack : OUT std_logic := '0'; - fl_busy : OUT std_logic; - fl_ready : OUT std_logic; - fl_write_ftu : IN std_logic; - fl_started_ftu : OUT std_logic := '0'; - fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0); - fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0) := (others => '0'); - -- - ping_ftu_start : OUT std_logic := '0'; - ping_ftu_started : IN std_logic; - ping_ftu_ready : IN std_logic; - dd_write_ftu : IN std_logic; - dd_started_ftu : OUT std_logic := '0'; - dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0); - dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0); - dd_busy : OUT std_logic; - dd_ready : OUT std_logic; - coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); - coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); - dd_block_ready_ftu : IN std_logic; - dd_block_start_ack_ftu : OUT std_logic := '0'; - dd_block_start_ftu : IN std_logic; - dd_send : IN std_logic; - dd_send_ack : OUT std_logic := '1'; - dd_send_ready : OUT std_logic := '1' - ); + PORT( + wiz_reset : OUT std_logic := '1'; + wiz_addr : OUT std_logic_vector (9 DOWNTO 0); + wiz_data : INOUT std_logic_vector (15 DOWNTO 0); + wiz_cs : OUT std_logic := '1'; + wiz_wr : OUT std_logic := '1'; + wiz_rd : OUT std_logic := '1'; + wiz_int : IN std_logic; + clk : IN std_logic; + sd_ready : OUT std_logic; + sd_busy : OUT std_logic; + led : OUT std_logic_vector (7 DOWNTO 0); + sd_read_ftu : IN std_logic; + sd_started_ftu : OUT std_logic := '0'; + cc_R0 : OUT std_logic_vector (31 DOWNTO 0); + cc_R1 : OUT std_logic_vector (31 DOWNTO 0); + cc_R11 : OUT std_logic_vector (31 DOWNTO 0); + cc_R13 : OUT std_logic_vector (31 DOWNTO 0); + cc_R14 : OUT std_logic_vector (31 DOWNTO 0); + cc_R15 : OUT std_logic_vector (31 DOWNTO 0); + cc_R8 : OUT std_logic_vector (31 DOWNTO 0); + cc_R9 : OUT std_logic_vector (31 DOWNTO 0); + coin_n_c : OUT std_logic_vector (15 DOWNTO 0); + coin_n_p : OUT std_logic_vector (15 DOWNTO 0); + dead_time : OUT std_logic_vector (15 DOWNTO 0); + -- data from config ram + general_settings : OUT std_logic_vector (15 DOWNTO 0); + lp1_amplitude : OUT std_logic_vector (15 DOWNTO 0); + lp1_delay : OUT std_logic_vector (15 DOWNTO 0); + lp2_amplitude : OUT std_logic_vector (15 DOWNTO 0); + lp2_delay : OUT std_logic_vector (15 DOWNTO 0); + lp_pt_freq : OUT std_logic_vector (15 DOWNTO 0); + lp_pt_ratio : OUT std_logic_vector (15 DOWNTO 0); + timemarker_delay : OUT std_logic_vector (15 DOWNTO 0); + trigger_delay : OUT std_logic_vector (15 DOWNTO 0); + sd_addr_ftu : IN std_logic_vector (11 DOWNTO 0); + sd_data_out_ftu : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0); + ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0); + ftu_active_cr2 : OUT std_logic_vector (15 DOWNTO 0); + ftu_active_cr3 : OUT std_logic_vector (15 DOWNTO 0); + new_config : OUT std_logic := '0'; + config_started : IN std_logic; + config_start_eth : IN std_logic; + config_started_eth : OUT std_logic := '0'; + config_ready_eth : OUT std_logic := '0'; + config_started_ack : OUT std_logic := '0'; + fl_busy : OUT std_logic; + fl_ready : OUT std_logic; + fl_write_ftu : IN std_logic; + fl_started_ftu : OUT std_logic := '0'; + fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0); + fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0) := (others => '0'); + ping_ftu_start : OUT std_logic := '0'; + ping_ftu_started : IN std_logic; + ping_ftu_ready : IN std_logic; + dd_write_ftu : IN std_logic; + dd_started_ftu : OUT std_logic := '0'; + dd_data_in_ftu : IN std_logic_vector (15 DOWNTO 0); + dd_addr_ftu : IN std_logic_vector (11 DOWNTO 0); + dd_busy : OUT std_logic; + dd_ready : OUT std_logic; + coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + dd_block_ready_ftu : IN std_logic; + dd_block_start_ack_ftu : OUT std_logic := '0'; + dd_block_start_ftu : IN std_logic; + dd_send : IN std_logic; + dd_send_ack : OUT std_logic := '1'; + dd_send_ready : OUT std_logic := '1'; + ftu_error_calls : IN std_logic_vector (15 DOWNTO 0); + ftu_error_data : IN std_logic_vector (223 DOWNTO 0); -- (28 * 8) - 1 + ftu_error_send : IN std_logic; + ftu_error_send_ack : OUT std_logic := '1'; + ftu_error_send_ready : OUT std_logic := '1'; + prescaling_FTU01 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + trigger_counter : IN std_logic_vector (31 DOWNTO 0) := (others => '0'); + trigger_counter_read : OUT std_logic := '0'; + trigger_counter_valid : IN std_logic + ); + END ethernet_modul ; @@ -241,4 +250,5 @@ coin_win_p : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); coin_win_c : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + prescaling_FTU01 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); ftu_active_cr0 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); ftu_active_cr1 : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); @@ -328,4 +338,7 @@ get_header_started : OUT std_logic := '0'; get_header_ready : OUT std_logic := '0'; + trigger_counter_read : OUT std_logic := '0'; + trigger_counter_valid : IN std_logic ; + trigger_counter : IN std_logic_vector (31 DOWNTO 0) := (others => '0'); header_board_id : OUT std_logic_vector (63 DOWNTO 0) := (others => '0'); header_firmware_id : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); @@ -386,4 +399,10 @@ fl_busy : IN std_logic ; -- + ftu_error_send : IN std_logic ; + ftu_error_send_ack : OUT std_logic := '1'; + ftu_error_send_ready : OUT std_logic := '1'; + ftu_error_calls : IN std_logic_vector (15 DOWNTO 0); + ftu_error_data : IN std_logic_vector (223 DOWNTO 0); -- (28 * 8) - 1 + -- get_header : OUT std_logic := '0'; get_header_started : IN std_logic ; @@ -395,18 +414,4 @@ ); END COMPONENT; - - -- Optional embedded configurations - -- pragma synthesis_off - -- FOR ALL : CRAM_4096_16b USE ENTITY FACT_FTM_lib.CRAM_4096_16b; - -- FOR ALL : DRAM_4096_16b USE ENTITY FACT_FTM_lib.DRAM_4096_16b; - -- FOR ALL : FRAM_4096_16b USE ENTITY FACT_FTM_lib.FRAM_4096_16b; - -- FOR ALL : cram_control USE ENTITY FACT_FTM_lib.cram_control; - -- FOR ALL : dd_write_general_modul USE ENTITY FACT_FTM_lib.dd_write_general_modul; - -- FOR ALL : dram_control USE ENTITY FACT_FTM_lib.dram_control; - -- FOR ALL : eth_config_modul USE ENTITY FACT_FTM_lib.eth_config_modul; - -- FOR ALL : fram_control USE ENTITY FACT_FTM_lib.fram_control; - -- FOR ALL : header_modul USE ENTITY FACT_FTM_lib.header_modul; - -- FOR ALL : w5300_modul USE ENTITY FACT_FTM_lib.w5300_modul; - -- pragma synthesis_on BEGIN @@ -492,4 +497,5 @@ coin_win_p => coin_win_p, coin_win_c => coin_win_c, + prescaling_FTU01 => prescaling_FTU01, ftu_active_cr0 => ftu_active_cr0, ftu_active_cr1 => ftu_active_cr1, @@ -574,4 +580,7 @@ get_header_started => get_header_started, get_header_ready => get_header_ready, + trigger_counter_read => trigger_counter_read, + trigger_counter_valid => trigger_counter_valid, + trigger_counter => trigger_counter, header_board_id => header_board_id, header_firmware_id => header_firmware_id, @@ -626,4 +635,9 @@ fl_ready => fl_ready_internal, fl_busy => fl_busy_internal, + ftu_error_send => ftu_error_send, + ftu_error_send_ack => ftu_error_send_ack, + ftu_error_send_ready => ftu_error_send_ready, + ftu_error_calls => ftu_error_calls, + ftu_error_data => ftu_error_data, get_header => get_header, get_header_started => get_header_started, Index: firmware/FTM/ethernet/header_modul_beha.vhd =================================================================== --- firmware/FTM/ethernet/header_modul_beha.vhd (revision 10328) +++ firmware/FTM/ethernet/header_modul_beha.vhd (revision 10366) @@ -8,12 +8,11 @@ -- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) -- - LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE IEEE.STD_LOGIC_UNSIGNED.all; --- LIBRARY FACT_FTM_lib; --- USE FACT_FTM_lib.ftm_array_types.all; --- USE FACT_FTM_lib.ftm_constants.all; +--LIBRARY FACT_FTM_lib; +--USE FACT_FTM_lib.ftm_array_types.all; +--USE FACT_FTM_lib.ftm_constants.all; library ftm_definitions; USE ftm_definitions.ftm_array_types.all; @@ -26,4 +25,7 @@ get_header_started : OUT std_logic := '0'; get_header_ready : OUT std_logic := '0'; + trigger_counter_read : OUT std_logic := '0'; + trigger_counter_valid : IN std_logic; + trigger_counter : IN std_logic_vector (31 DOWNTO 0) := (others => '0'); header_board_id : OUT std_logic_vector (63 DOWNTO 0) := (others => '0'); header_firmware_id : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); @@ -36,5 +38,5 @@ ARCHITECTURE beha OF header_modul IS - type state_header_proc_type is (HP_INIT, HP_CONFIG, HP_IDLE, HP_START, HP_END); + type state_header_proc_type is (HP_INIT, HP_CONFIG, HP_IDLE, HP_START, HP_TRG_CNT, HP_END); signal state_header_proc : state_header_proc_type := HP_INIT; @@ -62,7 +64,15 @@ header_board_id <= to_stdlogicvector (DNA_FOR_SIM); header_firmware_id <= X"00" & FIRMWARE_ID; - header_trigger_counter <= X"22221111"; header_timestamp_counter <= X"333322221111"; - state_header_proc <= HP_END; + + trigger_counter_read <= '1'; + state_header_proc <= HP_TRG_CNT; + + when HP_TRG_CNT => + trigger_counter_read <= '0'; + if (trigger_counter_valid = '1') then + header_trigger_counter <= trigger_counter; + state_header_proc <= HP_END; + end if; when HP_END => @@ -78,2 +88,3 @@ END ARCHITECTURE beha; + Index: firmware/FTM/ethernet/w5300_modul.vhd =================================================================== --- firmware/FTM/ethernet/w5300_modul.vhd (revision 10328) +++ firmware/FTM/ethernet/w5300_modul.vhd (revision 10366) @@ -23,7 +23,8 @@ USE IEEE.STD_LOGIC_ARITH.all; USE IEEE.STD_LOGIC_UNSIGNED.all; --- LIBRARY FACT_FTM_lib; --- USE FACT_FTM_lib.ftm_array_types.all; --- USE FACT_FTM_lib.ftm_constants.all; + +--LIBRARY FACT_FTM_lib; +--USE FACT_FTM_lib.ftm_array_types.all; +--USE FACT_FTM_lib.ftm_constants.all; library ftm_definitions; USE ftm_definitions.ftm_array_types.all; @@ -34,5 +35,4 @@ library UNISIM; use UNISIM.VComponents.all; - ENTITY w5300_modul IS @@ -88,4 +88,10 @@ fl_busy : IN std_logic; -- + ftu_error_send : IN std_logic; + ftu_error_send_ack : OUT std_logic := '1'; + ftu_error_send_ready : OUT std_logic := '1'; + ftu_error_calls : IN std_logic_vector (15 DOWNTO 0); + ftu_error_data : IN std_logic_vector (223 DOWNTO 0); -- (28 * 8) - 1 + -- get_header : OUT std_logic := '0'; get_header_started : IN std_logic; @@ -95,4 +101,5 @@ header_trigger_counter : IN std_logic_vector (31 DOWNTO 0); header_timestamp_counter : IN std_logic_vector (47 DOWNTO 0) + ); @@ -103,6 +110,6 @@ type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA, INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, - SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, - READ_DATA, WRITE_TO_SD_ADDR, READ_FROM_SD_ADDR, READ_FROM_DD_ADDR, READ_FROM_FL_ADDR, READ_FROM_HEADER_MODUL); + SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, SEND_FTU_ERROR, + READ_DATA, WRITE_TO_SD_ADDR, READ_FTU_ERROR, READ_FROM_SD_ADDR, READ_FROM_DD_ADDR, READ_FROM_FL_ADDR, READ_FROM_HEADER_MODUL); type state_write_type is (WR_START, WR_LENGTH, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08, WR_GET_HEADER, WR_GET_HEADER_WAIT, WR_FIFO_DATA, WR_FIFO_DATA_01, WR_FIFO_HEADER, WR_FIFO_HEADER_01); @@ -116,4 +123,5 @@ type state_read_dd_type is (READ_DD_START, READ_DD_WAIT, READ_DD_END); type state_read_dd_block_type is (READ_DD_BLOCK_START, READ_DD_BLOCK_WRITE_GENERAL, READ_DD_BLOCK_WRITE, READ_DD_BLOCK_END, READ_DD_BLOCK_INTERN); + type state_send_ftu_error_type is (SFE_START, SFE_END); signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120"; @@ -137,4 +145,5 @@ signal state_read_dd : state_read_dd_type := READ_DD_START; signal state_read_dd_block : state_read_dd_block_type := READ_DD_BLOCK_START; + signal state_send_ftu_error : state_send_ftu_error_type := SFE_START; @@ -144,5 +153,5 @@ signal zaehler : std_logic_vector (19 downto 0) := (others => '0'); signal data_cnt : integer := 0; - signal header_cnt : integer := 0; + signal header_cnt : std_logic_vector (7 DOWNTO 0) := X"00"; signal socket_cnt : std_logic_vector (2 downto 0) := "000"; @@ -164,4 +173,6 @@ signal internal_cmd : std_logic := '0'; + signal autosend_flag : std_logic := '1'; + -- -- -- signal led_int : std_logic_vector (7 downto 0) := X"00"; @@ -289,4 +300,5 @@ state_read_dd <= READ_DD_START; state_read_dd_block <= READ_DD_BLOCK_START; + state_send_ftu_error <= SFE_START; -- reset output signals new_config <= '0'; @@ -302,4 +314,6 @@ dd_write_general <= '0'; fl_read <= '0'; + ftu_error_send_ack <= '1'; + ftu_error_send_ready <= '1'; -- set internal signals new_config_flag <= '0'; @@ -312,5 +326,5 @@ end if; - -- Init + -- Init when INIT => par_addr <= W5300_MR; @@ -319,5 +333,5 @@ next_state <= IM; - -- Interrupt Mask + -- Interrupt Mask when IM => par_addr <= W5300_IMR; @@ -326,5 +340,5 @@ next_state <= MT; - -- Memory Type + -- Memory Type when MT => par_addr <= W5300_MTYPER; @@ -333,5 +347,5 @@ next_state <= STX; - -- Socket TX Memory Size + -- Socket TX Memory Size when STX => par_data <= X"4000"; -- 64K TX for socket 0, others 0 @@ -375,5 +389,5 @@ next_state <= MAC; - -- MAC + -- MAC when MAC => par_addr <= W5300_SHAR; @@ -392,5 +406,5 @@ next_state <= GW; - -- Gateway + -- Gateway when GW => par_addr <= W5300_GAR; @@ -406,5 +420,5 @@ next_state <= SNM; - -- Subnet Mask + -- Subnet Mask when SNM => par_addr <= W5300_SUBR; @@ -419,5 +433,5 @@ state_init <= WRITE_REG; next_state <= IP; - -- Own IP-Address + -- Own IP-Address when IP => par_addr <= W5300_SIPR; @@ -432,5 +446,5 @@ state_init <= WRITE_REG; next_state <= SI; - -- Socket Init + -- Socket Init when SI => par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC; @@ -438,5 +452,5 @@ state_init <= WRITE_REG; next_state <= SI1; - -- Sx Interrupt Mask + -- Sx Interrupt Mask when SI1 => par_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC; @@ -493,4 +507,6 @@ dd_send_ack <= '0'; dd_send_ready <= '0'; + ftu_error_send_ack <= '0'; + ftu_error_send_ready <= '0'; led_int <= X"00"; -- -- -- @@ -538,13 +554,39 @@ dd_send_ack <= '1'; dd_send_ready <= '0'; - -- "simulate" command read dynamic data block - cmd_array (0) <= CMD_START_DELIMITER; - cmd_array (1) <= CMD_READ; - cmd_array (2) <= PAR_READ_DD; - state_read_data <= RD_CMD_PARSE; + if (autosend_flag = '0') then + state_read_dd_block <= READ_DD_BLOCK_END; + end if; + state_read_data <= RD_READ_DD_BLOCK; state_init <= READ_DATA; + elsif (ftu_error_send = '1') then + ftu_error_send_ack <= '1'; + ftu_error_send_ready <= '0'; + if (autosend_flag = '0') then + state_send_ftu_error <= SFE_END; + end if; + state_init <= SEND_FTU_ERROR; end if; + -- send FTU error message + when SEND_FTU_ERROR => + case state_send_ftu_error is + when SFE_START => + next_state <= SEND_FTU_ERROR; + read_addr_state <= READ_FTU_ERROR; + local_sd_addr <= X"000"; + local_write_length <= "00000" & FTU_ERROR_LENGTH; + state_send_ftu_error <= SFE_END; + state_init <= WRITE_DATA; + when SFE_END => + if (ftu_error_send = '0') then + ftu_error_send_ack <= '0'; + ftu_error_send_ready <= '1'; + state_send_ftu_error <= SFE_START; + state_init <= MAIN; + end if; + end case; + + -- read data from socket 0 when READ_DATA => @@ -664,4 +706,15 @@ state_ping <= PING_START; state_read_data <= RD_PING; + + when CMD_AUTOSEND => + state_read_data <= RD_5; + case cmd_array (2) is + when PAR_AUTOSEND_EA => + autosend_flag <= '1'; + when PAR_AUTOSEND_DA => + autosend_flag <= '0'; + when others => + null; + end case; when others => @@ -791,30 +844,40 @@ end case; -- state_read_data - + + -- read FTU errors + when READ_FTU_ERROR => + state_init <= next_state; + if (data_cnt = 0) then + local_sd_data <= ftu_error_calls; + else + local_sd_data <= X"00" & ftu_error_data (((data_cnt * 8) - 1) DOWNTO ((data_cnt * 8) - 8)); + end if; + + -- read from header modul when READ_FROM_HEADER_MODUL => state_init <= next_state; case header_cnt is - when 0 => + when X"00" => local_sd_data <= header_board_id (63 DOWNTO 48); - when 1 => + when X"01" => local_sd_data <= header_board_id (47 DOWNTO 32); - when 2 => + when X"02" => local_sd_data <= header_board_id (31 DOWNTO 16); - when 3 => + when X"03" => local_sd_data <= header_board_id (15 DOWNTO 0); - when 4 => + when X"04" => local_sd_data <= header_firmware_id; - when 5 => + when X"05" => local_sd_data <= header_trigger_counter (31 DOWNTO 16); - when 6 => + when X"06" => local_sd_data <= header_trigger_counter (15 DOWNTO 0); - when 7 => + when X"07" => local_sd_data <= header_timestamp_counter (47 DOWNTO 32); - when 8 => + when X"08" => local_sd_data <= header_timestamp_counter (31 DOWNTO 16); - when 9 => + when X"09" => local_sd_data <= header_timestamp_counter (15 DOWNTO 0); - when 10 => + when X"0A" => local_sd_data <= X"FFFF"; -- spare when others => @@ -920,5 +983,5 @@ write_length_bytes <= (FTM_HEADER_LENGTH + local_write_length (15 downto 0)) & '0'; -- shift left (*2) data_cnt <= 0; - header_cnt <= 0; + header_cnt <= X"00"; state_write <= WR_01; -- Check FIFO Size @@ -1074,3 +1137,2 @@ end Behavioral; - Index: firmware/FTM/ftm_board.ucf =================================================================== --- firmware/FTM/ftm_board.ucf (revision 10328) +++ firmware/FTM/ftm_board.ucf (revision 10366) @@ -98,53 +98,53 @@ # crate 0 # crate A -# NET Trig_Prim_A<0> LOC = AC6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<0> -# NET Trig_Prim_A<1> LOC = AD6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<1> -# NET Trig_Prim_A<2> LOC = AF3 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<2> -# NET Trig_Prim_A<3> LOC = AE4 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<3> -# NET Trig_Prim_A<4> LOC = AE6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<4> -# NET Trig_Prim_A<5> LOC = AE7 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<5> -# NET Trig_Prim_A<6> LOC = AE8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<6> -# NET Trig_Prim_A<7> LOC = AC8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<7> -# NET Trig_Prim_A<8> LOC = AC11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<8> -# NET Trig_Prim_A<9> LOC = AD11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<9> +NET Trig_Prim_A<0> LOC = AC6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<0> +NET Trig_Prim_A<1> LOC = AD6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<1> +NET Trig_Prim_A<2> LOC = AF3 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<2> +NET Trig_Prim_A<3> LOC = AE4 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<3> +NET Trig_Prim_A<4> LOC = AE6 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<4> +NET Trig_Prim_A<5> LOC = AE7 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<5> +NET Trig_Prim_A<6> LOC = AE8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<6> +NET Trig_Prim_A<7> LOC = AC8 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<7> +NET Trig_Prim_A<8> LOC = AC11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<8> +NET Trig_Prim_A<9> LOC = AD11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<9> # crate 1 # crate B -# NET Trig_Prim_B<0> LOC = AB16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<0> -# NET Trig_Prim_B<1> LOC = AC15 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<1> -# NET Trig_Prim_B<2> LOC = AC16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<2> -# NET Trig_Prim_B<3> LOC = AE17 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<3> -# NET Trig_Prim_B<4> LOC = AD19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<4> -# NET Trig_Prim_B<5> LOC = AE19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<5> -# NET Trig_Prim_B<6> LOC = AE20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<6> -# NET Trig_Prim_B<7> LOC = AF20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<7> -# NET Trig_Prim_B<8> LOC = AD21 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<8> -# NET Trig_Prim_B<9> LOC = AE23 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<9> +NET Trig_Prim_B<0> LOC = AB16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<0> +NET Trig_Prim_B<1> LOC = AC15 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<1> +NET Trig_Prim_B<2> LOC = AC16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<2> +NET Trig_Prim_B<3> LOC = AE17 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<3> +NET Trig_Prim_B<4> LOC = AD19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<4> +NET Trig_Prim_B<5> LOC = AE19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<5> +NET Trig_Prim_B<6> LOC = AE20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<6> +NET Trig_Prim_B<7> LOC = AF20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<7> +NET Trig_Prim_B<8> LOC = AD21 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<8> +NET Trig_Prim_B<9> LOC = AE23 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<9> # crate 2 # crate C -# NET Trig_Prim_C<0> LOC = AF23 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<0> -# NET Trig_Prim_C<1> LOC = AC21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<1> -# NET Trig_Prim_C<2> LOC = AE21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<2> -# NET Trig_Prim_C<3> LOC = AD20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<3> -# NET Trig_Prim_C<4> LOC = AC20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<4> -# NET Trig_Prim_C<5> LOC = AF19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<5> -# NET Trig_Prim_C<6> LOC = AC19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<6> -# NET Trig_Prim_C<7> LOC = AD17 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<7> -# NET Trig_Prim_C<8> LOC = AD14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<8> -# NET Trig_Prim_C<9> LOC = AC14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<9> +NET Trig_Prim_C<0> LOC = AF23 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<0> +NET Trig_Prim_C<1> LOC = AC21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<1> +NET Trig_Prim_C<2> LOC = AE21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<2> +NET Trig_Prim_C<3> LOC = AD20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<3> +NET Trig_Prim_C<4> LOC = AC20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<4> +NET Trig_Prim_C<5> LOC = AF19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<5> +NET Trig_Prim_C<6> LOC = AC19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<6> +NET Trig_Prim_C<7> LOC = AD17 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<7> +NET Trig_Prim_C<8> LOC = AD14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<8> +NET Trig_Prim_C<9> LOC = AC14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<9> # crate 3 # crate D -# NET Trig_Prim_D<0> LOC = AB12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<0> -# NET Trig_Prim_D<1> LOC = AC12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<1> -# NET Trig_Prim_D<2> LOC = AC9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<2> -# NET Trig_Prim_D<3> LOC = AB9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<3> -# NET Trig_Prim_D<4> LOC = AB7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<4> -# NET Trig_Prim_D<5> LOC = AF8 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<5> -# NET Trig_Prim_D<6> LOC = AF4 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<6> -# NET Trig_Prim_D<7> LOC = AF5 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<7> -# NET Trig_Prim_D<8> LOC = AD7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<8> -# NET Trig_Prim_D<9> LOC = AE3 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<9> +NET Trig_Prim_D<0> LOC = AB12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<0> +NET Trig_Prim_D<1> LOC = AC12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<1> +NET Trig_Prim_D<2> LOC = AC9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<2> +NET Trig_Prim_D<3> LOC = AB9 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<3> +NET Trig_Prim_D<4> LOC = AB7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<4> +NET Trig_Prim_D<5> LOC = AF8 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<5> +NET Trig_Prim_D<6> LOC = AF4 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<6> +NET Trig_Prim_D<7> LOC = AF5 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<7> +NET Trig_Prim_D<8> LOC = AD7 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<8> +NET Trig_Prim_D<9> LOC = AE3 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<9> @@ -152,7 +152,7 @@ ####################################################### # on IO-Bank 3 -# NET ext_Trig<1> LOC = B1 | IOSTANDARD=LVCMOS33; # -# NET ext_Trig<2> LOC = B2 | IOSTANDARD=LVCMOS33; # -# NET Veto LOC = E4 | IOSTANDARD=LVCMOS33; # +NET ext_Trig<1> LOC = B1 | IOSTANDARD=LVCMOS33; # +NET ext_Trig<2> LOC = B2 | IOSTANDARD=LVCMOS33; # +NET Veto LOC = E4 | IOSTANDARD=LVCMOS33; # # NET NIM_In<0> LOC = D3 | IOSTANDARD=LVCMOS33; # # NET NIM_In<1> LOC = F4 | IOSTANDARD=LVCMOS33; # @@ -260,8 +260,8 @@ # on IO-Bank 3 ####################################################### -# NET Busy0 LOC = M4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -# NET Busy1 LOC = P2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -# NET Busy2 LOC = R4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -# NET Busy3 LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Busy0 LOC = M4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Busy1 LOC = P2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Busy2 LOC = R4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Busy3 LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # @@ -291,9 +291,9 @@ # NET RES_n LOC = C15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES- IO-Bank 0 -# NET TRG_p LOC = B15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG+ Trigger -# NET TRG_n LOC = A15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG- IO-Bank 0 - -# NET TIM_Run_p LOC = AF25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run+ Time Marker -# NET TIM_Run_n LOC = AE25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run- on IO-Bank2 +NET TRG_p LOC = B15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG+ Trigger +NET TRG_n LOC = A15 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG- IO-Bank 0 + +NET TIM_Run_p LOC = AF25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run+ Time Marker +NET TIM_Run_n LOC = AE25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run- on IO-Bank2 NET TIM_Sel LOC = AD22 | IOSTANDARD=LVCMOS33; # Time Marker selector IO-Bank 2 Index: firmware/FTM/ftm_definitions.vhd =================================================================== --- firmware/FTM/ftm_definitions.vhd (revision 10328) +++ firmware/FTM/ftm_definitions.vhd (revision 10366) @@ -29,4 +29,11 @@ -- kw 03.03.: added FTM_HEADER_LENGTH -- +-- modified: Quirin Weitzel, March 14 2011 +-- third merger with library file from dortmund (changes below) +-- kw 22.03.: added FTU_ERROR_LENGTH +-- kw 30.03.: added CMD_AUTOSEND, PAR_AUTOSEND_EA, PAR_AUTOSEND_DA +-- +---kw 11.04.: added SD_ADDR_ftu_prescaling_0 +-- ---------------------------------------------------------------------------------- @@ -72,4 +79,5 @@ use ftm_definitions.ftm_array_types.all; use IEEE.NUMERIC_STD.ALL; +use ieee.math_real.all; package ftm_constants is @@ -191,7 +199,14 @@ -- ping all FTUs constant CMD_PING : std_logic_vector := X"0010"; -- ping all FTUs + -- turn automatic sending of dd-block and ftu-error-list on or off + constant CMD_AUTOSEND : std_logic_vector := X"0020"; + constant PAR_AUTOSEND_EA : std_logic_vector := X"0001"; -- enable automatic sending + constant PAR_AUTOSEND_DA : std_logic_vector := X"0000"; -- disable automatic sending -- header length of data packages constant FTM_HEADER_LENGTH : std_logic_vector (7 DOWNTO 0) := X"0B"; + + -- FTU error message + constant FTU_ERROR_LENGTH : std_logic_vector (11 downto 0) := X"01D"; --(number of unsuccessful calls) + (28 * data) = 29 -- FTU-list parameters @@ -249,4 +264,5 @@ constant SD_ADDR_coin_win_p : std_logic_vector := X"01D"; constant SD_ADDR_coin_win_c : std_logic_vector := X"01E"; + constant SD_ADDR_ftu_prescaling_0 : std_logic_vector := X"029"; constant SD_ADDR_ftu_active_cr0 : std_logic_vector := X"1B0"; constant SD_ADDR_ftu_active_cr1 : std_logic_vector := X"1B1"; @@ -264,17 +280,21 @@ -- !!! to be defined !!! constant sd_block_default_array : sd_block_default_array_type := ( - X"0000", -- SD_ADDR_general_settings -- general settings + --X"0080", -- SD_ADDR_general_settings -- general settings + X"0060", -- SD_ADDR_general_settings -- general settings X"0000", -- SD_ADDR_led -- on-board status LEDs - X"0002", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency - X"0003", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers + --X"0400", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency + X"0001", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency + --X"0001", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers + X"0420", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers X"0004", -- SD_ADDR_lp1_amplitude -- light pulser 1 amplitude X"0005", -- SD_ADDR_lp2_amplitude -- light pulser 2 amplitude X"0006", -- SD_ADDR_lp1_delay -- light pulser 1 delay X"0007", -- SD_ADDR_lp2_delay -- light pulser 2 delay - X"0008", -- SD_ADDR_coin_n_p -- majority coincidence n (for physics) - X"0009", -- SD_ADDR_coin_n_c -- majority coincidence n (for calibration) - X"000A", -- SD_ADDR_trigger_delay -- trigger delay - X"000B", -- SD_ADDR_timemarker_delay -- timemarker delay - X"000C", -- SD_ADDR_dead_time -- dead time + X"0001", -- SD_ADDR_coin_n_p -- majority coincidence n (for physics) + X"001E", -- SD_ADDR_coin_n_c -- majority coincidence n (for calibration) + X"0000", -- SD_ADDR_trigger_delay -- trigger delay + X"0000", -- SD_ADDR_timemarker_delay -- timemarker delay + --X"0019", -- SD_ADDR_dead_time -- dead time, 8ns + 4x25ns = 108ns + X"0000", -- SD_ADDR_dead_time -- dead time, 8ns + 4x25ns = 108ns X"0003", -- SD_ADDR_cc_R0_HI -- clock conditioner R0 bits 31...16 X"8000", -- SD_ADDR_cc_R0_LO -- clock conditioner R0 bits 15...0 @@ -293,6 +313,6 @@ X"1400", -- SD_ADDR_cc_R15_HI -- clock conditioner R15 bits 31...16 X"FA0F", -- SD_ADDR_cc_R15_LO -- clock conditioner R15 bits 15...0 - X"001D", -- SD_ADDR_coin_win_p -- majority coincidence window (for physics) - X"001E", -- SD_ADDR_coin_win_c -- majority coincidence window (for calibration) + X"0001", -- SD_ADDR_coin_win_p -- majority coincidence window (for physics), 8ns + 4x1ns = 12ns + X"0001", -- SD_ADDR_coin_win_c -- majority coincidence window (for calibration), 8ns + 4x1ns = 12ns X"001F" -- -- Spare ); @@ -314,5 +334,5 @@ --default values for active FTU lists constant sd_block_default_ftu_active_list : sd_block_default_ftu_active_list_type := ( - X"0001", + X"0000", X"0000", X"0000", @@ -325,6 +345,23 @@ -- Timing counter --- constant tc_width : integer := 48; -- width (number of bits) of timing counter --- constant zero : unsigned (tc_width - 1 downto 0) := (others => '0'); - + -- constant tc_width : integer := 48; -- width (number of bits) of timing counter + -- constant zero : unsigned (tc_width - 1 downto 0) := (others => '0'); + + --====================================================================================== + -- Constants for calibration and pedestal triggers generation + --====================================================================================== + constant LOW_SPEED_CLOCK_FREQ : real := 50000000.0; + constant LOW_SPEED_CLOCK_PERIOD : real := 1.0/LOW_SPEED_CLOCK_FREQ; + constant MS_PERIOD : real := 0.001; + constant MAX_MS_COUNTER_WIDTH : integer := integer(ceil(log2(real(MS_PERIOD/LOW_SPEED_CLOCK_PERIOD)))); + constant MAX_MS_COUNTER_VAL : integer := integer(MS_PERIOD/LOW_SPEED_CLOCK_PERIOD); + --====================================================================================== + + --====================================================================================== + -- Constants for trigger and TIM signals width (8ns+value*4ns) + --====================================================================================== + constant TRIG_SIGNAL_PULSE_WIDTH : integer range 0 to 15 := 10; + constant TIM_SIGNAL_PULSE_WIDTH : integer range 0 to 15 := 0; + --====================================================================================== + end ftm_constants; Index: firmware/FTM/trigger/assembler/FTU_trigger_generator/FTU_trigger_counter.vhd =================================================================== --- firmware/FTM/trigger/assembler/FTU_trigger_generator/FTU_trigger_counter.vhd (revision 10366) +++ firmware/FTM/trigger/assembler/FTU_trigger_generator/FTU_trigger_counter.vhd (revision 10366) @@ -0,0 +1,185 @@ +--======================================================================================= +-- TITLE : Trigger counter top +-- DESCRIPTION : Top entity for trigger synchronization, detection and counting +-- FILE : FTU_trigger_counter.vhd +-- COMPANY : Micro-Cameras & Space Exploration SA +--======================================================================================= +-- CREATION +-- DATE AUTHOR PROJECT REVISION +-- 02/03/2011 JGi FTM 110302a +--======================================================================================= +-- MODIFICATION HISTORY +-- DATE AUTHOR PROJECT REVISION COMMENTS +-- 02/03/2011 JGi FTM 110302a Description +--======================================================================================= +-- Library Definition +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +-- Entity Definition +entity FTU_trigger_counter is + port( --clocks + clk_250MHz : in std_logic; + clk_250MHz_180 : in std_logic; + --control + phys_coinc_window : in std_logic_vector(3 downto 0); + calib_coinc_window : in std_logic_vector(3 downto 0); + active_FTU_list_0 : in std_logic_vector(9 downto 0); + active_FTU_list_1 : in std_logic_vector(9 downto 0); + active_FTU_list_2 : in std_logic_vector(9 downto 0); + active_FTU_list_3 : in std_logic_vector(9 downto 0); + --trigger primitives from FTUs + trig_prim_0 : in std_logic_vector(9 downto 0); --crate 0 + trig_prim_1 : in std_logic_vector(9 downto 0); --crate 1 + trig_prim_2 : in std_logic_vector(9 downto 0); --crate 2 + trig_prim_3 : in std_logic_vector(9 downto 0); --crate 3 + --trigger detection pulses + phys_events : out std_logic_vector(5 downto 0); + calib_events : out std_logic_vector(5 downto 0)); +end FTU_trigger_counter; + +-- Architecture Definition +architecture RTL of FTU_trigger_counter is + + component input_synch is + port( clk_250MHz : in std_logic; + clk_250MHz_180 : in std_logic; + trig_prim_0 : in std_logic_vector(9 downto 0); + trig_prim_1 : in std_logic_vector(9 downto 0); + trig_prim_2 : in std_logic_vector(9 downto 0); + trig_prim_3 : in std_logic_vector(9 downto 0); + trig_synch_0_rise : out std_logic_vector(9 downto 0); + trig_synch_1_rise : out std_logic_vector(9 downto 0); + trig_synch_2_rise : out std_logic_vector(9 downto 0); + trig_synch_3_rise : out std_logic_vector(9 downto 0); + trig_synch_0_fall : out std_logic_vector(9 downto 0); + trig_synch_1_fall : out std_logic_vector(9 downto 0); + trig_synch_2_fall : out std_logic_vector(9 downto 0); + trig_synch_3_fall : out std_logic_vector(9 downto 0)); + end component; + + signal i_trig_synch_0_rise : std_logic_vector(9 downto 0); + signal i_trig_synch_1_rise : std_logic_vector(9 downto 0); + signal i_trig_synch_2_rise : std_logic_vector(9 downto 0); + signal i_trig_synch_3_rise : std_logic_vector(9 downto 0); + signal i_trig_synch_0_fall : std_logic_vector(9 downto 0); + signal i_trig_synch_1_fall : std_logic_vector(9 downto 0); + signal i_trig_synch_2_fall : std_logic_vector(9 downto 0); + signal i_trig_synch_3_fall : std_logic_vector(9 downto 0); + + component time_window is + port( clk_250MHz : in std_logic; + coinc_window : in std_logic_vector(3 downto 0); + active_FTU_list_0 : in std_logic_vector(9 downto 0); + active_FTU_list_1 : in std_logic_vector(9 downto 0); + active_FTU_list_2 : in std_logic_vector(9 downto 0); + active_FTU_list_3 : in std_logic_vector(9 downto 0); + trig_synch_0_rise : in std_logic_vector(9 downto 0); + trig_synch_1_rise : in std_logic_vector(9 downto 0); + trig_synch_2_rise : in std_logic_vector(9 downto 0); + trig_synch_3_rise : in std_logic_vector(9 downto 0); + trig_synch_0_fall : in std_logic_vector(9 downto 0); + trig_synch_1_fall : in std_logic_vector(9 downto 0); + trig_synch_2_fall : in std_logic_vector(9 downto 0); + trig_synch_3_fall : in std_logic_vector(9 downto 0); + trig_window_0 : out std_logic_vector(9 downto 0); + trig_window_1 : out std_logic_vector(9 downto 0); + trig_window_2 : out std_logic_vector(9 downto 0); + trig_window_3 : out std_logic_vector(9 downto 0)); + end component; + + signal i_trig_phys_window_0 : std_logic_vector(9 downto 0); + signal i_trig_phys_window_1 : std_logic_vector(9 downto 0); + signal i_trig_phys_window_2 : std_logic_vector(9 downto 0); + signal i_trig_phys_window_3 : std_logic_vector(9 downto 0); + signal i_trig_calib_window_0 : std_logic_vector(9 downto 0); + signal i_trig_calib_window_1 : std_logic_vector(9 downto 0); + signal i_trig_calib_window_2 : std_logic_vector(9 downto 0); + signal i_trig_calib_window_3 : std_logic_vector(9 downto 0); + + component trigger_sum is + port( clk_250MHz : in std_logic; + trig_window_0 : in std_logic_vector(9 downto 0); + trig_window_1 : in std_logic_vector(9 downto 0); + trig_window_2 : in std_logic_vector(9 downto 0); + trig_window_3 : in std_logic_vector(9 downto 0); + number_of_events : out std_logic_vector(5 downto 0)); + end component; + +begin + + -- Component instantiation + inst_synch: input_synch + port map( clk_250MHz => clk_250MHz, + clk_250MHz_180 => clk_250MHz_180, + trig_prim_0 => trig_prim_0, + trig_prim_1 => trig_prim_1, + trig_prim_2 => trig_prim_2, + trig_prim_3 => trig_prim_3, + trig_synch_0_rise => i_trig_synch_0_rise, + trig_synch_1_rise => i_trig_synch_1_rise, + trig_synch_2_rise => i_trig_synch_2_rise, + trig_synch_3_rise => i_trig_synch_3_rise, + trig_synch_0_fall => i_trig_synch_0_fall, + trig_synch_1_fall => i_trig_synch_1_fall, + trig_synch_2_fall => i_trig_synch_2_fall, + trig_synch_3_fall => i_trig_synch_3_fall); + + inst_phys_window: time_window + port map( clk_250MHz => clk_250MHz, + coinc_window => phys_coinc_window, + active_FTU_list_0 => active_FTU_list_0, + active_FTU_list_1 => active_FTU_list_1, + active_FTU_list_2 => active_FTU_list_2, + active_FTU_list_3 => active_FTU_list_3, + trig_synch_0_rise => i_trig_synch_0_rise, + trig_synch_1_rise => i_trig_synch_1_rise, + trig_synch_2_rise => i_trig_synch_2_rise, + trig_synch_3_rise => i_trig_synch_3_rise, + trig_synch_0_fall => i_trig_synch_0_fall, + trig_synch_1_fall => i_trig_synch_1_fall, + trig_synch_2_fall => i_trig_synch_2_fall, + trig_synch_3_fall => i_trig_synch_3_fall, + trig_window_0 => i_trig_phys_window_0, + trig_window_1 => i_trig_phys_window_1, + trig_window_2 => i_trig_phys_window_2, + trig_window_3 => i_trig_phys_window_3); + + inst_calib_window: time_window + port map( clk_250MHz => clk_250MHz, + coinc_window => calib_coinc_window, + active_FTU_list_0 => active_FTU_list_0, + active_FTU_list_1 => active_FTU_list_1, + active_FTU_list_2 => active_FTU_list_2, + active_FTU_list_3 => active_FTU_list_3, + trig_synch_0_rise => i_trig_synch_0_rise, + trig_synch_1_rise => i_trig_synch_1_rise, + trig_synch_2_rise => i_trig_synch_2_rise, + trig_synch_3_rise => i_trig_synch_3_rise, + trig_synch_0_fall => i_trig_synch_0_fall, + trig_synch_1_fall => i_trig_synch_1_fall, + trig_synch_2_fall => i_trig_synch_2_fall, + trig_synch_3_fall => i_trig_synch_3_fall, + trig_window_0 => i_trig_calib_window_0, + trig_window_1 => i_trig_calib_window_1, + trig_window_2 => i_trig_calib_window_2, + trig_window_3 => i_trig_calib_window_3); + + inst_phys_final_sum: trigger_sum + port map( clk_250MHz => clk_250MHz, + trig_window_0 => i_trig_phys_window_0, + trig_window_1 => i_trig_phys_window_1, + trig_window_2 => i_trig_phys_window_2, + trig_window_3 => i_trig_phys_window_3, + number_of_events => phys_events); + + inst_calib_final_sum: trigger_sum + port map( clk_250MHz => clk_250MHz, + trig_window_0 => i_trig_calib_window_0, + trig_window_1 => i_trig_calib_window_1, + trig_window_2 => i_trig_calib_window_2, + trig_window_3 => i_trig_calib_window_3, + number_of_events => calib_events); + +end RTL; Index: firmware/FTM/trigger/drivers/calibration_pedestal/calibration_pedestal.vhd =================================================================== --- firmware/FTM/trigger/drivers/calibration_pedestal/calibration_pedestal.vhd (revision 10366) +++ firmware/FTM/trigger/drivers/calibration_pedestal/calibration_pedestal.vhd (revision 10366) @@ -0,0 +1,270 @@ +--======================================================================================= +-- TITLE : Calibration and pedestal triggers generation +-- DESCRIPTION : Generate LP1, LP2 and PEDESTAL pulses for calibration runs +-- FILE : calibration_pedestal.vhd +-- COMPANY : Micro-Cameras & Space Exploration SA +--======================================================================================= +-- CREATION +-- DATE AUTHOR PROJECT REVISION +-- 11/03/2011 JGi 110311a +--======================================================================================= +-- MODIFICATION HISTORY +-- DATE AUTHOR PROJECT REVISION COMMENTS +-- 11/03/2011 JGi 110311a Description +-- 13/04/2011 JGi 110413a Update pulse enable management to allow the +-- same pulse to be enabled if no others are. +--======================================================================================= +-- Library Definition +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library ftm_definitions; + use ftm_definitions.ftm_array_types.all; + use ftm_definitions.ftm_constants.all; + +-- Entity Definition +entity calibration_pedestal is + port( --clock + clk_50MHz : in std_logic; + --control + new_config : in std_logic; + --settings + general_settings : in std_logic_vector(7 downto 0); + LP_and_PED_freq : in std_logic_vector(9 downto 0); + LP1_LP2_PED_ratio : in std_logic_vector(14 downto 0); + --outputs + LP1_pulse : out std_logic; --send start signal to light pulser 1 + LP2_pulse : out std_logic; --send start signal to light pulser 2 + PED_pulse : out std_logic); +end calibration_pedestal; + +-- Architecture Definition +architecture RTL of calibration_pedestal is + + type t_reg is record + -- Internal register declaration + new_config : std_logic; + general_settings : std_logic_vector(7 downto 0); + LP_and_PED_freq : std_logic_vector(9 downto 0); + LP1_LP2_PED_ratio : std_logic_vector(14 downto 0); + ms_counter : unsigned(MAX_MS_COUNTER_WIDTH-1 downto 0); + ms_tick : std_logic; + tick_counter : unsigned(9 downto 0); + trigger_tick : std_logic; + trigger_counter : unsigned(4 downto 0); + enable_LP1 : std_logic; + enable_LP2 : std_logic; + enable_PED : std_logic; + -- Ouput register declaration + LP1_pulse : std_logic; + LP2_pulse : std_logic; + PED_pulse : std_logic; + end record; + + signal i_next_reg : t_reg := (new_config => '0', + general_settings => (others => '0'), + LP_and_PED_freq => (others => '0'), + LP1_LP2_PED_ratio => (others => '0'), + ms_counter => (others => '0'), + ms_tick => '0', + tick_counter => (others => '0'), + trigger_tick => '0', + trigger_counter => (others => '0'), + enable_LP1 => '0', + enable_LP2 => '0', + enable_PED => '0', + LP1_pulse => '0', + LP2_pulse => '0', + PED_pulse => '0'); + signal i_reg : t_reg := (new_config => '0', + general_settings => (others => '0'), + LP_and_PED_freq => (others => '0'), + LP1_LP2_PED_ratio => (others => '0'), + ms_counter => (others => '0'), + ms_tick => '0', + tick_counter => (others => '0'), + trigger_tick => '0', + trigger_counter => (others => '0'), + enable_LP1 => '0', + enable_LP2 => '0', + enable_PED => '0', + LP1_pulse => '0', + LP2_pulse => '0', + PED_pulse => '0'); + +begin + + -- Combinatorial logic + process(new_config, general_settings, LP_and_PED_freq, + LP1_LP2_PED_ratio, i_reg) + variable v_reg : t_reg := (new_config => '0', + general_settings => (others => '0'), + LP_and_PED_freq => (others => '0'), + LP1_LP2_PED_ratio => (others => '0'), + ms_counter => (others => '0'), + ms_tick => '0', + tick_counter => (others => '0'), + trigger_tick => '0', + trigger_counter => (others => '0'), + enable_LP1 => '0', + enable_LP2 => '0', + enable_PED => '0', + LP1_pulse => '0', + LP2_pulse => '0', + PED_pulse => '0'); + begin + v_reg := i_reg; + --=================================================================================== + + --=================================================================================== + -- Milliseconds counter + --=================================================================================== + v_reg.ms_tick := '0'; + + -- Counter management + -- Count until 1ms is reached + if i_reg.ms_counter = to_unsigned(MAX_MS_COUNTER_VAL, MAX_MS_COUNTER_WIDTH)-1 then + v_reg.ms_counter := (others => '0'); + v_reg.ms_tick := '1'; + else + v_reg.ms_counter := i_reg.ms_counter+1; + end if; + --=================================================================================== + + --=================================================================================== + -- Triggers counter + --=================================================================================== + v_reg.trigger_tick := '0'; + + -- Generate a tick each time the pulse generation period is reached + if i_reg.tick_counter = unsigned(i_reg.LP_and_PED_freq(9 downto 0)) then + v_reg.tick_counter := (others => '0'); + v_reg.trigger_tick := '1'; + elsif i_reg.ms_tick = '1' then + v_reg.tick_counter := i_reg.tick_counter+1; + end if; + --=================================================================================== + + --=================================================================================== + -- Triggers management + --=================================================================================== + v_reg.new_config := new_config; + + -- Register parameters when new configuration is set + if new_config = '1' and i_reg.new_config = '0' then + v_reg.general_settings := general_settings; + v_reg.LP_and_PED_freq := LP_and_PED_freq; + v_reg.LP1_LP2_PED_ratio := LP1_LP2_PED_ratio; + end if; + + -- Manages pulses + if i_reg.enable_LP1 = '1' then + -- Wait for set number of pulse of LP1 + if i_reg.trigger_tick = '1' then + v_reg.trigger_counter := i_reg.trigger_counter+1; + -- If number of pulse reached + elsif i_reg.trigger_counter = unsigned(i_reg.LP1_LP2_PED_ratio(4 downto 0)) then + v_reg.trigger_counter := (others => '0'); + v_reg.enable_LP1 := '0'; + -- Switch to next pulse enable + if i_reg.general_settings(5) = '1' then + v_reg.enable_LP2 := '1'; + elsif i_reg.general_settings(6) = '1' then + v_reg.enable_PED := '1'; + elsif i_reg.general_settings(4) = '1' then + v_reg.enable_LP1 := '1'; + end if; + end if; + elsif i_reg.enable_LP2 = '1' then + -- Wait for set number of pulse of LP2 + if i_reg.trigger_tick = '1' then + v_reg.trigger_counter := i_reg.trigger_counter+1; + -- If number of pulse reached + elsif i_reg.trigger_counter = unsigned(i_reg.LP1_LP2_PED_ratio(9 downto 5)) then + v_reg.trigger_counter := (others => '0'); + v_reg.enable_LP2 := '0'; + -- Switch to next pulse enable + if i_reg.general_settings(6) = '1' then + v_reg.enable_PED := '1'; + elsif i_reg.general_settings(4) = '1' then + v_reg.enable_LP1 := '1'; + elsif i_reg.general_settings(5) = '1' then + v_reg.enable_LP2 := '1'; + end if; + end if; + elsif i_reg.enable_PED = '1' then + -- Wait for set number of pulse of PED + if i_reg.trigger_tick = '1' then + v_reg.trigger_counter := i_reg.trigger_counter+1; + -- If number of pulse reached + elsif i_reg.trigger_counter = unsigned(i_reg.LP1_LP2_PED_ratio(14 downto 10)) then + v_reg.trigger_counter := (others => '0'); + v_reg.enable_PED := '0'; + -- Switch to next pulse enable + if i_reg.general_settings(4) = '1' then + v_reg.enable_LP1 := '1'; + elsif i_reg.general_settings(5) = '1' then + v_reg.enable_LP2 := '1'; + elsif i_reg.general_settings(6) = '1' then + v_reg.enable_PED := '1'; + end if; + end if; + else + v_reg.trigger_counter := (others => '0'); + end if; + + -- Enable first selected pulse when new configuration is registered + -- It's made after ratio counter to avoid error if new configuration + -- is done on the same time pulse enables change in the ratio counter + if new_config = '0' and i_reg.new_config = '1' then + v_reg.enable_LP1 := '0'; + v_reg.enable_LP2 := '0'; + v_reg.enable_PED := '0'; + if i_reg.general_settings(4) = '1' then + v_reg.enable_LP1 := '1'; + elsif i_reg.general_settings(5) = '1' then + v_reg.enable_LP2 := '1'; + elsif i_reg.general_settings(6) = '1' then + v_reg.enable_PED := '1'; + end if; + end if; + + -- Set enabled pulse on output + if i_reg.trigger_tick = '1' then + if i_reg.enable_LP1 = '1' then + v_reg.LP1_pulse := '1'; + elsif i_reg.enable_LP2 = '1' then + v_reg.LP2_pulse := '1'; + elsif i_reg.enable_PED = '1' then + v_reg.PED_pulse := '1'; + end if; + -- Once set, pulse is reset + else + v_reg.LP1_pulse := '0'; + v_reg.LP2_pulse := '0'; + v_reg.PED_pulse := '0'; + end if; + --=================================================================================== + + --=================================================================================== + -- Drive register input + i_next_reg <= v_reg; + + --=================================================================================== + -- Output assignation + LP1_pulse <= i_reg.LP1_pulse; + LP2_pulse <= i_reg.LP2_pulse; + PED_pulse <= i_reg.PED_pulse; + --=================================================================================== + end process; + + -- Sequential logic + process(clk_50MHz) + begin + if rising_edge(clk_50MHz) then + i_reg <= i_next_reg; + end if; + end process; + +end RTL; Index: firmware/FTM/trigger/drivers/deadtime_generator/deadtime_generator.vhd =================================================================== --- firmware/FTM/trigger/drivers/deadtime_generator/deadtime_generator.vhd (revision 10366) +++ firmware/FTM/trigger/drivers/deadtime_generator/deadtime_generator.vhd (revision 10366) @@ -0,0 +1,176 @@ +--======================================================================================= +-- TITLE : Deadtime manager +-- DESCRIPTION : Timer for deadtime generation +-- FILE : deadtime_generator.vhd +-- COMPANY : Micro-Cameras & Space Exploration SA +--======================================================================================= +-- CREATION +-- DATE AUTHOR PROJECT REVISION +-- 02/03/2011 JGi FTM 110302a +--======================================================================================= +-- MODIFICATION HISTORY +-- DATE AUTHOR PROJECT REVISION COMMENTS +-- 02/03/2011 JGi FTM 110302a Description +-- 13/04/2011 JGi FTM 110413a Remove unused signal +--======================================================================================= +-- Library Definition +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +-- Entity Definition +entity deadtime_generator is + port( --clock + clk_250MHz : in std_logic; + --control + deadtime : in std_logic_vector(15 downto 0); + --I/O + start : in std_logic; + waiting : out std_logic); +end deadtime_generator; + +-- Architecture Definition +architecture RTL of deadtime_generator is + + type t_reg is record + -- Internal register declaration + deadtime : std_logic_vector(15 downto 0); + deadtime_counter : std_logic_vector(15 downto 0); + deadtime_value_reached : std_logic_vector(3 downto 0); + deadtime_0_done : std_logic_vector(2 downto 0); + deadtime_1_done : std_logic_vector(1 downto 0); + deadtime_2_done : std_logic; + -- Ouput register declaration + busy : std_logic_vector(2 downto 0); + end record; + + signal i_next_reg : t_reg := (deadtime => (others => '0'), + deadtime_counter => (others => '0'), + deadtime_value_reached => (others => '0'), + deadtime_0_done => (others => '0'), + deadtime_1_done => (others => '0'), + deadtime_2_done => '0', + busy => (others => '0')); + signal i_reg : t_reg := (deadtime => (others => '0'), + deadtime_counter => (others => '0'), + deadtime_value_reached => (others => '0'), + deadtime_0_done => (others => '0'), + deadtime_1_done => (others => '0'), + deadtime_2_done => '0', + busy => (others => '0')); + +begin + + -- Combinatorial logic + process(start, deadtime, i_reg) + variable v_reg : t_reg := (deadtime => (others => '0'), + deadtime_counter => (others => '0'), + deadtime_value_reached => (others => '0'), + deadtime_0_done => (others => '0'), + deadtime_1_done => (others => '0'), + deadtime_2_done => '0', + busy => (others => '0')); + begin + v_reg := i_reg; + --=================================================================================== + + --=================================================================================== + -- Counter management + --=================================================================================== + -- Register deadtime to reduce delay + v_reg.deadtime := deadtime; + + -- If deadtime enabled, count + if i_reg.busy(0) = '1' then + v_reg.deadtime_counter(3 downto 0) := + std_logic_vector(unsigned(i_reg.deadtime_counter(3 downto 0))+1); + if i_reg.deadtime_0_done(2) = '1' then + v_reg.deadtime_counter(7 downto 4) := + std_logic_vector(unsigned(i_reg.deadtime_counter(7 downto 4))+1); + end if; + if i_reg.deadtime_1_done(1) = '1' then + v_reg.deadtime_counter(11 downto 8) := + std_logic_vector(unsigned(i_reg.deadtime_counter(11 downto 8))+1); + end if; + if i_reg.deadtime_2_done = '1' then + v_reg.deadtime_counter(15 downto 12) := + std_logic_vector(unsigned(i_reg.deadtime_counter(15 downto 12))+1); + end if; + else + v_reg.deadtime_counter := (others => '0'); + end if; + + -- If counter reached the deadtime value + if i_reg.deadtime_value_reached = "1111" then + v_reg.busy := (others => '0'); + end if; + + -- Start when input goes high + if start = '1' then + v_reg.busy := (others => '1'); + end if; + + -- Generate partial comparison to the programmed deadtime value + if i_reg.deadtime_counter(3 downto 0) = i_reg.deadtime(3 downto 0) then + v_reg.deadtime_value_reached(0) := i_reg.busy(1); + else + v_reg.deadtime_value_reached(0) := '0'; + end if; + if i_reg.deadtime_counter(7 downto 4) = i_reg.deadtime(7 downto 4) then + v_reg.deadtime_value_reached(1) := i_reg.busy(1); + else + v_reg.deadtime_value_reached(1) := '0'; + end if; + if i_reg.deadtime_counter(11 downto 8) = i_reg.deadtime(11 downto 8) then + v_reg.deadtime_value_reached(2) := i_reg.busy(1); + else + v_reg.deadtime_value_reached(2) := '0'; + end if; + if i_reg.deadtime_counter(15 downto 12) = i_reg.deadtime(15 downto 12) then + v_reg.deadtime_value_reached(3) := i_reg.busy(1); + else + v_reg.deadtime_value_reached(3) := '0'; + end if; + + -- Manage partial counters enable + if i_reg.deadtime_counter(3 downto 0) = "1100" then + v_reg.deadtime_0_done(0) := '1'; + else + v_reg.deadtime_0_done(0) := '0'; + end if; + v_reg.deadtime_0_done(1) := i_reg.deadtime_0_done(0); + v_reg.deadtime_0_done(2) := i_reg.deadtime_0_done(1); + + if i_reg.deadtime_counter(7 downto 4) = "1111" then + v_reg.deadtime_1_done(0) := i_reg.deadtime_0_done(0); + else + v_reg.deadtime_1_done(0) := '0'; + end if; + v_reg.deadtime_1_done(1) := i_reg.deadtime_1_done(0); + + if i_reg.deadtime_counter(11 downto 8) = "1111" then + v_reg.deadtime_2_done := i_reg.deadtime_0_done(1) and i_reg.deadtime_1_done(0); + else + v_reg.deadtime_2_done := '0'; + end if; + --=================================================================================== + + --=================================================================================== + -- Drive register input + i_next_reg <= v_reg; + + --=================================================================================== + -- Output assignation + waiting <= i_reg.busy(2); + --=================================================================================== + end process; + + -- Sequential logic + process(clk_250MHz) + begin + if rising_edge(clk_250MHz) then + i_reg <= i_next_reg; + end if; + end process; + +end RTL; Index: firmware/FTM/trigger/drivers/detection_logic/adder_3_bits.ngc =================================================================== --- firmware/FTM/trigger/drivers/detection_logic/adder_3_bits.ngc (revision 10366) +++ firmware/FTM/trigger/drivers/detection_logic/adder_3_bits.ngc (revision 10366) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.5e +$95x52=#Zl|bdaa:!3-647)<'82,)?40292*5c<;3CE\XZ5a=094;c<;3CE\XZ5b=094;`<;zn:4=>nff442(2a3=0DYY^ZT;q?7?6992<87O[=8:@VWZOINF;0O<<4CIG@OZJNKLDXIRZVPD08GL?BN:2LO=6I<;FLG6>O7:2C:56GAIUQWEQC53EC=7AANDDF4?II@AJKG86BZT378IP^DQj1Fmga}Vdppmjhd3DcecXjrrklj6=I9>90B<6<;O3:6>H5;2D9;N08KN7 i^`bw`dkgq$bSoo|ecnl|Zgclzi#caPphrfhlhnfn$dhQndeqvf*oXd|~?"dQcuu6\eabt}k%cmah|ul>1:3e<]9%bSoo|ecnl|+oXjhynnaaw_`fgwpd(ffU{e}kciokmc+romVkoh~{m/h]oqq2)aVf~x9Qndeqvf*oXy'cTdcld,rv`a(nm%dyy~zt=3=2f=R8&cTnl}jbmm{*lYeizoi`bvPaefpqg)igVzb|hbfnhld*qnbWhnoxl i^nvp1(nWe8Rokdrwa+lYv&`Uxe`~ce/sqab)al&e~x}{{<3<5g>S7'`Uim~kmlnz-mZdf{lhgcuQndeqvf*hhWyc{iagaioe-pmcXimnxyo!f_mww0+oXd|~?Sljkst`,mZw)aVyba}bj.ppfc*`c'f|xz33?4`?P6(aVhjhlcoy,j[ggtmkfdtRokdrwa+kiXx`zn`d`fnf,wl`Yflmy~n"gPltv7*lYk}}>Tmij|uc-j[t(nWzcf|ak!qsgd+cb(g|~{yy2;>7`8Q5)nWkkxiob`x/k\fdubjeesSljkst`,jjYwayogecgag/vkaZgclzi#dQcuu6-mZjr|=Ujhi}zb.k\u+oX{`g{`h ~rde,ba)h}}z~xR?9b:W3+lYeizoi`bv!i^`bw`dkgqUjhi}zb.ll[uowmeceeci!tig\eabt}k%bSa{{4/k\hpr3Whnoxl i^s-mZuneyfn"||jg.dg+jssx|~T>;l4U1-j[ggtmkfdt#gPb`qffiiWhnoxl nn]smuckagcek#zge^cg`vse'`Ugyy:!i^nvp1Yflmy~n"gPq/k\wlkwdl$z~hi fe-lqqvr|V9=n6[?/h]aevcedfr%eRlnsd`ok}Yflmy~n"``_qksaioiagm%xekPaefpqg)nWe8#gPltv7[dbc{|h$eR!i^qjiujb&xxnk"hk/nwwtprX%eRbzt5]b`aurj&cTdcld]nkack&jky~tv`r15g?P6(aVhjhlcoy,j[ggtmkfdtRokdrwa+kiXx`zn`d`fnf,wl`Yflmy~n"gPltv7*lYk}}>Tmij|uc-j[vojxeoTabjjl/k\cqY6&jky~tmgahldak]6U'ij~wbuy5g?P6(aVhjhlcoy,j[ggtmkfdtRokdrwa+kiXx`zn`d`fnf,wl`Yflmy~n"gPltv7*lYk}}>Tmij|uc-j[vojxeoTabjjl/k\cqY6&jky~tmgahldak]6U'ij~wwos5g?P6(aVhjhlcoy,j[ggtmkfdtRokdrwa+kiXx`zn`d`fnf,wl`Yflmy~n"gPltv7*lYk}}>Tmij|uc-j[vojxeoTabjjl/k\cqY6&jky~tmgahldak]5U'ij~wbuy5g?P6(aVhjhlcoy,j[ggtmkfdtRokdrwa+kiXx`zn`d`fnf,wl`Yflmy~n"gPltv7*lYk}}>Tmij|uc-j[vojxeoTabjjl/k\cqY6&jky~tmgahldak]5U'ij~wwos4e?P6(aVhjhlcoy,j[ggtmkfdtRokdrwa+kiXx`zn`d`fnf,wl`Yflmy~n"gPltv7*lYk}}>Tmij|uc-j[vojxeoTabjjl/k\cqY6&jky~tv`rums34=R8&cTnl}jbmm{*lYeizoi`bvPaefpqg)igVzb|hbfnhld*qnbWhnoxl i^nvp1(nWe8Rokdrwa+lYtadzgiRc`ddn-mZhbmmUfyu laspzip~7=k1^<"gPb`qffii&`Uim~kmlnz\eabt}k%ecR~fpdnjjlh`&}bnSljkst`,mZjr|=$bSa{{4^cg`vse'zfS~gbpmg?4;3e3\:$eRlnsd`ok}(nWkkxiob`x^cg`vse'geT|d~jlhljjb(s`lUjhi}zb.k\hpr3&`Ugyy:Paefpqg)t}dUxe`~ce=3=1g=R8&cTnl}jbmm{*lYeizoi`bvPaefpqg)igVzb|hbfnhld*qnbWhnoxl i^nvp1(nWe8Rokdrwa+vsjWzcf|ak32?7a?P6(aVhjhlcoy,j[ggtmkfdtRokdrwa+kiXx`zn`d`fnf,wl`Yflmy~n"gPltv7*lYk}}>Tmij|uc-pqhYtadzgi1=1a:WPAWYFD@KXo6[\ES]UMVOEDL90ZNM6;WKFSZR^XL;o7UGCIOZ.\AD'8';+_Y[M 1,2$DUDA@?0TB\LY79[WQJNJ>1S_YQHNE`8\ZEHZLUBBKA9;Yfa[Lba3QncS]|fmWgqwlii991Sh`QBakmqR`ttafd:<6Vkm^OjjjtQm{ybcc?;;^ad+dbcm{U8Sog{s/ldk1=f 9#?7l&>)59b,7/33h6;295n<0<5?d:5294?7l2=>29b`aeQmiuq/gZgclziS{?>_1.MKKC+FFDN=5:4aeffvZ5Xj`~x nQndeqvfZp69V:'wnQn_vkgpm;4$jUdyyQxievk91*dWhnoS`ake<2/gZnf{ViTcxz20-a\fZr~xl7: nQmosplsZjh4;'oRmj_ntfvwocmzUxoa|20-a\mhvkmdoexlzfoo?3(fYoizUxoa|20-a\hdrbfjs6=!mPh`q\f|vf{z7; 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Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2009 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file adder_3_bits.vhd when simulating +-- the core, adder_3_bits. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +Library XilinxCoreLib; +-- synthesis translate_on +ENTITY adder_3_bits IS + port ( + a: IN std_logic_VECTOR(2 downto 0); + b: IN std_logic_VECTOR(2 downto 0); + clk: IN std_logic; + s: OUT std_logic_VECTOR(3 downto 0)); +END adder_3_bits; + +ARCHITECTURE adder_3_bits_a OF adder_3_bits IS +-- synthesis translate_off +component wrapped_adder_3_bits + port ( + a: IN std_logic_VECTOR(2 downto 0); + b: IN std_logic_VECTOR(2 downto 0); + clk: IN std_logic; + s: OUT std_logic_VECTOR(3 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_adder_3_bits use entity XilinxCoreLib.c_addsub_v11_0(behavioral) + generic map( + c_a_width => 3, + c_out_width => 4, + c_add_mode => 0, + c_has_c_out => 0, + c_b_type => 1, + c_borrow_low => 1, + c_ce_overrides_sclr => 0, + c_implementation => 0, + c_has_sclr => 0, + c_verbosity => 0, + c_latency => 1, + c_has_bypass => 0, + c_ainit_val => "0", + c_bypass_low => 0, + c_has_ce => 0, + c_sclr_overrides_sset => 0, + c_sinit_val => "0", + c_has_sset => 0, + c_has_c_in => 0, + c_has_sinit => 0, + c_b_constant => 0, + c_ce_overrides_bypass => 1, + c_xdevicefamily => "spartan3adsp", + c_a_type => 1, + c_b_width => 3, + c_b_value => "000"); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_adder_3_bits + port map ( + a => a, + b => b, + clk => clk, + s => s); +-- synthesis translate_on + +END adder_3_bits_a; + Index: firmware/FTM/trigger/drivers/detection_logic/adder_4_bits.ngc =================================================================== --- firmware/FTM/trigger/drivers/detection_logic/adder_4_bits.ngc (revision 10366) +++ firmware/FTM/trigger/drivers/detection_logic/adder_4_bits.ngc (revision 10366) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.5e 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c_ce_overrides_bypass => 1, + c_xdevicefamily => "spartan3adsp", + c_a_type => 1, + c_b_width => 4, + c_b_value => "0000"); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_adder_4_bits + port map ( + a => a, + b => b, + clk => clk, + s => s); +-- synthesis translate_on + +END adder_4_bits_a; + Index: firmware/FTM/trigger/drivers/detection_logic/adder_5_bits.ngc =================================================================== --- firmware/FTM/trigger/drivers/detection_logic/adder_5_bits.ngc (revision 10366) +++ firmware/FTM/trigger/drivers/detection_logic/adder_5_bits.ngc (revision 10366) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.5e 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3>=:11vqclm:181M0>3tdio7>52zJ5=>{ijm0;6?uG689~jgc=838pD;74}o`e>5<5sA<27p`l0;296~N112weo<4?:3yK2<=zfj81<77}O>01vbn850;0xL3?vF99:mg<<72;qC:45rnbc94?4|@?30qcmm:181M0>3td2m7>51zJ5=>{iik0;65<6sA<27p`ne;295~N112wemk4?:0yK2<=zfk:1<7?tH7;8ykd6290:wE86;|la6?6=9rB=56sab283>4}O>01vbo:50;3xL3?6=4>{I4:?xhe>3:1=vF99:mf2<728qC:45rnc:94?7|@?30qcl6:182M0>3tdim7>51zJ5=>{zutJKOvkj:c50g12bitJKNv>r@ARxyEF Index: firmware/FTM/trigger/drivers/detection_logic/adder_5_bits.vhd =================================================================== --- firmware/FTM/trigger/drivers/detection_logic/adder_5_bits.vhd (revision 10366) +++ firmware/FTM/trigger/drivers/detection_logic/adder_5_bits.vhd (revision 10366) @@ -0,0 +1,102 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2009 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file adder_5_bits.vhd when simulating +-- the core, adder_5_bits. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +Library XilinxCoreLib; +-- synthesis translate_on +ENTITY adder_5_bits IS + port ( + a: IN std_logic_VECTOR(4 downto 0); + b: IN std_logic_VECTOR(4 downto 0); + clk: IN std_logic; + s: OUT std_logic_VECTOR(5 downto 0)); +END adder_5_bits; + +ARCHITECTURE adder_5_bits_a OF adder_5_bits IS +-- synthesis translate_off +component wrapped_adder_5_bits + port ( + a: IN std_logic_VECTOR(4 downto 0); + b: IN std_logic_VECTOR(4 downto 0); + clk: IN std_logic; + s: OUT std_logic_VECTOR(5 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_adder_5_bits use entity XilinxCoreLib.c_addsub_v11_0(behavioral) + generic map( + c_a_width => 5, + c_out_width => 6, + c_add_mode => 0, + c_has_c_out => 0, + c_b_type => 1, + c_borrow_low => 1, + c_ce_overrides_sclr => 0, + c_implementation => 0, + c_has_sclr => 0, + c_verbosity => 0, + c_latency => 1, + c_has_bypass => 0, + c_ainit_val => "0", + c_bypass_low => 0, + c_has_ce => 0, + c_sclr_overrides_sset => 0, + c_sinit_val => "0", + c_has_sset => 0, + c_has_c_in => 0, + c_has_sinit => 0, + c_b_constant => 0, + c_ce_overrides_bypass => 1, + c_xdevicefamily => "spartan3adsp", + c_a_type => 1, + c_b_width => 5, + c_b_value => "00000"); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_adder_5_bits + port map ( + a => a, + b => b, + clk => clk, + s => s); +-- synthesis translate_on + +END adder_5_bits_a; + Index: firmware/FTM/trigger/drivers/detection_logic/trigger_sum.vhd =================================================================== --- firmware/FTM/trigger/drivers/detection_logic/trigger_sum.vhd (revision 10366) +++ firmware/FTM/trigger/drivers/detection_logic/trigger_sum.vhd (revision 10366) @@ -0,0 +1,169 @@ +--======================================================================================= +-- TITLE : Sum of physics or calibration triggers +-- DESCRIPTION : Convert number of inputs to '1' on 40bits to a sum on 6bits. +-- FILE : trigger_sum.vhd +-- COMPANY : Micro-Cameras & Space Exploration SA +--======================================================================================= +-- CREATION +-- DATE AUTHOR PROJECT REVISION +-- 07/03/2011 JGi 110307a +--======================================================================================= +-- MODIFICATION HISTORY +-- DATE AUTHOR PROJECT REVISION COMMENTS +-- 07/03/2011 JGi 110307a Description +--======================================================================================= +-- Library Definition +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +-- Entity Definition +entity trigger_sum is + port( --clk + clk_250MHz : in std_logic; + --inputs + trig_window_0 : in std_logic_vector(9 downto 0); + trig_window_1 : in std_logic_vector(9 downto 0); + trig_window_2 : in std_logic_vector(9 downto 0); + trig_window_3 : in std_logic_vector(9 downto 0); + --output + number_of_events : out std_logic_vector(5 downto 0)); +end trigger_sum; + +-- Architecture Definition +architecture RTL of trigger_sum is + + component unary_to_binary is + port( clk_250MHz : in std_logic; + vector_in : in std_logic_vector(4 downto 0); + result : out std_logic_vector(2 downto 0)); + end component; + + signal i_bin_to_dec_result_0 : std_logic_vector(2 downto 0); + signal i_bin_to_dec_result_1 : std_logic_vector(2 downto 0); + signal i_bin_to_dec_result_2 : std_logic_vector(2 downto 0); + signal i_bin_to_dec_result_3 : std_logic_vector(2 downto 0); + signal i_bin_to_dec_result_4 : std_logic_vector(2 downto 0); + signal i_bin_to_dec_result_5 : std_logic_vector(2 downto 0); + signal i_bin_to_dec_result_6 : std_logic_vector(2 downto 0); + signal i_bin_to_dec_result_7 : std_logic_vector(2 downto 0); + + component adder_3_bits is + port( a : in std_logic_vector(2 downto 0); + b : in std_logic_vector(2 downto 0); + clk : in std_logic; + s : out std_logic_vector(3 downto 0)); + end component; + + signal i_add_3_bits_result_0 : std_logic_vector(3 downto 0); + signal i_add_3_bits_result_1 : std_logic_vector(3 downto 0); + signal i_add_3_bits_result_2 : std_logic_vector(3 downto 0); + signal i_add_3_bits_result_3 : std_logic_vector(3 downto 0); + + component adder_4_bits is + port( a : in std_logic_vector(3 downto 0); + b : in std_logic_vector(3 downto 0); + clk : in std_logic; + s : out std_logic_vector(4 downto 0)); + end component; + + signal i_add_4_bits_result_0 : std_logic_vector(4 downto 0); + signal i_add_4_bits_result_1 : std_logic_vector(4 downto 0); + + component adder_5_bits is + port( a : in std_logic_vector(4 downto 0); + b : in std_logic_vector(4 downto 0); + clk : in std_logic; + s : out std_logic_vector(5 downto 0)); + end component; + +begin + + -- Component instantiation + -- Binary to decimal + bin_to_dec_0: unary_to_binary + port map( clk_250MHz => clk_250MHz, + vector_in => trig_window_0(4 downto 0), + result => i_bin_to_dec_result_0); + + bin_to_dec_1: unary_to_binary + port map( clk_250MHz => clk_250MHz, + vector_in => trig_window_0(9 downto 5), + result => i_bin_to_dec_result_1); + + bin_to_dec_2: unary_to_binary + port map( clk_250MHz => clk_250MHz, + vector_in => trig_window_1(4 downto 0), + result => i_bin_to_dec_result_2); + + bin_to_dec_3: unary_to_binary + port map( clk_250MHz => clk_250MHz, + vector_in => trig_window_1(9 downto 5), + result => i_bin_to_dec_result_3); + + bin_to_dec_4: unary_to_binary + port map( clk_250MHz => clk_250MHz, + vector_in => trig_window_2(4 downto 0), + result => i_bin_to_dec_result_4); + + bin_to_dec_5: unary_to_binary + port map( clk_250MHz => clk_250MHz, + vector_in => trig_window_2(9 downto 5), + result => i_bin_to_dec_result_5); + + bin_to_dec_6: unary_to_binary + port map( clk_250MHz => clk_250MHz, + vector_in => trig_window_3(4 downto 0), + result => i_bin_to_dec_result_6); + + bin_to_dec_7: unary_to_binary + port map( clk_250MHz => clk_250MHz, + vector_in => trig_window_3(9 downto 5), + result => i_bin_to_dec_result_7); + + -- 3 bits adders + inst_3_bits_add_0: adder_3_bits + port map( clk => clk_250MHz, + a => i_bin_to_dec_result_0, + b => i_bin_to_dec_result_1, + s => i_add_3_bits_result_0); + + inst_3_bits_add_1: adder_3_bits + port map( clk => clk_250MHz, + a => i_bin_to_dec_result_2, + b => i_bin_to_dec_result_3, + s => i_add_3_bits_result_1); + + inst_3_bits_add_2: adder_3_bits + port map( clk => clk_250MHz, + a => i_bin_to_dec_result_4, + b => i_bin_to_dec_result_5, + s => i_add_3_bits_result_2); + + inst_3_bits_add_3: adder_3_bits + port map( clk => clk_250MHz, + a => i_bin_to_dec_result_6, + b => i_bin_to_dec_result_7, + s => i_add_3_bits_result_3); + + -- 4 bits adders + inst_4_bits_add_0: adder_4_bits + port map( clk => clk_250MHz, + a => i_add_3_bits_result_0, + b => i_add_3_bits_result_1, + s => i_add_4_bits_result_0); + + inst_4_bits_add_1: adder_4_bits + port map( clk => clk_250MHz, + a => i_add_3_bits_result_2, + b => i_add_3_bits_result_3, + s => i_add_4_bits_result_1); + + ---- Final 5 bits adders + inst_5_bits_add_0: adder_5_bits + port map( clk => clk_250MHz, + a => i_add_4_bits_result_0, + b => i_add_4_bits_result_1, + s => number_of_events); + +end RTL; Index: firmware/FTM/trigger/drivers/detection_logic/unary_to_binary.vhd =================================================================== --- firmware/FTM/trigger/drivers/detection_logic/unary_to_binary.vhd (revision 10366) +++ firmware/FTM/trigger/drivers/detection_logic/unary_to_binary.vhd (revision 10366) @@ -0,0 +1,86 @@ +--======================================================================================= +-- TITLE : Binary to decimal converter +-- DESCRIPTION : Convert 5bits to the sum on 3bits of the bits to '1' in input vector +-- FILE : binary_to_decimal.vhd +-- COMPANY : Micro-Cameras & Space Exploration SA +--======================================================================================= +-- CREATION +-- DATE AUTHOR PROJECT REVISION +-- 07/03/2011 JGi 110307a +--======================================================================================= +-- MODIFICATION HISTORY +-- DATE AUTHOR PROJECT REVISION COMMENTS +-- 07/03/2011 JGi 110307a Description +--======================================================================================= +-- Library Definition +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +-- Entity Definition +entity unary_to_binary is + port( --clock + clk_250MHz : in std_logic; + --input + vector_in : in std_logic_vector(4 downto 0); + --output + result : out std_logic_vector(2 downto 0)); +end unary_to_binary; + +-- Architecture Definition +architecture RTL of unary_to_binary is + + type t_reg is record + -- Internal register declaration + -- Ouput register declaration + result : std_logic_vector(2 downto 0); + end record; + + signal i_next_reg : t_reg := (result => (others => '0')); + signal i_reg : t_reg := (result => (others => '0')); + +begin + + -- Combinatorial logic + process(vector_in, i_reg) + variable v_reg : t_reg := (result => (others => '0')); + variable temp_vect_0, temp_vect_1, temp_vect_2, temp_vect_3, temp_vect_4 : + unsigned(2 downto 0) := (others => '0'); + begin + v_reg := i_reg; + --=================================================================================== + + --=================================================================================== + -- Bit count processing + --=================================================================================== + -- Simulate 5 vectors of 3 bits for the sum + temp_vect_0 := "00" & vector_in(0); + temp_vect_1 := "00" & vector_in(1); + temp_vect_2 := "00" & vector_in(2); + temp_vect_3 := "00" & vector_in(3); + temp_vect_4 := "00" & vector_in(4); + + -- Sum all the simulated vectors + v_reg.result := std_logic_vector(temp_vect_0 + temp_vect_1 + temp_vect_2 + + temp_vect_3 + temp_vect_4); + --=================================================================================== + + --=================================================================================== + -- Drive register input + i_next_reg <= v_reg; + + --=================================================================================== + -- Output assignation + result <= i_reg.result; + --=================================================================================== + end process; + + -- Sequential logic + process(clk_250MHz) + begin + if rising_edge(clk_250MHz) then + i_reg <= i_next_reg; + end if; + end process; + +end RTL; Index: firmware/FTM/trigger/drivers/input_synch/input_synch.vhd =================================================================== --- firmware/FTM/trigger/drivers/input_synch/input_synch.vhd (revision 10366) +++ firmware/FTM/trigger/drivers/input_synch/input_synch.vhd (revision 10366) @@ -0,0 +1,216 @@ +--======================================================================================= +-- TITLE : Input synchronization block +-- DESCRIPTION : Synchronization of FTUs signals using FPGA DDR input registers +-- FILE : input_synch.vhd +-- COMPANY : Micro-Cameras & Space Exploration SA +--======================================================================================= +-- CREATION +-- DATE AUTHOR PROJECT REVISION +-- 02/03/2011 JGi FTM 110302a +--======================================================================================= +-- MODIFICATION HISTORY +-- DATE AUTHOR PROJECT REVISION COMMENTS +-- 02/03/2011 JGi FTM 110302a Description +--======================================================================================= +-- Library Definition +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +library unisim; + use unisim.vcomponents.all; + +-- Entity Definition +entity input_synch is + port( --clock + clk_250MHz : in std_logic; + clk_250MHz_180 : in std_logic; + --trigger primitives from FTUs + trig_prim_0 : in std_logic_vector(9 downto 0); --crate 0 + trig_prim_1 : in std_logic_vector(9 downto 0); --crate 1 + trig_prim_2 : in std_logic_vector(9 downto 0); --crate 2 + trig_prim_3 : in std_logic_vector(9 downto 0); --crate 3 + --synchronized trigger primitives + trig_synch_0_rise : out std_logic_vector(9 downto 0); --crate 0 + trig_synch_1_rise : out std_logic_vector(9 downto 0); --crate 1 + trig_synch_2_rise : out std_logic_vector(9 downto 0); --crate 2 + trig_synch_3_rise : out std_logic_vector(9 downto 0); --crate 3 + trig_synch_0_fall : out std_logic_vector(9 downto 0); --crate 0 + trig_synch_1_fall : out std_logic_vector(9 downto 0); --crate 1 + trig_synch_2_fall : out std_logic_vector(9 downto 0); --crate 2 + trig_synch_3_fall : out std_logic_vector(9 downto 0)); --crate 3 +end input_synch; + +-- Architecture Definition +architecture RTL of input_synch is + + type t_reg is record + -- Internal register declaration + -- Ouput register declaration + trig_synch_0_rise : std_logic_vector(9 downto 0); + trig_synch_1_rise : std_logic_vector(9 downto 0); + trig_synch_2_rise : std_logic_vector(9 downto 0); + trig_synch_3_rise : std_logic_vector(9 downto 0); + trig_synch_0_fall : std_logic_vector(9 downto 0); + trig_synch_1_fall : std_logic_vector(9 downto 0); + trig_synch_2_fall : std_logic_vector(9 downto 0); + trig_synch_3_fall : std_logic_vector(9 downto 0); + end record; + + signal i_trig_synch_0_rise : std_logic_vector(9 downto 0) := (others => '0'); + signal i_trig_synch_1_rise : std_logic_vector(9 downto 0) := (others => '0'); + signal i_trig_synch_2_rise : std_logic_vector(9 downto 0) := (others => '0'); + signal i_trig_synch_3_rise : std_logic_vector(9 downto 0) := (others => '0'); + signal i_trig_synch_0_fall : std_logic_vector(9 downto 0) := (others => '0'); + signal i_trig_synch_1_fall : std_logic_vector(9 downto 0) := (others => '0'); + signal i_trig_synch_2_fall : std_logic_vector(9 downto 0) := (others => '0'); + signal i_trig_synch_3_fall : std_logic_vector(9 downto 0) := (others => '0'); + + signal i_next_reg : t_reg := (trig_synch_0_rise => (others => '0'), + trig_synch_1_rise => (others => '0'), + trig_synch_2_rise => (others => '0'), + trig_synch_3_rise => (others => '0'), + trig_synch_0_fall => (others => '0'), + trig_synch_1_fall => (others => '0'), + trig_synch_2_fall => (others => '0'), + trig_synch_3_fall => (others => '0')); + signal i_reg : t_reg := (trig_synch_0_rise => (others => '0'), + trig_synch_1_rise => (others => '0'), + trig_synch_2_rise => (others => '0'), + trig_synch_3_rise => (others => '0'), + trig_synch_0_fall => (others => '0'), + trig_synch_1_fall => (others => '0'), + trig_synch_2_fall => (others => '0'), + trig_synch_3_fall => (others => '0')); + +begin + + -- Input DDR flip-flops instantiation for crate 0 + input_ddr_0: for i in 0 to 9 generate + iddr2_inst_trig_synch_0 : IDDR2 + generic map(DDR_ALIGNMENT => "NONE", -- sets output alignment to "none", "c0", "c1" + INIT_Q0 => '0', -- sets initial state of the q0 output to '0' or '1' + INIT_Q1 => '0', -- sets initial state of the q1 output to '0' or '1' + SRTYPE => "SYNC") -- specifies "sync" or "async" set/reset + port map( Q0 => i_trig_synch_0_rise(i), -- 1-bit output captured with c0 clock + Q1 => i_trig_synch_0_fall(i), -- 1-bit output captured with c1 clock + C0 => clk_250mhz, -- 1-bit clock input + C1 => clk_250mhz_180, -- 1-bit clock input + CE => '1', -- 1-bit clock enable input + D => trig_prim_0(i), -- 1-bit data input + R => '0', -- 1-bit reset input + S => '0'); -- 1-bit set input + end generate input_ddr_0; + + -- Input DDR flip-flops instantiation for crate 1 + input_ddr_1: for i in 0 to 9 generate + iddr2_inst_trig_synch_1 : IDDR2 + generic map(DDR_ALIGNMENT => "NONE", + INIT_Q0 => '0', + INIT_Q1 => '0', + SRTYPE => "SYNC") + port map( Q0 => i_trig_synch_1_rise(i), + Q1 => i_trig_synch_1_fall(i), + C0 => clk_250mhz, + C1 => clk_250mhz_180, + CE => '1', + D => trig_prim_1(i), + R => '0', + S => '0'); + end generate input_ddr_1; + + -- Input DDR flip-flops instantiation for crate 2 + input_ddr_2: for i in 0 to 9 generate + iddr2_inst_trig_synch_2 : IDDR2 + generic map(DDR_ALIGNMENT => "NONE", + INIT_Q0 => '0', + INIT_Q1 => '0', + SRTYPE => "SYNC") + port map( Q0 => i_trig_synch_2_rise(i), + Q1 => i_trig_synch_2_fall(i), + C0 => clk_250mhz, + C1 => clk_250mhz_180, + CE => '1', + D => trig_prim_2(i), + R => '0', + S => '0'); + end generate input_ddr_2; + + -- Input DDR flip-flops instantiation for crate 3 + input_ddr_3: for i in 0 to 9 generate + iddr2_inst_trig_synch_3 : IDDR2 + generic map(DDR_ALIGNMENT => "NONE", + INIT_Q0 => '0', + INIT_Q1 => '0', + SRTYPE => "SYNC") + port map( Q0 => i_trig_synch_3_rise(i), + Q1 => i_trig_synch_3_fall(i), + C0 => clk_250mhz, + C1 => clk_250mhz_180, + CE => '1', + D => trig_prim_3(i), + R => '0', + S => '0'); + end generate input_ddr_3; + + -- Combinatorial logic + process(i_trig_synch_0_rise, i_trig_synch_1_rise, i_trig_synch_2_rise, + i_trig_synch_3_rise, i_trig_synch_0_fall, i_trig_synch_1_fall, + i_trig_synch_2_fall, i_trig_synch_3_fall, i_reg) + variable v_reg : t_reg := (trig_synch_0_rise => (others => '0'), + trig_synch_1_rise => (others => '0'), + trig_synch_2_rise => (others => '0'), + trig_synch_3_rise => (others => '0'), + trig_synch_0_fall => (others => '0'), + trig_synch_1_fall => (others => '0'), + trig_synch_2_fall => (others => '0'), + trig_synch_3_fall => (others => '0')); + begin + v_reg := i_reg; + --=================================================================================== + + --=================================================================================== + -- Delay management for rising edge data + --=================================================================================== + v_reg.trig_synch_0_rise := i_trig_synch_0_rise; + v_reg.trig_synch_1_rise := i_trig_synch_1_rise; + v_reg.trig_synch_2_rise := i_trig_synch_2_rise; + v_reg.trig_synch_3_rise := i_trig_synch_3_rise; + --=================================================================================== + + --=================================================================================== + -- Delay management for falling edge data + --=================================================================================== + v_reg.trig_synch_0_fall := i_trig_synch_0_fall; + v_reg.trig_synch_1_fall := i_trig_synch_1_fall; + v_reg.trig_synch_2_fall := i_trig_synch_2_fall; + v_reg.trig_synch_3_fall := i_trig_synch_3_fall; + --=================================================================================== + + --=================================================================================== + -- Drive register input + i_next_reg <= v_reg; + + --=================================================================================== + -- Output assignation + trig_synch_0_rise <= i_reg.trig_synch_0_rise; + trig_synch_1_rise <= i_reg.trig_synch_1_rise; + trig_synch_2_rise <= i_reg.trig_synch_2_rise; + trig_synch_3_rise <= i_reg.trig_synch_3_rise; + trig_synch_0_fall <= i_reg.trig_synch_0_fall; + trig_synch_1_fall <= i_reg.trig_synch_1_fall; + trig_synch_2_fall <= i_reg.trig_synch_2_fall; + trig_synch_3_fall <= i_reg.trig_synch_3_fall; + --=================================================================================== + end process; + + -- Sequential logic + process(clk_250MHz) + begin + if rising_edge(clk_250MHz) then + i_reg <= i_next_reg; + end if; + end process; + +end RTL; Index: firmware/FTM/trigger/drivers/interface_sync/interface_sync_250MHz.vhd =================================================================== --- firmware/FTM/trigger/drivers/interface_sync/interface_sync_250MHz.vhd (revision 10366) +++ firmware/FTM/trigger/drivers/interface_sync/interface_sync_250MHz.vhd (revision 10366) @@ -0,0 +1,306 @@ +--======================================================================================= +-- TITLE : Interface synchronization to 250MHz +-- DESCRIPTION : Synchronize incoming settings to the 250MHz clock +-- FILE : interface_sync_250MHz.vhd +-- COMPANY : Micro-Cameras & Space Exploration SA +--======================================================================================= +-- CREATION +-- DATE AUTHOR PROJECT REVISION +-- 11/03/2011 JGi 110311a +--======================================================================================= +-- MODIFICATION HISTORY +-- DATE AUTHOR PROJECT REVISION COMMENTS +-- 11/03/2011 JGi 110311a Description +--======================================================================================= +-- Library Definition +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +-- Entity Definition +entity interface_sync_250MHz is + port( --clock + clk_250MHz : in std_logic; + --inputs + start_run : in std_logic; + stop_run : in std_logic; + new_config : in std_logic; + general_settings : in std_logic_vector(15 downto 0); + LP_and_PED_freq : in std_logic_vector(15 downto 0); + LP1_LP2_PED_ratio : in std_logic_vector(15 downto 0); + maj_coinc_n_phys : in std_logic_vector(15 downto 0); + maj_coinc_n_calib : in std_logic_vector(15 downto 0); + trigger_delay : in std_logic_vector(15 downto 0); + TIM_delay : in std_logic_vector(15 downto 0); + dead_time : in std_logic_vector(15 downto 0); + coinc_window_phys : in std_logic_vector(15 downto 0); + coinc_window_calib : in std_logic_vector(15 downto 0); + active_FTU_list_0 : in std_logic_vector(15 downto 0); + active_FTU_list_1 : in std_logic_vector(15 downto 0); + active_FTU_list_2 : in std_logic_vector(15 downto 0); + active_FTU_list_3 : in std_logic_vector(15 downto 0); + --outputs + config_done : out std_logic; + sync_start_run : out std_logic; + sync_stop_run : out std_logic; + sync_general_settings : out std_logic_vector(7 downto 0); + sync_LP_and_PED_freq : out std_logic_vector(9 downto 0); + sync_LP1_LP2_PED_ratio : out std_logic_vector(14 downto 0); + sync_maj_coinc_n_phys : out std_logic_vector(5 downto 0); + sync_maj_coinc_n_calib : out std_logic_vector(5 downto 0); + sync_trigger_delay : out std_logic_vector(9 downto 0); + sync_TIM_delay : out std_logic_vector(9 downto 0); + sync_dead_time : out std_logic_vector(15 downto 0); + sync_coinc_window_phys : out std_logic_vector(3 downto 0); + sync_coinc_window_calib : out std_logic_vector(3 downto 0); + sync_active_FTU_list_0 : out std_logic_vector(9 downto 0); + sync_active_FTU_list_1 : out std_logic_vector(9 downto 0); + sync_active_FTU_list_2 : out std_logic_vector(9 downto 0); + sync_active_FTU_list_3 : out std_logic_vector(9 downto 0)); +end interface_sync_250MHz; + +-- Architecture Definition +architecture RTL of interface_sync_250MHz is + + type t_reg is record + -- Internal register declaration + -- Ouput register declaration + config_done : std_logic_vector(1 downto 0); + sync_0_start_run : std_logic; + sync_1_start_run : std_logic; + sync_0_stop_run : std_logic; + sync_1_stop_run : std_logic; + sync_0_new_config : std_logic; + sync_1_new_config : std_logic; + sync_0_general_settings : std_logic_vector(7 downto 0); + sync_1_general_settings : std_logic_vector(7 downto 0); + sync_0_LP_and_PED_freq : std_logic_vector(9 downto 0); + sync_1_LP_and_PED_freq : std_logic_vector(9 downto 0); + sync_0_LP1_LP2_PED_ratio : std_logic_vector(14 downto 0); + sync_1_LP1_LP2_PED_ratio : std_logic_vector(14 downto 0); + sync_0_maj_coinc_n_phys : std_logic_vector(5 downto 0); + sync_1_maj_coinc_n_phys : std_logic_vector(5 downto 0); + sync_0_maj_coinc_n_calib : std_logic_vector(5 downto 0); + sync_1_maj_coinc_n_calib : std_logic_vector(5 downto 0); + sync_0_trigger_delay : std_logic_vector(9 downto 0); + sync_1_trigger_delay : std_logic_vector(9 downto 0); + sync_0_TIM_delay : std_logic_vector(9 downto 0); + sync_1_TIM_delay : std_logic_vector(9 downto 0); + sync_0_dead_time : std_logic_vector(15 downto 0); + sync_1_dead_time : std_logic_vector(15 downto 0); + sync_0_coinc_window_phys : std_logic_vector(3 downto 0); + sync_1_coinc_window_phys : std_logic_vector(3 downto 0); + sync_0_coinc_window_calib : std_logic_vector(3 downto 0); + sync_1_coinc_window_calib : std_logic_vector(3 downto 0); + sync_0_active_FTU_list_0 : std_logic_vector(9 downto 0); + sync_1_active_FTU_list_0 : std_logic_vector(9 downto 0); + sync_0_active_FTU_list_1 : std_logic_vector(9 downto 0); + sync_1_active_FTU_list_1 : std_logic_vector(9 downto 0); + sync_0_active_FTU_list_2 : std_logic_vector(9 downto 0); + sync_1_active_FTU_list_2 : std_logic_vector(9 downto 0); + sync_0_active_FTU_list_3 : std_logic_vector(9 downto 0); + sync_1_active_FTU_list_3 : std_logic_vector(9 downto 0); + end record; + + signal i_next_reg : t_reg := (config_done => (others => '0'), + sync_0_start_run => '0', + sync_1_start_run => '0', + sync_0_stop_run => '0', + sync_1_stop_run => '0', + sync_0_new_config => '0', + sync_1_new_config => '0', + sync_0_general_settings => (others => '0'), + sync_1_general_settings => (others => '0'), + sync_0_LP_and_PED_freq => (others => '0'), + sync_1_LP_and_PED_freq => (others => '0'), + sync_0_LP1_LP2_PED_ratio => (others => '0'), + sync_1_LP1_LP2_PED_ratio => (others => '0'), + sync_0_maj_coinc_n_phys => (others => '1'), + sync_1_maj_coinc_n_phys => (others => '1'), + sync_0_maj_coinc_n_calib => (others => '1'), + sync_1_maj_coinc_n_calib => (others => '1'), + sync_0_trigger_delay => (others => '0'), + sync_1_trigger_delay => (others => '0'), + sync_0_TIM_delay => (others => '0'), + sync_1_TIM_delay => (others => '0'), + sync_0_dead_time => (others => '0'), + sync_1_dead_time => (others => '0'), + sync_0_coinc_window_phys => (others => '0'), + sync_1_coinc_window_phys => (others => '0'), + sync_0_coinc_window_calib => (others => '0'), + sync_1_coinc_window_calib => (others => '0'), + sync_0_active_FTU_list_0 => (others => '0'), + sync_1_active_FTU_list_0 => (others => '0'), + sync_0_active_FTU_list_1 => (others => '0'), + sync_1_active_FTU_list_1 => (others => '0'), + sync_0_active_FTU_list_2 => (others => '0'), + sync_1_active_FTU_list_2 => (others => '0'), + sync_0_active_FTU_list_3 => (others => '0'), + sync_1_active_FTU_list_3 => (others => '0')); + signal i_reg : t_reg := (config_done => (others => '0'), + sync_0_start_run => '0', + sync_1_start_run => '0', + sync_0_stop_run => '0', + sync_1_stop_run => '0', + sync_0_new_config => '0', + sync_1_new_config => '0', + sync_0_general_settings => (others => '0'), + sync_1_general_settings => (others => '0'), + sync_0_LP_and_PED_freq => (others => '0'), + sync_1_LP_and_PED_freq => (others => '0'), + sync_0_LP1_LP2_PED_ratio => (others => '0'), + sync_1_LP1_LP2_PED_ratio => (others => '0'), + sync_0_maj_coinc_n_phys => (others => '1'), + sync_1_maj_coinc_n_phys => (others => '1'), + sync_0_maj_coinc_n_calib => (others => '1'), + sync_1_maj_coinc_n_calib => (others => '1'), + sync_0_trigger_delay => (others => '0'), + sync_1_trigger_delay => (others => '0'), + sync_0_TIM_delay => (others => '0'), + sync_1_TIM_delay => (others => '0'), + sync_0_dead_time => (others => '0'), + sync_1_dead_time => (others => '0'), + sync_0_coinc_window_phys => (others => '0'), + sync_1_coinc_window_phys => (others => '0'), + sync_0_coinc_window_calib => (others => '0'), + sync_1_coinc_window_calib => (others => '0'), + sync_0_active_FTU_list_0 => (others => '0'), + sync_1_active_FTU_list_0 => (others => '0'), + sync_0_active_FTU_list_1 => (others => '0'), + sync_1_active_FTU_list_1 => (others => '0'), + sync_0_active_FTU_list_2 => (others => '0'), + sync_1_active_FTU_list_2 => (others => '0'), + sync_0_active_FTU_list_3 => (others => '0'), + sync_1_active_FTU_list_3 => (others => '0')); + +begin + + -- Component instantiation + + -- Combinatorial logic + process(start_run, stop_run, new_config, general_settings, LP_and_PED_freq, + LP1_LP2_PED_ratio, maj_coinc_n_phys, maj_coinc_n_calib, trigger_delay, + TIM_delay, dead_time, coinc_window_phys, coinc_window_calib, active_FTU_list_0, + active_FTU_list_1, active_FTU_list_2, active_FTU_list_3, i_reg) + variable v_reg : t_reg := (config_done => (others => '0'), + sync_0_start_run => '0', + sync_1_start_run => '0', + sync_0_stop_run => '0', + sync_1_stop_run => '0', + sync_0_new_config => '0', + sync_1_new_config => '0', + sync_0_general_settings => (others => '0'), + sync_1_general_settings => (others => '0'), + sync_0_LP_and_PED_freq => (others => '0'), + sync_1_LP_and_PED_freq => (others => '0'), + sync_0_LP1_LP2_PED_ratio => (others => '0'), + sync_1_LP1_LP2_PED_ratio => (others => '0'), + sync_0_maj_coinc_n_phys => (others => '1'), + sync_1_maj_coinc_n_phys => (others => '1'), + sync_0_maj_coinc_n_calib => (others => '1'), + sync_1_maj_coinc_n_calib => (others => '1'), + sync_0_trigger_delay => (others => '0'), + sync_1_trigger_delay => (others => '0'), + sync_0_TIM_delay => (others => '0'), + sync_1_TIM_delay => (others => '0'), + sync_0_dead_time => (others => '0'), + sync_1_dead_time => (others => '0'), + sync_0_coinc_window_phys => (others => '0'), + sync_1_coinc_window_phys => (others => '0'), + sync_0_coinc_window_calib => (others => '0'), + sync_1_coinc_window_calib => (others => '0'), + sync_0_active_FTU_list_0 => (others => '0'), + sync_1_active_FTU_list_0 => (others => '0'), + sync_0_active_FTU_list_1 => (others => '0'), + sync_1_active_FTU_list_1 => (others => '0'), + sync_0_active_FTU_list_2 => (others => '0'), + sync_1_active_FTU_list_2 => (others => '0'), + sync_0_active_FTU_list_3 => (others => '0'), + sync_1_active_FTU_list_3 => (others => '0')); + begin + v_reg := i_reg; + --=================================================================================== + + --=================================================================================== + -- Double synchronization of incoming signals + --=================================================================================== + -- Double synchonize command signals + v_reg.sync_0_start_run := start_run; + v_reg.sync_1_start_run := i_reg.sync_0_start_run; + v_reg.sync_0_stop_run := stop_run; + v_reg.sync_1_stop_run := i_reg.sync_0_stop_run; + v_reg.sync_0_new_config := new_config; + v_reg.sync_1_new_config := i_reg.sync_0_new_config; + + v_reg.config_done(0) := '0'; + v_reg.config_done(1) := i_reg.config_done(0); + + -- If new configuration is received, register settings + if i_reg.sync_1_new_config = '1' then + v_reg.config_done(0) := '1'; + v_reg.sync_0_general_settings := general_settings(7 downto 0); + v_reg.sync_0_LP_and_PED_freq := LP_and_PED_freq(9 downto 0); + v_reg.sync_0_LP1_LP2_PED_ratio := LP1_LP2_PED_ratio(14 downto 0); + v_reg.sync_0_maj_coinc_n_phys := maj_coinc_n_phys(5 downto 0); + v_reg.sync_0_maj_coinc_n_calib := maj_coinc_n_calib(5 downto 0); + v_reg.sync_0_trigger_delay := trigger_delay(9 downto 0); + v_reg.sync_0_TIM_delay := TIM_delay(9 downto 0); + v_reg.sync_0_dead_time := dead_time(15 downto 0); + v_reg.sync_0_coinc_window_phys := coinc_window_phys(3 downto 0); + v_reg.sync_0_coinc_window_calib := coinc_window_calib(3 downto 0); + v_reg.sync_0_active_FTU_list_0 := active_FTU_list_0(9 downto 0); + v_reg.sync_0_active_FTU_list_1 := active_FTU_list_1(9 downto 0); + v_reg.sync_0_active_FTU_list_2 := active_FTU_list_2(9 downto 0); + v_reg.sync_0_active_FTU_list_3 := active_FTU_list_3(9 downto 0); + end if; + v_reg.sync_1_general_settings := i_reg.sync_0_general_settings; + v_reg.sync_1_LP_and_PED_freq := i_reg.sync_0_LP_and_PED_freq; + v_reg.sync_1_LP1_LP2_PED_ratio := i_reg.sync_0_LP1_LP2_PED_ratio; + v_reg.sync_1_maj_coinc_n_phys := i_reg.sync_0_maj_coinc_n_phys; + v_reg.sync_1_maj_coinc_n_calib := i_reg.sync_0_maj_coinc_n_calib; + v_reg.sync_1_trigger_delay := i_reg.sync_0_trigger_delay; + v_reg.sync_1_TIM_delay := i_reg.sync_0_TIM_delay; + v_reg.sync_1_dead_time := i_reg.sync_0_dead_time; + v_reg.sync_1_coinc_window_phys := i_reg.sync_0_coinc_window_phys; + v_reg.sync_1_coinc_window_calib := i_reg.sync_0_coinc_window_calib; + v_reg.sync_1_active_FTU_list_0 := i_reg.sync_0_active_FTU_list_0; + v_reg.sync_1_active_FTU_list_1 := i_reg.sync_0_active_FTU_list_1; + v_reg.sync_1_active_FTU_list_2 := i_reg.sync_0_active_FTU_list_2; + v_reg.sync_1_active_FTU_list_3 := i_reg.sync_0_active_FTU_list_3; + --=================================================================================== + + --=================================================================================== + -- Drive register input + i_next_reg <= v_reg; + + --=================================================================================== + -- Output assignation + config_done <= i_reg.config_done(1); + sync_start_run <= i_reg.sync_1_start_run; + sync_stop_run <= i_reg.sync_1_stop_run; + sync_general_settings <= i_reg.sync_1_general_settings; + sync_LP_and_PED_freq <= i_reg.sync_1_LP_and_PED_freq; + sync_LP1_LP2_PED_ratio <= i_reg.sync_1_LP1_LP2_PED_ratio; + sync_maj_coinc_n_phys <= i_reg.sync_1_maj_coinc_n_phys; + sync_maj_coinc_n_calib <= i_reg.sync_1_maj_coinc_n_calib; + sync_trigger_delay <= i_reg.sync_1_trigger_delay; + sync_TIM_delay <= i_reg.sync_1_TIM_delay; + sync_dead_time <= i_reg.sync_1_dead_time; + sync_coinc_window_phys <= i_reg.sync_1_coinc_window_phys; + sync_coinc_window_calib <= i_reg.sync_1_coinc_window_calib; + sync_active_FTU_list_0 <= i_reg.sync_1_active_FTU_list_0; + sync_active_FTU_list_1 <= i_reg.sync_1_active_FTU_list_1; + sync_active_FTU_list_2 <= i_reg.sync_1_active_FTU_list_2; + sync_active_FTU_list_3 <= i_reg.sync_1_active_FTU_list_3; + --=================================================================================== + end process; + + -- Sequential logic + process(clk_250MHz) + begin + if rising_edge(clk_250MHz) then + i_reg <= i_next_reg; + end if; + end process; + +end RTL; Index: firmware/FTM/trigger/drivers/interface_sync/interface_sync_50MHz.vhd =================================================================== --- firmware/FTM/trigger/drivers/interface_sync/interface_sync_50MHz.vhd (revision 10366) +++ firmware/FTM/trigger/drivers/interface_sync/interface_sync_50MHz.vhd (revision 10366) @@ -0,0 +1,243 @@ +--======================================================================================= +-- TITLE : Interface synchronization on the 50MHz clock +-- DESCRIPTION : Manage interface between 250MHz clock domain and 50MHz clock domain +-- FILE : interface_sync_50MHz.vhd +-- COMPANY : Micro-Cameras & Space Exploration SA +--======================================================================================= +-- CREATION +-- DATE AUTHOR PROJECT REVISION +-- 25/03/2011 JGi 110325a +--======================================================================================= +-- MODIFICATION HISTORY +-- DATE AUTHOR PROJECT REVISION COMMENTS +-- 25/03/2011 JGi 110325a Description +--======================================================================================= +-- Library Definition +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +-- Entity Definition +entity interface_sync_50MHz is + port( --clock + clk_50MHz : in std_logic; + clk_250MHz : in std_logic; + --250MHz inputs + config_done : in std_logic; + trigger_active : in std_logic; + trigger_ID_done : in std_logic; + trigger_ID : in std_logic_vector(55 downto 0); + --50MHz inputs + trigger_ID_read : in std_logic; + trigger_cnt_read : in std_logic; + --outputs + sync_config_done : out std_logic; + sync_trigger_active : out std_logic; + sync_trigger_ID_ready : out std_logic; + sync_trigger_ID : out std_logic_vector(55 downto 0); + trigger_cnt_valid : out std_logic; + trigger_cnt_copy : out std_logic_vector(31 downto 0)); +end interface_sync_50MHz; + +-- Architecture Definition +architecture RTL of interface_sync_50MHz is + + type t_reg_50 is record + -- Ouput register declaration + sync_config_done : std_logic_vector(3 downto 0); + sync_trigger_active : std_logic_vector(3 downto 0); + sync_trigger_ID_ready : std_logic_vector(3 downto 0); + sync_trigger_ID : std_logic_vector(111 downto 0); + trigger_cnt_valid : std_logic; + trigger_cnt_copy : std_logic_vector(31 downto 0); + end record; + + type t_reg_250 is record + -- Internal register declaration + config_done : std_logic; + sync_config_done : std_logic_vector(1 downto 0); + trigger_active : std_logic; + sync_trigger_active : std_logic_vector(1 downto 0); + trigger_ID_done : std_logic; + sync_trigger_ID_done : std_logic_vector(1 downto 0); + end record; + + signal i_next_reg_250 : t_reg_250 := (config_done => '0', + sync_config_done => (others => '0'), + trigger_active => '0', + sync_trigger_active => (others => '0'), + trigger_ID_done => '0', + sync_trigger_ID_done => (others => '0')); + signal i_reg_250 : t_reg_250 := (config_done => '0', + sync_config_done => (others => '0'), + trigger_active => '0', + sync_trigger_active => (others => '0'), + trigger_ID_done => '0', + sync_trigger_ID_done => (others => '0')); + signal i_next_reg_50 : t_reg_50 := (sync_config_done => (others => '0'), + sync_trigger_active => (others => '0'), + sync_trigger_ID_ready => (others => '0'), + sync_trigger_ID => (others => '0'), + trigger_cnt_valid => '0', + trigger_cnt_copy => (others => '0')); + signal i_reg_50 : t_reg_50 := (sync_config_done => (others => '0'), + sync_trigger_active => (others => '0'), + sync_trigger_ID_ready => (others => '0'), + sync_trigger_ID => (others => '0'), + trigger_cnt_valid => '0', + trigger_cnt_copy => (others => '0')); + +begin + + -- Combinatorial logic + -- Manage signals on the 250MHz side + process(config_done, trigger_active, trigger_ID_done, i_reg_50, i_reg_250) + variable v_reg : t_reg_250 := (config_done => '0', + sync_config_done => (others => '0'), + trigger_active => '0', + sync_trigger_active => (others => '0'), + trigger_ID_done => '0', + sync_trigger_ID_done => (others => '0')); + begin + v_reg := i_reg_250; + --=================================================================================== + + --=================================================================================== + -- Generate signals until they have been received by the 50MHz interface + --=================================================================================== + -- Synchronized config done from 50MHz interface + v_reg.sync_config_done(0) := i_reg_50.sync_config_done(1); + v_reg.sync_config_done(1) := i_reg_250.sync_config_done(0); + + -- Set config done high when detected at input + if config_done = '1' then + v_reg.config_done := '1'; + -- Reset config done when set high by the 50MHz part + elsif i_reg_250.sync_config_done(1) = '1' then + v_reg.config_done := '0'; + end if; + + -- Synchronized trigger active from 50MHz interface + v_reg.sync_trigger_active(0) := i_reg_50.sync_trigger_active(1); + v_reg.sync_trigger_active(1) := i_reg_250.sync_trigger_active(0); + + -- Set trigger active high when detected at input + if trigger_active = '1' then + v_reg.trigger_active := '1'; + -- Reset trigger active when set high by the 50MHz part + elsif i_reg_250.sync_trigger_active(1) = '1' then + v_reg.trigger_active := '0'; + end if; + + -- Detect rising edge on trigger ID ready from 50MHz interface + if i_reg_50.sync_trigger_ID_ready(1) = '1' and + i_reg_50.sync_trigger_ID_ready(2) = '0' then + v_reg.sync_trigger_ID_done(0) := '1'; + else + v_reg.sync_trigger_ID_done(0) := '0'; + end if; + v_reg.sync_trigger_ID_done(1) := i_reg_250.sync_trigger_ID_done(0); + + -- Set trigger ID done high when detected at input + if trigger_ID_done = '1' then + v_reg.trigger_ID_done := '1'; + -- Reset trigger ID done when set high by the 50MHz part + elsif i_reg_250.sync_trigger_ID_done(1) = '1' then + v_reg.trigger_ID_done := '0'; + end if; + --=================================================================================== + + --=================================================================================== + -- Drive register input + i_next_reg_250 <= v_reg; + --=================================================================================== + end process; + + -- Manage signals on the 50MHz side + process(trigger_ID_read, trigger_ID, trigger_cnt_read, i_reg_250, i_reg_50) + variable v_reg : t_reg_50 := (sync_config_done => (others => '0'), + sync_trigger_active => (others => '0'), + sync_trigger_ID_ready => (others => '0'), + sync_trigger_ID => (others => '0'), + trigger_cnt_valid => '0', + trigger_cnt_copy => (others => '0')); + begin + v_reg := i_reg_50; + --=================================================================================== + + --=================================================================================== + -- Synchronize signals from the 250MHz side + --=================================================================================== + -- Synchronize config done from the 250MHz interface + v_reg.sync_config_done(0) := i_reg_250.config_done; + v_reg.sync_config_done(1) := i_reg_50.sync_config_done(0); + v_reg.sync_config_done(2) := i_reg_50.sync_config_done(1); + + -- Set config done on 50MHz when set by 250MHz interface + if i_reg_50.sync_config_done(1) = '1' and i_reg_50.sync_config_done(2) = '0' and + i_reg_50.sync_config_done(3) = '0' then + v_reg.sync_config_done(3) := '1'; + else + v_reg.sync_config_done(3) := '0'; + end if; + + -- Synchronize trigger active from the 250MHz interface + v_reg.sync_trigger_active(0) := i_reg_250.trigger_active; + v_reg.sync_trigger_active(1) := i_reg_50.sync_trigger_active(0); + + -- Synchronize trigger ID ready from the 250MHz interface + v_reg.sync_trigger_ID_ready(0) := i_reg_250.trigger_ID_done; + v_reg.sync_trigger_ID_ready(1) := i_reg_50.sync_trigger_ID_ready(0); + v_reg.sync_trigger_ID_ready(2) := i_reg_50.sync_trigger_ID_ready(1); + + -- Set trigger ready when set on the 250MHz side and release it + -- when read by the 50MHz side + if trigger_ID_read = '1' then + v_reg.sync_trigger_ID_ready(3) := '0'; + elsif i_reg_50.sync_trigger_ID_ready(1) = '1' and + i_reg_50.sync_trigger_ID_ready(2) = '0' then + v_reg.sync_trigger_ID_ready(3) := '1'; + end if; + + -- Simply synchronize trigger ID + v_reg.sync_trigger_ID(55 downto 0) := trigger_ID; + v_reg.sync_trigger_ID(111 downto 56) := i_reg_50.sync_trigger_ID(55 downto 0); + + -- Counter is a simple copy of the counter of the synchronized trigger ID + v_reg.trigger_cnt_valid := trigger_cnt_read; + if trigger_cnt_read = '1' then + v_reg.trigger_cnt_copy := i_reg_50.sync_trigger_ID(87 downto 56); + end if; + --=================================================================================== + + --=================================================================================== + -- Drive register input + i_next_reg_50 <= v_reg; + + --=================================================================================== + -- Output assignation + sync_config_done <= i_reg_50.sync_config_done(3); + sync_trigger_active <= i_reg_50.sync_trigger_active(1); + sync_trigger_ID_ready <= i_reg_50.sync_trigger_ID_ready(3); + sync_trigger_ID <= i_reg_50.sync_trigger_ID(111 downto 56); + trigger_cnt_valid <= i_reg_50.trigger_cnt_valid; + trigger_cnt_copy <= i_reg_50.trigger_cnt_copy; + --=================================================================================== + end process; + + -- Sequential logic + process(clk_250MHz) + begin + if rising_edge(clk_250MHz) then + i_reg_250 <= i_next_reg_250; + end if; + end process; + + process(clk_50MHz) + begin + if rising_edge(clk_50MHz) then + i_reg_50 <= i_next_reg_50; + end if; + end process; + +end RTL; Index: firmware/FTM/trigger/drivers/time_window/time_counter.vhd =================================================================== --- firmware/FTM/trigger/drivers/time_window/time_counter.vhd (revision 10366) +++ firmware/FTM/trigger/drivers/time_window/time_counter.vhd (revision 10366) @@ -0,0 +1,124 @@ +--======================================================================================= +-- TITLE : Timer +-- DESCRIPTION : Timer for time coincidence windows +-- FILE : time_counter.vhd +-- COMPANY : Micro-Cameras & Space Exploration SA +--======================================================================================= +-- CREATION +-- DATE AUTHOR PROJECT REVISION +-- 02/03/2011 JGi FTM 110302a +--======================================================================================= +-- MODIFICATION HISTORY +-- DATE AUTHOR PROJECT REVISION COMMENTS +-- 02/03/2011 JGi FTM 110302a Description +--======================================================================================= +-- Library Definition +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +-- Entity Definition +entity time_counter is + port( --clock + clk_250MHz : in std_logic; + --control + enable : in std_logic; + window : in std_logic_vector(3 downto 0); + --I/O + start_rise : in std_logic; + start_fall : in std_logic; + counting : out std_logic); +end time_counter; + +-- Architecture Definition +architecture RTL of time_counter is + + type t_reg is record + -- Internal register declaration + enable : std_logic; + started : std_logic; + done : std_logic; + window : unsigned(3 downto 0); + counter : unsigned(3 downto 0); + -- Ouput register declaration + counting : std_logic; + end record; + + signal i_next_reg : t_reg := (enable => '0', + started => '0', + done => '0', + window => (others => '0'), + counter => (others => '0'), + counting => '0'); + signal i_reg : t_reg := (enable => '0', + started => '0', + done => '0', + window => (others => '0'), + counter => (others => '0'), + counting => '0'); + +begin + + -- Combinatorial logic + process(enable, window, start_rise, start_fall, i_reg) + variable v_reg : t_reg := (enable => '0', + started => '0', + done => '0', + window => (others => '0'), + counter => (others => '0'), + counting => '0'); + begin + v_reg := i_reg; + --=================================================================================== + + --=================================================================================== + -- Counter management + --=================================================================================== + -- Register activation signal (From active FTU list) + v_reg.enable := enable; + -- Register window width to improve speed + v_reg.window := unsigned(window); + -- Register enables to detect rising edges on them + v_reg.started := start_rise or start_fall; + + -- Counter is counting permanently + v_reg.counter := i_reg.counter+1; + + -- If enabled and input rising edge, reset counter + if i_reg.enable = '1' and (start_rise = '1' or start_fall = '1') and + i_reg.started = '0' then + v_reg.counting := '1'; + v_reg.counter := (others => '0'); + end if; + + v_reg.done := '0'; + -- If inputs rised and counter reahc the value then done + if i_reg.counter = i_reg.window and i_reg.counting = '1' then + v_reg.done := '1'; + end if; + + -- Disable counter comparison if done + if i_reg.done = '1' then + v_reg.counting := '0'; + end if; + --=================================================================================== + + --=================================================================================== + -- Drive register input + i_next_reg <= v_reg; + + --=================================================================================== + -- Output assignation + counting <= i_reg.counting; + --=================================================================================== + end process; + + -- Sequential logic + process(clk_250MHz) + begin + if rising_edge(clk_250MHz) then + i_reg <= i_next_reg; + end if; + end process; + +end RTL; Index: firmware/FTM/trigger/drivers/time_window/time_window.vhd =================================================================== --- firmware/FTM/trigger/drivers/time_window/time_window.vhd (revision 10366) +++ firmware/FTM/trigger/drivers/time_window/time_window.vhd (revision 10366) @@ -0,0 +1,101 @@ +--======================================================================================= +-- TITLE : Time window +-- DESCRIPTION : Time window generation for trigger detection +-- FILE : time_window.vhd +-- COMPANY : Micro-Cameras & Space Exploration SA +--======================================================================================= +-- CREATION +-- DATE AUTHOR PROJECT REVISION +-- 02/03/2011 JGi FTM 110302a +--======================================================================================= +-- MODIFICATION HISTORY +-- DATE AUTHOR PROJECT REVISION COMMENTS +-- 02/03/2011 JGi FTM 110302a Description +--======================================================================================= +-- Library Definition +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +-- Entity Definition +entity time_window is + port( --clock + clk_250MHz : in std_logic; + --control signal + coinc_window : in std_logic_vector(3 downto 0); + active_FTU_list_0 : in std_logic_vector(9 downto 0); + active_FTU_list_1 : in std_logic_vector(9 downto 0); + active_FTU_list_2 : in std_logic_vector(9 downto 0); + active_FTU_list_3 : in std_logic_vector(9 downto 0); + --trigger detection pulses + trig_synch_0_rise : in std_logic_vector(9 downto 0); --crate 0 + trig_synch_1_rise : in std_logic_vector(9 downto 0); --crate 1 + trig_synch_2_rise : in std_logic_vector(9 downto 0); --crate 2 + trig_synch_3_rise : in std_logic_vector(9 downto 0); --crate 3 + trig_synch_0_fall : in std_logic_vector(9 downto 0); --crate 0 + trig_synch_1_fall : in std_logic_vector(9 downto 0); --crate 1 + trig_synch_2_fall : in std_logic_vector(9 downto 0); --crate 2 + trig_synch_3_fall : in std_logic_vector(9 downto 0); --crate 3 + --programmed width pulses + trig_window_0 : out std_logic_vector(9 downto 0); --crate 0 + trig_window_1 : out std_logic_vector(9 downto 0); --crate 1 + trig_window_2 : out std_logic_vector(9 downto 0); --crate 2 + trig_window_3 : out std_logic_vector(9 downto 0)); --crate 3 +end time_window; + +-- Architecture Definition +architecture RTL of time_window is + + component time_counter is + port( clk_250MHz : in std_logic; + enable : in std_logic; + window : in std_logic_vector(3 downto 0); + start_rise : in std_logic; + start_fall : in std_logic; + counting : out std_logic); + end component; + +begin + + -- Component instantiation + ftu_list_0: for i in 0 to 9 generate + time_counter_inst_0: time_counter + port map( clk_250MHz => clk_250MHz, + enable => active_FTU_list_0(i), + window => coinc_window, + start_rise => trig_synch_0_rise(i), + start_fall => trig_synch_0_fall(i), + counting => trig_window_0(i)); + end generate ftu_list_0; + + ftu_list_1: for i in 0 to 9 generate + time_counter_inst_1: time_counter + port map( clk_250MHz => clk_250MHz, + enable => active_FTU_list_1(i), + window => coinc_window, + start_rise => trig_synch_1_rise(i), + start_fall => trig_synch_1_fall(i), + counting => trig_window_1(i)); + end generate ftu_list_1; + + ftu_list_2: for i in 0 to 9 generate + time_counter_inst_2: time_counter + port map( clk_250MHz => clk_250MHz, + enable => active_FTU_list_2(i), + window => coinc_window, + start_rise => trig_synch_2_rise(i), + start_fall => trig_synch_2_fall(i), + counting => trig_window_2(i)); + end generate ftu_list_2; + + ftu_list_3: for i in 0 to 9 generate + time_counter_inst_3: time_counter + port map( clk_250MHz => clk_250MHz, + enable => active_FTU_list_3(i), + window => coinc_window, + start_rise => trig_synch_3_rise(i), + start_fall => trig_synch_3_fall(i), + counting => trig_window_3(i)); + end generate ftu_list_3; + +end RTL; Index: firmware/FTM/trigger/drivers/trigger_count_ID/trigger_ID_count.vhd =================================================================== --- firmware/FTM/trigger/drivers/trigger_count_ID/trigger_ID_count.vhd (revision 10366) +++ firmware/FTM/trigger/drivers/trigger_count_ID/trigger_ID_count.vhd (revision 10366) @@ -0,0 +1,305 @@ +--======================================================================================= +-- TITLE : Trigger ID generator +-- DESCRIPTION : Generates ID each time a counter happen and increment counter +-- FILE : trigger_ID_count.vhd +-- COMPANY : Micro-Cameras & Space Exploration SA +--======================================================================================= +-- CREATION +-- DATE AUTHOR PROJECT REVISION +-- 23/03/2011 JGi 110323a +--======================================================================================= +-- MODIFICATION HISTORY +-- DATE AUTHOR PROJECT REVISION COMMENTS +-- 23/03/2011 JGi 110323a Description +--======================================================================================= +-- Library Definition +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +-- Entity Definition +entity trigger_ID_count is + port( --clock + clk_250MHz : in std_logic; + --control + start_run : in std_logic; + stop_run : in std_logic; + maj_coinc_n_phys : in std_logic_vector(5 downto 0); + maj_coinc_n_calib : in std_logic_vector(5 downto 0); + --triggers + trigger : in std_logic_vector(8 downto 0); + phys_trigger : in std_logic; + calib_trigger : in std_logic; + internal_trigger : in std_logic_vector(1 downto 0); + external_trigger : in std_logic_vector(1 downto 0); + --outputs + trigger_ID_done : out std_logic; + trigger_ID : out std_logic_vector(55 downto 0)); +end trigger_ID_count; + +-- Architecture Definition +architecture RTL of trigger_ID_count is + + type t_reg is record + -- Internal register declaration + start_run : std_logic; + stop_run : std_logic; + reset_counter : std_logic; + counter : std_logic_vector(31 downto 0); + counter_0_done : std_logic; + counter_1_done : std_logic_vector(1 downto 0); + counter_2_done : std_logic_vector(1 downto 0); + counter_3_done : std_logic_vector(1 downto 0); + counter_4_done : std_logic_vector(2 downto 0); + counter_5_done : std_logic_vector(2 downto 0); + counter_6_done : std_logic_vector(2 downto 0); + triggers_delay : std_logic_vector(5 downto 0); + trigger_type_1 : std_logic_vector(7 downto 0); + trigger_type_2 : std_logic_vector(7 downto 0); + -- Ouput register declaration + trigger_ID_done : std_logic_vector(1 downto 0); + trigger_ID : std_logic_vector(55 downto 0); + end record; + + signal i_next_reg : t_reg := (start_run => '0', + stop_run => '0', + reset_counter => '0', + counter => (others => '0'), + counter_0_done => '0', + counter_1_done => (others => '0'), + counter_2_done => (others => '0'), + counter_3_done => (others => '0'), + counter_4_done => (others => '0'), + counter_5_done => (others => '0'), + counter_6_done => (others => '0'), + triggers_delay => (others => '0'), + trigger_type_1 => (others => '0'), + trigger_type_2 => (others => '0'), + trigger_ID_done => (others => '0'), + trigger_ID => (others => '0')); + signal i_reg : t_reg := (start_run => '0', + stop_run => '0', + reset_counter => '0', + counter => (others => '0'), + counter_0_done => '0', + counter_1_done => (others => '0'), + counter_2_done => (others => '0'), + counter_3_done => (others => '0'), + counter_4_done => (others => '0'), + counter_5_done => (others => '0'), + counter_6_done => (others => '0'), + triggers_delay => (others => '0'), + trigger_type_1 => (others => '0'), + trigger_type_2 => (others => '0'), + trigger_ID_done => (others => '0'), + trigger_ID => (others => '0')); + +begin + + -- Component instantiation + + -- Combinatorial logic + process(start_run, stop_run, trigger, phys_trigger, calib_trigger, internal_trigger, + external_trigger, maj_coinc_n_phys, maj_coinc_n_calib, i_reg) + variable v_reg : t_reg := (start_run => '0', + stop_run => '0', + reset_counter => '0', + counter => (others => '0'), + counter_0_done => '0', + counter_1_done => (others => '0'), + counter_2_done => (others => '0'), + counter_3_done => (others => '0'), + counter_4_done => (others => '0'), + counter_5_done => (others => '0'), + counter_6_done => (others => '0'), + triggers_delay => (others => '0'), + trigger_type_1 => (others => '0'), + trigger_type_2 => (others => '0'), + trigger_ID_done => (others => '0'), + trigger_ID => (others => '0')); + begin + v_reg := i_reg; + --=================================================================================== + + --=================================================================================== + -- Trigger counter management + --=================================================================================== + -- Register inputs + v_reg.start_run := start_run; + v_reg.stop_run := stop_run; + -- Reset counter when run is started or stopped + v_reg.reset_counter := (start_run and not(i_reg.start_run)) or + (stop_run and not(i_reg.stop_run)); + -- Reset counter when starting or stopping run + if i_reg.reset_counter = '1' then + v_reg.counter := (others => '0'); + -- Count when trigger is activated + -- 32-bits Counter is splitted on 8 4-bits counter with enables + else + if trigger(0) = '1' then + v_reg.counter(3 downto 0) := std_logic_vector(unsigned(i_reg.counter(3 downto 0))+1); + end if; + if trigger(1) = '1' then + if i_reg.counter_0_done = '1' then + v_reg.counter(7 downto 4) := std_logic_vector(unsigned(i_reg.counter(7 downto 4))+1); + end if; + end if; + if trigger(2) = '1' then + if i_reg.counter_1_done(1) = '1' then + v_reg.counter(11 downto 8) := std_logic_vector(unsigned(i_reg.counter(11 downto 8))+1); + end if; + end if; + if trigger(3) = '1' then + if i_reg.counter_2_done(1) = '1' then + v_reg.counter(15 downto 12) := std_logic_vector(unsigned(i_reg.counter(15 downto 12))+1); + end if; + end if; + if trigger(4) = '1' then + if i_reg.counter_3_done(1) = '1' then + v_reg.counter(19 downto 16) := std_logic_vector(unsigned(i_reg.counter(19 downto 16))+1); + end if; + end if; + if trigger(5) = '1' then + if i_reg.counter_4_done(2) = '1' then + v_reg.counter(23 downto 20) := std_logic_vector(unsigned(i_reg.counter(23 downto 20))+1); + end if; + end if; + if trigger(6) = '1' then + if i_reg.counter_5_done(2) = '1' then + v_reg.counter(27 downto 24) := std_logic_vector(unsigned(i_reg.counter(27 downto 24))+1); + end if; + end if; + if trigger(7) = '1' then + if i_reg.counter_6_done(2) = '1' then + v_reg.counter(31 downto 28) := std_logic_vector(unsigned(i_reg.counter(31 downto 28))+1); + end if; + end if; + end if; + + -- Manage splitted counters done signals + if i_reg.counter(3 downto 0) = "1111" then + v_reg.counter_0_done := '1'; + else + v_reg.counter_0_done := '0'; + end if; + if i_reg.counter(7 downto 4) = "1111" then + v_reg.counter_1_done(0) := '1'; + else + v_reg.counter_1_done(0) := '0'; + end if; + if i_reg.counter(11 downto 8) = "1111" then + v_reg.counter_2_done(0) := '1'; + else + v_reg.counter_2_done(0) := '0'; + end if; + if i_reg.counter(15 downto 12) = "1111" then + v_reg.counter_3_done(0) := '1'; + else + v_reg.counter_3_done(0) := '0'; + end if; + if i_reg.counter(19 downto 16) = "1111" then + v_reg.counter_4_done(0) := '1'; + else + v_reg.counter_4_done(0) := '0'; + end if; + if i_reg.counter(23 downto 20) = "1111" then + v_reg.counter_5_done(0) := '1'; + else + v_reg.counter_5_done(0) := '0'; + end if; + if i_reg.counter(27 downto 24) = "1111" then + v_reg.counter_6_done(0) := '1'; + else + v_reg.counter_6_done(0) := '0'; + end if; + + -- Enables are splitted to use only 4-bits LUT + -- Delay between two trigger is long enough to allow delay on enables + v_reg.counter_1_done(1) := i_reg.counter_0_done and i_reg.counter_1_done(0); + v_reg.counter_2_done(1) := i_reg.counter_0_done and i_reg.counter_1_done(0) and + i_reg.counter_2_done(0); + v_reg.counter_3_done(1) := i_reg.counter_0_done and i_reg.counter_1_done(0) and + i_reg.counter_2_done(0) and i_reg.counter_3_done(0); + v_reg.counter_4_done(1) := i_reg.counter_0_done and i_reg.counter_1_done(0) and + i_reg.counter_2_done(0) and i_reg.counter_3_done(0); + v_reg.counter_4_done(2) := i_reg.counter_4_done(1) and i_reg.counter_4_done(0); + v_reg.counter_5_done(1) := i_reg.counter_0_done and i_reg.counter_1_done(0) and + i_reg.counter_2_done(0) and i_reg.counter_3_done(0); + v_reg.counter_5_done(2) := i_reg.counter_5_done(1) and i_reg.counter_4_done(0) and + i_reg.counter_5_done(0); + v_reg.counter_6_done(1) := i_reg.counter_0_done and i_reg.counter_1_done(0) and + i_reg.counter_2_done(0) and i_reg.counter_3_done(0); + v_reg.counter_6_done(2) := i_reg.counter_6_done(1) and i_reg.counter_4_done(0) and + i_reg.counter_5_done(0) and i_reg.counter_6_done(0); + --=================================================================================== + + --=================================================================================== + -- Trigger type management + --=================================================================================== + -- Register trigger types inputs + v_reg.triggers_delay(0) := phys_trigger; + v_reg.triggers_delay(1) := calib_trigger; + v_reg.triggers_delay(2) := internal_trigger(0); + v_reg.triggers_delay(3) := internal_trigger(1); + v_reg.triggers_delay(4) := external_trigger(0); + v_reg.triggers_delay(5) := external_trigger(1); + v_reg.trigger_ID_done(0) := '0'; + v_reg.trigger_ID_done(1) := i_reg.trigger_ID_done(0); + + -- If master trigger fires + if trigger(8) = '1' then + -- Manage trigger ready output + v_reg.trigger_ID_done(0) := '1'; + -- Manage trigger ID content + -- If physics event + if i_reg.triggers_delay(0) = '1' then + v_reg.trigger_type_1(7 downto 2) := maj_coinc_n_phys; + -- If calibration events + elsif i_reg.triggers_delay(1) = '1' then + v_reg.trigger_type_1(7 downto 2) := maj_coinc_n_calib; + else + v_reg.trigger_type_1(7 downto 2) := (others => '0'); + end if; + v_reg.trigger_type_2(7 downto 3) := (others => '0'); + -- If not a physics event + if i_reg.triggers_delay(0) = '0' then + v_reg.trigger_type_1(1 downto 0) := i_reg.triggers_delay(5 downto 4); + v_reg.trigger_type_2(2) := i_reg.triggers_delay(3); + v_reg.trigger_type_2(1) := i_reg.triggers_delay(2); + v_reg.trigger_type_2(0) := i_reg.triggers_delay(1); + else + v_reg.trigger_type_1(1 downto 0) := (others => '0'); + v_reg.trigger_type_2(2 downto 0) := (others => '0'); + end if; + end if; + --=================================================================================== + + --=================================================================================== + -- Trigger ID management + --=================================================================================== + v_reg.trigger_ID(31 downto 0) := i_reg.counter; + v_reg.trigger_ID(39 downto 32) := i_reg.trigger_type_1; + v_reg.trigger_ID(47 downto 40) := i_reg.trigger_type_2; + v_reg.trigger_ID(55 downto 48) := (others => '0'); + --=================================================================================== + + --=================================================================================== + -- Drive register input + i_next_reg <= v_reg; + + --=================================================================================== + -- Output assignation + trigger_ID_done <= i_reg.trigger_ID_done(1); + trigger_ID <= i_reg.trigger_ID; + --=================================================================================== + end process; + + -- Sequential logic + process(clk_250MHz) + begin + if rising_edge(clk_250MHz) then + i_reg <= i_next_reg; + end if; + end process; + +end RTL; Index: firmware/FTM/trigger/drivers/trigger_delayed_pulse/delayed_pulse.vhd =================================================================== --- firmware/FTM/trigger/drivers/trigger_delayed_pulse/delayed_pulse.vhd (revision 10366) +++ firmware/FTM/trigger/drivers/trigger_delayed_pulse/delayed_pulse.vhd (revision 10366) @@ -0,0 +1,208 @@ +--======================================================================================= +-- TITLE : Pulse generation with programmable delay +-- DESCRIPTION : Generate pulse from an input with a programmable delay and width +-- FILE : time_counter.vhd +-- COMPANY : Micro-Cameras & Space Exploration SA +--======================================================================================= +-- CREATION +-- DATE AUTHOR PROJECT REVISION +-- 02/03/2011 JGi FTM 110302a +--======================================================================================= +-- MODIFICATION HISTORY +-- DATE AUTHOR PROJECT REVISION COMMENTS +-- 02/03/2011 JGi FTM 110302a Description +--======================================================================================= +-- Library Definition +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library unisim; + use unisim.vcomponents.all; + +-- Entity Definition +entity delayed_pulse is + generic( pulse_width : integer range 0 to 15 := 10); + port( --clock + clk_250MHz : in std_logic; + --control + delay : in std_logic_vector(9 downto 0); + --I/O + input : in std_logic; + output : out std_logic); +end delayed_pulse; + +-- Architecture Definition +architecture RTL of delayed_pulse is + + type t_reg is record + -- Internal register declaration + delayed_input : std_logic; + enable : std_logic_vector(3 downto 0); + delay : std_logic_vector(9 downto 0); + delay_counter : std_logic_vector(9 downto 0); + delay_value_reached : std_logic_vector(2 downto 0); + delay_0_done : std_logic_vector(1 downto 0); + delay_1_done : std_logic; + pulse_shifter : std_logic_vector(pulse_width downto 0); + -- Ouput register declaration + output : std_logic_vector(1 downto 0); + end record; + + signal i_next_reg : t_reg := (delayed_input => '0', + enable => (others => '0'), + delay => (others => '0'), + delay_counter => (others => '0'), + delay_value_reached => (others => '0'), + delay_0_done => (others => '0'), + delay_1_done => '0', + pulse_shifter => (others => '0'), + output => (others => '0')); + signal i_reg : t_reg := (delayed_input => '0', + enable => (others => '0'), + delay => (others => '0'), + delay_counter => (others => '0'), + delay_value_reached => (others => '0'), + delay_0_done => (others => '0'), + delay_1_done => '0', + pulse_shifter => (others => '0'), + output => (others => '0')); + + signal i_shifted_data : std_logic; + +begin + + -- Generate shift register depending on pulse width generic + -- defined in ftm_definitions + -- Shifter logic + gen_shifter_0: if pulse_width = 0 generate + process(clk_250MHz) + variable shifter : std_logic := '0'; + begin + if rising_edge(clk_250MHz) then + shifter := i_reg.output(0) and not(i_reg.output(1)); + end if; + i_shifted_data <= shifter; + end process; + end generate gen_shifter_0; + gen_shifter_1: if pulse_width > 0 generate + process(clk_250MHz) + variable shifter : std_logic_vector(pulse_width downto 0) := (others => '0'); + begin + if rising_edge(clk_250MHz) then + shifter := shifter(pulse_width-1 downto 0) & (i_reg.output(0) and not(i_reg.output(1))); + end if; + i_shifted_data <= shifter(pulse_width); + end process; + end generate gen_shifter_1; + + -- Combinatorial logic + process(input, delay, i_shifted_data, i_reg) + variable v_reg : t_reg := (delayed_input => '0', + enable => (others => '0'), + delay => (others => '0'), + delay_counter => (others => '0'), + delay_value_reached => (others => '0'), + delay_0_done => (others => '0'), + delay_1_done => '0', + pulse_shifter => (others => '0'), + output => (others => '0')); + begin + v_reg := i_reg; + --=================================================================================== + + --=================================================================================== + -- Delay Counter management + --=================================================================================== + -- Register delay + v_reg.delay := delay; + + -- Count delay when input (master trigger) rising edge detected + if i_reg.enable(0) = '1' then + v_reg.delay_counter(3 downto 0) := std_logic_vector(unsigned(i_reg.delay_counter(3 downto 0))+1); + if i_reg.delay_0_done(1) = '1' then + v_reg.delay_counter(7 downto 4) := std_logic_vector(unsigned(i_reg.delay_counter(7 downto 4))+1); + end if; + if i_reg.delay_1_done = '1' then + v_reg.delay_counter(9 downto 8) := std_logic_vector(unsigned(i_reg.delay_counter(9 downto 8))+1); + end if; + else + v_reg.delay_counter := (others => '0'); + end if; + + v_reg.delayed_input := input; + + -- Detect input (master trigger) rising edge to enable counting + if input = '1' and i_reg.delayed_input = '0' then + v_reg.enable := (others => '1'); + end if; + + -- Generate partial comparison between counter and setting + if i_reg.delay_counter(3 downto 0) = i_reg.delay(3 downto 0) then + v_reg.delay_value_reached(0) := i_reg.enable(1); + else + v_reg.delay_value_reached(0) := '0'; + end if; + if i_reg.delay_counter(7 downto 4) = i_reg.delay(7 downto 4) then + v_reg.delay_value_reached(1) := i_reg.enable(1); + else + v_reg.delay_value_reached(1) := '0'; + end if; + if i_reg.delay_counter(9 downto 8) = i_reg.delay(9 downto 8) then + v_reg.delay_value_reached(2) := i_reg.enable(1); + else + v_reg.delay_value_reached(2) := '0'; + end if; + + -- Generate partial counter enable + if i_reg.delay_counter(3 downto 0) = "1101" then + v_reg.delay_0_done(0) := i_reg.enable(2); + else + v_reg.delay_0_done(0) := '0'; + end if; + v_reg.delay_0_done(1) := i_reg.delay_0_done(0) and i_reg.enable(2); + + if i_reg.delay_counter(7 downto 4) = "1111" then + v_reg.delay_1_done := i_reg.delay_0_done(0) and i_reg.enable(2); + end if; + --=================================================================================== + + --=================================================================================== + -- Pulse Counter management + --=================================================================================== + -- Enable output when delay is reached, and disable it after shift register + -- has finished + if i_shifted_data = '1' then + v_reg.output(0) := '0'; + elsif i_reg.delay_value_reached = "111" and i_reg.enable(3) = '1' then + v_reg.output(0) := '1'; + v_reg.pulse_shifter(0) := '1'; + end if; + + -- Once the output falls, reset enable + if i_reg.output(1) = '1' and i_reg.output(0) = '0' then + v_reg.enable := (others => '0'); + end if; + + v_reg.output(1) := i_reg.output(0); + --=================================================================================== + + --=================================================================================== + -- Drive register input + i_next_reg <= v_reg; + + --=================================================================================== + -- Output assignation + output <= i_reg.output(0); + --=================================================================================== + end process; + + -- Sequential logic + process(clk_250MHz) + begin + if rising_edge(clk_250MHz) then + i_reg <= i_next_reg; + end if; + end process; + +end RTL; Index: firmware/FTM/trigger/ftm_trigger/trigger_manager.vhd =================================================================== --- firmware/FTM/trigger/ftm_trigger/trigger_manager.vhd (revision 10366) +++ firmware/FTM/trigger/ftm_trigger/trigger_manager.vhd (revision 10366) @@ -0,0 +1,331 @@ +--======================================================================================= +-- TITLE : Trigger manager +-- DESCRIPTION : Top architecture file to detect events and generate triggers +-- FILE : trigger_manager.vhd +-- COMPANY : Micro-Cameras & Space Exploration SA +--======================================================================================= +-- CREATION +-- DATE AUTHOR PROJECT REVISION +-- 09/03/2011 JGi 110309a +--======================================================================================= +-- MODIFICATION HISTORY +-- DATE AUTHOR PROJECT REVISION COMMENTS +-- 09/03/2011 JGi 110309a Description +--======================================================================================= +-- Library Definition +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +-- Entity Definition +entity trigger_manager is + port( --clocks + clk_50MHz : in std_logic; + clk_250MHz : in std_logic; + clk_250MHz_180 : in std_logic; + --trigger primitives from FTUs + trig_prim_0 : in std_logic_vector(9 downto 0); --crate 0 + trig_prim_1 : in std_logic_vector(9 downto 0); --crate 1 + trig_prim_2 : in std_logic_vector(9 downto 0); --crate 2 + trig_prim_3 : in std_logic_vector(9 downto 0); --crate 3 + --external signals + ext_trig_1 : in std_logic; + ext_trig_2 : in std_logic; + ext_veto : in std_logic; + FAD_busy_0 : in std_logic; --crate 0 + FAD_busy_1 : in std_logic; --crate 1 + FAD_busy_2 : in std_logic; --crate 2 + FAD_busy_3 : in std_logic; --crate 3 + --control signals from e.g. main control + start_run : in std_logic; --enable trigger output + stop_run : in std_logic; --disable trigger output + new_config : in std_logic; + --settings register (see FTM Firmware Specifications) + general_settings : in std_logic_vector(15 downto 0); + LP_and_PED_freq : in std_logic_vector(15 downto 0); + LP1_LP2_PED_ratio : in std_logic_vector(15 downto 0); + maj_coinc_n_phys : in std_logic_vector(15 downto 0); + maj_coinc_n_calib : in std_logic_vector(15 downto 0); + trigger_delay : in std_logic_vector(15 downto 0); + TIM_delay : in std_logic_vector(15 downto 0); + dead_time : in std_logic_vector(15 downto 0); + coinc_window_phys : in std_logic_vector(15 downto 0); + coinc_window_calib : in std_logic_vector(15 downto 0); + active_FTU_list_0 : in std_logic_vector(15 downto 0); + active_FTU_list_1 : in std_logic_vector(15 downto 0); + active_FTU_list_2 : in std_logic_vector(15 downto 0); + active_FTU_list_3 : in std_logic_vector(15 downto 0); + --control signals or information for other entities + trigger_ID_read : in std_logic; + trig_cnt_copy_read : in std_logic; + trigger_ID_ready : out std_logic; + trigger_ID : out std_logic_vector(55 downto 0); + trig_cnt_copy : out std_logic_vector(31 downto 0); --counter reading + trig_cnt_copy_valid : out std_logic; --trigger counter reading is valid + trigger_active : out std_logic; --phys triggers are enabled/active + config_done : out std_logic; + LP1_pulse : out std_logic; --send start signal to light pulser 1 + LP2_pulse : out std_logic; --send start signal to light pulser 2 + --trigger and time marker output signals to FADs + trigger_signal : out std_logic; + TIM_signal : out std_logic); +end trigger_manager; + +-- Architecture Definition +architecture RTL of trigger_manager is + + component interface_sync_250MHz is + port( clk_250MHz : in std_logic; + start_run : in std_logic; + stop_run : in std_logic; + new_config : in std_logic; + general_settings : in std_logic_vector(15 downto 0); + LP_and_PED_freq : in std_logic_vector(15 downto 0); + LP1_LP2_PED_ratio : in std_logic_vector(15 downto 0); + maj_coinc_n_phys : in std_logic_vector(15 downto 0); + maj_coinc_n_calib : in std_logic_vector(15 downto 0); + trigger_delay : in std_logic_vector(15 downto 0); + TIM_delay : in std_logic_vector(15 downto 0); + dead_time : in std_logic_vector(15 downto 0); + coinc_window_phys : in std_logic_vector(15 downto 0); + coinc_window_calib : in std_logic_vector(15 downto 0); + active_FTU_list_0 : in std_logic_vector(15 downto 0); + active_FTU_list_1 : in std_logic_vector(15 downto 0); + active_FTU_list_2 : in std_logic_vector(15 downto 0); + active_FTU_list_3 : in std_logic_vector(15 downto 0); + config_done : out std_logic; + sync_start_run : out std_logic; + sync_stop_run : out std_logic; + sync_general_settings : out std_logic_vector(7 downto 0); + sync_LP_and_PED_freq : out std_logic_vector(9 downto 0); + sync_LP1_LP2_PED_ratio : out std_logic_vector(14 downto 0); + sync_maj_coinc_n_phys : out std_logic_vector(5 downto 0); + sync_maj_coinc_n_calib : out std_logic_vector(5 downto 0); + sync_trigger_delay : out std_logic_vector(9 downto 0); + sync_TIM_delay : out std_logic_vector(9 downto 0); + sync_dead_time : out std_logic_vector(15 downto 0); + sync_coinc_window_phys : out std_logic_vector(3 downto 0); + sync_coinc_window_calib : out std_logic_vector(3 downto 0); + sync_active_FTU_list_0 : out std_logic_vector(9 downto 0); + sync_active_FTU_list_1 : out std_logic_vector(9 downto 0); + sync_active_FTU_list_2 : out std_logic_vector(9 downto 0); + sync_active_FTU_list_3 : out std_logic_vector(9 downto 0)); + end component; + + signal i_config_done : std_logic := '0'; + signal i_sync_start_run : std_logic := '0'; + signal i_sync_stop_run : std_logic := '0'; + signal i_sync_general_settings : std_logic_vector(7 downto 0) := (others => '0'); + signal i_sync_LP_and_PED_freq : std_logic_vector(9 downto 0) := (others => '0'); + signal i_sync_LP1_LP2_PED_ratio : std_logic_vector(14 downto 0) := (others => '0'); + signal i_sync_maj_coinc_n_phys : std_logic_vector(5 downto 0) := (others => '0'); + signal i_sync_maj_coinc_n_calib : std_logic_vector(5 downto 0) := (others => '0'); + signal i_sync_trigger_delay : std_logic_vector(9 downto 0) := (others => '0'); + signal i_sync_TIM_delay : std_logic_vector(9 downto 0) := (others => '0'); + signal i_sync_dead_time : std_logic_vector(15 downto 0) := (others => '0'); + signal i_sync_coinc_window_phys : std_logic_vector(3 downto 0) := (others => '0'); + signal i_sync_coinc_window_calib : std_logic_vector(3 downto 0) := (others => '0'); + signal i_sync_active_FTU_list_0 : std_logic_vector(9 downto 0) := (others => '0'); + signal i_sync_active_FTU_list_1 : std_logic_vector(9 downto 0) := (others => '0'); + signal i_sync_active_FTU_list_2 : std_logic_vector(9 downto 0) := (others => '0'); + signal i_sync_active_FTU_list_3 : std_logic_vector(9 downto 0) := (others => '0'); + + component interface_sync_50MHz is + port( clk_50MHz : in std_logic; + clk_250MHz : in std_logic; + config_done : in std_logic; + trigger_active : in std_logic; + trigger_ID_done : in std_logic; + trigger_ID : in std_logic_vector(55 downto 0); + trigger_ID_read : in std_logic; + trigger_cnt_read : in std_logic; + sync_config_done : out std_logic; + sync_trigger_active : out std_logic; + sync_trigger_ID_ready : out std_logic; + sync_trigger_ID : out std_logic_vector(55 downto 0); + trigger_cnt_valid : out std_logic; + trigger_cnt_copy : out std_logic_vector(31 downto 0)); + end component; + + component FTU_trigger_counter is + port( clk_250MHz : in std_logic; + clk_250MHz_180 : in std_logic; + phys_coinc_window : in std_logic_vector(3 downto 0); + calib_coinc_window : in std_logic_vector(3 downto 0); + active_FTU_list_0 : in std_logic_vector(9 downto 0); + active_FTU_list_1 : in std_logic_vector(9 downto 0); + active_FTU_list_2 : in std_logic_vector(9 downto 0); + active_FTU_list_3 : in std_logic_vector(9 downto 0); + trig_prim_0 : in std_logic_vector(9 downto 0); + trig_prim_1 : in std_logic_vector(9 downto 0); + trig_prim_2 : in std_logic_vector(9 downto 0); + trig_prim_3 : in std_logic_vector(9 downto 0); + phys_events : out std_logic_vector(5 downto 0); + calib_events : out std_logic_vector(5 downto 0)); + end component; + + signal i_phys_events : std_logic_vector(5 downto 0) := (others => '0'); + signal i_calib_events : std_logic_vector(5 downto 0) := (others => '0'); + + component calibration_pedestal is + port( clk_50MHz : in std_logic; + new_config : in std_logic; + general_settings : in std_logic_vector(7 downto 0); + LP_and_PED_freq : in std_logic_vector(9 downto 0); + LP1_LP2_PED_ratio : in std_logic_vector(14 downto 0); + LP1_pulse : out std_logic; + LP2_pulse : out std_logic; + PED_pulse : out std_logic); + end component; + + signal i_LP1_pulse : std_logic; + signal i_LP2_pulse : std_logic; + signal i_PED_pulse : std_logic; + + component trigger_generator is + port( clk_250MHz : in std_logic; + start_run : in std_logic; + stop_run : in std_logic; + general_settings : in std_logic_vector(7 downto 0); + maj_coinc_n_phys : in std_logic_vector(5 downto 0); + maj_coinc_n_calib : in std_logic_vector(5 downto 0); + trigger_delay : in std_logic_vector(9 downto 0); + TIM_delay : in std_logic_vector(9 downto 0); + dead_time : in std_logic_vector(15 downto 0); + ext_trig_1 : in std_logic; + ext_trig_2 : in std_logic; + ext_veto : in std_logic; + FAD_busy_0 : in std_logic; + FAD_busy_1 : in std_logic; + FAD_busy_2 : in std_logic; + FAD_busy_3 : in std_logic; + phys_events : in std_logic_vector(5 downto 0); + calib_events : in std_logic_vector(5 downto 0); + LP1_pulse : in std_logic; + LP2_pulse : in std_logic; + PED_pulse : in std_logic; + trigger_ID_done : out std_logic; + trigger_ID : out std_logic_vector(55 downto 0); + trigger_active : out std_logic; + trigger_signal : out std_logic; + TIM_signal : out std_logic); + end component; + + signal i_trigger_active : std_logic; + signal i_trigger_ID_done : std_logic; + signal i_trigger_ID : std_logic_vector(55 downto 0); + +begin + + -- Component instantiation + inst_settings_sync: interface_sync_250MHz + port map( clk_250MHz => clk_250MHz, + start_run => start_run, + stop_run => stop_run, + new_config => new_config, + general_settings => general_settings, + LP_and_PED_freq => LP_and_PED_freq, + LP1_LP2_PED_ratio => LP1_LP2_PED_ratio, + maj_coinc_n_phys => maj_coinc_n_phys, + maj_coinc_n_calib => maj_coinc_n_calib, + trigger_delay => trigger_delay, + TIM_delay => TIM_delay, + dead_time => dead_time, + coinc_window_phys => coinc_window_phys, + coinc_window_calib => coinc_window_calib, + active_FTU_list_0 => active_FTU_list_0, + active_FTU_list_1 => active_FTU_list_1, + active_FTU_list_2 => active_FTU_list_2, + active_FTU_list_3 => active_FTU_list_3, + config_done => i_config_done, + sync_start_run => i_sync_start_run, + sync_stop_run => i_sync_stop_run, + sync_general_settings => i_sync_general_settings, + sync_LP_and_PED_freq => i_sync_LP_and_PED_freq, + sync_LP1_LP2_PED_ratio => i_sync_LP1_LP2_PED_ratio, + sync_maj_coinc_n_phys => i_sync_maj_coinc_n_phys, + sync_maj_coinc_n_calib => i_sync_maj_coinc_n_calib, + sync_trigger_delay => i_sync_trigger_delay, + sync_TIM_delay => i_sync_TIM_delay, + sync_dead_time => i_sync_dead_time, + sync_coinc_window_phys => i_sync_coinc_window_phys, + sync_coinc_window_calib => i_sync_coinc_window_calib, + sync_active_FTU_list_0 => i_sync_active_FTU_list_0, + sync_active_FTU_list_1 => i_sync_active_FTU_list_1, + sync_active_FTU_list_2 => i_sync_active_FTU_list_2, + sync_active_FTU_list_3 => i_sync_active_FTU_list_3); + + inst_interface_sync: interface_sync_50MHz + port map( clk_50MHz => clk_50MHz, + clk_250MHz => clk_250MHz, + config_done => i_config_done, + trigger_active => i_trigger_active, + trigger_ID_done => i_trigger_ID_done, + trigger_ID => i_trigger_ID, + trigger_ID_read => trigger_ID_read, + trigger_cnt_read => trig_cnt_copy_read, + sync_config_done => config_done, + sync_trigger_active => trigger_active, + sync_trigger_ID_ready => trigger_ID_ready, + sync_trigger_ID => trigger_ID, + trigger_cnt_valid => trig_cnt_copy_valid, + trigger_cnt_copy => trig_cnt_copy); + + inst_FTU_trig: FTU_trigger_counter + port map( clk_250MHz => clk_250MHz, + clk_250MHz_180 => clk_250MHz_180, + phys_coinc_window => i_sync_coinc_window_phys, + calib_coinc_window => i_sync_coinc_window_calib, + active_FTU_list_0 => i_sync_active_FTU_list_0, + active_FTU_list_1 => i_sync_active_FTU_list_1, + active_FTU_list_2 => i_sync_active_FTU_list_2, + active_FTU_list_3 => i_sync_active_FTU_list_3, + trig_prim_0 => trig_prim_0, + trig_prim_1 => trig_prim_1, + trig_prim_2 => trig_prim_2, + trig_prim_3 => trig_prim_3, + phys_events => i_phys_events, + calib_events => i_calib_events); + + inst_internal_trig: calibration_pedestal + port map( clk_50MHz => clk_50MHz, + new_config => new_config, + general_settings => general_settings(7 downto 0), + LP_and_PED_freq => LP_and_PED_freq(9 downto 0), + LP1_LP2_PED_ratio => LP1_LP2_PED_ratio(14 downto 0), + LP1_pulse => i_LP1_pulse, + LP2_pulse => i_LP2_pulse, + PED_pulse => i_PED_pulse); + + inst_trig_gen: trigger_generator + port map( clk_250MHz => clk_250MHz, + start_run => i_sync_start_run, + stop_run => i_sync_stop_run, + general_settings => i_sync_general_settings, + maj_coinc_n_phys => i_sync_maj_coinc_n_phys, + maj_coinc_n_calib => i_sync_maj_coinc_n_calib, + trigger_delay => i_sync_trigger_delay, + TIM_delay => i_sync_TIM_delay, + dead_time => i_sync_dead_time, + ext_trig_1 => ext_trig_1, + ext_trig_2 => ext_trig_2, + ext_veto => ext_veto, + FAD_busy_0 => FAD_busy_0, + FAD_busy_1 => FAD_busy_1, + FAD_busy_2 => FAD_busy_2, + FAD_busy_3 => FAD_busy_3, + phys_events => i_phys_events, + calib_events => i_calib_events, + LP1_pulse => i_LP1_pulse, + LP2_pulse => i_LP2_pulse, + PED_pulse => i_PED_pulse, + trigger_ID_done => i_trigger_ID_done, + trigger_ID => i_trigger_ID, + trigger_active => i_trigger_active, + trigger_signal => trigger_signal, + TIM_signal => TIM_signal); + + LP1_pulse <= i_LP1_pulse; + LP2_pulse <= i_LP2_pulse; + +end RTL; Index: firmware/FTM/trigger/kernel/trigger_generator/trigger_generator.vhd =================================================================== --- firmware/FTM/trigger/kernel/trigger_generator/trigger_generator.vhd (revision 10366) +++ firmware/FTM/trigger/kernel/trigger_generator/trigger_generator.vhd (revision 10366) @@ -0,0 +1,434 @@ +--======================================================================================= +-- TITLE : Trigger generator +-- DESCRIPTION : Generates triggers from events, calibration pulses or external inputs +-- FILE : trigger_generator.vhd +-- COMPANY : Micro-Cameras & Space Exploration SA +--======================================================================================= +-- CREATION +-- DATE AUTHOR PROJECT REVISION +-- 14/03/2011 JGi 110314a +--======================================================================================= +-- MODIFICATION HISTORY +-- DATE AUTHOR PROJECT REVISION COMMENTS +-- 14/03/2011 JGi 110314a Description +-- 13/04/2011 JGi 110413a Update trigger enable management +--======================================================================================= +-- Library Definition +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library ftm_definitions; + use ftm_definitions.ftm_array_types.all; + use ftm_definitions.ftm_constants.all; + +-- Entity Definition +entity trigger_generator is + port( --clock + clk_250MHz : in std_logic; + --config inputs + start_run : in std_logic; + stop_run : in std_logic; + general_settings : in std_logic_vector(7 downto 0); + maj_coinc_n_phys : in std_logic_vector(5 downto 0); + maj_coinc_n_calib : in std_logic_vector(5 downto 0); + trigger_delay : in std_logic_vector(9 downto 0); + TIM_delay : in std_logic_vector(9 downto 0); + dead_time : in std_logic_vector(15 downto 0); + --trigger inputs + ext_trig_1 : in std_logic; + ext_trig_2 : in std_logic; + ext_veto : in std_logic; + FAD_busy_0 : in std_logic; + FAD_busy_1 : in std_logic; + FAD_busy_2 : in std_logic; + FAD_busy_3 : in std_logic; + phys_events : in std_logic_vector(5 downto 0); + calib_events : in std_logic_vector(5 downto 0); + LP1_pulse : in std_logic; + LP2_pulse : in std_logic; + PED_pulse : in std_logic; + --outputs + trigger_ID_done : out std_logic; + trigger_ID : out std_logic_vector(55 downto 0); + trigger_active : out std_logic; + trigger_signal : out std_logic; + TIM_signal : out std_logic); +end trigger_generator; + +-- Architecture Definition +architecture RTL of trigger_generator is + + component deadtime_generator is + port( clk_250MHz : in std_logic; + deadtime : in std_logic_vector(15 downto 0); + start : in std_logic; + waiting : out std_logic); + end component; + + signal i_deadtime : std_logic; + + component delayed_pulse is + generic( pulse_width : integer range 0 to 15); + port( clk_250MHz : in std_logic; + delay : in std_logic_vector(9 downto 0); + input : in std_logic; + output : out std_logic); + end component; + + signal i_trigger_signal : std_logic; + signal i_TIM_signal : std_logic; + + component trigger_ID_count is + port( clk_250MHz : in std_logic; + start_run : in std_logic; + stop_run : in std_logic; + maj_coinc_n_phys : in std_logic_vector(5 downto 0); + maj_coinc_n_calib : in std_logic_vector(5 downto 0); + trigger : in std_logic_vector(8 downto 0); + phys_trigger : in std_logic; + calib_trigger : in std_logic; + internal_trigger : in std_logic_vector(1 downto 0); + external_trigger : in std_logic_vector(1 downto 0); + trigger_ID_done : out std_logic; + trigger_ID : out std_logic_vector(55 downto 0)); + end component; + + type t_reg is record + -- Internal register declaration + start_run : std_logic; + LP1_delay : std_logic_vector(2 downto 0); + LP2_delay : std_logic_vector(2 downto 0); + PED_delay : std_logic_vector(2 downto 0); + ext_trig_1 : std_logic_vector(2 downto 0); + ext_trig_2 : std_logic_vector(2 downto 0); + ext_veto : std_logic_vector(1 downto 0); + FAD_busy_0 : std_logic_vector(1 downto 0); + FAD_busy_1 : std_logic_vector(1 downto 0); + FAD_busy_2 : std_logic_vector(1 downto 0); + FAD_busy_3 : std_logic_vector(1 downto 0); + general_settings : std_logic_vector(7 downto 0); + maj_coinc_n_phys : std_logic_vector(5 downto 0); + maj_coinc_n_calib : std_logic_vector(5 downto 0); + enable_trigger : std_logic; + phys_compare : std_logic_vector(1 downto 0); + phys_trigger : std_logic; + ext_trigger : std_logic_vector(1 downto 0); + calib_compare : std_logic_vector(1 downto 0); + calib_trigger : std_logic; + wait_for_calib : std_logic; + internal_trigger : std_logic_vector(1 downto 0); + trigger : std_logic_vector(12 downto 0); + trigger_active : std_logic; + -- Ouput register declaration + end record; + + signal i_next_reg : t_reg := (start_run => '0', + LP1_delay => (others => '0'), + LP2_delay => (others => '0'), + PED_delay => (others => '0'), + ext_trig_1 => (others => '0'), + ext_trig_2 => (others => '0'), + ext_veto => (others => '0'), + FAD_busy_0 => (others => '0'), + FAD_busy_1 => (others => '0'), + FAD_busy_2 => (others => '0'), + FAD_busy_3 => (others => '0'), + general_settings => (others => '0'), + maj_coinc_n_phys => (others => '1'), + maj_coinc_n_calib => (others => '1'), + enable_trigger => '0', + phys_compare => (others => '0'), + phys_trigger => '0', + ext_trigger => (others => '0'), + calib_compare => (others => '0'), + calib_trigger => '0', + wait_for_calib => '0', + internal_trigger => (others => '0'), + trigger => (others => '0'), + trigger_active => '1'); + signal i_reg : t_reg := (start_run => '0', + LP1_delay => (others => '0'), + LP2_delay => (others => '0'), + PED_delay => (others => '0'), + ext_trig_1 => (others => '0'), + ext_trig_2 => (others => '0'), + ext_veto => (others => '0'), + FAD_busy_0 => (others => '0'), + FAD_busy_1 => (others => '0'), + FAD_busy_2 => (others => '0'), + FAD_busy_3 => (others => '0'), + general_settings => (others => '0'), + maj_coinc_n_phys => (others => '1'), + maj_coinc_n_calib => (others => '1'), + enable_trigger => '0', + phys_compare => (others => '0'), + phys_trigger => '0', + ext_trigger => (others => '0'), + calib_compare => (others => '0'), + calib_trigger => '0', + wait_for_calib => '0', + internal_trigger => (others => '0'), + trigger => (others => '0'), + trigger_active => '1'); + +begin + + -- Component instantiation + inst_deadtime: deadtime_generator + port map( clk_250MHz => clk_250MHz, + deadtime => dead_time, + start => i_reg.trigger(0), + waiting => i_deadtime); + + inst_phys_trig: delayed_pulse + generic map( pulse_width => TRIG_SIGNAL_PULSE_WIDTH) + port map( clk_250MHz => clk_250MHz, + delay => trigger_delay, + input => i_reg.trigger(1), + output => i_trigger_signal); + + trigger_signal <= i_trigger_signal and i_reg.start_run; + + inst_phys_TIM: delayed_pulse + generic map( pulse_width => TIM_SIGNAL_PULSE_WIDTH) + port map( clk_250MHz => clk_250MHz, + delay => TIM_delay, + input => i_reg.trigger(2), + output => i_TIM_signal); + + TIM_signal <= i_TIM_signal and i_reg.start_run; + + inst_trig_ID: trigger_ID_count + port map( clk_250MHz => clk_250MHz, + start_run => start_run, + stop_run => stop_run, + maj_coinc_n_phys => maj_coinc_n_phys, + maj_coinc_n_calib => maj_coinc_n_calib, + trigger => i_reg.trigger(12 downto 4), + phys_trigger => i_reg.phys_trigger, + calib_trigger => i_reg.calib_trigger, + internal_trigger => i_reg.internal_trigger, + external_trigger => i_reg.ext_trigger, + trigger_ID_done => trigger_ID_done, + trigger_ID => trigger_ID); + + -- Combinatorial logic + process(start_run, general_settings, maj_coinc_n_phys, maj_coinc_n_calib, + ext_trig_1, ext_trig_2, ext_veto, FAD_busy_0, FAD_busy_1, FAD_busy_2, + FAD_busy_3, phys_events, calib_events, LP1_pulse, LP2_pulse, PED_pulse, + i_deadtime, i_reg) + variable v_reg : t_reg := (start_run => '0', + LP1_delay => (others => '0'), + LP2_delay => (others => '0'), + PED_delay => (others => '0'), + ext_trig_1 => (others => '0'), + ext_trig_2 => (others => '0'), + ext_veto => (others => '0'), + FAD_busy_0 => (others => '0'), + FAD_busy_1 => (others => '0'), + FAD_busy_2 => (others => '0'), + FAD_busy_3 => (others => '0'), + general_settings => (others => '0'), + maj_coinc_n_phys => (others => '1'), + maj_coinc_n_calib => (others => '1'), + enable_trigger => '0', + phys_compare => (others => '0'), + phys_trigger => '0', + ext_trigger => (others => '0'), + calib_compare => (others => '0'), + calib_trigger => '0', + wait_for_calib => '0', + internal_trigger => (others => '0'), + trigger => (others => '0'), + trigger_active => '1'); + begin + v_reg := i_reg; + --=================================================================================== + + --=================================================================================== + -- External inputs double-sync + --=================================================================================== + v_reg.ext_trig_1(0) := ext_trig_1; + v_reg.ext_trig_1(1) := i_reg.ext_trig_1(0); + v_reg.ext_trig_1(2) := i_reg.ext_trig_1(1); + v_reg.ext_trig_2(0) := ext_trig_2; + v_reg.ext_trig_2(1) := i_reg.ext_trig_2(0); + v_reg.ext_trig_2(2) := i_reg.ext_trig_2(1); + v_reg.ext_veto(0) := ext_veto; + v_reg.ext_veto(1) := i_reg.ext_veto(0); + v_reg.FAD_busy_0(0) := FAD_busy_0; + v_reg.FAD_busy_0(1) := i_reg.FAD_busy_0(0); + v_reg.FAD_busy_1(0) := FAD_busy_1; + v_reg.FAD_busy_1(1) := i_reg.FAD_busy_1(0); + v_reg.FAD_busy_2(0) := FAD_busy_2; + v_reg.FAD_busy_2(1) := i_reg.FAD_busy_2(0); + v_reg.FAD_busy_3(0) := FAD_busy_3; + v_reg.FAD_busy_3(1) := i_reg.FAD_busy_3(0); + --=================================================================================== + + --=================================================================================== + -- Re-sync of calibration and pedestal triggers to the 250MHz clock + --=================================================================================== + v_reg.LP1_delay(0) := LP1_pulse; + v_reg.LP1_delay(1) := i_reg.LP1_delay(0); + v_reg.LP1_delay(2) := i_reg.LP1_delay(1); + v_reg.LP2_delay(0) := LP2_pulse; + v_reg.LP2_delay(1) := i_reg.LP2_delay(0); + v_reg.LP2_delay(2) := i_reg.LP2_delay(1); + v_reg.PED_delay(0) := PED_pulse; + v_reg.PED_delay(1) := i_reg.PED_delay(0); + v_reg.PED_delay(2) := i_reg.PED_delay(1); + --=================================================================================== + + --=================================================================================== + -- Settings registration + --=================================================================================== + v_reg.general_settings := general_settings; + v_reg.maj_coinc_n_phys := maj_coinc_n_phys; + v_reg.maj_coinc_n_calib := maj_coinc_n_calib; + --=================================================================================== + + --=================================================================================== + -- Master enable management + --=================================================================================== + v_reg.start_run := start_run; + --=================================================================================== + + --=================================================================================== + -- Trigger generation + --=================================================================================== + -- Enable trigger generation only if veto is not active, FAD are not busy and + -- deadtime is not enabled + if i_reg.trigger(3) = '1' or i_deadtime = '1' or + (i_reg.ext_veto(1) = '1' and i_reg.general_settings(1) = '1') or + i_reg.FAD_busy_0(1) = '1' or i_reg.FAD_busy_1(1) = '1' or + i_reg.FAD_busy_2(1) = '1' or i_reg.FAD_busy_3(1) = '1' then + v_reg.enable_trigger := '0'; + else + v_reg.enable_trigger := '1'; + end if; + + -- Compare number of detected physics event to the physics threshold + if phys_events >= i_reg.maj_coinc_n_phys then + v_reg.phys_compare(0) := '1'; + else + v_reg.phys_compare(0) := '0'; + end if; + v_reg.phys_compare(1) := i_reg.phys_compare(0); + + -- Activate physics trigger when enabled by settings and physics threhsold is reached + if i_reg.general_settings(7) = '1' and i_reg.wait_for_calib = '0' and + i_reg.phys_compare(0) = '1' and i_reg.phys_compare(1) = '0' and + i_reg.enable_trigger = '1' then + v_reg.phys_trigger := '1'; + else + v_reg.phys_trigger := '0'; + end if; + + -- Lock trigger generator when a pulse on LP1 is detected and wait for FTU events + -- counter reach the calibration threshold + if i_reg.LP1_delay(1) = '1' and i_reg.LP1_delay(2) = '0' and + general_settings(4) = '1' then + v_reg.wait_for_calib := '1'; + elsif i_reg.enable_trigger = '0' then + v_reg.wait_for_calib := '0'; + end if; + + -- Compare number of detected physics event to the calibration threshold + if calib_events >= i_reg.maj_coinc_n_calib then + v_reg.calib_compare(0) := '1'; + else + v_reg.calib_compare(0) := '0'; + end if; + v_reg.calib_compare(1) := i_reg.calib_compare(0); + + -- Activate calibration trigger when enabled by settings and + -- calibration threhsold is reached + if i_reg.general_settings(4) = '1' and i_reg.wait_for_calib = '1' and + i_reg.calib_compare(0) = '1' and i_reg.calib_compare(1) = '0' and + i_reg.enable_trigger = '1' then + v_reg.calib_trigger := '1'; + else + v_reg.calib_trigger := '0'; + end if; + + -- Activate trigger number 1 from external NIM inputs + if i_reg.ext_trig_1(1) = '1' and i_reg.ext_trig_1(2) = '0' and + i_reg.general_settings(2) = '1' and i_reg.wait_for_calib = '0' and + i_reg.enable_trigger = '1' then + v_reg.ext_trigger(0) := '1'; + else + v_reg.ext_trigger(0) := '0'; + end if; + + -- Activate trigger number 2 from external NIM inputs + if i_reg.ext_trig_2(1) = '1' and i_reg.ext_trig_2(2) = '0' and + i_reg.general_settings(3) = '1' and i_reg.wait_for_calib = '0' and + i_reg.enable_trigger = '1' then + v_reg.ext_trigger(1) := '1'; + else + v_reg.ext_trigger(1) := '0'; + end if; + + -- Activate calibration trigger from LP2 pulse + if i_reg.LP2_delay(1) = '1' and i_reg.LP2_delay(2) = '0' and + i_reg.general_settings(5) = '1' and i_reg.wait_for_calib = '0' and + i_reg.enable_trigger = '1' then + v_reg.internal_trigger(0) := '1'; + else + v_reg.internal_trigger(0) := '0'; + end if; + + -- Activate calibration trigger from Pedestal signal + if i_reg.PED_delay(1) = '1' and i_reg.PED_delay(2) = '0' and + i_reg.general_settings(6) = '1' and i_reg.wait_for_calib = '0' and + i_reg.enable_trigger = '1' then + v_reg.internal_trigger(1) := '1'; + else + v_reg.internal_trigger(1) := '0'; + end if; + + -- Generate master trigger for deadtime, trigger and TIM signals, + -- triggers counting and ID generation + -- It is replicated to limit fanout and improve speed + v_reg.trigger(0) := i_reg.phys_trigger or i_reg.calib_trigger or + i_reg.ext_trigger(0) or i_reg.ext_trigger(1) or + i_reg.internal_trigger(0) or i_reg.internal_trigger(1); + v_reg.trigger(1) := v_reg.trigger(0); + v_reg.trigger(2) := v_reg.trigger(0); + v_reg.trigger(3) := v_reg.trigger(0); + v_reg.trigger(4) := v_reg.trigger(0); + v_reg.trigger(5) := v_reg.trigger(0); + v_reg.trigger(6) := v_reg.trigger(0); + v_reg.trigger(7) := v_reg.trigger(0); + v_reg.trigger(8) := v_reg.trigger(0); + v_reg.trigger(9) := v_reg.trigger(0); + v_reg.trigger(10) := v_reg.trigger(0); + v_reg.trigger(11) := v_reg.trigger(0); + v_reg.trigger(12) := v_reg.trigger(0); + + -- Manage trigger active signal + -- Set low when a trigger is processed or FAD are busy or veto is active + v_reg.trigger_active := i_reg.enable_trigger and not(i_reg.wait_for_calib); + --=================================================================================== + + --=================================================================================== + -- Drive register input + i_next_reg <= v_reg; + + --=================================================================================== + -- Output assignation + trigger_active <= i_reg.trigger_active; + --=================================================================================== + end process; + + -- Sequential logic + process(clk_250MHz) + begin + if rising_edge(clk_250MHz) then + i_reg <= i_next_reg; + end if; + end process; + +end RTL; Index: firmware/FTM/trigger/readme.txt =================================================================== --- firmware/FTM/trigger/readme.txt (revision 10366) +++ firmware/FTM/trigger/readme.txt (revision 10366) @@ -0,0 +1,70 @@ +****************************************************************************************** +** Johan Giampiccolo +** MicroCameras & Space Exploration SA +** Puits Godet 10a +** CH-2000 Neuchâtel +** johan.giampiccolo@microcameras.ch +** +41 32 566 76 74 +****************************************************************************************** + +This folder contains all the files of the Trigger Manager HDL entity for the FACT project. + +This folder is organized as following: + +----> HDL Code + | + |----> assembler + | | + | |----> FTU_trigger_generator + | | + | |----> FTU_trigger_counter.vhd + | + |----> drivers + | | + | |----> calibration_pedestal + | | | + | | |----> calibration_pedestal.vhd + | | + | |----> deadtime_generator + | | | + | | |----> deadtime_generator.vhd + | | + | |----> detection_logic + | | | + | | |----> adder_3_bits.vhd + | | |----> adder_4_bits.vhd + | | |----> adder_5_bits.vhd + | | |----> trigger_sum.vhd + | | |----> unary_to_binary.vhd + | | + | |----> input_synch + | | | + | | |----> input_synch.vhd + | | + | |----> interface_sync + | | | + | | |----> interface_sync_50MHz.vhd + | | |----> interface_sync_250MHz.vhd + | | + | |----> time_window + | | | + | | |----> time_counter.vhd + | | |----> time_window.vhd + | | + | |----> trigger_count_ID + | | | + | | |----> trigger_ID_count.vhd + | | + | |----> trigger_delayed_pulse + | | | + | | |----> delayed_pulse.vhd + | + |----> ftm_trigger + | | + | |----> trigger_manager.vhd + | + |----> kernel + | + |----> trigger_generator + | + |----> trigger_generator.vhd