Index: firmware/FTM/ftu_control/FTM_ftu_control.vhd
===================================================================
--- firmware/FTM/ftu_control/FTM_ftu_control.vhd	(revision 10328)
+++ firmware/FTM/ftu_control/FTM_ftu_control.vhd	(revision 10418)
@@ -74,4 +74,11 @@
     ftu_active_cr2 : in std_logic_vector (15 downto 0);
     ftu_active_cr3 : in std_logic_vector (15 downto 0);
+
+    --error message interface to ethernet control
+    ftu_error_calls      : out std_logic_vector (15 DOWNTO 0) := (others => '0');
+    ftu_error_data       : out std_logic_vector ((FTU_RS485_BLOCK_WIDTH - 1) downto 0) := (others => '0');
+    ftu_error_send       : out std_logic := '0';
+    ftu_error_send_ack   :  in std_logic;
+    ftu_error_send_ready :  in std_logic;
     
     -- communication with static (config) RAM
@@ -146,4 +153,5 @@
   signal FTU_enable_array_sig  : FTU_enable_array_type;  -- initialized in interpreter
   signal FTU_rate_array_sig    : FTU_rate_array_type;  -- initialized in interpreter
+  signal FTU_overflow_sig      : std_logic_vector(7 downto 0);  -- initialized in interpreter
   signal FTU_prescaling_sig    : std_logic_vector(7 downto 0);  -- initialized in interpreter
   signal FTU_crc_error_cnt_sig : std_logic_vector(7 downto 0);  -- initialized in interpreter
@@ -199,4 +207,5 @@
   signal enable_crc_from_interpreter_sig : std_logic;
   signal crc_data_from_FSM_sig           : std_logic_vector (FTU_RS485_BLOCK_WIDTH - 9 downto 0) := (others => '0');
+  signal crc_data_from_FSM_sig_cp        : std_logic_vector (FTU_RS485_BLOCK_WIDTH - 9 downto 0) := (others => '0');
   signal crc_sig                         : std_logic_vector(CRC_POLYNOMIAL'length - 1 downto 0);
   signal crc_sig_inv                     : std_logic_vector(CRC_POLYNOMIAL'length - 1 downto 0);
@@ -211,8 +220,13 @@
   signal FTU_list_reg_cnt    : integer range 0 to NO_OF_FTU_LIST_REG := 0;
   signal FTU_list_header_cnt : integer range 0 to FTU_LIST_RAM_OFFSET := 0;
-
+  signal DD_RAM_reg_cnt      : integer range 0 to NO_OF_DD_RAM_REG := 0;
+  
   -- counter to define timeout and number of retries
   signal timeout_cnt : integer range 0 to FTU_RS485_TIMEOUT := 0;
   signal retry_cnt   : integer range 0 to FTU_RS485_NO_OF_RETRY := 0;
+
+  --Zwischenrechnungen
+  signal FTU_cnt_offset_sig   : integer range 0 to (NO_OF_DD_RAM_REG * NO_OF_FTUS_PER_CRATE) := 0;
+  signal crate_cnt_offset_sig : integer range 0 to (NO_OF_CRATES * NO_OF_FTUS_PER_CRATE * NO_OF_DD_RAM_REG) := 0;
   
   component FTM_ftu_rs485_interface
@@ -260,4 +274,5 @@
       FTU_enable_array  : OUT FTU_enable_array_type;
       FTU_rate_array    : OUT FTU_rate_array_type;
+      FTU_overflow      : OUT std_logic_vector(7 downto 0);
       FTU_prescaling    : OUT std_logic_vector(7 downto 0);
       FTU_crc_error_cnt : OUT std_logic_vector(7 downto 0);
@@ -285,5 +300,7 @@
   type FTM_ftu_rs485_control_StateType is (INIT, IDLE, ACTIVE_LIST, READ_CONFIG, TRANSMIT_CONFIG,
                                            PING, PING_END, FTU_LIST,
+                                           SEND_ERROR_1, SEND_ERROR_2,
                                            RATES, RATES_1, RATES_2, RATES_3,
+                                           DD_RAM, DD_RAM_1, DD_RAM_2, DD_RAM_3,
                                            READ_CONFIG_1, READ_CONFIG_2, READ_CONFIG_3,
                                            TRANSMIT_CONFIG_1, TRANSMIT_CONFIG_2, TRANSMIT_CONFIG_3,
@@ -291,8 +308,9 @@
                                            FTU_LIST_1, FTU_LIST_2, FTU_LIST_3);
   signal FTM_ftu_rs485_control_State : FTM_ftu_rs485_control_StateType;
+  signal after_error_State : FTM_ftu_rs485_control_StateType;
 
 begin
   
-  Inst_FTM_fTU_rs485_interface_0 : FTM_ftu_rs485_interface  -- crate 0
+  Inst_FTM_ftu_rs485_interface_0 : FTM_ftu_rs485_interface  -- crate 0
     port map(
       clk      => clk_50MHz,
@@ -311,5 +329,5 @@
     );
 
-  Inst_FTM_fTU_rs485_interface_1 : FTM_ftu_rs485_interface  -- crate 1
+  Inst_FTM_ftu_rs485_interface_1 : FTM_ftu_rs485_interface  -- crate 1
     port map(
       clk      => clk_50MHz,
@@ -328,5 +346,5 @@
     );
 
-  Inst_FTM_fTU_rs485_interface_2 : FTM_ftu_rs485_interface  -- crate 2
+  Inst_FTM_ftu_rs485_interface_2 : FTM_ftu_rs485_interface  -- crate 2
     port map(
       clk      => clk_50MHz,
@@ -345,5 +363,5 @@
     );
 
-  Inst_FTM_fTU_rs485_interface_3 : FTM_ftu_rs485_interface  -- crate 3
+  Inst_FTM_ftu_rs485_interface_3 : FTM_ftu_rs485_interface  -- crate 3
     port map(
       clk      => clk_50MHz,
@@ -387,4 +405,5 @@
       FTU_enable_array  => FTU_enable_array_sig,
       FTU_rate_array    => FTU_rate_array_sig,
+      FTU_overflow      => FTU_overflow_sig,
       FTU_prescaling    => FTU_prescaling_sig,
       FTU_crc_error_cnt => FTU_crc_error_cnt_sig,
@@ -602,4 +621,5 @@
         when TRANSMIT_CONFIG_1 =>  -- wait one cycle for CRC calculation
           enable_crc_from_FSM_sig <= '0';
+          crc_data_from_FSM_sig_cp <= crc_data_from_FSM_sig;
           FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_2;
           
@@ -614,4 +634,5 @@
             elsif (frame_cnt = 27) then
               frame_cnt <= frame_cnt + 1;
+              ftu_error_data <= crc_sig & crc_data_from_FSM_sig_cp;
               tx_data_sig <= crc_sig;
               tx_start_sig <= '1';
@@ -633,5 +654,11 @@
             retry_cnt <= 0;
             sel_crc_input_source_sig <= '0';
-            FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG;
+            if (retry_cnt = 0) then  -- no errors 
+              FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG;
+            else  -- send error message and move to next command;
+              ftu_error_calls <= conv_std_logic_vector((retry_cnt + 1), 16);
+              after_error_State <= TRANSMIT_CONFIG;
+              FTM_ftu_rs485_control_State <= SEND_ERROR_1;
+            end if;
           else
             if (timeout_cnt < FTU_RS485_TIMEOUT) then
@@ -649,10 +676,24 @@
               else
                 retry_cnt <= 0;
-                FTU_command_cnt <= FTU_command_cnt;  -- move to next command;
-                FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG;
+                FTU_command_cnt <= FTU_command_cnt;  -- send error message and move to next command
+                ftu_error_calls <= (others => '0');
+                after_error_State <= TRANSMIT_CONFIG;
+                FTM_ftu_rs485_control_State <= SEND_ERROR_1;
               end if;
             end if;
           end if;
 
+        when SEND_ERROR_1 =>  -- send an error message
+          ftu_error_send <= '1';
+          if (ftu_error_send_ack = '1') then
+            ftu_error_send <= '0';
+            FTM_ftu_rs485_control_State <= SEND_ERROR_2;
+          end if;
+
+        when SEND_ERROR_2 =>
+          if (ftu_error_send_ready = '1') then
+            FTM_ftu_rs485_control_State <= after_error_state;
+          end if;
+          
         when PING =>  -- ping all FTUs
           rec_reset_sig <= '0';
@@ -759,5 +800,6 @@
             write_FTUlist_RAM <= '1';
             addr_FTUlist_RAM <= conv_std_logic_vector(FTU_LIST_RAM_OFFSET +
-                                                      (FTU_cnt - 1)* NO_OF_FTU_LIST_REG +
+                                                      (crate_cnt * NO_OF_FTUS_PER_CRATE * NO_OF_FTU_LIST_REG) +
+                                                      ((FTU_cnt - 1) * NO_OF_FTU_LIST_REG) +
                                                       (FTU_list_reg_cnt - 1), FTU_LIST_RAM_ADDR_WIDTH);
             if (retry_cnt < FTU_RS485_NO_OF_RETRY) then
@@ -871,4 +913,5 @@
         when RATES_1 =>  -- wait one cycle for CRC calculation
           enable_crc_from_FSM_sig <= '0';
+          crc_data_from_FSM_sig_cp <= crc_data_from_FSM_sig;
           FTM_ftu_rs485_control_State <= RATES_2;
 
@@ -883,4 +926,5 @@
             elsif (frame_cnt = 27) then
               frame_cnt <= frame_cnt + 1;
+              ftu_error_data <= crc_sig & crc_data_from_FSM_sig_cp;
               tx_data_sig <= crc_sig;
               tx_start_sig <= '1';
@@ -901,5 +945,12 @@
             timeout_cnt <= 0;
             sel_crc_input_source_sig <= '0';
-            FTM_ftu_rs485_control_State <= RATES;
+            --FTM_ftu_rs485_control_State <= RATES;
+            if (retry_cnt = 0) then  -- no errors 
+              FTM_ftu_rs485_control_State <= DD_RAM;
+            else  -- send error message and move to next command;
+              ftu_error_calls <= conv_std_logic_vector((retry_cnt + 1), 16);
+              after_error_State <= DD_RAM;
+              FTM_ftu_rs485_control_State <= SEND_ERROR_1;
+            end if;
           else
             if (timeout_cnt < FTU_RS485_TIMEOUT) then
@@ -916,9 +967,89 @@
                 FTM_ftu_rs485_control_State <= RATES;
               else
-                retry_cnt <= 0;
+                --retry_cnt <= 0;
                 FTU_cnt <= FTU_cnt;  -- move on
-                FTM_ftu_rs485_control_State <= RATES;
+                ftu_error_calls <= (others => '0');
+                after_error_State <= DD_RAM;
+                FTM_ftu_rs485_control_State <= SEND_ERROR_1;
               end if;
             end if;
+          end if;
+
+        when DD_RAM =>  -- write rates of actual FTU to DD RAM
+          rec_reset_sig <= '0';
+          if (DD_RAM_reg_cnt < NO_OF_DD_RAM_REG) then
+            DD_RAM_reg_cnt <= DD_RAM_reg_cnt + 1;
+            FTU_cnt_offset_sig <= ((FTU_cnt - 1) * NO_OF_DD_RAM_REG);
+            crate_cnt_offset_sig <= (crate_cnt * NO_OF_FTUS_PER_CRATE * NO_OF_DD_RAM_REG);
+            FTM_ftu_rs485_control_State <= DD_RAM_1;
+          else
+            DD_RAM_reg_cnt <= 0;
+            retry_cnt <= 0;
+            FTM_ftu_rs485_control_State <= RATES;
+          end if;
+
+        when DD_RAM_1 =>
+          if (dynamic_RAM_busy = '0') then
+            write_dynamic_RAM <= '1';
+            addr_dynamic_RAM <= conv_std_logic_vector(DD_BLOCK_SIZE_GENERAL +
+                                                      crate_cnt_offset_sig +
+                                                      --(crate_cnt * NO_OF_FTUS_PER_CRATE * NO_OF_DD_RAM_REG) +
+                                                      --((FTU_cnt - 1) * NO_OF_DD_RAM_REG) +
+                                                      FTU_cnt_offset_sig +
+                                                      (DD_RAM_reg_cnt - 1), DYNAMIC_RAM_ADDR_WIDTH);
+            if ( (retry_cnt < FTU_RS485_NO_OF_RETRY)
+                 and (FTU_cnt_offset_sig < (NO_OF_FTUS_PER_CRATE * NO_OF_DD_RAM_REG))
+                 and (crate_cnt_offset_sig < (NO_OF_CRATES * NO_OF_FTUS_PER_CRATE * NO_OF_DD_RAM_REG)) ) then
+              if ((DD_RAM_reg_cnt - 1) = 0) then
+                data_dynamic_RAM <= FTU_rate_array_sig(0)(31 downto 16);
+              elsif ((DD_RAM_reg_cnt - 1) = 1) then
+                data_dynamic_RAM <= FTU_rate_array_sig(0)(15 downto 0);
+              elsif ((DD_RAM_reg_cnt - 1) = 2) then
+                data_dynamic_RAM <= FTU_rate_array_sig(1)(31 downto 16);
+              elsif ((DD_RAM_reg_cnt - 1) = 3) then
+                data_dynamic_RAM <= FTU_rate_array_sig(1)(15 downto 0);
+              elsif ((DD_RAM_reg_cnt - 1) = 4) then
+                data_dynamic_RAM <= FTU_rate_array_sig(2)(31 downto 16);
+              elsif ((DD_RAM_reg_cnt - 1) = 5) then
+                data_dynamic_RAM <= FTU_rate_array_sig(2)(15 downto 0);
+              elsif ((DD_RAM_reg_cnt - 1) = 6) then
+                data_dynamic_RAM <= FTU_rate_array_sig(3)(31 downto 16);
+              elsif ((DD_RAM_reg_cnt - 1) = 7) then
+                data_dynamic_RAM <= FTU_rate_array_sig(3)(15 downto 0);
+              elsif ((DD_RAM_reg_cnt - 1) = 8) then
+                data_dynamic_RAM <= FTU_rate_array_sig(4)(31 downto 16);
+              elsif ((DD_RAM_reg_cnt - 1) = 9) then
+                data_dynamic_RAM <= FTU_rate_array_sig(4)(15 downto 0);
+              elsif ((DD_RAM_reg_cnt - 1) = 10) then
+                data_dynamic_RAM <= "00000000" & FTU_overflow_sig;
+              elsif ((DD_RAM_reg_cnt - 1) = 11) then
+                data_dynamic_RAM <= "00000000" & FTU_crc_error_cnt_sig;
+--              elsif ((DD_RAM_reg_cnt - 1) = 10) then
+--                data_dynamic_RAM <= "0000" & conv_std_logic_vector(DD_BLOCK_SIZE_GENERAL +
+--                                                                   --((FTU_cnt - 1) * NO_OF_DD_RAM_REG) +
+--                                                                   FTU_cnt_offset_sig +
+--                                                                   (DD_RAM_reg_cnt - 1), DYNAMIC_RAM_ADDR_WIDTH);
+--              elsif ((DD_RAM_reg_cnt - 1) = 11) then
+--                --data_dynamic_RAM <= "0000" & conv_std_logic_vector(FTU_cnt_offset_sig, DYNAMIC_RAM_ADDR_WIDTH);
+--                data_dynamic_RAM <= "0000" & conv_std_logic_vector(DD_BLOCK_SIZE_GENERAL +
+--                                                                   --((FTU_cnt - 1) * NO_OF_DD_RAM_REG) +
+--                                                                   FTU_cnt_offset_sig +
+--                                                                   (DD_RAM_reg_cnt - 1), DYNAMIC_RAM_ADDR_WIDTH);
+              end if;
+            else
+              data_dynamic_RAM <= (others => '0');
+            end if;
+            FTM_ftu_rs485_control_State <= DD_RAM_2;
+          end if;
+            
+        when DD_RAM_2 =>
+          if (dynamic_RAM_started = '1') then
+            write_dynamic_RAM <= '0';
+            FTM_ftu_rs485_control_State <= DD_RAM_3;
+          end if;
+
+        when DD_RAM_3 =>
+          if (dynamic_RAM_ready = '1') then
+            FTM_ftu_rs485_control_State <= DD_RAM;
           end if;
           
Index: firmware/FTM/ftu_control/FTM_ftu_rs485_interpreter.vhd
===================================================================
--- firmware/FTM/ftu_control/FTM_ftu_rs485_interpreter.vhd	(revision 10328)
+++ firmware/FTM/ftu_control/FTM_ftu_rs485_interpreter.vhd	(revision 10418)
@@ -47,4 +47,5 @@
     FTU_enable_array  : OUT FTU_enable_array_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'));
     FTU_rate_array    : OUT FTU_rate_array_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'));
+    FTU_overflow      : OUT std_logic_vector(7 downto 0) := (others => '0');
     FTU_prescaling    : OUT std_logic_vector(7 downto 0) := (others => '0');
     FTU_crc_error_cnt : OUT std_logic_vector(7 downto 0) := (others => '0');
@@ -144,4 +145,5 @@
                                data_block(199 downto 168)                                
                                );
+            FTU_overflow <= data_block(207 downto 200);
             FTU_crc_error_cnt <= data_block(215 downto 208);
             FTM_ftu_rs485_interpreter_State <= WAIT_FOR_DATA;
@@ -165,4 +167,5 @@
           elsif (data_block(39 downto 32) = "00000111") then -- read counter mode
             FTU_prescaling <= data_block(47 downto 40);
+            FTU_overflow <= data_block(55 downto 48);
             FTM_ftu_rs485_interpreter_State <= WAIT_FOR_DATA;
           elsif (data_block(39 downto 32) = "00000101") then -- ping pong
