Index: firmware/FTM/FTM_central_control.vhd =================================================================== --- firmware/FTM/FTM_central_control.vhd (revision 10366) +++ firmware/FTM/FTM_central_control.vhd (revision 10418) @@ -59,9 +59,14 @@ dd_send_ack : IN std_logic; dd_send_ready : IN std_logic; + dd_block_ready_ftu : out std_logic := '0'; + dd_block_start_ack_ftu : in std_logic; + dd_block_start_ftu : out std_logic := '0'; config_start_cc : out std_logic := '0'; config_started_cc : in std_logic; config_ready_cc : in std_logic; config_trigger : out std_logic := '0'; - config_trigger_done : in std_logic + config_trigger_done : in std_logic; + dna_start : out std_logic := '0'; + dna_ready : in std_logic ); end FTM_central_control; @@ -80,5 +85,5 @@ signal prescaling_FTU01_sig : std_logic_vector(7 downto 0) := "00100111"; - type state_central_proc_type is (CP_INIT, + type state_central_proc_type is (CP_INIT, CP_INIT_DNA, CP_CONFIG_START, CP_CONFIG, CP_CONFIG_01, CP_CONFIG_CC, CP_CONFIG_CC_01, @@ -86,5 +91,5 @@ CP_CONFIG_SCALER, CP_CONFIG_SCALER_01, CP_CONFIG_TRIGGER, CP_CONFIG_TRIGGER_01, - CP_IDLE, CP_PING, CP_READ_RATES, CP_READ_RATES_01, + CP_IDLE, CP_PING, CP_START_RATES, CP_READ_RATES, CP_READ_RATES_01, CP_SEND_START, CP_SEND_END); signal state_central_proc : state_central_proc_type := CP_INIT; @@ -97,9 +102,18 @@ case state_central_proc is - when CP_INIT => + when CP_INIT => -- wait for DCMs to lock if (clk_ready = '1') then + state_central_proc <= CP_INIT_DNA; + end if; + + when CP_INIT_DNA => -- get FPGA DNA + if (dna_ready = '1') then state_central_proc <= CP_CONFIG; - end if; - + dna_start <= '0'; + else + dna_start <= '1'; + state_central_proc <= CP_INIT_DNA; + end if; + when CP_CONFIG_START => if (config_started_ack = '1') then @@ -189,6 +203,7 @@ elsif (new_period_sig = '1') then new_period_ack_sig <= '1'; - rates_ftu <= '1'; - state_central_proc <= CP_READ_RATES; + --rates_ftu <= '1'; + --state_central_proc <= CP_READ_RATES; + state_central_proc <= CP_START_RATES; end if; @@ -202,4 +217,14 @@ end if; + when CP_START_RATES => + new_period_ack_sig <= '0'; + dd_block_start_ftu <= '1'; + dd_block_ready_ftu <= '0'; + if (dd_block_start_ack_ftu = '1') then + dd_block_start_ftu <= '0'; + rates_ftu <= '1'; + state_central_proc <= CP_READ_RATES; + end if; + when CP_READ_RATES => new_period_ack_sig <= '0'; @@ -211,4 +236,5 @@ when CP_READ_RATES_01 => if (rates_ready_ftu = '1') then + dd_block_ready_ftu <= '1'; state_central_proc <= CP_SEND_START; end if; Index: firmware/FTM/FTM_top.vhd =================================================================== --- firmware/FTM/FTM_top.vhd (revision 10366) +++ firmware/FTM/FTM_top.vhd (revision 10418) @@ -146,18 +146,18 @@ -- Bus 2: Trigger-ID to FAD boards - -- Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable - -- Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable - - -- Bus2_RxD_0 : in STD_LOGIC; -- crate 0 - -- Bus2_TxD_0 : out STD_LOGIC; - - -- Bus2_RxD_1 : in STD_LOGIC; -- crate 1 - -- Bus2_TxD_1 : out STD_LOGIC; - - -- Bus2_RxD_2 : in STD_LOGIC; -- crate 2 - -- Bus2_TxD_2 : out STD_LOGIC; - - -- Bus2_RxD_3 : in STD_LOGIC; -- crate 3 - -- Bus2_TxD_3 : out STD_LOGIC; + Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable + Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable + + Bus2_RxD_0 : in STD_LOGIC; -- crate 0 + Bus2_TxD_0 : out STD_LOGIC; + + Bus2_RxD_1 : in STD_LOGIC; -- crate 1 + Bus2_TxD_1 : out STD_LOGIC; + + Bus2_RxD_2 : in STD_LOGIC; -- crate 2 + Bus2_TxD_2 : out STD_LOGIC; + + Bus2_RxD_3 : in STD_LOGIC; -- crate 3 + Bus2_TxD_3 : out STD_LOGIC; @@ -326,7 +326,7 @@ signal dd_data_sig : std_logic_vector(15 DOWNTO 0) := (others => '0'); signal dd_addr_sig : std_logic_vector(11 DOWNTO 0) := (others => '0'); - signal dd_block_start_sig : std_logic := '0'; + signal dd_block_start_ftu_sig : std_logic := '0'; signal dd_block_start_ack_ftu_sig : std_logic := '0'; - signal dd_block_ready_sig : std_logic := '0'; + signal dd_block_ready_ftu_sig : std_logic := '0'; signal dd_busy_sig : std_logic; signal dd_write_sig : std_logic := '0'; @@ -361,8 +361,17 @@ signal clk_ready_sig : STD_LOGIC := '0'; -- set high by FTM_clk_gen when DCMs have locked + signal trigger_ID_ready_sig : std_logic; -- initialized in trigger manager + signal trigger_ID_sig : std_logic_vector(55 downto 0); -- initialized in trigger manager + signal trigger_ID_read_sig : std_logic; -- initialized in FTM_fad_broadcast + signal reset_sig : STD_LOGIC := '0'; -- initialize to 0 on power-up signal trigger_signal_sig : std_logic := '0'; signal TIM_signal_sig : std_logic := '0'; + + --signals for FPGA DNA identifier + signal dna_sig : STD_LOGIC_VECTOR(63 downto 0); -- initialized in FTM_dna_gen + signal dna_start_sig : STD_LOGIC; -- initialized in FTM_central_control + signal dna_ready_sig : STD_LOGIC; -- initialized in FTM_dna_gen signal led_sig : std_logic_vector(7 downto 0) := (others => '0'); @@ -389,4 +398,13 @@ clk_250_ps : OUT STD_LOGIC; ready : OUT STD_LOGIC + ); + end component; + + component FTM_dna_gen + port( + clk : IN STD_LOGIC; + start : IN STD_LOGIC; + dna : OUT STD_LOGIC_VECTOR(63 downto 0); + ready : OUT STD_LOGIC ); end component; @@ -498,9 +516,14 @@ dd_send_ack : IN std_logic; dd_send_ready : IN std_logic; + dd_block_ready_ftu : out std_logic := '0'; + dd_block_start_ack_ftu : in std_logic; + dd_block_start_ftu : out std_logic := '0'; config_start_cc : out std_logic := '0'; config_started_cc : in std_logic; config_ready_cc : in std_logic; config_trigger : out std_logic; - config_trigger_done : in std_logic + config_trigger_done : in std_logic; + dna_start : out std_logic; + dna_ready : in std_logic ); end component; @@ -532,4 +555,9 @@ ftu_active_cr2 : in std_logic_vector (15 downto 0); ftu_active_cr3 : in std_logic_vector (15 downto 0); + ftu_error_calls : out std_logic_vector (15 DOWNTO 0) := (others => '0'); + ftu_error_data : out std_logic_vector ((FTU_RS485_BLOCK_WIDTH - 1) downto 0) := (others => '0'); + ftu_error_send : out std_logic := '0'; + ftu_error_send_ack : in std_logic; + ftu_error_send_ready : in std_logic; static_RAM_busy : in std_logic; static_RAM_started : in std_logic; @@ -553,4 +581,26 @@ end component; + component FTM_fad_broadcast + port( + clk_50MHz : in std_logic; + rx_en : out STD_LOGIC; + tx_en : out STD_LOGIC; + rx_d_0 : in STD_LOGIC; + tx_d_0 : out STD_LOGIC; + rx_d_1 : in STD_LOGIC; + tx_d_1 : out STD_LOGIC; + rx_d_2 : in STD_LOGIC; + tx_d_2 : out STD_LOGIC; + rx_d_3 : in STD_LOGIC; + tx_d_3 : out STD_LOGIC; + enable_ID_sending : in std_logic; + TIM_source : in std_logic; + LP_settings : in std_logic_vector(3 downto 0); + trigger_ID_ready : in std_logic; + trigger_ID : in std_logic_vector(FAD_RS485_BLOCK_WIDTH - 1 downto 0); + trigger_ID_read : out std_logic + ); + end component; + component ethernet_modul port( @@ -674,4 +724,12 @@ ready => clk_ready_sig ); + + Inst_FTM_dna_gen : FTM_dna_gen + port map( + clk => clk_50M_sig, + start => dna_start_sig, + dna => dna_sig, + ready => dna_ready_sig + ); --differential output buffer for trigger signal @@ -730,8 +788,8 @@ active_FTU_list_3 => ftu_active_cr3_sig, --control signals or information for other entities - trigger_ID_read => '0', + trigger_ID_read => trigger_ID_read_sig, trig_cnt_copy_read => trigger_counter_read_sig, - trigger_ID_ready => open, - trigger_ID => open, + trigger_ID_ready => trigger_ID_ready_sig, + trigger_ID => trigger_ID_sig, trig_cnt_copy => trigger_counter_sig, --counter reading trig_cnt_copy_valid => trigger_counter_valid_sig, --trigger counter reading is valid @@ -795,9 +853,14 @@ dd_send_ack => dd_send_ack_sig, dd_send_ready => dd_send_ready_sig, + dd_block_ready_ftu => dd_block_ready_ftu_sig, + dd_block_start_ack_ftu => dd_block_start_ack_ftu_sig, + dd_block_start_ftu => dd_block_start_ftu_sig, config_start_cc => config_start_cc_sig, config_started_cc => config_started_cc_sig, config_ready_cc => config_ready_cc_sig, config_trigger => config_trigger_sig, - config_trigger_done => config_trigger_done_sig + config_trigger_done => config_trigger_done_sig, + dna_start => dna_start_sig, + dna_ready => dna_ready_sig ); @@ -828,4 +891,9 @@ ftu_active_cr2 => ftu_active_cr2_sig, ftu_active_cr3 => ftu_active_cr3_sig, + ftu_error_calls => ftu_error_calls_sig, + ftu_error_data => ftu_error_data_sig, + ftu_error_send => ftu_error_send_sig, + ftu_error_send_ack => ftu_error_send_ack_sig, + ftu_error_send_ready=> ftu_error_send_ready_sig, static_RAM_busy => sd_busy_sig, static_RAM_started => sd_started_ftu_sig, @@ -846,4 +914,25 @@ write_FTUlist_RAM => fl_write_sig, addr_FTUlist_RAM => fl_addr_sig + ); + + Inst_FTM_fad_broadcast : FTM_fad_broadcast + port map( + clk_50MHz => clk_50M_sig, + rx_en => Bus2_Rx_En, + tx_en => Bus2_Tx_En, + rx_d_0 => Bus2_RxD_0, + tx_d_0 => Bus2_TxD_0, + rx_d_1 => Bus2_RxD_1, + tx_d_1 => Bus2_TxD_1, + rx_d_2 => Bus2_RxD_2, + tx_d_2 => Bus2_TxD_2, + rx_d_3 => Bus2_RxD_3, + tx_d_3 => Bus2_TxD_3, + enable_ID_sending => '1', + TIM_source => general_settings_sig(0), + LP_settings => "0000", + trigger_ID_ready => trigger_ID_ready_sig, + trigger_ID => trigger_ID_sig, + trigger_ID_read => trigger_ID_read_sig ); @@ -913,7 +1002,7 @@ coin_win_p => coin_win_p_sig, --new stuff - dd_block_ready_ftu => dd_block_ready_sig, + dd_block_ready_ftu => dd_block_ready_ftu_sig, dd_block_start_ack_ftu => dd_block_start_ack_ftu_sig, - dd_block_start_ftu => dd_block_start_sig, + dd_block_start_ftu => dd_block_start_ftu_sig, dd_send => dd_send_sig, dd_send_ack => dd_send_ack_sig, Index: firmware/FTM/FTM_top_tb.vhd =================================================================== --- firmware/FTM/FTM_top_tb.vhd (revision 10366) +++ firmware/FTM/FTM_top_tb.vhd (revision 10418) @@ -145,18 +145,18 @@ -- Bus 2: Trigger-ID to FAD boards - -- Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable - -- Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable - - -- Bus2_RxD_0 : in STD_LOGIC; -- crate 0 - -- Bus2_TxD_0 : out STD_LOGIC; - - -- Bus2_RxD_1 : in STD_LOGIC; -- crate 1 - -- Bus2_TxD_1 : out STD_LOGIC; - - -- Bus2_RxD_2 : in STD_LOGIC; -- crate 2 - -- Bus2_TxD_2 : out STD_LOGIC; - - -- Bus2_RxD_3 : in STD_LOGIC; -- crate 3 - -- Bus2_TxD_3 : out STD_LOGIC; + Bus2_Tx_En : out STD_LOGIC; -- bus 2: transmitter enable + Bus2_Rx_En : out STD_LOGIC; -- bus 2: receiver enable + + Bus2_RxD_0 : in STD_LOGIC; -- crate 0 + Bus2_TxD_0 : out STD_LOGIC; + + Bus2_RxD_1 : in STD_LOGIC; -- crate 1 + Bus2_TxD_1 : out STD_LOGIC; + + Bus2_RxD_2 : in STD_LOGIC; -- crate 2 + Bus2_TxD_2 : out STD_LOGIC; + + Bus2_RxD_3 : in STD_LOGIC; -- crate 3 + Bus2_TxD_3 : out STD_LOGIC; @@ -347,6 +347,7 @@ -- Clock period definitions - constant clk_period : TIME := 25 ns; -- 40 MHZ oscillator U47 - constant baud_rate_period : TIME := 4 us; -- 250 kHz baud rate + constant clk_period : TIME := 25 ns; -- 40 MHZ oscillator U47 + --constant baud_rate_period : TIME := 4 us; -- 250 kHz baud rate + constant baud_rate_period : TIME := 100 ns; -- 10 MHz baud rate begin @@ -394,14 +395,14 @@ Bus1_RxD_3 => Bus1_RxD_3_sig, Bus1_TxD_3 => Bus1_TxD_3_sig, --- Bus2_Tx_En => Bus2_Tx_En_sig, --- Bus2_Rx_En => Bus2_Rx_En_sig, --- Bus2_RxD_0 => Bus2_RxD_0_sig, --- Bus2_TxD_0 => Bus2_TxD_0_sig, --- Bus2_RxD_1 => Bus2_RxD_1_sig, --- Bus2_TxD_1 => Bus2_TxD_1_sig, --- Bus2_RxD_2 => Bus2_RxD_2_sig, --- Bus2_TxD_2 => Bus2_TxD_2_sig, --- Bus2_RxD_3 => Bus2_RxD_3_sig, --- Bus2_TxD_3 => Bus2_TxD_3_sig, + Bus2_Tx_En => Bus2_Tx_En_sig, + Bus2_Rx_En => Bus2_Rx_En_sig, + Bus2_RxD_0 => Bus2_RxD_0_sig, + Bus2_TxD_0 => Bus2_TxD_0_sig, + Bus2_RxD_1 => Bus2_RxD_1_sig, + Bus2_TxD_1 => Bus2_TxD_1_sig, + Bus2_RxD_2 => Bus2_RxD_2_sig, + Bus2_TxD_2 => Bus2_TxD_2_sig, + Bus2_RxD_3 => Bus2_RxD_3_sig, + Bus2_TxD_3 => Bus2_TxD_3_sig, -- Crate_Res0 => Crate_Res0_sig, -- Crate_Res1 => Crate_Res1_sig, @@ -453,8 +454,8 @@ wait for 100us; Busy0_sig <= '0'; - wait for 1ms; - Busy0_sig <= '1'; - wait for 500us; - Busy0_sig <= '0'; +-- wait for 1ms; +-- Busy0_sig <= '1'; +-- wait for 500us; +-- Busy0_sig <= '0'; wait; end process busy_proc; @@ -531,5 +532,5 @@ -- time of FTU answer --------------------------------------------------------------------------- - wait for 2ms; + wait for 1.24ms; --------------------------------------------------------------------------- -- data package of FTU answer (28 byte) @@ -543,9 +544,9 @@ assign_rs485_0(X"01"); --FTM firmware ID wait for 0ns; - assign_rs485_0(X"05"); --instruction + assign_rs485_0(X"02"); --instruction wait for 0us; assign_rs485_0(X"00"); --data byte 01 wait for 0ns; - assign_rs485_0(X"00"); --data byte 02 + assign_rs485_0(X"F0"); --data byte 02 wait for 0ns; assign_rs485_0(X"00"); --data byte 03 @@ -589,6 +590,6 @@ assign_rs485_0(X"00"); --CRC error counter (not used) wait for 0ns; - --assign_rs485_0(X"9E"); --check sum for rates - assign_rs485_0(X"A5"); --check sum for ping + assign_rs485_0(X"98"); --check sum for rates + --assign_rs485_0(X"A5"); --check sum for ping --------------------------------------------------------------------------- -- don't forget final wait! Index: firmware/FTM/dna/FTM_dna_gen.vhd =================================================================== --- firmware/FTM/dna/FTM_dna_gen.vhd (revision 10418) +++ firmware/FTM/dna/FTM_dna_gen.vhd (revision 10418) @@ -0,0 +1,112 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: Q. Weitzel +-- +-- Create Date: 04/15/2010 +-- Design Name: +-- Module Name: FTM_dna_gen - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: entity to read out the FPGA DNA identifier +-- +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library ftm_definitions; +USE ftm_definitions.ftm_constants.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +entity FTM_dna_gen is + Port ( + clk : IN STD_LOGIC; + start : IN STD_LOGIC; + dna : OUT STD_LOGIC_VECTOR(63 downto 0) := (others => '0'); + ready : OUT STD_LOGIC := '0' + ); +end FTM_dna_gen; + +architecture Behavioral of FTM_dna_gen is + + signal dout_sig : STD_LOGIC := '0'; + signal read_sig : STD_LOGIC := '0'; + signal shift_sig : STD_LOGIC := '0'; + signal dna_sig : STD_LOGIC_VECTOR(63 downto 0) := (others => '0'); + + type FTM_dna_gen_StateType is (IDLE, READ_DNA, SHIFT_DNA, DNA_READY); + signal FTM_dna_gen_State : FTM_dna_gen_StateType; + + signal shift_cntr : INTEGER range 0 to 64 := 0; + +begin + + DNA_PORT_inst : DNA_PORT + generic map ( + SIM_DNA_VALUE => DNA_FOR_SIM) -- Specifies the Pre-programmed factory ID value + port map ( + DOUT => dout_sig, -- 1-bit DNA output data + CLK => clk, -- 1-bit clock input + DIN => '0', -- 1-bit user data input pin + READ => read_sig, -- 1-bit input, active high load DNA, active low read + SHIFT => shift_sig -- 1-bit input, active high shift enable + ); + + FTM_dna_gen_FSM : process(clk) + begin + if Falling_edge(clk) then + case FTM_dna_gen_State is + when IDLE => + ready <= '0'; + read_sig <= '0'; + shift_sig <= '0'; + if (start = '1') then + FTM_dna_gen_State <= READ_DNA; + else + FTM_dna_gen_State <= IDLE; + end if; + when READ_DNA => + ready <= '0'; + read_sig <= '1'; + shift_sig <= '0'; + FTM_dna_gen_State <= SHIFT_DNA; + when SHIFT_DNA => + shift_cntr <= shift_cntr + 1; + ready <= '0'; + read_sig <= '0'; + if (shift_cntr < 57) then + dna_sig <= dna_sig(62 downto 0) & dout_sig; -- put in from right + shift_sig <= '1'; + FTM_dna_gen_State <= SHIFT_DNA; + --elsif (shift_cntr = 56) then + --dna_sig <= dna_sig(62 downto 0) & dout_sig; -- put in from right + --shift_sig <= '0'; + --FTM_dna_gen_State <= SHIFT_DNA; + else + shift_sig <= '1'; + FTM_dna_gen_State <= DNA_READY; + end if; + when DNA_READY => + ready <= '1'; + read_sig <= '0'; + shift_sig <= '0'; + end case; + end if; + end process FTM_dna_gen_FSM; + + dna <= dna_sig; + +end Behavioral; Index: firmware/FTM/ethernet/dd_write_general_modul_beha.vhd =================================================================== --- firmware/FTM/ethernet/dd_write_general_modul_beha.vhd (revision 10366) +++ firmware/FTM/ethernet/dd_write_general_modul_beha.vhd (revision 10418) @@ -118,4 +118,5 @@ when WGP_WRITE_READY => if (dd_write_general = '0') then + dd_write_general_started <= '0'; dd_write_general_ready <= '1'; state_write_general_proc <= WGP_IDLE; Index: firmware/FTM/fad_broadcast/FTM_fad_broadcast.vhd =================================================================== --- firmware/FTM/fad_broadcast/FTM_fad_broadcast.vhd (revision 10418) +++ firmware/FTM/fad_broadcast/FTM_fad_broadcast.vhd (revision 10418) @@ -0,0 +1,322 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: Q. Weitzel +-- +-- Create Date: 04/13/2011 +-- Design Name: +-- Module Name: FTM_fad_broadcast - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Broadcast of trigger ID to FAD boards +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library ftm_definitions; +USE ftm_definitions.ftm_array_types.all; +USE ftm_definitions.ftm_constants.all; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity FTM_fad_broadcast is + port( + clk_50MHz : in std_logic; -- main clock + + -- global bus 2 enables for crates 0-3 + rx_en : out STD_LOGIC; -- receiver enable + tx_en : out STD_LOGIC; -- transmitter enable + + -- crate 0 data I/O + rx_d_0 : in STD_LOGIC; + tx_d_0 : out STD_LOGIC; + + -- crate 1 data I/O + rx_d_1 : in STD_LOGIC; + tx_d_1 : out STD_LOGIC; + + -- crate 2 data I/O + rx_d_2 : in STD_LOGIC; + tx_d_2 : out STD_LOGIC; + + -- crate 3 data I/O + rx_d_3 : in STD_LOGIC; + tx_d_3 : out STD_LOGIC; + + -- start/stop run from central control + enable_ID_sending : in std_logic; + + -- missing information for trigger ID + TIM_source : in std_logic; + LP_settings : in std_logic_vector(3 downto 0); + + -- communication with trigger_manager + trigger_ID_ready : in std_logic; + trigger_ID : in std_logic_vector(FAD_RS485_BLOCK_WIDTH - 1 downto 0); + trigger_ID_read : out std_logic + ); +end FTM_fad_broadcast; + +architecture Behavioral of FTM_fad_broadcast is + + -- internal registers to store trigger ID + signal trigger_ID_sig : std_logic_vector(FAD_RS485_BLOCK_WIDTH - 1 downto 0) := (others => '0'); + signal TIM_source_sig : std_logic := '0'; + signal LP_settings_sig : std_logic_vector(3 downto 0) := (others => '0'); + + signal tx_start_sig : std_logic := '0'; + signal tx_data_sig : std_logic_vector (7 DOWNTO 0) := (others => '0'); + + -- rx_enable and tx_enable lines from different FTM_fad_rs485_interface + -- initialized in corresponding interface + -- the signals from interface 0 are used to drive the global enables + signal rx_en_0_sig : STD_LOGIC; + signal tx_en_0_sig : STD_LOGIC; + signal rx_en_1_sig : STD_LOGIC; + signal tx_en_1_sig : STD_LOGIC; + signal rx_en_2_sig : STD_LOGIC; + signal tx_en_2_sig : STD_LOGIC; + signal rx_en_3_sig : STD_LOGIC; + signal tx_en_3_sig : STD_LOGIC; + + signal tx_busy_0_sig : std_logic; -- initialized in FTM_fad_rs485_interface_0 + signal rx_valid_0_sig : std_logic; -- initialized in FTM_fad_rs485_interface_0 + signal rx_data_0_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_fad_rs485_interface_0 + signal rx_busy_0_sig : std_logic; -- initialized in FTU_fad_rs485_interface_0 + + signal tx_busy_1_sig : std_logic; -- initialized in FTM_fad_rs485_interface_1 + signal rx_valid_1_sig : std_logic; -- initialized in FTM_fad_rs485_interface_1 + signal rx_data_1_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_fad_rs485_interface_1 + signal rx_busy_1_sig : std_logic; -- initialized in FTU_fad_rs485_interface_1 + + signal tx_busy_2_sig : std_logic; -- initialized in FTM_fad_rs485_interface_2 + signal rx_valid_2_sig : std_logic; -- initialized in FTM_fad_rs485_interface_2 + signal rx_data_2_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_fad_rs485_interface_2 + signal rx_busy_2_sig : std_logic; -- initialized in FTU_fad_rs485_interface_2 + + signal tx_busy_3_sig : std_logic; -- initialized in FTM_fad_rs485_interface_3 + signal rx_valid_3_sig : std_logic; -- initialized in FTM_fad_rs485_interface_3 + signal rx_data_3_sig : std_logic_vector (7 DOWNTO 0); -- initialized in FTM_fad_rs485_interface_3 + signal rx_busy_3_sig : std_logic; -- initialized in FTU_fad_rs485_interface_3 + + -- signals to control and read out CRC + signal reset_crc_sig : std_logic; + signal enable_crc_sig : std_logic; + signal crc_data_sig : std_logic_vector (FAD_RS485_BLOCK_WIDTH - 9 downto 0) := (others => '0'); + signal crc_sig : std_logic_vector(CRC_POLYNOMIAL'length - 1 downto 0); + signal crc_sig_inv : std_logic_vector(CRC_POLYNOMIAL'length - 1 downto 0); + + -- various loop counters + signal frame_cnt : integer range 0 to (FAD_RS485_BLOCK_WIDTH / 8) := 0; + + component FTM_fad_rs485_interface + port( + clk : IN std_logic; + -- RS485 + rx_d : IN std_logic; + rx_en : OUT std_logic; + tx_d : OUT std_logic; + tx_en : OUT std_logic; + -- FPGA + rx_data : OUT std_logic_vector (7 DOWNTO 0); + rx_busy : OUT std_logic := '0'; + rx_valid : OUT std_logic := '0'; + tx_data : IN std_logic_vector (7 DOWNTO 0); + tx_busy : OUT std_logic := '0'; + tx_start : IN std_logic + ); + end component; + + component ucrc_par + generic( + POLYNOMIAL : std_logic_vector; + INIT_VALUE : std_logic_vector; + DATA_WIDTH : integer range 2 to 256; + SYNC_RESET : integer range 0 to 1 + ); + port( + clk_i : in std_logic; + rst_i : in std_logic; + clken_i : in std_logic; + data_i : in std_logic_vector(DATA_WIDTH - 1 downto 0); + match_o : out std_logic; + crc_o : out std_logic_vector(POLYNOMIAL'length - 1 downto 0) + ); + end component; + + type FTM_fad_broadcast_StateType is (INIT, IDLE, ACK, SEND_01, SEND_02, SEND_03); + signal FTM_fad_broadcast_State : FTM_fad_broadcast_StateType; + +begin + + Inst_FTM_fad_rs485_interface_0 : FTM_fad_rs485_interface -- crate 0 + port map( + clk => clk_50MHz, + -- RS485 + rx_d => rx_d_0, + rx_en => rx_en_0_sig, + tx_d => tx_d_0, + tx_en => tx_en_0_sig, + -- FPGA + rx_data => rx_data_0_sig, + rx_busy => rx_busy_0_sig, + rx_valid => rx_valid_0_sig, + tx_data => tx_data_sig, + tx_busy => tx_busy_0_sig, + tx_start => tx_start_sig + ); + + Inst_FTM_fad_rs485_interface_1 : FTM_fad_rs485_interface -- crate 1 + port map( + clk => clk_50MHz, + -- RS485 + rx_d => rx_d_1, + rx_en => rx_en_1_sig, + tx_d => tx_d_1, + tx_en => tx_en_1_sig, + -- FPGA + rx_data => rx_data_1_sig, + rx_busy => rx_busy_1_sig, + rx_valid => rx_valid_1_sig, + tx_data => tx_data_sig, + tx_busy => tx_busy_1_sig, + tx_start => tx_start_sig + ); + + Inst_FTM_fad_rs485_interface_2 : FTM_fad_rs485_interface -- crate 2 + port map( + clk => clk_50MHz, + -- RS485 + rx_d => rx_d_2, + rx_en => rx_en_2_sig, + tx_d => tx_d_2, + tx_en => tx_en_2_sig, + -- FPGA + rx_data => rx_data_2_sig, + rx_busy => rx_busy_2_sig, + rx_valid => rx_valid_2_sig, + tx_data => tx_data_sig, + tx_busy => tx_busy_2_sig, + tx_start => tx_start_sig + ); + + Inst_FTM_fad_rs485_interface_3 : FTM_fad_rs485_interface -- crate 3 + port map( + clk => clk_50MHz, + -- RS485 + rx_d => rx_d_3, + rx_en => rx_en_3_sig, + tx_d => tx_d_3, + tx_en => tx_en_3_sig, + -- FPGA + rx_data => rx_data_3_sig, + rx_busy => rx_busy_3_sig, + rx_valid => rx_valid_3_sig, + tx_data => tx_data_sig, + tx_busy => tx_busy_3_sig, + tx_start => tx_start_sig + ); + + Inst_ucrc_par : ucrc_par + generic map( + POLYNOMIAL => CRC_POLYNOMIAL, + INIT_VALUE => CRC_INIT_VALUE, + DATA_WIDTH => (FAD_RS485_BLOCK_WIDTH - 8), + SYNC_RESET => 1 + ) + port map( + clk_i => clk_50MHz, + rst_i => reset_crc_sig, + clken_i => enable_crc_sig, + data_i => crc_data_sig, + match_o => open, + crc_o => crc_sig_inv + ); + + -- Main finite state machine to control all 40 FTUs + FTM_fad_broadcast_FSM: process (clk_50MHz) + begin + if Rising_edge(clk_50MHz) then + case FTM_fad_broadcast_State is + + when INIT => -- reset CRC register + reset_crc_sig <= '1'; + FTM_fad_broadcast_State <= IDLE; + + when IDLE => -- wait for trigger_ID_ready flag + reset_crc_sig <= '0'; + enable_crc_sig <= '0'; + trigger_ID_read <= '0'; + if (trigger_ID_ready = '1') then + TIM_source_sig <= TIM_source; + LP_settings_sig <= LP_settings; + trigger_ID_sig <= trigger_ID; + if (enable_ID_sending = '0') then + FTM_fad_broadcast_State <= ACK; + else + FTM_fad_broadcast_State <= SEND_01; + end if; + end if; + + when ACK => -- just acknowledge trigger ID without sending it + trigger_ID_read <= '1'; + reset_crc_sig <= '0'; + if (trigger_ID_ready = '0') then + FTM_fad_broadcast_State <= IDLE; + end if; + + when SEND_01 => -- prepare CRC calculation + enable_crc_sig <= '1'; + crc_data_sig <= TIM_source & LP_settings & trigger_ID(42 downto 0); + FTM_fad_broadcast_State <= SEND_02; + + when SEND_02 => -- wait one cycle for CRC calculation + enable_crc_sig <= '0'; + FTM_fad_broadcast_State <= SEND_03; + + when SEND_03 => -- transmit byte by byte + if ( (tx_busy_0_sig = '0') and (tx_busy_1_sig = '0') and (tx_busy_2_sig = '0') and (tx_busy_3_sig = '0') ) then + if (frame_cnt < 6) then + frame_cnt <= frame_cnt + 1; + tx_data_sig <= crc_data_sig (7 downto 0); + crc_data_sig <= "00000000" & crc_data_sig ((FAD_RS485_BLOCK_WIDTH - 9) downto 8); + tx_start_sig <= '1'; + FTM_fad_broadcast_State <= SEND_03; + elsif (frame_cnt = 6) then + frame_cnt <= frame_cnt + 1; + tx_data_sig <= crc_sig; + tx_start_sig <= '1'; + FTM_fad_broadcast_State <= SEND_03; + else + frame_cnt <= 0; + reset_crc_sig <= '1'; + FTM_fad_broadcast_State <= ACK; + end if; + else + tx_start_sig <= '0'; + FTM_fad_broadcast_State <= SEND_03; + end if; + + end case; + end if; + end process FTM_fad_broadcast_FSM; + + rx_en <= rx_en_0_sig; + tx_en <= tx_en_0_sig; + + crc_sig <= crc_sig_inv(0) & crc_sig_inv(1) & crc_sig_inv(2) & crc_sig_inv(3) & crc_sig_inv(4) & crc_sig_inv(5) & crc_sig_inv(6) & crc_sig_inv(7); + +end Behavioral; + Index: firmware/FTM/fad_broadcast/FTM_fad_rs485_interface.vhd =================================================================== --- firmware/FTM/fad_broadcast/FTM_fad_rs485_interface.vhd (revision 10418) +++ firmware/FTM/fad_broadcast/FTM_fad_rs485_interface.vhd (revision 10418) @@ -0,0 +1,126 @@ +-- +-- VHDL Architecture FACT_FAD_lib.rs485_interface.beha +-- +-- Created: +-- by - Benjamin Krumm.UNKNOWN (EEPC8) +-- at - 13:24:23 08.06.2010 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +-- +-- modified for FTM design by Q. Weitzel, 13 April 2011 +-- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +library ftm_definitions; +USE ftm_definitions.ftm_array_types.all; +USE ftm_definitions.ftm_constants.all; + +ENTITY FTM_fad_rs485_interface IS + GENERIC( + CLOCK_FREQUENCY : integer := INT_CLK_FREQUENCY_1; + BAUD_RATE : integer := FAD_RS485_BAUD_RATE + ); + PORT( + clk : IN std_logic; + -- RS485 + rx_d : IN std_logic; + rx_en : OUT std_logic; + tx_d : OUT std_logic; + tx_en : OUT std_logic; + -- FPGA + rx_data : OUT std_logic_vector (7 DOWNTO 0); + rx_busy : OUT std_logic := '0'; + rx_valid : OUT std_logic := '0'; + tx_data : IN std_logic_vector (7 DOWNTO 0); + tx_busy : OUT std_logic := '0'; + tx_start : IN std_logic + ); + +END FTM_fad_rs485_interface; + +ARCHITECTURE beha OF FTM_fad_rs485_interface IS + + signal flow_ctrl : std_logic := '0'; -- '0' -> RX enable, '1' -> TX enable + + --transmit + signal tx_start_f : std_logic := '0'; + signal tx_sr : std_logic_vector(10 downto 0) := (others => '1'); -- start bit, 8 data bits, 2 stop bits + signal tx_bitcnt : integer range 0 to 11 := 11; + signal tx_cnt : integer range 0 to ((CLOCK_FREQUENCY / BAUD_RATE) - 1); + + --receive + signal rx_dsr : std_logic_vector(3 downto 0) := (others => '1'); + signal rx_sr : std_logic_vector(7 downto 0) := (others => '0'); + signal rx_bitcnt : integer range 0 to 11 := 11; + signal rx_cnt : integer range 0 to ((CLOCK_FREQUENCY / BAUD_RATE) - 1); + +BEGIN + + -- Senden + tx_data_proc: process(clk) + begin + if rising_edge(clk) then + tx_start_f <= tx_start; + if (tx_start = '1' or tx_bitcnt < 11) then + flow_ctrl <= '1'; + else + flow_ctrl <= '0'; + end if; + if (tx_start = '1' and tx_start_f = '0') then -- steigende Flanke, los gehts + tx_cnt <= 0; -- Zaehler initialisieren + tx_bitcnt <= 0; + tx_sr <= "11" & tx_data & '0'; -- 2 x Stopbit, 8 Datenbits, Startbit, rechts gehts los + else + if (tx_cnt < (CLOCK_FREQUENCY/BAUD_RATE) - 1) then + tx_cnt <= tx_cnt + 1; + else -- naechstes Bit ausgeben + if (tx_bitcnt < 11) then + tx_cnt <= 0; + tx_bitcnt <= tx_bitcnt + 1; + tx_sr <= '1' & tx_sr(tx_sr'left downto 1); + end if; + end if; + end if; + end if; + end process; + + tx_en <= flow_ctrl; + tx_d <= tx_sr(0); -- LSB first + tx_busy <= '1' when (tx_start = '1' or tx_bitcnt < 11) else '0'; + + -- Empfangen + rx_data_proc: process(clk) + begin + if rising_edge(clk) then + rx_dsr <= rx_dsr(rx_dsr'left - 1 downto 0) & rx_d; + if (rx_bitcnt < 11) then -- Empfang laeuft + if (rx_cnt < (CLOCK_FREQUENCY/BAUD_RATE) - 1) then + rx_cnt <= rx_cnt + 1; + else + rx_cnt <= 0; + rx_bitcnt <= rx_bitcnt + 1; + if (rx_bitcnt < 9) then + rx_sr <= rx_dsr(rx_dsr'left - 1) & rx_sr(rx_sr'left downto 1); -- rechts schieben, weil LSB first + else + rx_valid <= '1'; + end if; + end if; + else + if (rx_dsr(3 downto 2) = "10") then -- warten auf Start bit + rx_valid <= '0'; + rx_cnt <= ((CLOCK_FREQUENCY / BAUD_RATE) - 1) / 2; + rx_bitcnt <= 0; + end if; + end if; + end if; + end process; + + rx_en <= flow_ctrl; + rx_data <= rx_sr; + rx_busy <= '1' when (rx_bitcnt < 11) else '0'; + +END ARCHITECTURE beha; Index: firmware/FTM/ftm_board.ucf =================================================================== --- firmware/FTM/ftm_board.ucf (revision 10366) +++ firmware/FTM/ftm_board.ucf (revision 10418) @@ -217,22 +217,22 @@ # Bus 2: Trigger-ID to FAD boards -# NET Bus2_Tx_En LOC = K2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -# NET Bus2_Rx_En LOC = K4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Bus2_Tx_En LOC = K2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Bus2_Rx_En LOC = K4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # # crate 0 -# NET Bus2_RxD_0 LOC = L4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -# NET Bus2_TxD_0 LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Bus2_RxD_0 LOC = L4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Bus2_TxD_0 LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # # crate 1 -# NET Bus2_RxD_1 LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -# NET Bus2_TxD_1 LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Bus2_RxD_1 LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Bus2_TxD_1 LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # # crate 2 -# NET Bus2_RxD_2 LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -# NET Bus2_TxD_2 LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Bus2_RxD_2 LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Bus2_TxD_2 LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # # crate 3 -# NET Bus2_RxD_3 LOC = U4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -# NET Bus2_TxD_3 LOC = U2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Bus2_RxD_3 LOC = U4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Bus2_TxD_3 LOC = U2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # Index: firmware/FTM/ftm_definitions.vhd =================================================================== --- firmware/FTM/ftm_definitions.vhd (revision 10366) +++ firmware/FTM/ftm_definitions.vhd (revision 10418) @@ -109,4 +109,8 @@ constant FTU_RS485_BLOCK_WIDTH : integer := 224; -- 28 byte protocol constant FTU_RS485_START_DELIM : std_logic_vector(7 downto 0) := "01000000"; -- start delimiter "@" + + --broadcast to FADs + constant FAD_RS485_BAUD_RATE : integer := 250000; -- bits / sec in our case + constant FAD_RS485_BLOCK_WIDTH : integer := 56; -- 7 byte trigger ID --CRC setup @@ -115,5 +119,5 @@ --DNA identifier for simulation - constant DNA_FOR_SIM : bit_vector := X"01710000E0000501"; + constant DNA_FOR_SIM : bit_vector := X"01710000F0000501"; -- Clock conditioner (LMK03000, National semiconductor) interface @@ -215,4 +219,6 @@ constant FTU_LIST_RAM_OFFSET : integer := 16#009#; constant FTU_LIST_RAM_ADDR_WIDTH : integer := 12; + + constant NO_OF_DD_RAM_REG : integer := 12; -- Static data block @@ -226,9 +232,10 @@ constant SD_FTU_ACTIVE_NUM : integer := 4; -- number of active FTU lists (cr0 to cr3) constant SD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1B4"; -- total size of static data block - + -- dynamic data block --constant DD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"010"; -- 7 + (40 * 12) = 0x1E7 --total size of dynamic data block - constant DD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1E7"; -- 7 + (40 * 12) = 0x1E7 --total size of dynamic data block - constant DD_BLOCK_SIZE_GENERAL : integer := 7; -- dynamic block size without FTU data + constant DD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1E7"; -- 7 + (40 * 12) = 0x1E7 --total size of dynamic data block + constant DD_BLOCK_SIZE_GENERAL : integer := 7; -- dynamic block size without FTU data + constant DYNAMIC_RAM_ADDR_WIDTH : integer := 12; -- addresses in static data block @@ -280,11 +287,11 @@ -- !!! to be defined !!! constant sd_block_default_array : sd_block_default_array_type := ( - --X"0080", -- SD_ADDR_general_settings -- general settings - X"0060", -- SD_ADDR_general_settings -- general settings + X"0080", -- SD_ADDR_general_settings -- general settings + --X"0010", -- SD_ADDR_general_settings -- general settings X"0000", -- SD_ADDR_led -- on-board status LEDs - --X"0400", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency - X"0001", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency + X"03FF", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency + --X"0001", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency --X"0001", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers - X"0420", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers + X"0001", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers X"0004", -- SD_ADDR_lp1_amplitude -- light pulser 1 amplitude X"0005", -- SD_ADDR_lp2_amplitude -- light pulser 2 amplitude @@ -295,6 +302,6 @@ X"0000", -- SD_ADDR_trigger_delay -- trigger delay X"0000", -- SD_ADDR_timemarker_delay -- timemarker delay - --X"0019", -- SD_ADDR_dead_time -- dead time, 8ns + 4x25ns = 108ns - X"0000", -- SD_ADDR_dead_time -- dead time, 8ns + 4x25ns = 108ns + X"0017", -- SD_ADDR_dead_time -- dead time, 8ns + 4x23ns = 100ns + --X"0000", -- SD_ADDR_dead_time -- dead time, 8ns + 4x25ns = 108ns X"0003", -- SD_ADDR_cc_R0_HI -- clock conditioner R0 bits 31...16 X"8000", -- SD_ADDR_cc_R0_LO -- clock conditioner R0 bits 15...0 @@ -334,5 +341,5 @@ --default values for active FTU lists constant sd_block_default_ftu_active_list : sd_block_default_ftu_active_list_type := ( - X"0000", + X"0001", X"0000", X"0000", Index: firmware/FTM/ftu_control/FTM_ftu_control.vhd =================================================================== --- firmware/FTM/ftu_control/FTM_ftu_control.vhd (revision 10366) +++ firmware/FTM/ftu_control/FTM_ftu_control.vhd (revision 10418) @@ -74,4 +74,11 @@ ftu_active_cr2 : in std_logic_vector (15 downto 0); ftu_active_cr3 : in std_logic_vector (15 downto 0); + + --error message interface to ethernet control + ftu_error_calls : out std_logic_vector (15 DOWNTO 0) := (others => '0'); + ftu_error_data : out std_logic_vector ((FTU_RS485_BLOCK_WIDTH - 1) downto 0) := (others => '0'); + ftu_error_send : out std_logic := '0'; + ftu_error_send_ack : in std_logic; + ftu_error_send_ready : in std_logic; -- communication with static (config) RAM @@ -146,4 +153,5 @@ signal FTU_enable_array_sig : FTU_enable_array_type; -- initialized in interpreter signal FTU_rate_array_sig : FTU_rate_array_type; -- initialized in interpreter + signal FTU_overflow_sig : std_logic_vector(7 downto 0); -- initialized in interpreter signal FTU_prescaling_sig : std_logic_vector(7 downto 0); -- initialized in interpreter signal FTU_crc_error_cnt_sig : std_logic_vector(7 downto 0); -- initialized in interpreter @@ -199,4 +207,5 @@ signal enable_crc_from_interpreter_sig : std_logic; signal crc_data_from_FSM_sig : std_logic_vector (FTU_RS485_BLOCK_WIDTH - 9 downto 0) := (others => '0'); + signal crc_data_from_FSM_sig_cp : std_logic_vector (FTU_RS485_BLOCK_WIDTH - 9 downto 0) := (others => '0'); signal crc_sig : std_logic_vector(CRC_POLYNOMIAL'length - 1 downto 0); signal crc_sig_inv : std_logic_vector(CRC_POLYNOMIAL'length - 1 downto 0); @@ -211,8 +220,13 @@ signal FTU_list_reg_cnt : integer range 0 to NO_OF_FTU_LIST_REG := 0; signal FTU_list_header_cnt : integer range 0 to FTU_LIST_RAM_OFFSET := 0; - + signal DD_RAM_reg_cnt : integer range 0 to NO_OF_DD_RAM_REG := 0; + -- counter to define timeout and number of retries signal timeout_cnt : integer range 0 to FTU_RS485_TIMEOUT := 0; signal retry_cnt : integer range 0 to FTU_RS485_NO_OF_RETRY := 0; + + --Zwischenrechnungen + signal FTU_cnt_offset_sig : integer range 0 to (NO_OF_DD_RAM_REG * NO_OF_FTUS_PER_CRATE) := 0; + signal crate_cnt_offset_sig : integer range 0 to (NO_OF_CRATES * NO_OF_FTUS_PER_CRATE * NO_OF_DD_RAM_REG) := 0; component FTM_ftu_rs485_interface @@ -260,4 +274,5 @@ FTU_enable_array : OUT FTU_enable_array_type; FTU_rate_array : OUT FTU_rate_array_type; + FTU_overflow : OUT std_logic_vector(7 downto 0); FTU_prescaling : OUT std_logic_vector(7 downto 0); FTU_crc_error_cnt : OUT std_logic_vector(7 downto 0); @@ -285,5 +300,7 @@ type FTM_ftu_rs485_control_StateType is (INIT, IDLE, ACTIVE_LIST, READ_CONFIG, TRANSMIT_CONFIG, PING, PING_END, FTU_LIST, + SEND_ERROR_1, SEND_ERROR_2, RATES, RATES_1, RATES_2, RATES_3, + DD_RAM, DD_RAM_1, DD_RAM_2, DD_RAM_3, READ_CONFIG_1, READ_CONFIG_2, READ_CONFIG_3, TRANSMIT_CONFIG_1, TRANSMIT_CONFIG_2, TRANSMIT_CONFIG_3, @@ -291,8 +308,9 @@ FTU_LIST_1, FTU_LIST_2, FTU_LIST_3); signal FTM_ftu_rs485_control_State : FTM_ftu_rs485_control_StateType; + signal after_error_State : FTM_ftu_rs485_control_StateType; begin - Inst_FTM_fTU_rs485_interface_0 : FTM_ftu_rs485_interface -- crate 0 + Inst_FTM_ftu_rs485_interface_0 : FTM_ftu_rs485_interface -- crate 0 port map( clk => clk_50MHz, @@ -311,5 +329,5 @@ ); - Inst_FTM_fTU_rs485_interface_1 : FTM_ftu_rs485_interface -- crate 1 + Inst_FTM_ftu_rs485_interface_1 : FTM_ftu_rs485_interface -- crate 1 port map( clk => clk_50MHz, @@ -328,5 +346,5 @@ ); - Inst_FTM_fTU_rs485_interface_2 : FTM_ftu_rs485_interface -- crate 2 + Inst_FTM_ftu_rs485_interface_2 : FTM_ftu_rs485_interface -- crate 2 port map( clk => clk_50MHz, @@ -345,5 +363,5 @@ ); - Inst_FTM_fTU_rs485_interface_3 : FTM_ftu_rs485_interface -- crate 3 + Inst_FTM_ftu_rs485_interface_3 : FTM_ftu_rs485_interface -- crate 3 port map( clk => clk_50MHz, @@ -387,4 +405,5 @@ FTU_enable_array => FTU_enable_array_sig, FTU_rate_array => FTU_rate_array_sig, + FTU_overflow => FTU_overflow_sig, FTU_prescaling => FTU_prescaling_sig, FTU_crc_error_cnt => FTU_crc_error_cnt_sig, @@ -602,4 +621,5 @@ when TRANSMIT_CONFIG_1 => -- wait one cycle for CRC calculation enable_crc_from_FSM_sig <= '0'; + crc_data_from_FSM_sig_cp <= crc_data_from_FSM_sig; FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG_2; @@ -614,4 +634,5 @@ elsif (frame_cnt = 27) then frame_cnt <= frame_cnt + 1; + ftu_error_data <= crc_sig & crc_data_from_FSM_sig_cp; tx_data_sig <= crc_sig; tx_start_sig <= '1'; @@ -633,5 +654,11 @@ retry_cnt <= 0; sel_crc_input_source_sig <= '0'; - FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG; + if (retry_cnt = 0) then -- no errors + FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG; + else -- send error message and move to next command; + ftu_error_calls <= conv_std_logic_vector((retry_cnt + 1), 16); + after_error_State <= TRANSMIT_CONFIG; + FTM_ftu_rs485_control_State <= SEND_ERROR_1; + end if; else if (timeout_cnt < FTU_RS485_TIMEOUT) then @@ -649,10 +676,24 @@ else retry_cnt <= 0; - FTU_command_cnt <= FTU_command_cnt; -- move to next command; - FTM_ftu_rs485_control_State <= TRANSMIT_CONFIG; + FTU_command_cnt <= FTU_command_cnt; -- send error message and move to next command + ftu_error_calls <= (others => '0'); + after_error_State <= TRANSMIT_CONFIG; + FTM_ftu_rs485_control_State <= SEND_ERROR_1; end if; end if; end if; + when SEND_ERROR_1 => -- send an error message + ftu_error_send <= '1'; + if (ftu_error_send_ack = '1') then + ftu_error_send <= '0'; + FTM_ftu_rs485_control_State <= SEND_ERROR_2; + end if; + + when SEND_ERROR_2 => + if (ftu_error_send_ready = '1') then + FTM_ftu_rs485_control_State <= after_error_state; + end if; + when PING => -- ping all FTUs rec_reset_sig <= '0'; @@ -759,5 +800,6 @@ write_FTUlist_RAM <= '1'; addr_FTUlist_RAM <= conv_std_logic_vector(FTU_LIST_RAM_OFFSET + - (FTU_cnt - 1)* NO_OF_FTU_LIST_REG + + (crate_cnt * NO_OF_FTUS_PER_CRATE * NO_OF_FTU_LIST_REG) + + ((FTU_cnt - 1) * NO_OF_FTU_LIST_REG) + (FTU_list_reg_cnt - 1), FTU_LIST_RAM_ADDR_WIDTH); if (retry_cnt < FTU_RS485_NO_OF_RETRY) then @@ -871,4 +913,5 @@ when RATES_1 => -- wait one cycle for CRC calculation enable_crc_from_FSM_sig <= '0'; + crc_data_from_FSM_sig_cp <= crc_data_from_FSM_sig; FTM_ftu_rs485_control_State <= RATES_2; @@ -883,4 +926,5 @@ elsif (frame_cnt = 27) then frame_cnt <= frame_cnt + 1; + ftu_error_data <= crc_sig & crc_data_from_FSM_sig_cp; tx_data_sig <= crc_sig; tx_start_sig <= '1'; @@ -901,5 +945,12 @@ timeout_cnt <= 0; sel_crc_input_source_sig <= '0'; - FTM_ftu_rs485_control_State <= RATES; + --FTM_ftu_rs485_control_State <= RATES; + if (retry_cnt = 0) then -- no errors + FTM_ftu_rs485_control_State <= DD_RAM; + else -- send error message and move to next command; + ftu_error_calls <= conv_std_logic_vector((retry_cnt + 1), 16); + after_error_State <= DD_RAM; + FTM_ftu_rs485_control_State <= SEND_ERROR_1; + end if; else if (timeout_cnt < FTU_RS485_TIMEOUT) then @@ -916,9 +967,89 @@ FTM_ftu_rs485_control_State <= RATES; else - retry_cnt <= 0; + --retry_cnt <= 0; FTU_cnt <= FTU_cnt; -- move on - FTM_ftu_rs485_control_State <= RATES; + ftu_error_calls <= (others => '0'); + after_error_State <= DD_RAM; + FTM_ftu_rs485_control_State <= SEND_ERROR_1; end if; end if; + end if; + + when DD_RAM => -- write rates of actual FTU to DD RAM + rec_reset_sig <= '0'; + if (DD_RAM_reg_cnt < NO_OF_DD_RAM_REG) then + DD_RAM_reg_cnt <= DD_RAM_reg_cnt + 1; + FTU_cnt_offset_sig <= ((FTU_cnt - 1) * NO_OF_DD_RAM_REG); + crate_cnt_offset_sig <= (crate_cnt * NO_OF_FTUS_PER_CRATE * NO_OF_DD_RAM_REG); + FTM_ftu_rs485_control_State <= DD_RAM_1; + else + DD_RAM_reg_cnt <= 0; + retry_cnt <= 0; + FTM_ftu_rs485_control_State <= RATES; + end if; + + when DD_RAM_1 => + if (dynamic_RAM_busy = '0') then + write_dynamic_RAM <= '1'; + addr_dynamic_RAM <= conv_std_logic_vector(DD_BLOCK_SIZE_GENERAL + + crate_cnt_offset_sig + + --(crate_cnt * NO_OF_FTUS_PER_CRATE * NO_OF_DD_RAM_REG) + + --((FTU_cnt - 1) * NO_OF_DD_RAM_REG) + + FTU_cnt_offset_sig + + (DD_RAM_reg_cnt - 1), DYNAMIC_RAM_ADDR_WIDTH); + if ( (retry_cnt < FTU_RS485_NO_OF_RETRY) + and (FTU_cnt_offset_sig < (NO_OF_FTUS_PER_CRATE * NO_OF_DD_RAM_REG)) + and (crate_cnt_offset_sig < (NO_OF_CRATES * NO_OF_FTUS_PER_CRATE * NO_OF_DD_RAM_REG)) ) then + if ((DD_RAM_reg_cnt - 1) = 0) then + data_dynamic_RAM <= FTU_rate_array_sig(0)(31 downto 16); + elsif ((DD_RAM_reg_cnt - 1) = 1) then + data_dynamic_RAM <= FTU_rate_array_sig(0)(15 downto 0); + elsif ((DD_RAM_reg_cnt - 1) = 2) then + data_dynamic_RAM <= FTU_rate_array_sig(1)(31 downto 16); + elsif ((DD_RAM_reg_cnt - 1) = 3) then + data_dynamic_RAM <= FTU_rate_array_sig(1)(15 downto 0); + elsif ((DD_RAM_reg_cnt - 1) = 4) then + data_dynamic_RAM <= FTU_rate_array_sig(2)(31 downto 16); + elsif ((DD_RAM_reg_cnt - 1) = 5) then + data_dynamic_RAM <= FTU_rate_array_sig(2)(15 downto 0); + elsif ((DD_RAM_reg_cnt - 1) = 6) then + data_dynamic_RAM <= FTU_rate_array_sig(3)(31 downto 16); + elsif ((DD_RAM_reg_cnt - 1) = 7) then + data_dynamic_RAM <= FTU_rate_array_sig(3)(15 downto 0); + elsif ((DD_RAM_reg_cnt - 1) = 8) then + data_dynamic_RAM <= FTU_rate_array_sig(4)(31 downto 16); + elsif ((DD_RAM_reg_cnt - 1) = 9) then + data_dynamic_RAM <= FTU_rate_array_sig(4)(15 downto 0); + elsif ((DD_RAM_reg_cnt - 1) = 10) then + data_dynamic_RAM <= "00000000" & FTU_overflow_sig; + elsif ((DD_RAM_reg_cnt - 1) = 11) then + data_dynamic_RAM <= "00000000" & FTU_crc_error_cnt_sig; +-- elsif ((DD_RAM_reg_cnt - 1) = 10) then +-- data_dynamic_RAM <= "0000" & conv_std_logic_vector(DD_BLOCK_SIZE_GENERAL + +-- --((FTU_cnt - 1) * NO_OF_DD_RAM_REG) + +-- FTU_cnt_offset_sig + +-- (DD_RAM_reg_cnt - 1), DYNAMIC_RAM_ADDR_WIDTH); +-- elsif ((DD_RAM_reg_cnt - 1) = 11) then +-- --data_dynamic_RAM <= "0000" & conv_std_logic_vector(FTU_cnt_offset_sig, DYNAMIC_RAM_ADDR_WIDTH); +-- data_dynamic_RAM <= "0000" & conv_std_logic_vector(DD_BLOCK_SIZE_GENERAL + +-- --((FTU_cnt - 1) * NO_OF_DD_RAM_REG) + +-- FTU_cnt_offset_sig + +-- (DD_RAM_reg_cnt - 1), DYNAMIC_RAM_ADDR_WIDTH); + end if; + else + data_dynamic_RAM <= (others => '0'); + end if; + FTM_ftu_rs485_control_State <= DD_RAM_2; + end if; + + when DD_RAM_2 => + if (dynamic_RAM_started = '1') then + write_dynamic_RAM <= '0'; + FTM_ftu_rs485_control_State <= DD_RAM_3; + end if; + + when DD_RAM_3 => + if (dynamic_RAM_ready = '1') then + FTM_ftu_rs485_control_State <= DD_RAM; end if; Index: firmware/FTM/ftu_control/FTM_ftu_rs485_interpreter.vhd =================================================================== --- firmware/FTM/ftu_control/FTM_ftu_rs485_interpreter.vhd (revision 10366) +++ firmware/FTM/ftu_control/FTM_ftu_rs485_interpreter.vhd (revision 10418) @@ -47,4 +47,5 @@ FTU_enable_array : OUT FTU_enable_array_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0')); FTU_rate_array : OUT FTU_rate_array_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0')); + FTU_overflow : OUT std_logic_vector(7 downto 0) := (others => '0'); FTU_prescaling : OUT std_logic_vector(7 downto 0) := (others => '0'); FTU_crc_error_cnt : OUT std_logic_vector(7 downto 0) := (others => '0'); @@ -144,4 +145,5 @@ data_block(199 downto 168) ); + FTU_overflow <= data_block(207 downto 200); FTU_crc_error_cnt <= data_block(215 downto 208); FTM_ftu_rs485_interpreter_State <= WAIT_FOR_DATA; @@ -165,4 +167,5 @@ elsif (data_block(39 downto 32) = "00000111") then -- read counter mode FTU_prescaling <= data_block(47 downto 40); + FTU_overflow <= data_block(55 downto 48); FTM_ftu_rs485_interpreter_State <= WAIT_FOR_DATA; elsif (data_block(39 downto 32) = "00000101") then -- ping pong Index: firmware/FTM/trigger/kernel/trigger_generator/trigger_generator.vhd =================================================================== --- firmware/FTM/trigger/kernel/trigger_generator/trigger_generator.vhd (revision 10366) +++ firmware/FTM/trigger/kernel/trigger_generator/trigger_generator.vhd (revision 10418) @@ -13,4 +13,8 @@ -- 14/03/2011 JGi 110314a Description -- 13/04/2011 JGi 110413a Update trigger enable management +-- 15/04/2011 JGi 110415a Update LP1 "N-out-of-40" logic detection +-- in order to allow user to reset it by +-- disabling LP1 pulse as trigger source if the +-- N is never reached and system is locked --======================================================================================= -- Library Definition @@ -332,5 +336,7 @@ general_settings(4) = '1' then v_reg.wait_for_calib := '1'; - elsif i_reg.enable_trigger = '0' then + -- If trigger is processed or disabled by user, reset detection logic to avoid + -- remaining in locked state + elsif i_reg.enable_trigger = '0' or general_settings(4) = '0' then v_reg.wait_for_calib := '0'; end if;