Index: /firmware/FTM/FTM_central_control.vhd =================================================================== --- /firmware/FTM/FTM_central_control.vhd (revision 10440) +++ /firmware/FTM/FTM_central_control.vhd (revision 10441) @@ -68,5 +68,17 @@ config_trigger_done : in std_logic; dna_start : out std_logic := '0'; - dna_ready : in std_logic + dna_ready : in std_logic; + crate_reset : IN std_logic; + crate_reset_ack : OUT std_logic := '1'; + crate_reset_param : IN std_logic_vector (15 DOWNTO 0); + start_run : IN std_logic; + start_run_ack : OUT std_logic := '0'; + stop_run : IN std_logic; + stop_run_ack : OUT std_logic := '0'; + current_cc_state : OUT std_logic_vector (15 DOWNTO 0) := X"FFFF"; + start_run_param : IN std_logic_vector (15 DOWNTO 0); + start_run_num_events : IN std_logic_vector (31 DOWNTO 0); + trigger_start : out std_logic := '0'; + trigger_stop : out std_logic := '1' ); end FTM_central_control; @@ -86,4 +98,5 @@ type state_central_proc_type is (CP_INIT, CP_INIT_DNA, + CP_RUNNING, CP_RUNNING_01, CP_RUNNING_02, CP_CONFIG_ACK, CP_CONFIG_START, CP_CONFIG, CP_CONFIG_01, CP_CONFIG_CC, CP_CONFIG_CC_01, @@ -94,4 +107,7 @@ CP_SEND_START, CP_SEND_END); signal state_central_proc : state_central_proc_type := CP_INIT; + + signal after_rates_state : state_central_proc_type := CP_IDLE; + signal after_ping_state : state_central_proc_type := CP_IDLE; begin @@ -189,6 +205,10 @@ when CP_IDLE => + current_cc_state <= FTM_STATE_IDLE; + stop_run_ack <= '1'; + start_run_ack <= '0'; if (new_config = '1') then config_started <= '1'; + start_run_ack <= '1'; state_central_proc <= CP_CONFIG_START; elsif (ping_ftu_start = '1') then @@ -198,4 +218,5 @@ ping_ftu_started <= '1'; ping_ftu_ready <= '0'; + after_ping_state <= CP_IDLE; state_central_proc <= CP_PING; end if; @@ -205,7 +226,63 @@ --rates_ftu <= '1'; --state_central_proc <= CP_READ_RATES; + after_rates_state <= CP_IDLE; state_central_proc <= CP_START_RATES; - end if; - + elsif (start_run = '1') then + start_run_ack <= '1'; + if (start_run_param = PAR_START_RUN) then + state_central_proc <= CP_RUNNING; + end if; + end if; + + when CP_RUNNING => + current_cc_state <= FTM_STATE_RUN; + if (start_run = '0') then + start_run_ack <= '0'; + stop_run_ack <= '0'; + state_central_proc <= CP_RUNNING_01; + end if; + + when CP_RUNNING_01 => + current_cc_state <= FTM_STATE_RUN; + start_run_ack <= '1'; + trigger_start <= '1'; + trigger_stop <= '0'; + if (new_config = '1') then + config_started <= '1'; + state_central_proc <= CP_CONFIG_ACK; + elsif (ping_ftu_start = '1') then + ping_ftu_start_ftu <= '1'; + if (ping_ftu_started_ftu = '1') then + ping_ftu_start_ftu <= '0'; + ping_ftu_started <= '1'; + ping_ftu_ready <= '0'; + after_ping_state <= CP_RUNNING_01; + state_central_proc <= CP_PING; + end if; + elsif (new_period_sig = '1') then + new_period_ack_sig <= '1'; + --rates_ftu <= '1'; + --state_central_proc <= CP_READ_RATES; + after_rates_state <= CP_RUNNING_01; + state_central_proc <= CP_START_RATES; + elsif (stop_run = '1') then + stop_run_ack <= '1'; + trigger_start <= '0'; + trigger_stop <= '1'; + state_central_proc <= CP_RUNNING_02; + end if; + + when CP_RUNNING_02 => + if (stop_run = '0') then + stop_run_ack <= '0'; + state_central_proc <= CP_IDLE; + end if; + + when CP_CONFIG_ACK => + if (config_started_ack = '1') then + config_started <= '0'; + state_central_proc <= CP_RUNNING_01; + end if; + when CP_PING => if (ping_ftu_ready_ftu = '1') then @@ -213,5 +290,6 @@ ping_ftu_started <= '0'; ping_ftu_ready <= '1'; - state_central_proc <= CP_IDLE; + --state_central_proc <= CP_IDLE; + state_central_proc <= after_ping_state; end if; end if; @@ -237,5 +315,9 @@ if (rates_ready_ftu = '1') then dd_block_ready_ftu <= '1'; - state_central_proc <= CP_SEND_START; + if ( (start_run = '1') or (stop_run = '1') ) then + state_central_proc <= after_rates_state; + else + state_central_proc <= CP_SEND_START; + end if; end if; @@ -249,5 +331,6 @@ when CP_SEND_END => if (dd_send_ready = '1') then - state_central_proc <= CP_IDLE; + --state_central_proc <= CP_IDLE; + state_central_proc <= after_rates_state; end if; Index: /firmware/FTM/FTM_top.vhd =================================================================== --- /firmware/FTM/FTM_top.vhd (revision 10440) +++ /firmware/FTM/FTM_top.vhd (revision 10441) @@ -376,4 +376,28 @@ signal led_sig : std_logic_vector(7 downto 0) := (others => '0'); + + signal get_ot_counter_sig : std_logic; + signal get_ot_counter_started_sig : std_logic; + signal get_ot_counter_ready_sig : std_logic; + signal on_time_counter_sig : std_logic_vector(47 downto 0); + + signal get_ts_counter_sig : std_logic; + signal get_ts_counter_started_sig : std_logic; + signal get_ts_counter_ready_sig : std_logic; + signal timestamp_counter_sig : std_logic_vector(47 downto 0); + + signal crate_reset_sig : std_logic; + signal crate_reset_ack_sig : std_logic; + signal crate_reset_param_sig : std_logic_vector (15 DOWNTO 0); + signal start_run_sig : std_logic; + signal start_run_ack_sig : std_logic; + signal stop_run_sig : std_logic; + signal stop_run_ack_sig : std_logic; + signal current_cc_state_sig : std_logic_vector (15 DOWNTO 0); + signal start_run_param_sig : std_logic_vector (15 DOWNTO 0); + signal start_run_num_events_sig : std_logic_vector (31 DOWNTO 0); + + signal trigger_start_sig : std_logic; + signal trigger_stop_sig : std_logic; -- component FTM_clk_gen @@ -525,5 +549,17 @@ config_trigger_done : in std_logic; dna_start : out std_logic; - dna_ready : in std_logic + dna_ready : in std_logic; + crate_reset : IN std_logic; + crate_reset_ack : OUT std_logic; + crate_reset_param : IN std_logic_vector (15 DOWNTO 0); + start_run : IN std_logic; + start_run_ack : OUT std_logic; + stop_run : IN std_logic; + stop_run_ack : OUT std_logic; + current_cc_state : OUT std_logic_vector (15 DOWNTO 0); + start_run_param : IN std_logic_vector (15 DOWNTO 0); + start_run_num_events : IN std_logic_vector (31 DOWNTO 0); + trigger_start : out std_logic; + trigger_stop : out std_logic ); end component; @@ -683,8 +719,40 @@ trigger_counter : IN std_logic_vector (31 DOWNTO 0) := (others => '0'); trigger_counter_read : OUT std_logic := '0'; - trigger_counter_valid : IN std_logic + trigger_counter_valid : IN std_logic; + --newest stuff + board_id : IN std_logic_vector (63 DOWNTO 0); + get_ts_counter : OUT std_logic := '0'; + get_ts_counter_ready : IN std_logic; + get_ts_counter_started : IN std_logic; + timestamp_counter : IN std_logic_vector (47 DOWNTO 0); + get_ot_counter : OUT std_logic := '0'; + get_ot_counter_ready : IN std_logic; + get_ot_counter_started : IN std_logic; + on_time_counter : IN std_logic_vector (47 DOWNTO 0); + temp_sensor_array : IN sensor_array_type; + temp_sensor_ready : IN std_logic; + crate_reset : OUT std_logic := '0'; + crate_reset_ack : IN std_logic; + crate_reset_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + start_run : OUT std_logic := '0'; + start_run_ack : IN std_logic; + stop_run : OUT std_logic := '0'; + stop_run_ack : IN std_logic; + current_cc_state : IN std_logic_vector (15 DOWNTO 0); + start_run_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + start_run_num_events : OUT std_logic_vector (31 DOWNTO 0) := (others => '0') ); end component; - + + component counter_dummy IS + PORT( + clk : IN std_logic; + get_counter : IN std_logic; + get_counter_started : OUT std_logic := '0'; + get_counter_ready : OUT std_logic := '0'; + counter : OUT std_logic_vector (47 DOWNTO 0) := (others => '0') + ); + end component; + begin @@ -769,6 +837,6 @@ FAD_busy_3 => Busy3, --crate 3 --control signals from e.g. main control - start_run => '1', --enable trigger output - stop_run => '0', --disable trigger output + start_run => trigger_start_sig, --enable trigger output + stop_run => trigger_stop_sig, --disable trigger output new_config => config_trigger_sig, --settings register (see FTM Firmware Specifications) @@ -862,5 +930,17 @@ config_trigger_done => config_trigger_done_sig, dna_start => dna_start_sig, - dna_ready => dna_ready_sig + dna_ready => dna_ready_sig, + crate_reset => crate_reset_sig, + crate_reset_ack => crate_reset_ack_sig, + crate_reset_param => crate_reset_param_sig, + start_run => start_run_sig, + start_run_ack => start_run_ack_sig, + stop_run => stop_run_sig, + stop_run_ack => stop_run_ack_sig, + current_cc_state => current_cc_state_sig, + start_run_param => start_run_param_sig, + start_run_num_events => start_run_num_events_sig, + trigger_start => trigger_start_sig, + trigger_stop => trigger_stop_sig ); @@ -1017,7 +1097,47 @@ trigger_counter => trigger_counter_sig, trigger_counter_read => trigger_counter_read_sig, - trigger_counter_valid => trigger_counter_valid_sig - ); - + trigger_counter_valid => trigger_counter_valid_sig, + --newest stuff + board_id => dna_sig, + get_ts_counter => get_ts_counter_sig, + get_ts_counter_ready => get_ts_counter_ready_sig, + get_ts_counter_started => get_ts_counter_started_sig, + timestamp_counter => timestamp_counter_sig, + get_ot_counter => get_ot_counter_sig, + get_ot_counter_ready => get_ot_counter_ready_sig, + get_ot_counter_started => get_ot_counter_started_sig, + on_time_counter => on_time_counter_sig, + temp_sensor_array => (35, 45, 55, 65), + temp_sensor_ready => '1', + crate_reset => crate_reset_sig, + crate_reset_ack => crate_reset_ack_sig, + crate_reset_param => crate_reset_param_sig, + start_run => start_run_sig, + start_run_ack => start_run_ack_sig, + stop_run => stop_run_sig, + stop_run_ack => stop_run_ack_sig, + current_cc_state => current_cc_state_sig, + start_run_param => start_run_param_sig, + start_run_num_events => start_run_num_events_sig + ); + + Inst_counter_dummy_ts : counter_dummy + port map( + clk => clk_50M_sig, + get_counter => get_ts_counter_sig, + get_counter_started => get_ts_counter_started_sig, + get_counter_ready => get_ts_counter_ready_sig, + counter => timestamp_counter_sig + ); + + Inst_counter_dummy_ot : counter_dummy + port map( + clk => clk_50M_sig, + get_counter => get_ot_counter_sig, + get_counter_started => get_ot_counter_started_sig, + get_counter_ready => get_ot_counter_ready_sig, + counter => on_time_counter_sig + ); + LED_red <= led_sig(3 downto 0); LED_ye <= led_sig(5 downto 4); Index: /firmware/FTM/ethernet/dd_write_general_modul_beha.vhd =================================================================== --- /firmware/FTM/ethernet/dd_write_general_modul_beha.vhd (revision 10440) +++ /firmware/FTM/ethernet/dd_write_general_modul_beha.vhd (revision 10441) @@ -8,12 +8,9 @@ -- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) -- - LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE IEEE.STD_LOGIC_UNSIGNED.all; --- LIBRARY FACT_FTM_lib; --- USE FACT_FTM_lib.ftm_array_types.all; --- USE FACT_FTM_lib.ftm_constants.all; + library ftm_definitions; USE ftm_definitions.ftm_array_types.all; @@ -26,10 +23,16 @@ dd_write_general_started : OUT std_logic := '0'; dd_write_general_ready : OUT std_logic := '0'; - dd_busy : IN std_logic; - dd_write : OUT std_logic := '0'; - dd_started : IN std_logic; - dd_ready : IN std_logic; - dd_addr : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); - dd_data : OUT std_logic_vector (15 DOWNTO 0) := (others => '0') + dd_busy : IN std_logic; + dd_write : OUT std_logic := '0'; + dd_started : IN std_logic; + dd_ready : IN std_logic; + dd_addr : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); + dd_data : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + get_ot_counter : OUT std_logic := '0'; + get_ot_counter_started : IN std_logic; + get_ot_counter_ready : IN std_logic; + on_time_counter : IN std_logic_vector (47 DOWNTO 0); + temp_sensor_ready : IN std_logic; + temp_sensor_array : IN sensor_array_type ); END ENTITY dd_write_general_modul; @@ -38,5 +41,7 @@ ARCHITECTURE beha OF dd_write_general_modul IS - type state_write_general_proc_type is (WGP_INIT, WGP_CONFIG, WGP_IDLE, WGP_WRITE_COUNTER_01, WGP_WRITE_COUNTER_02, WGP_WRITE_COUNTER_03, + type state_write_general_proc_type is (WGP_INIT, WGP_CONFIG, WGP_IDLE, + WGP_OT_CNT, WGP_OT_CNT_END, + WGP_WRITE_COUNTER_00, WGP_WRITE_COUNTER_01, WGP_WRITE_COUNTER_02, WGP_WRITE_COUNTER_03, WGP_WRITE_TEMP_01, WGP_WRITE_TEMP_02, WGP_WRITE_TEMP_03, WGP_WRITE_TEMP_04, WGP_WRITE_READY, WRITE_TO_DD_ADDR); type state_write_dd_type is (WRITE_DD_START, WRITE_DD_WAIT, WRITE_DD_END); @@ -49,9 +54,4 @@ signal local_dd_data : std_logic_vector (15 DOWNTO 0) := (others => '0'); - signal on_time_counter : std_logic_vector (47 DOWNTO 0) := X"333322221111"; - signal temp_sensor_0 : std_logic_vector (15 DOWNTO 0) := X"00FF"; - signal temp_sensor_1 : std_logic_vector (15 DOWNTO 0) := X"11FF"; - signal temp_sensor_2 : std_logic_vector (15 DOWNTO 0) := X"22FF"; - signal temp_sensor_3 : std_logic_vector (15 DOWNTO 0) := X"33FF"; BEGIN @@ -71,9 +71,27 @@ dd_write_general_started <= '1'; dd_write_general_ready <= '0'; - state_write_general_proc <= WGP_WRITE_COUNTER_01; + get_ot_counter <= '1'; + state_write_general_proc <= WGP_OT_CNT; end if; + when WGP_OT_CNT => + if (get_ot_counter_started = '1') then + get_ot_counter <= '0'; + state_write_general_proc <= WGP_OT_CNT_END; + end if; + + when WGP_OT_CNT_END => + if (get_ot_counter_ready = '1') then + state_write_general_proc <= WGP_WRITE_COUNTER_00; + end if; + + when WGP_WRITE_COUNTER_00 => + local_dd_addr <= X"000"; + local_dd_data <= X"0000"; + next_state_dd <= WGP_WRITE_COUNTER_01; + state_write_general_proc <= WRITE_TO_DD_ADDR; + when WGP_WRITE_COUNTER_01 => - local_dd_addr <= X"000"; + local_dd_addr <= X"001"; local_dd_data <= on_time_counter (47 DOWNTO 32); next_state_dd <= WGP_WRITE_COUNTER_02; @@ -81,5 +99,5 @@ when WGP_WRITE_COUNTER_02 => - local_dd_addr <= X"001"; + local_dd_addr <= X"002"; local_dd_data <= on_time_counter (31 DOWNTO 16); next_state_dd <= WGP_WRITE_COUNTER_03; @@ -87,5 +105,5 @@ when WGP_WRITE_COUNTER_03 => - local_dd_addr <= X"002"; + local_dd_addr <= X"003"; local_dd_data <= on_time_counter (15 DOWNTO 0); next_state_dd <= WGP_WRITE_TEMP_01; @@ -93,26 +111,34 @@ when WGP_WRITE_TEMP_01 => - local_dd_addr <= X"003"; - local_dd_data <= temp_sensor_0; - next_state_dd <= WGP_WRITE_TEMP_02; - state_write_general_proc <= WRITE_TO_DD_ADDR; + if (temp_sensor_ready = '1') then + local_dd_addr <= X"004"; + local_dd_data <= conv_std_logic_vector (temp_sensor_array (0), 16); + next_state_dd <= WGP_WRITE_TEMP_02; + state_write_general_proc <= WRITE_TO_DD_ADDR; + end if; when WGP_WRITE_TEMP_02 => - local_dd_addr <= X"004"; - local_dd_data <= temp_sensor_1; - next_state_dd <= WGP_WRITE_TEMP_03; - state_write_general_proc <= WRITE_TO_DD_ADDR; + if (temp_sensor_ready = '1') then + local_dd_addr <= X"005"; + local_dd_data <= conv_std_logic_vector (temp_sensor_array (1), 16); + next_state_dd <= WGP_WRITE_TEMP_03; + state_write_general_proc <= WRITE_TO_DD_ADDR; + end if; when WGP_WRITE_TEMP_03 => - local_dd_addr <= X"005"; - local_dd_data <= temp_sensor_2; - next_state_dd <= WGP_WRITE_TEMP_04; - state_write_general_proc <= WRITE_TO_DD_ADDR; + if (temp_sensor_ready = '1') then + local_dd_addr <= X"006"; + local_dd_data <= conv_std_logic_vector (temp_sensor_array (2), 16); + next_state_dd <= WGP_WRITE_TEMP_04; + state_write_general_proc <= WRITE_TO_DD_ADDR; + end if; when WGP_WRITE_TEMP_04 => - local_dd_addr <= X"006"; - local_dd_data <= temp_sensor_3; - next_state_dd <= WGP_WRITE_READY; - state_write_general_proc <= WRITE_TO_DD_ADDR; + if (temp_sensor_ready = '1') then + local_dd_addr <= X"007"; + local_dd_data <= conv_std_logic_vector (temp_sensor_array (3), 16); + next_state_dd <= WGP_WRITE_READY; + state_write_general_proc <= WRITE_TO_DD_ADDR; + end if; when WGP_WRITE_READY => @@ -150,2 +176,3 @@ END ARCHITECTURE beha; + Index: /firmware/FTM/ethernet/ethernet_modul_beha.vhd =================================================================== --- /firmware/FTM/ethernet/ethernet_modul_beha.vhd (revision 10440) +++ /firmware/FTM/ethernet/ethernet_modul_beha.vhd (revision 10441) @@ -3,5 +3,5 @@ -- Created: -- by - kai.users (tpkw.local.priv) --- at - 10:39:41 04/13/11 +-- at - 11:20:56 04/20/11 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) @@ -10,9 +10,8 @@ USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ---LIBRARY FACT_FTM_lib; + library ftm_definitions; USE ftm_definitions.ftm_array_types.all; USE ftm_definitions.ftm_constants.all; - ENTITY ethernet_modul IS @@ -70,4 +69,5 @@ fl_addr_ftu : IN std_logic_vector (11 DOWNTO 0); fl_data_in_ftu : IN std_logic_vector (15 DOWNTO 0) := (others => '0'); + -- ping_ftu_start : OUT std_logic := '0'; ping_ftu_started : IN std_logic; @@ -89,4 +89,5 @@ ftu_error_calls : IN std_logic_vector (15 DOWNTO 0); ftu_error_data : IN std_logic_vector (223 DOWNTO 0); -- (28 * 8) - 1 + -- ftu_error_send : IN std_logic; ftu_error_send_ack : OUT std_logic := '1'; @@ -95,5 +96,27 @@ trigger_counter : IN std_logic_vector (31 DOWNTO 0) := (others => '0'); trigger_counter_read : OUT std_logic := '0'; - trigger_counter_valid : IN std_logic + trigger_counter_valid : IN std_logic; + board_id : IN std_logic_vector (63 DOWNTO 0); + get_ts_counter : OUT std_logic := '0'; + get_ts_counter_ready : IN std_logic; + get_ts_counter_started : IN std_logic; + timestamp_counter : IN std_logic_vector (47 DOWNTO 0); + get_ot_counter : OUT std_logic := '0'; + get_ot_counter_ready : IN std_logic; + get_ot_counter_started : IN std_logic; + on_time_counter : IN std_logic_vector (47 DOWNTO 0); + temp_sensor_array : IN sensor_array_type; + temp_sensor_ready : IN std_logic; + crate_reset : OUT std_logic := '0'; + crate_reset_ack : IN std_logic; + crate_reset_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + -- + start_run : OUT std_logic := '0'; + start_run_ack : IN std_logic; + stop_run : OUT std_logic := '0'; + stop_run_ack : IN std_logic; + current_cc_state : IN std_logic_vector (15 DOWNTO 0); + start_run_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + start_run_num_events : OUT std_logic_vector (31 DOWNTO 0) := (others => '0') ); @@ -159,4 +182,5 @@ SIGNAL header_timestamp_counter : std_logic_vector(47 DOWNTO 0); SIGNAL header_trigger_counter : std_logic_vector(31 DOWNTO 0); + SIGNAL header_current_state : std_logic_vector(15 DOWNTO 0) := (others => '0'); -- Implicit buffer signal declarations @@ -268,5 +292,11 @@ dd_ready : IN std_logic ; dd_addr : OUT std_logic_vector (11 DOWNTO 0) := (others => '0'); - dd_data : OUT std_logic_vector (15 DOWNTO 0) := (others => '0') + dd_data : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + get_ot_counter : OUT std_logic := '0'; + get_ot_counter_started : IN std_logic ; + get_ot_counter_ready : IN std_logic ; + on_time_counter : IN std_logic_vector (47 DOWNTO 0); + temp_sensor_ready : IN std_logic ; + temp_sensor_array : IN sensor_array_type ); END COMPONENT; @@ -338,11 +368,18 @@ get_header_started : OUT std_logic := '0'; get_header_ready : OUT std_logic := '0'; + board_id : IN std_logic_vector (63 DOWNTO 0); trigger_counter_read : OUT std_logic := '0'; trigger_counter_valid : IN std_logic ; trigger_counter : IN std_logic_vector (31 DOWNTO 0) := (others => '0'); + get_ts_counter : OUT std_logic := '0'; + get_ts_counter_started : IN std_logic ; + get_ts_counter_ready : IN std_logic ; + timestamp_counter : IN std_logic_vector (47 DOWNTO 0); header_board_id : OUT std_logic_vector (63 DOWNTO 0) := (others => '0'); header_firmware_id : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); header_trigger_counter : OUT std_logic_vector (31 DOWNTO 0) := (others => '0'); - header_timestamp_counter : OUT std_logic_vector (47 DOWNTO 0) := (others => '0') + header_timestamp_counter : OUT std_logic_vector (47 DOWNTO 0) := (others => '0'); + header_current_state : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + current_cc_state : IN std_logic_vector (15 DOWNTO 0) ); END COMPONENT; @@ -411,5 +448,16 @@ header_firmware_id : IN std_logic_vector (15 DOWNTO 0); header_trigger_counter : IN std_logic_vector (31 DOWNTO 0); - header_timestamp_counter : IN std_logic_vector (47 DOWNTO 0) + header_timestamp_counter : IN std_logic_vector (47 DOWNTO 0); + header_current_state : IN std_logic_vector (15 DOWNTO 0); + -- + start_run : OUT std_logic := '0'; + start_run_ack : IN std_logic ; + start_run_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + start_run_num_events : OUT std_logic_vector (31 DOWNTO 0) := (others => '0'); + stop_run : OUT std_logic := '0'; + stop_run_ack : IN std_logic ; + crate_reset : OUT std_logic := '0'; + crate_reset_ack : IN std_logic ; + crate_reset_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0') ); END COMPONENT; @@ -514,5 +562,11 @@ dd_ready => dd_ready_internal, dd_addr => dd_addr1, - dd_data => dd_data + dd_data => dd_data, + get_ot_counter => get_ot_counter, + get_ot_counter_started => get_ot_counter_started, + get_ot_counter_ready => get_ot_counter_ready, + on_time_counter => on_time_counter, + temp_sensor_ready => temp_sensor_ready, + temp_sensor_array => temp_sensor_array ); U_8 : dram_control @@ -580,11 +634,18 @@ get_header_started => get_header_started, get_header_ready => get_header_ready, + board_id => board_id, trigger_counter_read => trigger_counter_read, trigger_counter_valid => trigger_counter_valid, trigger_counter => trigger_counter, + get_ts_counter => get_ts_counter, + get_ts_counter_started => get_ts_counter_started, + get_ts_counter_ready => get_ts_counter_ready, + timestamp_counter => timestamp_counter, header_board_id => header_board_id, header_firmware_id => header_firmware_id, header_trigger_counter => header_trigger_counter, - header_timestamp_counter => header_timestamp_counter + header_timestamp_counter => header_timestamp_counter, + header_current_state => header_current_state, + current_cc_state => current_cc_state ); U_0 : w5300_modul @@ -646,5 +707,15 @@ header_firmware_id => header_firmware_id, header_trigger_counter => header_trigger_counter, - header_timestamp_counter => header_timestamp_counter + header_timestamp_counter => header_timestamp_counter, + header_current_state => header_current_state, + start_run => start_run, + start_run_ack => start_run_ack, + start_run_param => start_run_param, + start_run_num_events => start_run_num_events, + stop_run => stop_run, + stop_run_ack => stop_run_ack, + crate_reset => crate_reset, + crate_reset_ack => crate_reset_ack, + crate_reset_param => crate_reset_param ); Index: /firmware/FTM/ethernet/header_modul_beha.vhd =================================================================== --- /firmware/FTM/ethernet/header_modul_beha.vhd (revision 10440) +++ /firmware/FTM/ethernet/header_modul_beha.vhd (revision 10441) @@ -12,7 +12,5 @@ USE ieee.std_logic_arith.all; USE IEEE.STD_LOGIC_UNSIGNED.all; ---LIBRARY FACT_FTM_lib; ---USE FACT_FTM_lib.ftm_array_types.all; ---USE FACT_FTM_lib.ftm_constants.all; + library ftm_definitions; USE ftm_definitions.ftm_array_types.all; @@ -25,11 +23,18 @@ get_header_started : OUT std_logic := '0'; get_header_ready : OUT std_logic := '0'; + board_id : IN std_logic_vector (63 DOWNTO 0); trigger_counter_read : OUT std_logic := '0'; trigger_counter_valid : IN std_logic; trigger_counter : IN std_logic_vector (31 DOWNTO 0) := (others => '0'); + get_ts_counter : OUT std_logic := '0'; + get_ts_counter_started : IN std_logic; + get_ts_counter_ready : IN std_logic; + timestamp_counter : IN std_logic_vector (47 DOWNTO 0); header_board_id : OUT std_logic_vector (63 DOWNTO 0) := (others => '0'); header_firmware_id : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); header_trigger_counter : OUT std_logic_vector (31 DOWNTO 0) := (others => '0'); - header_timestamp_counter : OUT std_logic_vector (47 DOWNTO 0) := (others => '0') + header_timestamp_counter : OUT std_logic_vector (47 DOWNTO 0) := (others => '0'); + header_current_state : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + current_cc_state : IN std_logic_vector (15 DOWNTO 0) ); END ENTITY header_modul; @@ -38,5 +43,6 @@ ARCHITECTURE beha OF header_modul IS - type state_header_proc_type is (HP_INIT, HP_CONFIG, HP_IDLE, HP_START, HP_TRG_CNT, HP_END); + type state_header_proc_type is (HP_INIT, HP_CONFIG, HP_IDLE, HP_START, HP_TRG_CNT, + HP_TS_CNT, HP_TS_CNT_END, HP_END); signal state_header_proc : state_header_proc_type := HP_INIT; @@ -47,40 +53,53 @@ if rising_edge (clk) then case state_header_proc is - - when HP_INIT => - state_header_proc <= HP_CONFIG; - when HP_CONFIG => - state_header_proc <= HP_IDLE; + when HP_INIT => + state_header_proc <= HP_CONFIG; + + when HP_CONFIG => + state_header_proc <= HP_IDLE; + + when HP_IDLE => + if (get_header = '1') then + get_header_started <= '1'; + get_header_ready <= '0'; + state_header_proc <= HP_START; + end if; + + when HP_START => + header_board_id <= board_id; + header_firmware_id <= X"00" & FIRMWARE_ID; + header_current_state <= current_cc_state; + + trigger_counter_read <= '1'; + state_header_proc <= HP_TRG_CNT; + + when HP_TRG_CNT => + trigger_counter_read <= '0'; + if (trigger_counter_valid = '1') then + header_trigger_counter <= trigger_counter; + get_ts_counter <= '1'; + state_header_proc <= HP_TS_CNT; + end if; + + when HP_TS_CNT => + if (get_ts_counter_started = '1') then + get_ts_counter <= '0'; + state_header_proc <= HP_TS_CNT_END; + end if; + + when HP_TS_CNT_END => + if (get_ts_counter_ready = '1') then + header_timestamp_counter <= timestamp_counter; + state_header_proc <= HP_END; + end if; + + when HP_END => + if (get_header <= '0') then + get_header_started <= '0'; + get_header_ready <= '1'; + state_header_proc <= HP_IDLE; + end if; - when HP_IDLE => - if (get_header = '1') then - get_header_started <= '1'; - get_header_ready <= '0'; - state_header_proc <= HP_START; - end if; - - when HP_START => - header_board_id <= to_stdlogicvector (DNA_FOR_SIM); - header_firmware_id <= X"00" & FIRMWARE_ID; - header_timestamp_counter <= X"333322221111"; - - trigger_counter_read <= '1'; - state_header_proc <= HP_TRG_CNT; - - when HP_TRG_CNT => - trigger_counter_read <= '0'; - if (trigger_counter_valid = '1') then - header_trigger_counter <= trigger_counter; - state_header_proc <= HP_END; - end if; - - when HP_END => - if (get_header <= '0') then - get_header_started <= '0'; - get_header_ready <= '1'; - state_header_proc <= HP_IDLE; - end if; - end case; end if; Index: /firmware/FTM/ethernet/w5300_modul.vhd =================================================================== --- /firmware/FTM/ethernet/w5300_modul.vhd (revision 10440) +++ /firmware/FTM/ethernet/w5300_modul.vhd (revision 10441) @@ -18,5 +18,5 @@ -- ---------------------------------------------------------------------------------- - +-- hds interface_start LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; @@ -24,7 +24,4 @@ USE IEEE.STD_LOGIC_UNSIGNED.all; ---LIBRARY FACT_FTM_lib; ---USE FACT_FTM_lib.ftm_array_types.all; ---USE FACT_FTM_lib.ftm_constants.all; library ftm_definitions; USE ftm_definitions.ftm_array_types.all; @@ -100,6 +97,16 @@ header_firmware_id : IN std_logic_vector (15 DOWNTO 0); header_trigger_counter : IN std_logic_vector (31 DOWNTO 0); - header_timestamp_counter : IN std_logic_vector (47 DOWNTO 0) - + header_timestamp_counter : IN std_logic_vector (47 DOWNTO 0); + header_current_state : IN std_logic_vector (15 DOWNTO 0); + -- + start_run : OUT std_logic := '0'; + start_run_ack : IN std_logic; + start_run_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + start_run_num_events : OUT std_logic_vector (31 DOWNTO 0) := (others => '0'); + stop_run : OUT std_logic := '0'; + stop_run_ack : IN std_logic; + crate_reset : OUT std_logic := '0'; + crate_reset_ack : IN std_logic; + crate_reset_param : OUT std_logic_vector (15 DOWNTO 0) := (others => '0') ); @@ -113,8 +120,8 @@ READ_DATA, WRITE_TO_SD_ADDR, READ_FTU_ERROR, READ_FROM_SD_ADDR, READ_FROM_DD_ADDR, READ_FROM_FL_ADDR, READ_FROM_HEADER_MODUL); type state_write_type is (WR_START, WR_LENGTH, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08, - WR_GET_HEADER, WR_GET_HEADER_WAIT, WR_FIFO_DATA, WR_FIFO_DATA_01, WR_FIFO_HEADER, WR_FIFO_HEADER_01); + WR_WRITE_START_DEL, WR_GET_HEADER, WR_GET_HEADER_WAIT, WR_FIFO_DATA, WR_FIFO_DATA_01, WR_FIFO_HEADER, WR_FIFO_HEADER_01, WR_WRITE_END_DEL); type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04); type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06); - type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_CMD, RD_CMD_PARSE, RD_PING, RD_WRITE_SD_ADDR, RD_READ_SD_ADDR, RD_READ_SD_BLOCK, RD_READ_DD_BLOCK, RD_WRITE_SD_BLOCK, RD_END); + type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_CMD, RD_CMD_PARSE, RD_PING, RD_WRITE_SD_ADDR, RD_READ_SD_ADDR, RD_READ_SD_BLOCK, RD_READ_DD_BLOCK, RD_WRITE_SD_BLOCK, RD_X_EVNTS,RD_END); type state_write_sd_type is (WRITE_SD_START, WRITE_SD_WAIT, WRITE_SD_END); type state_read_sd_type is (READ_SD_START, READ_SD_WAIT, READ_SD_END); @@ -163,5 +170,5 @@ signal next_packet_data_cnt : integer range 0 to 4095 := 0; - signal rx_packets_cnt : std_logic_vector (15 downto 0); + signal rx_packets_cnt : std_logic_vector (15 downto 0) := X"0000"; signal new_config_flag : std_logic := '0'; @@ -182,4 +189,7 @@ signal local_sd_addr : std_logic_vector (11 downto 0); signal local_sd_data : std_logic_vector (15 downto 0); + + signal data_package_type : std_logic_vector (15 downto 0) := X"0000"; + signal data_package_length : std_logic_vector (15 downto 0) := X"0000"; @@ -574,4 +584,6 @@ when SFE_START => next_state <= SEND_FTU_ERROR; + data_package_type <= FTM_PACKAGE_TYPE_FTU_ERR; + data_package_length <= FTU_ERROR_LENGTH + 1; -- +1 := package end read_addr_state <= READ_FTU_ERROR; local_sd_addr <= X"000"; @@ -626,4 +638,10 @@ when RD_END => + if (new_config_flag = '1') then + new_config_flag <= '0'; + next_state <= CONFIG; + else + next_state <= MAIN; + end if; if (internal_cmd = '0') then par_addr <= W5300_S0_CR; @@ -632,10 +650,5 @@ else internal_cmd <= '0'; - end if; - if (new_config_flag = '1') then - new_config_flag <= '0'; - next_state <= CONFIG; - else - next_state <= MAIN; + state_init <= MAIN; end if; @@ -670,4 +683,37 @@ led_int <= NOT led_int; state_read_data <= RD_5; + + when CMD_START => + case cmd_array (2) is + -- start "normal" run + when PAR_START_RUN => + start_run <= '1'; + start_run_param <= cmd_array (2); + if (start_run_ack = '1') then + start_run <= '0'; + state_read_data <= RD_5; + end if; + -- start run an take X events + when PAR_START_X_EVNTS => + next_state_read_data <= RD_X_EVNTS; + state_read_data <= RD_5; + when others => + state_read_data <= RD_5; + end case; + + when CMD_STOP => + stop_run <= '1'; + if (stop_run_ack = '1') then + stop_run <= '0'; + state_read_data <= RD_5; + end if; + + when CMD_CRESET => + crate_reset <= '1'; + crate_reset_param <= cmd_array (2); + if (crate_reset_ack = '1') then + crate_reset <= '0'; + state_read_data <= RD_5; + end if; when CMD_WRITE => @@ -739,4 +785,6 @@ when PING_WRITE_LIST => state_read_data <= RD_5; + data_package_type <= FTM_PACKAGE_TYPE_FTU_LIST; + data_package_length <= FL_BLOCK_SIZE + 1; -- +1 := package end read_addr_state <= READ_FROM_FL_ADDR; local_sd_addr <= X"000"; --start at address 0x000 @@ -767,4 +815,6 @@ when READ_DD_BLOCK_WRITE => if (dd_write_general_ready = '1') then + data_package_type <= FTM_PACKAGE_TYPE_DD; + data_package_length <= DD_BLOCK_SIZE + 1; -- +1 := package end read_addr_state <= READ_FROM_DD_ADDR; local_sd_addr <= X"000"; -- start at address 0x000 @@ -796,4 +846,6 @@ -- read static data block and write it to ethernet when RD_READ_SD_BLOCK => + data_package_type <= FTM_PACKAGE_TYPE_SD; + data_package_length <= SD_BLOCK_SIZE + 1; -- +1 := package end state_read_data <= RD_5; read_addr_state <= READ_FROM_SD_ADDR; @@ -806,4 +858,6 @@ -- read from address in static data ram and write data to ethernet when RD_READ_SD_ADDR => + data_package_type <= FTM_PACKAGE_TYPE_SD_WORD; + data_package_length <= SD_SINGLE_WORD_SIZE + 1; -- +1 := package end state_read_data <= RD_5; read_addr_state <= READ_FROM_SD_ADDR; @@ -841,4 +895,20 @@ state_init <= WRITE_TO_SD_ADDR; end if; + + -- read X events + when RD_X_EVNTS => + if (next_packet_data_cnt = 0) then + start_run_num_events (31 downto 16) <= data_read; + else + start_run_num_events (15 downto 0) <= data_read; + start_run_param <= cmd_array (2); + start_run <= '1'; + if (start_run_ack = '1') then + start_run <= '0'; + next_packet_data_cnt <= 0; + next_state_read_data <= RD_CMD; + state_read_data <= RD_5; + end if; + end if; end case; -- state_read_data @@ -860,25 +930,31 @@ case header_cnt is when X"00" => + local_sd_data <= data_package_type; + when X"01" => + local_sd_data <= data_package_length; + when X"02" => + local_sd_data <= header_current_state; + when X"03" => local_sd_data <= header_board_id (63 DOWNTO 48); - when X"01" => + when X"04" => local_sd_data <= header_board_id (47 DOWNTO 32); - when X"02" => + when X"05" => local_sd_data <= header_board_id (31 DOWNTO 16); - when X"03" => + when X"06" => local_sd_data <= header_board_id (15 DOWNTO 0); - when X"04" => + when X"07" => local_sd_data <= header_firmware_id; - when X"05" => + when X"08" => local_sd_data <= header_trigger_counter (31 DOWNTO 16); - when X"06" => + when X"09" => local_sd_data <= header_trigger_counter (15 DOWNTO 0); - when X"07" => + when X"0A" => + local_sd_data <= X"0000"; + when X"0B" => local_sd_data <= header_timestamp_counter (47 DOWNTO 32); - when X"08" => + when X"0C" => local_sd_data <= header_timestamp_counter (31 DOWNTO 16); - when X"09" => + when X"0D" => local_sd_data <= header_timestamp_counter (15 DOWNTO 0); - when X"0A" => - local_sd_data <= X"FFFF"; -- spare when others => null; @@ -981,5 +1057,6 @@ local_socket_nr <= "000"; next_state_tmp <= next_state; - write_length_bytes <= (FTM_HEADER_LENGTH + local_write_length (15 downto 0)) & '0'; -- shift left (*2) + -- Write Length: 2 := START and END of package + write_length_bytes <= (2 + FTM_HEADER_LENGTH + local_write_length (15 downto 0)) & '0'; -- shift left (*2) data_cnt <= 0; header_cnt <= X"00"; @@ -1004,6 +1081,14 @@ state_write <= WR_01; else - state_write <= WR_GET_HEADER; - end if; + state_write <= WR_WRITE_START_DEL; + end if; + + -- write package start delimiter + when WR_WRITE_START_DEL => + par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; + par_data <= FTM_PACKAGE_START; + state_init <= WRITE_REG; + next_state <= WRITE_DATA; + state_write <= WR_GET_HEADER; -- get header data @@ -1053,6 +1138,14 @@ state_write <= WR_FIFO_DATA; else - state_write <= WR_05; - end if; + state_write <= WR_WRITE_END_DEL; + end if; + + -- write package end delimiter + when WR_WRITE_END_DEL => + par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; + par_data <= FTM_PACKAGE_END; + state_init <= WRITE_REG; + next_state <= WRITE_DATA; + state_write <= WR_05; -- Send FIFO @@ -1137,2 +1230,3 @@ end Behavioral; + Index: /firmware/FTM/ftm_definitions.vhd =================================================================== --- /firmware/FTM/ftm_definitions.vhd (revision 10440) +++ /firmware/FTM/ftm_definitions.vhd (revision 10441) @@ -35,4 +35,15 @@ -- ---kw 11.04.: added SD_ADDR_ftu_prescaling_0 +-- +-- modified: Quirin Weitzel, April 20 2011 +-- next merger with library file from dortmund (changes below) +-- kw 14.04.: added sensor_array_type (temperature sensors) +-- changed CMD_AUTOSEND to X"0040" +-- added "start run / take X events", "stop run", "crate reset" +-- kw 18.04.: removed PAR_READ_DD_ADDR, changed PAR_WRITE_SD_ADDR to 0x0004 +-- added FTM_PACKAGE_START and FTM_PACKAGE_END +-- increased DD_BLOCK_SIZE and DD_BLOCK_SIZE_GENERAL by 1 (64 bit on-time counter) +-- changed FTM_HEADER_LENGTH to 0x0E +-- kw 20.04.: added "package types", SD_SINGLE_WORD_SIZE -- ---------------------------------------------------------------------------------- @@ -196,18 +207,45 @@ -- only for debugging: data_block (0) = ADDR constant PAR_READ_SD_ADDR : std_logic_vector := X"0004"; -- read from address in static data block - constant PAR_READ_DD_ADDR : std_logic_vector := X"0008"; -- read from address in dynamic data block constant CMD_WRITE : std_logic_vector := X"0002"; constant PAR_WRITE_SD : std_logic_vector := X"0001"; -- write static data block -- only for debugging: data_block (0) = ADDR, data_block (1) = DATA - constant PAR_WRITE_SD_ADDR : std_logic_vector := X"0002"; -- write to address in static data ram + constant PAR_WRITE_SD_ADDR : std_logic_vector := X"0004"; -- write to address in static data ram -- ping all FTUs constant CMD_PING : std_logic_vector := X"0010"; -- ping all FTUs -- turn automatic sending of dd-block and ftu-error-list on or off - constant CMD_AUTOSEND : std_logic_vector := X"0020"; + constant CMD_AUTOSEND : std_logic_vector := X"0040"; constant PAR_AUTOSEND_EA : std_logic_vector := X"0001"; -- enable automatic sending constant PAR_AUTOSEND_DA : std_logic_vector := X"0000"; -- disable automatic sending + -- start run / take X events + constant CMD_START : std_logic_vector := X"0004"; + constant PAR_START_RUN : std_logic_vector := X"0001"; + constant PAR_START_X_EVNTS : std_logic_vector := X"0002"; + + -- stop run + constant CMD_STOP : std_logic_vector := X"0008"; + + -- crate reset + constant CMD_CRESET : std_logic_vector := X"0020"; + + -- start and end of package + constant FTM_PACKAGE_START : std_logic_vector := X"FB01"; + constant FTM_PACKAGE_END : std_logic_vector := X"04FE"; + + -- package types + constant FTM_PACKAGE_TYPE_SD : std_logic_vector := X"0001"; + constant FTM_PACKAGE_TYPE_DD : std_logic_vector := X"0002"; + constant FTM_PACKAGE_TYPE_FTU_LIST : std_logic_vector := X"0003"; + constant FTM_PACKAGE_TYPE_FTU_ERR : std_logic_vector := X"0004"; + constant FTM_PACKAGE_TYPE_SD_WORD : std_logic_vector := X"0005"; + + -- state types + constant FTM_STATE_IDLE : std_logic_vector := X"0001"; + constant FTM_STATE_CFG : std_logic_vector := X"0002"; + constant FTM_STATE_RUN : std_logic_vector := X"0003"; + constant FTM_STATE_CALIB : std_logic_vector := X"0004"; + -- header length of data packages - constant FTM_HEADER_LENGTH : std_logic_vector (7 DOWNTO 0) := X"0B"; + constant FTM_HEADER_LENGTH : std_logic_vector (7 DOWNTO 0) := X"0E"; -- FTU error message @@ -232,9 +270,9 @@ constant SD_FTU_ACTIVE_NUM : integer := 4; -- number of active FTU lists (cr0 to cr3) constant SD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1B4"; -- total size of static data block + constant SD_SINGLE_WORD_SIZE : std_logic_vector := X"001"; -- dynamic data block - --constant DD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"010"; -- 7 + (40 * 12) = 0x1E7 --total size of dynamic data block - constant DD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1E7"; -- 7 + (40 * 12) = 0x1E7 --total size of dynamic data block - constant DD_BLOCK_SIZE_GENERAL : integer := 7; -- dynamic block size without FTU data + constant DD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1E8"; -- 8 + (40 * 12) = 0x1E8 --total size of dynamic data block + constant DD_BLOCK_SIZE_GENERAL : integer := 8; -- dynamic block size without FTU data constant DYNAMIC_RAM_ADDR_WIDTH : integer := 12; Index: /firmware/FTM/test_firmware/counter_dummy/counter_dummy_beha.vhd =================================================================== --- /firmware/FTM/test_firmware/counter_dummy/counter_dummy_beha.vhd (revision 10441) +++ /firmware/FTM/test_firmware/counter_dummy/counter_dummy_beha.vhd (revision 10441) @@ -0,0 +1,72 @@ +-- +-- VHDL Architecture FACT_FTM_Boards.counter_dummy.beha +-- +-- Created: +-- by - kai.users (tpkw.local.priv) +-- at - 15:37:00 04/13/11 +-- +-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE IEEE.STD_LOGIC_UNSIGNED.all; + +ENTITY counter_dummy IS + PORT( + clk : IN std_logic; + get_counter : IN std_logic; + get_counter_started : OUT std_logic := '0'; + get_counter_ready : OUT std_logic := '0'; + counter : OUT std_logic_vector (47 DOWNTO 0) := (others => '0') + ); + +-- Declarations + +END counter_dummy ; + +-- +ARCHITECTURE beha OF counter_dummy IS + + type state_counter_proc_type is (CP_INIT, CP_CONFIG, CP_IDLE, CP_CNT_START, CP_CNT_END); + signal state_counter_proc : state_counter_proc_type := CP_INIT; + + signal counter_int : std_logic_vector (47 DOWNTO 0) := (others => '0'); + +BEGIN + counter_proc : process (clk) + begin + if rising_edge (clk) then + case state_counter_proc is + + when CP_INIT => + state_counter_proc <= CP_CONFIG; + + when CP_CONFIG => + state_counter_proc <= CP_IDLE; + + when CP_IDLE => + if (get_counter = '1') then + counter_int <= counter_int + 1; + get_counter_started <= '1'; + get_counter_ready <= '0'; + state_counter_proc <= CP_CNT_START; + end if; + + when CP_CNT_START => + counter <= counter_int; + state_counter_proc <= CP_CNT_END; + + when CP_CNT_END => + if (get_counter = '0') then + get_counter_started <= '0'; + get_counter_ready <= '1'; + state_counter_proc <= CP_IDLE; + end if; + + end case; + end if; + end process counter_proc; + +END ARCHITECTURE beha; +