Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/FAD_rs485_interface.vhd
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/FAD_rs485_interface.vhd	(revision 10462)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/FAD_rs485_interface.vhd	(revision 10462)
@@ -0,0 +1,128 @@
+--
+-- VHDL Architecture FACT_FAD_lib.rs485_interface.beha
+--
+-- Created:
+--          by - Benjamin Krumm.UNKNOWN (EEPC8)
+--          at - 13:24:23 08.06.2010
+--
+-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
+--
+--
+-- modified for FTU design by Q. Weitzel, 30 July 2010
+--
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+--library fad_rs485_definitions;
+--USE fad_rs485_definitions.fad_rs485_constants.all;
+library fact_fad_lib;
+use fact_fad_lib.fad_rs485_constants.all;
+
+
+ENTITY FAD_rs485_interface IS
+  GENERIC( 
+    CLOCK_FREQUENCY : integer := FAD_RS485_INPUT_CLK_F;
+    BAUD_RATE       : integer := RS485_BAUD_RATE
+  );
+  PORT( 
+    clk      : IN     std_logic;
+    -- RS485
+    rx_d     : IN     std_logic;
+    rx_en    : OUT    std_logic;
+    tx_d     : OUT    std_logic;
+    tx_en    : OUT    std_logic;
+    -- FPGA
+    rx_data  : OUT    std_logic_vector (7 DOWNTO 0);
+    --rx_busy  : OUT    std_logic  := '0';
+    rx_valid : OUT    std_logic  := '0';
+    tx_data  : IN     std_logic_vector (7 DOWNTO 0);
+    tx_busy  : OUT    std_logic  := '0';
+    tx_start : IN     std_logic
+  );
+
+END FAD_rs485_interface;
+
+ARCHITECTURE beha OF FAD_rs485_interface IS
+  
+  signal flow_ctrl : std_logic := '0'; -- '0' -> RX enable, '1' -> TX enable
+
+  --transmit
+  signal tx_start_f : std_logic := '0';
+  signal tx_sr : std_logic_vector(10 downto 0) := (others => '1');  -- start bit, 8 data bits, 2 stop bits
+  signal tx_bitcnt : integer range 0 to 11 := 11;
+  signal tx_cnt : integer range 0 to ((CLOCK_FREQUENCY / BAUD_RATE) - 1);
+
+  --receive
+  signal rx_dsr : std_logic_vector(3 downto 0) := (others => '1');
+  signal rx_sr : std_logic_vector(7 downto 0) := (others => '0');
+  signal rx_bitcnt : integer range 0 to 11 := 11;
+  signal rx_cnt : integer range 0 to ((CLOCK_FREQUENCY / BAUD_RATE) - 1);
+  
+BEGIN
+
+  -- Senden
+  tx_data_proc: process(clk)
+  begin
+    if rising_edge(clk) then
+      tx_start_f <= tx_start;
+      if (tx_start = '1' or tx_bitcnt < 11) then
+        flow_ctrl <= '1';
+      else
+        flow_ctrl <= '0';
+      end if;
+      if (tx_start = '1' and tx_start_f = '0') then -- steigende Flanke, los gehts
+        tx_cnt <= 0;                                -- Zaehler initialisieren
+        tx_bitcnt <= 0;                      
+        tx_sr <= "11" & tx_data & '0';              -- 2 x Stopbit, 8 Datenbits, Startbit, rechts gehts los
+      else
+        if (tx_cnt < (CLOCK_FREQUENCY/BAUD_RATE) - 1) then
+          tx_cnt <= tx_cnt + 1;
+        else  -- naechstes Bit ausgeben  
+          if (tx_bitcnt < 11) then
+            tx_cnt <= 0;
+            tx_bitcnt <= tx_bitcnt + 1;
+            tx_sr <= '1' & tx_sr(tx_sr'left downto 1);
+          end if;
+        end if;
+      end if;
+  end if;
+  end process;
+
+  tx_en <= flow_ctrl;
+  tx_d <= tx_sr(0);  -- LSB first
+  tx_busy <= '1' when (tx_start = '1' or tx_bitcnt < 11) else '0';
+
+  -- Empfangen
+  rx_data_proc: process(clk) 
+  begin
+    if rising_edge(clk) then
+      rx_dsr <= rx_dsr(rx_dsr'left - 1 downto 0) & rx_d;
+      if (rx_bitcnt < 11) then    -- Empfang laeuft
+        if (rx_cnt < (CLOCK_FREQUENCY/BAUD_RATE) - 1) then 
+          rx_cnt <= rx_cnt + 1;
+        else
+          rx_cnt <= 0; 
+          rx_bitcnt <= rx_bitcnt + 1;
+          if (rx_bitcnt < 9) then
+            rx_sr <= rx_dsr(rx_dsr'left - 1) & rx_sr(rx_sr'left downto 1); -- rechts schieben, weil LSB first
+          else 
+            rx_valid <= '1';
+          end if;
+        end if;
+      else
+        if (rx_dsr(3 downto 2) = "10") then   -- warten auf Start bit
+          rx_valid <= '0';
+          rx_cnt <= ((CLOCK_FREQUENCY / BAUD_RATE) - 1) / 2;
+          rx_bitcnt <= 0;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  rx_en <= flow_ctrl;
+  rx_data <= rx_sr;
+  --rx_busy <= '1' when (rx_bitcnt < 11) else '0';
+
+END ARCHITECTURE beha;
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/FAD_rs485_receiver.vhd
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/FAD_rs485_receiver.vhd	(revision 10462)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/FAD_rs485_receiver.vhd	(revision 10462)
@@ -0,0 +1,141 @@
+--
+-- VHDL Architecture FACT_FAD_lib.rs485_receiver.beha
+--
+-- Created:
+--          by - Benjamin Krumm.UNKNOWN (EEPC8)
+--          at - 12:16:57 11.06.2010
+--
+-- using Mentor Graphics HDL Designer(TM) 2009.2 (Build 10)
+--
+--
+-- modified for FTU design by Q. Weitzel, 13 September 2010
+-- timeout added, Q. Weitzel, 26 October 2010
+-- 
+-- modified for FAD design by D.Neise, 12. April 2011
+-- modified library include statements mainly.
+--
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+--library fad_rs485_definitions;
+--USE fad_rs485_definitions.fad_rs485_constants.all;
+library fact_fad_lib;
+use fact_fad_lib.fad_rs485_constants.all;
+
+ENTITY FAD_rs485_receiver IS
+  generic(
+    -- defined in fad_rs485_definitions.fad_rs485_constants
+    RX_BYTES  : integer := RS485_MESSAGE_LEN_BYTES; -- no. of bytes to receive
+    RX_WIDTH  : integer := RS485_MESSAGE_LEN_BYTES * 8  -- no. of bits to receive
+  );
+  port(
+    rec_clk   : in  std_logic;
+ 
+	-- Interface to MAX3485:
+		rx_d     : IN  std_logic;
+		rx_en    : OUT std_logic;
+		tx_d     : OUT std_logic;
+		tx_en    : OUT std_logic;
+	
+	
+	rec_start : in std_logic;
+	rec_timeout_occured : out std_logic := '0';
+    rec_dout  : out std_logic_vector(RX_WIDTH - 1 downto 0) := (others => '0');
+    rec_valid : out std_logic := '0'
+  );
+END ENTITY FAD_rs485_receiver;
+
+ARCHITECTURE beha OF FAD_rs485_receiver IS
+  
+  signal rxcnt			: integer range 0 to RX_BYTES := 0;
+  signal rxsr			: std_logic_vector(3 downto 0) := (others => '0');
+  signal timeout_cnt	: integer range 0 to RS485_TIMEOUT + 1 := 0;
+  signal rec_den		: std_logic := '0';
+  signal rec_din		: std_logic_vector(7 downto 0) := (others => '0');
+  signal start_sr		: std_logic_vector(1 downto 0) := (others => '0');
+  signal started		: std_logic := '0'; -- 0-not running; 1-running
+  
+	component FAD_rs485_interface
+	port(
+		clk      : IN  std_logic;
+		-- RS485
+		rx_d     : IN  std_logic;
+		rx_en    : OUT std_logic;
+		tx_d     : OUT std_logic;
+		tx_en    : OUT std_logic;
+		-- FPGA
+		rx_data  : OUT std_logic_vector (7 DOWNTO 0);
+		--rx_busy  : OUT std_logic  := '0';
+		rx_valid : OUT std_logic  := '0';
+		tx_data  : IN  std_logic_vector (7 DOWNTO 0);
+		tx_busy  : OUT std_logic  := '0';
+		tx_start : IN  std_logic );
+	end component;
+
+  
+BEGIN
+
+	Inst_FAD_rs485_interface : FAD_rs485_interface
+		port map(
+			clk      => rec_clk,
+			-- RS485
+			rx_d     => rx_d,
+			rx_en    => rx_en,
+			tx_d     => tx_d,
+			tx_en    => tx_en,
+			-- FPGA
+			rx_data  => rec_din,
+			
+			rx_valid => rec_den,
+			tx_data  => "00000000",
+			tx_busy  => open,
+			tx_start => '0'
+		);
+
+process(rec_clk)
+	begin
+		if rising_edge(rec_clk) then
+			start_sr <= start_sr(0) & rec_start;
+			rxsr <= rxsr(2 downto 0) & rec_den;
+			
+			
+			if (start_sr = "01") then
+				started <= '1';
+			end if;
+			
+			if ((rxcnt > 0) or (started = '1')) then
+				timeout_cnt <= timeout_cnt + 1;
+			else
+				timeout_cnt <= 0;
+			end if;
+			
+			if (timeout_cnt = RS485_TIMEOUT) then
+				rxcnt <= 0;
+				started <= '0';
+				rec_timeout_occured <= '1';
+				rec_valid <= '1';
+			else
+				if (rxsr(3 downto 2) = "01") then -- identify rising edge
+					if (rxcnt = 0) then
+						rec_dout <= (others => '0');
+					end if;
+					rec_dout((rxcnt*rec_din'length + rec_din'length - 1) downto (rxcnt*rec_din'length)) <= rec_din;
+					rxcnt <= rxcnt + 1;
+					if (rxcnt < RX_BYTES - 1) then
+						rec_valid <= '0';
+						rec_timeout_occured <= '0';
+					else
+						rxcnt <= 0;
+						rec_valid <= '1';
+					end if;
+				end if;
+			end if;
+		
+		end if; --if rising_edge(rec_clk)
+	end process ;
+
+	
+
+END ARCHITECTURE beha;
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd	(revision 10448)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd	(revision 10462)
@@ -54,4 +54,5 @@
 	FTM_RS485_ready			: in	std_logic;
 	FTM_trigger_info		: in	std_logic_vector (55 downto 0); --7 byte
+	FTM_receiver_status : in std_logic;
 
 -- EVT HEADER - part 3
@@ -98,5 +99,6 @@
 	drs_s_cell_array		: in	drs_s_cell_array_type;
 
-	drs_readout_started		: out	std_logic := '0'
+	drs_readout_started		: out	std_logic := '0';
+	trigger_veto : out std_logic := '1'
 );
 end data_generator ;
@@ -119,5 +121,5 @@
 	WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_FILLING,
 	WAIT_FOR_ADC, WRITE_ADC_DATA,
-	WRITE_EXTERNAL_TRIGGER,
+	WAIT_FOR_EXTERNAL_TRIGGER_READY, WRITE_EXTERNAL_TRIGGER,
 	WRITE_END_FLAG,
 	WRITE_DATA_END, WRITE_DATA_END_WAIT,
@@ -148,5 +150,5 @@
 signal sig_drs_readout_started : std_logic := '0';
 
-
+signal FTM_trigger_info_local_copy : std_logic_vector (55 downto 0) := (others => '0'); --7 byte
 
 -- self configuration signals:
@@ -213,5 +215,5 @@
 		when IDLE =>
 			state_generate <= IDLE;
-			
+			trigger_veto <= '0';
 			if (config_start_sig = '1') then
 				config_start_sig <= '0';
@@ -221,4 +223,5 @@
 			if (ram_write_ea = '1' and trigger_sr = "01") then
 				sig_drs_readout_started <= '1'; -- is set to '0' in next state ... just a pulse.
+				trigger_veto <= '1';
 				start_read_drs_stop_cell <= '1';
 				adc_output_enable_inverted <= '0';
@@ -385,8 +388,9 @@
 		when WRITE_ADC_DATA =>
 			if (data_cntr < roi_max_int (channel_id)) then
-				data_out <= "000" & adc_otr(3) & adc_data_array(3) &	--exchange ... with data_cntr when testbenching. 
-							"000" & adc_otr(2) & adc_data_array(2) &
-							"000" & adc_otr(1) & adc_data_array(1) &
-							"000" & adc_otr(0) & adc_data_array(0);
+				data_out <= adc_data_array(3)(7 downto 0) & "000" & adc_otr(3) & adc_data_array(3)(11 downto 8) &
+          adc_data_array(2)(7 downto 0) & "000" & adc_otr(2) & adc_data_array(2)(11 downto 8) &
+          adc_data_array(1)(7 downto 0) & "000" & adc_otr(1) & adc_data_array(1)(11 downto 8) &
+          adc_data_array(0)(7 downto 0) & "000" & adc_otr(0) & adc_data_array(0)(11 downto 8) ;
+
 				addr_cntr <= addr_cntr + 1;
 				state_generate <= WRITE_ADC_DATA;
@@ -396,5 +400,5 @@
 				--adc_output_enable_inverted <= '1'; -- nur für Emulator
 				if (channel_id = 8) then
-					state_generate <= WRITE_EXTERNAL_TRIGGER;
+					state_generate <= WAIT_FOR_EXTERNAL_TRIGGER_READY;
 					adc_output_enable_inverted <= '1';
 					-- switch off ADC_CLK
@@ -406,11 +410,20 @@
 				end if;
 			end if;
- 
+		
+		when WAIT_FOR_EXTERNAL_TRIGGER_READY =>
+			state_generate <= WAIT_FOR_EXTERNAL_TRIGGER_READY;
+			if (FTM_RS485_ready = '1') then
+				--make local copy and proceed
+				FTM_trigger_info_local_copy <= FTM_trigger_info;
+				state_generate <= WRITE_EXTERNAL_TRIGGER;
+			end if;
+		
+		
 		when WRITE_EXTERNAL_TRIGGER =>    -- external trigger ID
 			addr_out <= start_addr + conv_std_logic_vector(1, RAM_ADDR_WIDTH);
-			data_out <=	FTM_trigger_info(15 downto 0) &
-						FTM_trigger_info(31 downto 16) &
-						FTM_trigger_info(47 downto 32) &
-						X"00" & FTM_trigger_info(55 downto 48);
+			data_out <=	FTM_trigger_info_local_copy(15 downto 0) &
+						FTM_trigger_info_local_copy(31 downto 16) &
+						FTM_trigger_info_local_copy(47 downto 32) &
+						"0000000"& FTM_receiver_status & FTM_trigger_info_local_copy(55 downto 48);
 			state_generate <= WRITE_END_FLAG;
 
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd	(revision 10448)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd	(revision 10462)
@@ -3,5 +3,5 @@
 -- Created:
 --          by - daqct3.UNKNOWN (IHP110)
---          at - 08:30:59 04.03.2011
+--          at - 17:31:46 26.04.2011
 --
 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
@@ -76,5 +76,5 @@
 -- Created:
 --          by - daqct3.UNKNOWN (IHP110)
---          at - 08:30:59 04.03.2011
+--          at - 17:31:46 26.04.2011
 --
 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
@@ -116,4 +116,5 @@
       CLK                   : IN     std_logic ;
       D_T_in                : IN     std_logic_vector (1 DOWNTO 0);
+      FTM_RS485_rx_d        : IN     std_logic ;
       SROUT_in_0            : IN     std_logic ;
       SROUT_in_1            : IN     std_logic ;
@@ -131,4 +132,7 @@
       CLK_25_PS             : OUT    std_logic ;
       CLK_50                : OUT    std_logic ;
+      FTM_RS485_rx_en       : OUT    std_logic ;
+      FTM_RS485_tx_d        : OUT    std_logic ;
+      FTM_RS485_tx_en       : OUT    std_logic ;
       RSRLOAD               : OUT    std_logic                     := '0';
       SRCLK                 : OUT    std_logic                     := '0';
@@ -149,4 +153,5 @@
       sclk                  : OUT    std_logic ;
       sensor_cs             : OUT    std_logic_vector (3 DOWNTO 0);
+      trigger_veto          : OUT    std_logic                     := '1';
       wiz_addr              : OUT    std_logic_vector (9 DOWNTO 0);
       wiz_cs                : OUT    std_logic                     := '1';
@@ -191,4 +196,5 @@
    --D_T <= (others => '0');
    --D_T2 <= ( others => '0' );
+   D_T2(1) <= '0';
    -- A0_T(7 downto 0) <= (others => '0');
    --A1_T(7 downto 0) <= (others => '0');
@@ -205,12 +211,4 @@
    A0_T <= led;
    
-   -- MAX3485 for FTM trigger ID is switched into receive mode
-   RS485_E_RE <= '0';
-   RS485_E_DE <= '0';
-   -- in receive mode, the DI input of this MAX is in 'don't care' state
-   RS485_E_DO <= '0';
-   -- the receive pin is fed out as well
-   D_T2(1) <= RS485_E_DI; 
-   
    -- additional MAX3485 is switched to shutdown mode
    RS485_C_RE <= '1';  --inverted logic
@@ -223,7 +221,4 @@
    EE_CS <= '1';
 
-
-   -- ModuleWare code(v1.9) for instance 'I0' of 'gnd'
-   TRG_V <= '0';
 
    -- Instance port mappings.
@@ -235,4 +230,5 @@
          CLK                   => X_50M,
          D_T_in                => D_T_in,
+         FTM_RS485_rx_d        => RS485_E_DI,
          SROUT_in_0            => D0_SROUT,
          SROUT_in_1            => D1_SROUT,
@@ -250,4 +246,7 @@
          CLK_25_PS             => OPEN,
          CLK_50                => CLK_50,
+         FTM_RS485_rx_en       => RS485_E_RE,
+         FTM_RS485_tx_d        => RS485_E_DO,
+         FTM_RS485_tx_en       => RS485_E_DE,
          RSRLOAD               => RSRLOAD,
          SRCLK                 => SRCLK,
@@ -268,4 +267,5 @@
          sclk                  => S_CLK,
          sensor_cs             => TCS,
+         trigger_veto          => TRG_V,
          wiz_addr              => W_A,
          wiz_cs                => W_CS,
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd	(revision 10448)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd	(revision 10462)
@@ -179,4 +179,2 @@
 
 end fad_definitions;
-
-
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd	(revision 10448)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd	(revision 10462)
@@ -3,5 +3,5 @@
 -- Created:
 --          by - daqct3.UNKNOWN (IHP110)
---          at - 08:30:56 04.03.2011
+--          at - 17:31:44 26.04.2011
 --
 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
@@ -20,4 +20,5 @@
       CLK                   : IN     std_logic;
       D_T_in                : IN     std_logic_vector (1 DOWNTO 0);
+      FTM_RS485_rx_d        : IN     std_logic;
       SROUT_in_0            : IN     std_logic;
       SROUT_in_1            : IN     std_logic;
@@ -35,4 +36,7 @@
       CLK_25_PS             : OUT    std_logic;
       CLK_50                : OUT    std_logic;
+      FTM_RS485_rx_en       : OUT    std_logic;
+      FTM_RS485_tx_d        : OUT    std_logic;
+      FTM_RS485_tx_en       : OUT    std_logic;
       RSRLOAD               : OUT    std_logic                     := '0';
       SRCLK                 : OUT    std_logic                     := '0';
@@ -53,4 +57,5 @@
       sclk                  : OUT    std_logic;
       sensor_cs             : OUT    std_logic_vector (3 DOWNTO 0);
+      trigger_veto          : OUT    std_logic                     := '1';
       wiz_addr              : OUT    std_logic_vector (9 DOWNTO 0);
       wiz_cs                : OUT    std_logic                     := '1';
@@ -71,5 +76,5 @@
 -- Created:
 --          by - daqct3.UNKNOWN (IHP110)
---          at - 08:30:58 04.03.2011
+--          at - 17:31:45 26.04.2011
 --
 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
@@ -87,4 +92,5 @@
 USE IEEE.NUMERIC_STD.all;
 USE IEEE.std_logic_signed.all;
+USE fact_fad_lib.fad_rs485_constants.all;
 
 LIBRARY FACT_FAD_lib;
@@ -114,5 +120,4 @@
    SIGNAL c_trigger_mult               : std_logic_vector(15 DOWNTO 0);
    SIGNAL cont_trigger                 : std_logic;
-   SIGNAL crc                          : std_logic_vector(7 DOWNTO 0);
    SIGNAL current_dac_array            : dac_array_type                               := ( others => 0);
    SIGNAL dac_setting                  : dac_array_type                               := DEFAULT_DAC;        --<<-- default defined in fad_definitions.vhd
@@ -161,4 +166,5 @@
    SIGNAL ram_write_ready_ack          : std_logic                                    := '0';
    SIGNAL ready                        : STD_LOGIC                                    := '0';
+   SIGNAL rec_timeout_occured          : std_logic                                    := '0';
    SIGNAL reset                        : std_logic;
    SIGNAL reset_synch_i                : std_logic;
@@ -184,6 +190,4 @@
    SIGNAL trigger_or_s_trigger         : std_logic;
    SIGNAL trigger_out                  : std_logic;
-   SIGNAL trigger_type1                : std_logic_vector(7 DOWNTO 0);
-   SIGNAL trigger_type2                : std_logic_vector(7 DOWNTO 0);
    SIGNAL wiz_ack                      : std_logic;
    SIGNAL wiz_busy                     : std_logic;
@@ -208,4 +212,22 @@
 
    -- Component Declarations
+   COMPONENT FAD_rs485_receiver
+   GENERIC (
+      -- defined in fad_rs485_definitions.fad_rs485_constants
+      RX_BYTES : integer := RS485_MESSAGE_LEN_BYTES;         -- no. of bytes to receive
+      RX_WIDTH : integer := RS485_MESSAGE_LEN_BYTES * 8      -- no. of bits to receive
+   );
+   PORT (
+      rec_clk             : IN     std_logic;
+      rec_start           : IN     std_logic;
+      rx_d                : IN     std_logic;
+      rec_dout            : OUT    std_logic_vector (RX_WIDTH - 1 DOWNTO 0) := (others => '0');
+      rec_timeout_occured : OUT    std_logic                                := '0';
+      rec_valid           : OUT    std_logic                                := '0';
+      rx_en               : OUT    std_logic;
+      tx_d                : OUT    std_logic;
+      tx_en               : OUT    std_logic
+   );
+   END COMPONENT;
    COMPONENT REFCLK_counter
    PORT (
@@ -215,14 +237,4 @@
       alarm_refclk_too_low  : OUT    std_logic                      := '0';
       counter_result        : OUT    std_logic_vector (11 DOWNTO 0) := (others => '0')
-   );
-   END COMPONENT;
-   COMPONENT RS485_receiver_fake
-   PORT (
-      crc           : IN     std_logic_vector (7 DOWNTO 0);
-      trigger_no    : IN     std_logic_vector (31 DOWNTO 0);
-      trigger_type1 : IN     std_logic_vector (7 DOWNTO 0);
-      trigger_type2 : IN     std_logic_vector (7 DOWNTO 0);
-      rs465_data    : OUT    std_logic_vector (55 DOWNTO 0);
-      rs485_ready   : OUT    std_logic
    );
    END COMPONENT;
@@ -303,4 +315,5 @@
       FTM_RS485_ready            : IN     std_logic ;
       FTM_trigger_info           : IN     std_logic_vector (55 DOWNTO 0);                 --7 byte
+      FTM_receiver_status        : IN     std_logic ;
       -- EVT HEADER - part 3
       fad_event_counter          : IN     std_logic_vector (31 DOWNTO 0);
@@ -337,10 +350,11 @@
       drs_read_s_cell_ready      : IN     std_logic ;
       drs_s_cell_array           : IN     drs_s_cell_array_type ;
-      drs_readout_started        : OUT    std_logic                     := '0'
+      drs_readout_started        : OUT    std_logic                     := '0';
+      trigger_veto               : OUT    std_logic                     := '1'
    );
    END COMPONENT;
    COMPONENT dna_gen
    PORT (
-      clk   : IN     STD_LOGIC;
+      clk   : IN     STD_LOGIC ;
       dna   : OUT    STD_LOGIC_VECTOR (63 DOWNTO 0) := (others => '0');
       ready : OUT    STD_LOGIC                      := '0'
@@ -540,6 +554,6 @@
    -- Optional embedded configurations
    -- pragma synthesis_off
+   FOR ALL : FAD_rs485_receiver USE ENTITY FACT_FAD_lib.FAD_rs485_receiver;
    FOR ALL : REFCLK_counter USE ENTITY FACT_FAD_lib.REFCLK_counter;
-   FOR ALL : RS485_receiver_fake USE ENTITY FACT_FAD_lib.RS485_receiver_fake;
    FOR ALL : adc_buffer USE ENTITY FACT_FAD_lib.adc_buffer;
    FOR ALL : clock_generator_var_ps USE ENTITY FACT_FAD_lib.clock_generator_var_ps;
@@ -560,10 +574,4 @@
 
 BEGIN
-   -- Architecture concurrent statements
-   -- HDL Embedded Text Block 1 eb1
-   trigger_type1 <= "00000010";
-   trigger_type2 <= "00000000";
-   crc <= X"5A";
-
 
    -- ModuleWare code(v1.9) for instance 'I6' of 'and'
@@ -633,4 +641,20 @@
 
    -- Instance port mappings.
+   U_7 : FAD_rs485_receiver
+      GENERIC MAP (
+         RX_BYTES => RS485_MESSAGE_LEN_BYTES,            -- no. of bytes to receive
+         RX_WIDTH => RS485_MESSAGE_LEN_BYTES * 8         -- no. of bits to receive
+      )
+      PORT MAP (
+         rec_clk             => CLK_50_internal,
+         rx_d                => FTM_RS485_rx_d,
+         rx_en               => FTM_RS485_rx_en,
+         tx_d                => FTM_RS485_tx_d,
+         tx_en               => FTM_RS485_tx_en,
+         rec_start           => drs_readout_started,
+         rec_timeout_occured => rec_timeout_occured,
+         rec_dout            => rs465_data,
+         rec_valid           => FTM_RS485_ready
+      );
    REFCLK_counter_main : REFCLK_counter
       PORT MAP (
@@ -640,13 +664,4 @@
          alarm_refclk_too_high => alarm_refclk_too_high_internal,
          alarm_refclk_too_low  => alarm_refclk_too_low_internal
-      );
-   RS485_receiver_fake_instance : RS485_receiver_fake
-      PORT MAP (
-         trigger_no    => trigger_id,
-         trigger_type1 => trigger_type1,
-         trigger_type2 => trigger_type2,
-         crc           => crc,
-         rs465_data    => rs465_data,
-         rs485_ready   => FTM_RS485_ready
       );
    I_main_adc_buffer : adc_buffer
@@ -718,4 +733,5 @@
          FTM_RS485_ready            => FTM_RS485_ready,
          FTM_trigger_info           => rs465_data,
+         FTM_receiver_status        => rec_timeout_occured,
          fad_event_counter          => trigger_id,
          refclk_counter             => counter_result_internal,
@@ -747,5 +763,6 @@
          drs_read_s_cell_ready      => drs_read_s_cell_ready,
          drs_s_cell_array           => drs_s_cell_array,
-         drs_readout_started        => drs_readout_started
+         drs_readout_started        => drs_readout_started,
+         trigger_veto               => trigger_veto
       );
    dna_gen_instance : dna_gen
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_rs485_definitions.vhd
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_rs485_definitions.vhd	(revision 10462)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_rs485_definitions.vhd	(revision 10462)
@@ -0,0 +1,46 @@
+----------------------------------------------------------------------------------
+-- Company:        TU Dortmund, Lehrstuhl fuer experimentelle Physik 5b, Astroteilchenphysik 
+-- Engineer:       D.Neise
+-- 
+-- Create Date:    April 2011
+-- Design Name:    
+-- Module Name:    fad_rs485_definitions
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description:    library file for FAD design										
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- 
+-- Additional Comments: 
+--	Many thanks to Q. Weitzel
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.ALL;
+-- use IEEE.STD_LOGIC_UNSIGNED.ALL;
+-- use IEEE.NUMERIC_STD.ALL;
+
+package fad_rs485_constants is
+
+  constant FAD_RS485_INPUT_CLK_F : integer := 50000000;		-- 50MHz
+  --communication with FTM
+  constant RS485_BAUD_RATE			: integer := 250000;  	-- bits / sec in our case
+  constant RS485_MESSAGE_LEN_BYTES	: integer := 7;			-- @250kbaud --> 308us in total or (@50Mhz) 15400 clk cycles.
+  -- notes about the timeout:
+  -- the timeout is measured *after* the receiption of the 1st byte ... not after the 1st startbit.
+  -- one byte consists of 1 startbit, 8 databits, 2 stopbit2 --> 11 bits in total.
+  -- in order to have some ~10% contingency, we decided to put 13 bits instead of 11
+  --
+  -- so this timeout evaluates to 18200 clk cycles or 364us *after* the 1st byte was received.
+  -- this means, one message is trunkated only, if it is longer than ~356us in total.
+  -- this might be subject to changes.
+  -- keep in mind that, there is an additional timeout 
+  constant RS485_TIMEOUT			: integer := (RS485_MESSAGE_LEN_BYTES * 13) * (FAD_RS485_INPUT_CLK_F / RS485_BAUD_RATE);   
+
+end fad_rs485_constants;
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd	(revision 10448)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd	(revision 10462)
@@ -939,5 +939,5 @@
 						  when WR_GET_EVT_ID1 =>
 						  		event_number(31 downto 16) <= ram_data;
-						  		ram_addr <= local_ram_start_addr + 7; -- Address of LOW word of Event ID
+						  		ram_addr <= local_ram_start_addr + 9; -- Address of LOW word of Event ID
 						  		state_write <= WR_GET_EVT_ID_WAIT2;
 					  		when WR_GET_EVT_ID_WAIT2 =>
