Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd (revision 10462) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd (revision 10500) @@ -75,4 +75,5 @@ -- EVT HEADER - part 6 + runnumber : in std_logic_vector (31 downto 0); timer_value : in std_logic_vector (31 downto 0); -- time in units of 100us @@ -151,4 +152,5 @@ signal FTM_trigger_info_local_copy : std_logic_vector (55 downto 0) := (others => '0'); --7 byte +signal runnumber_local_copy : std_logic_vector (31 downto 0); -- self configuration signals: @@ -223,4 +225,5 @@ if (ram_write_ea = '1' and trigger_sr = "01") then sig_drs_readout_started <= '1'; -- is set to '0' in next state ... just a pulse. + runnumber_local_copy <= runnumber; trigger_veto <= '1'; start_read_drs_stop_cell <= '1'; @@ -290,6 +293,6 @@ when WRITE_TIMER => data_out <= - X"0000" & -- 2times 16bit reserved for additional status info - X"0000" & + runnumber_local_copy(15 downto 0) & -- 2times 16bit reserved for additional status info + runnumber_local_copy(31 downto 16) & timer_value(15 downto 0) & timer_value(31 downto 16); Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd (revision 10462) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd (revision 10500) @@ -3,5 +3,5 @@ -- Created: -- by - daqct3.UNKNOWN (IHP110) --- at - 17:31:46 26.04.2011 +-- at - 14:00:29 29.04.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) @@ -76,5 +76,5 @@ -- Created: -- by - daqct3.UNKNOWN (IHP110) --- at - 17:31:46 26.04.2011 +-- at - 14:00:29 29.04.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd (revision 10462) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd (revision 10500) @@ -159,4 +159,5 @@ constant CMD_TRIGGERS_OFF : std_logic_vector := X"19"; constant CMD_TRIGGER_S : std_logic_vector := X"20"; +constant CMD_RESET_TRIGGER_ID : std_logic_vector := X"2A"; constant CMD_START : std_logic_vector := X"22"; -- set data generator in RUN-mnode @@ -166,4 +167,6 @@ constant CMD_TRIGGER : std_logic_vector := X"A0"; constant CMD_TRIGGER_C : std_logic_vector := X"B0"; + + Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd (revision 10462) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd (revision 10500) @@ -3,5 +3,5 @@ -- Created: -- by - daqct3.UNKNOWN (IHP110) --- at - 17:31:44 26.04.2011 +-- at - 14:00:28 29.04.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) @@ -76,5 +76,5 @@ -- Created: -- by - daqct3.UNKNOWN (IHP110) --- at - 17:31:45 26.04.2011 +-- at - 14:00:29 29.04.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) @@ -121,13 +121,13 @@ SIGNAL cont_trigger : std_logic; SIGNAL current_dac_array : dac_array_type := ( others => 0); - SIGNAL dac_setting : dac_array_type := DEFAULT_DAC; --<<-- default defined in fad_definitions.vhd + SIGNAL dac_setting : dac_array_type := DEFAULT_DAC; --<<-- default defined in fad_definitions.vhd SIGNAL data_generator_config_start : std_logic := '0'; SIGNAL data_generator_config_valid : std_logic; SIGNAL data_out : std_logic_vector(63 DOWNTO 0); SIGNAL data_ram_empty : std_logic; - SIGNAL denable_inhibit : std_logic := '0'; -- default domino wave off - SIGNAL denable_prim : std_logic := '0'; -- default domino wave off - SIGNAL denable_sig : std_logic := '0'; -- default domino wave off - SIGNAL din1 : std_logic := '0'; -- default domino wave off + SIGNAL denable_inhibit : std_logic := '0'; -- default domino wave off + SIGNAL denable_prim : std_logic := '0'; -- default domino wave off + SIGNAL denable_sig : std_logic := '0'; -- default domino wave off + SIGNAL din1 : std_logic := '0'; -- default domino wave off SIGNAL dna : STD_LOGIC_VECTOR(63 DOWNTO 0) := (others => '0'); SIGNAL dout : STD_LOGIC; @@ -155,7 +155,7 @@ SIGNAL memory_manager_config_valid : std_logic; SIGNAL package_length : std_logic_vector(15 DOWNTO 0); - SIGNAL ps_direction : std_logic := '1'; -- default phase shift upwards - SIGNAL ps_do_phase_shift : std_logic := '0'; --pulse this to phase shift once - SIGNAL ps_reset : std_logic := '0'; -- pulse this to reset the variable phase shift + SIGNAL ps_direction : std_logic := '1'; -- default phase shift upwards + SIGNAL ps_do_phase_shift : std_logic := '0'; --pulse this to phase shift once + SIGNAL ps_reset : std_logic := '0'; -- pulse this to reset the variable phase shift SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0); SIGNAL ram_data : std_logic_vector(15 DOWNTO 0); @@ -167,9 +167,10 @@ SIGNAL ready : STD_LOGIC := '0'; SIGNAL rec_timeout_occured : std_logic := '0'; - SIGNAL reset : std_logic; SIGNAL reset_synch_i : std_logic; + SIGNAL reset_trigger_id : std_logic := '0'; SIGNAL roi_max : roi_max_type; SIGNAL roi_setting : roi_array_type; - SIGNAL rs465_data : std_logic_vector(55 DOWNTO 0); --7 byte + SIGNAL rs465_data : std_logic_vector(55 DOWNTO 0); --7 byte + SIGNAL runnumber : std_logic_vector(31 DOWNTO 0) := conv_std_logic_vector(0 ,31); SIGNAL s_trigger : std_logic; SIGNAL s_trigger_or_cont_trigger : std_logic; @@ -332,4 +333,5 @@ dna : IN std_logic_vector (63 DOWNTO 0); -- EVT HEADER - part 6 + runnumber : IN std_logic_vector (31 DOWNTO 0); timer_value : IN std_logic_vector (31 DOWNTO 0); -- time in units of 100us trigger : IN std_logic ; @@ -515,4 +517,6 @@ dac_setting : OUT dac_array_type := DEFAULT_DAC; --<<-- default defined in fad_definitions.vhd roi_setting : OUT roi_array_type := DEFAULT_ROI; --<<-- default defined in fad_definitions.vhd + runnumber : OUT std_logic_vector (31 DOWNTO 0) := conv_std_logic_vector(0 ,31); + reset_trigger_id : OUT std_logic := '0'; data_ram_empty : IN std_logic ; ------------------------------------------------------------------------------ @@ -600,7 +604,4 @@ denable <= denable_sig; - -- ModuleWare code(v1.9) for instance 'U_6' of 'gnd' - reset <= '0'; - -- ModuleWare code(v1.9) for instance 'U_15' of 'gnd' reset_synch_i <= '0'; @@ -746,4 +747,5 @@ TRG_GEN_div => c_trigger_mult, dna => dna, + runnumber => runnumber, timer_value => time, trigger => trigger_out, @@ -867,5 +869,5 @@ trigger_id => trigger_id, trigger => trigger_out, - reset => reset, + reset => reset_trigger_id, clk => CLK_25_PS_internal ); @@ -914,4 +916,6 @@ dac_setting => dac_setting, roi_setting => roi_setting, + runnumber => runnumber, + reset_trigger_id => reset_trigger_id, data_ram_empty => data_ram_empty, MAC_jumper => D_T_in, Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd (revision 10462) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd (revision 10500) @@ -48,6 +48,9 @@ dac_setting : out dac_array_type := DEFAULT_DAC; --<<-- default defined in fad_definitions.vhd roi_setting : out roi_array_type := DEFAULT_ROI; --<<-- default defined in fad_definitions.vhd - - data_ram_empty : IN std_logic; + + runnumber : out std_logic_vector (31 DOWNTO 0) := conv_std_logic_vector(0 ,31); + reset_trigger_id : out std_logic := '0'; + + data_ram_empty : IN std_logic; ------------------------------------------------------------------------------ @@ -184,5 +187,5 @@ signal config_addr : integer range 0 to 44; -type config_data_type is array (0 to 44) of std_logic_vector(15 downto 0); +type config_data_type is array (0 to 46) of std_logic_vector(15 downto 0); signal config_setting : config_data_type := ( -- X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", --<<-- ROIs TESTING ONLY @@ -197,5 +200,6 @@ X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", X"0400", --<<-- ROIs X"61A8", X"0000", X"0000", X"0000", X"7080", X"7080", X"7080", X"7080", --<<-- DACs - X"0000" + X"0000", + X"0000", X"0000" ); @@ -283,4 +287,6 @@ end generate dac_mapping; c_trigger_mult <= config_setting(44); + +runnumber <= config_setting(45) & config_setting(46); trigger_enable <= trigger_enable_sig; @@ -661,11 +667,11 @@ end case; - when CONFIG => + when CONFIG => -- Triggers are disabled here! trigger_enable_storage_sig <= trigger_enable_sig; -- store last value of this signal. trigger_enable_sig <= '0'; --no triggers must occur, while configurating. state_init <= WAIT_FOR_OLLI; -- now wait until the last event was send down.. - when WAIT_FOR_OLLI => - state_init <= WAIT_FOR_DATA_RAM_EMPTY; + when WAIT_FOR_OLLI => -- This single wait state is not needed, I guess. + state_init <= WAIT_FOR_DATA_RAM_EMPTY; -- should be removed asap, but not now. 28.04.11 DN @@ -803,4 +809,6 @@ s_trigger <= '0'; ps_do_phase_shift <= '0'; + reset_trigger_id <= '0'; + if (rx_packets_cnt > 0) then rx_packets_cnt <= rx_packets_cnt - '1'; @@ -882,4 +890,9 @@ ps_direction <= '0'; state_read_data <= RD_5; + + when CMD_RESET_TRIGGER_ID => + reset_trigger_id <= '1'; + state_read_data <= RD_5; + when CMD_WRITE => config_addr <= conv_integer(data_read (7 downto 0)); @@ -890,5 +903,5 @@ -- read data - -- these states are beeing precessed, if the 'command' was a 'write command' + -- these states are beeing processed, if the 'command' was a 'write command' -- so it is assumed, that some data in config RAM changed, and we need full (re)config when READ_COMMAND_DATA_SECTION => @@ -907,6 +920,8 @@ if (config_addr < 36) then update_of_rois <= '1'; - else - update_of_lessimportant <= '1'; + else + if (config_addr < 45 ) then + update_of_lessimportant <= '1'; + end if; end if; state_read_data <= RD_5;