Ignore:
Timestamp:
05/10/11 08:52:40 (14 years ago)
Author:
weitzel
Message:
FTM: keep-alive of Wiznet actiated, clock conditioner interface updated, trigger ID sending updated
File:
1 edited

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  • firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd

    r10260 r10639  
    2020-- modifications:  February 21  2011 by Patrick Vogler
    2121--                 March    23  2011 by Patrick Vogler
     22--                 May      03  2011 by Patrick Vogler and Quirin Weitzel
    2223----------------------------------------------------------------------------------
    2324
    … …  
    3738
    3839
    39 
    4040entity Clock_cond_interface is
    4141  port(
    42 
    4342   
    44 -- Clock
    45 -------------------------------------------------------------------------------
    46    clk   : IN  STD_LOGIC;               -- 50 MHz system clock
    47 
    48    
    49 -- Clock conditioner LMK03000
    50 -------------------------------------------------------------------------------
    51    CLK_Clk_Cond  : out STD_LOGIC;  -- clock conditioner MICROWIRE interface clock
    52    LE_Clk_Cond   : out STD_LOGIC;  -- clock conditioner MICROWIRE interface latch enable   
    53    DATA_Clk_Cond : out STD_LOGIC;  -- clock conditioner MICROWIRE interface data
    54    
    55    SYNC_Clk_Cond : out STD_LOGIC;  -- clock conditioner global clock synchronization
    56    LD_Clk_Cond   : in STD_LOGIC;   -- clock conditioner lock detect                 
    57 
    58    
    59 -- Time Marker
    60 -------------------------------------------------------------------------------
    61    TIM_Sel    : out STD_LOGIC;   -- Time Marker selector
     43    -- Clock
     44    -------------------------------------------------------------------------------
     45    clk   : IN  STD_LOGIC;               -- 50 MHz system clock
     46
     47   
     48    -- Clock conditioner LMK03000
     49    -------------------------------------------------------------------------------
     50    CLK_Clk_Cond  : out STD_LOGIC;  -- clock conditioner MICROWIRE interface clock
     51    LE_Clk_Cond   : out STD_LOGIC;  -- clock conditioner MICROWIRE interface latch enable   
     52    DATA_Clk_Cond : out STD_LOGIC;  -- clock conditioner MICROWIRE interface data
     53   
     54    SYNC_Clk_Cond : out STD_LOGIC;  -- clock conditioner global clock synchronization
     55    LD_Clk_Cond   : in STD_LOGIC;   -- clock conditioner lock detect                 
     56
     57   
     58    -- Time Marker
     59    -------------------------------------------------------------------------------
     60    TIM_Sel    : out STD_LOGIC;  -- Time Marker selector
    6261                                 -- 1 = time marker from Clock conditioner
    6362                                 --     for DRS timing calibration
    … …  
    6766
    6867   
    69    
    70 -- FPGA intern clock conditioner configuration data
    71 -------------------------------------------------------------------------------
    72    cc_R0             : in std_logic_vector (31 downto 0) := (others => '0');
    73    cc_R1             : in std_logic_vector (31 downto 0) := (others => '0');
    74    cc_R8             : in std_logic_vector (31 downto 0) := (others => '0');
    75    cc_R9             : in std_logic_vector (31 downto 0) := (others => '0');
    76    cc_R11            : in std_logic_vector (31 downto 0) := (others => '0');
    77    cc_R13            : in std_logic_vector (31 downto 0) := (others => '0');
    78    cc_R14            : in std_logic_vector (31 downto 0) := (others => '0');
    79    cc_R15            : in std_logic_vector (31 downto 0) := (others => '0');
    80 
    81  
    82  
    83    
    84 -- FPGA intern control signals
    85 -------------------------------------------------------------------------------
    86    start_config : in STD_LOGIC;        -- load new configuration into the clock
     68    -- FPGA intern clock conditioner configuration data
     69    -------------------------------------------------------------------------------
     70    cc_R0             : in std_logic_vector (31 downto 0) := (others => '0');
     71    cc_R1             : in std_logic_vector (31 downto 0) := (others => '0');
     72    cc_R8             : in std_logic_vector (31 downto 0) := (others => '0');
     73    cc_R9             : in std_logic_vector (31 downto 0) := (others => '0');
     74    cc_R11            : in std_logic_vector (31 downto 0) := (others => '0');
     75    cc_R13            : in std_logic_vector (31 downto 0) := (others => '0');
     76    cc_R14            : in std_logic_vector (31 downto 0) := (others => '0');
     77    cc_R15            : in std_logic_vector (31 downto 0) := (others => '0');
     78
     79   
     80    -- FPGA intern control signals
     81    -------------------------------------------------------------------------------
     82    start_config : in STD_LOGIC;       -- load new configuration into the clock
    8783                                       -- conditioner
    8884   
    89    config_started : out STD_LOGIC;     -- indicates that the new configuration
     85    config_started : out STD_LOGIC;    -- indicates that the new configuration
    9086                                       -- is currently loaded into the clock conditioner
    9187
    92    config_done : out STD_LOGIC;        -- indicates that the configuration has
     88    config_done : out STD_LOGIC;       -- indicates that the configuration has
    9389                                       -- been loaded and the clock conditioners
    9490                                       -- PLL is locked
    9591
    96    timemarker_select: in STD_LOGIC     -- selects time marker source
     92    timemarker_select: in STD_LOGIC    -- selects time marker source
    9793                                       --
    9894                                       -- 1 = time marker from Clock conditioner
    … …  
    106102
    107103
    108 
    109 
    110104architecture Behavioral of Clock_cond_interface is
    111105 
    112106 
    113 component microwire_interface IS
    114    PORT(
     107  component microwire_interface IS
     108    PORT(
    115109      clk               : IN     std_logic;
    116110      clk_uwire         : OUT    std_logic;  --- IN or OUT ?         
    … …  
    121115      config_ready      : OUT    std_logic;
    122116      config_started    : OUT    std_logic     
    123    );
    124 end component;
    125 
    126 
     117    );
     118  end component;
    127119
    128120 
    129121  signal clk_50M_sig : STD_LOGIC;       -- system clock
    130 --  signal start_config_sig : STD_LOGIC; 
     122  --signal start_config_sig : STD_LOGIC; 
    131123
    132124  signal config_ready_sig : STD_LOGIC;
    … …  
    154146  signal cc_R15_sig            : std_logic_vector (31 downto 0);
    155147
    156 
     148  signal timemarker_select_sig : std_logic := '0';
     149
     150  type TIM_SEL_STATE_TYPE is (IDLE, CONFIG);
     151  signal tim_sel_state : TIM_SEL_STATE_TYPE := IDLE;
    157152
    158153
    … …  
    173168        config_ready        => config_ready_sig,
    174169        config_started      => config_started_sig
    175        );
     170    );
    176171
    177172 
    178173       
    179   config_done <= config_ready_sig;  -- indicates that the configuration
     174  --config_done <= config_ready_sig;  -- indicates that the configuration
    180175                                    -- has been loaded
    181176
    182177
    183178 
    184  -- config_done <= (config_ready_sig AND LD_Clk_Cond);  -- indicates that the configuration
     179  config_done <= (config_ready_sig AND LD_Clk_Cond);  -- indicates that the configuration
    185180                                                      -- has been loaded and
    186181                                                      -- the PLL is locked again
    … …  
    188183
    189184 
    190   TIM_Sel <= timemarker_select;                                   
     185  --TIM_Sel <= timemarker_select;                                   
     186
     187  TIM_Sel <= timemarker_select_sig;
     188
     189  tim_sel_proc : process (clk_uwire_sig)
     190  begin
     191    if rising_edge(clk_uwire_sig) then
     192      case tim_sel_state is
     193        when IDLE =>
     194          if start_config = '1' then
     195            timemarker_select_sig <= '0';
     196            tim_sel_state <= CONFIG;
     197          end if;
     198        when CONFIG =>
     199          if config_ready_sig = '1' then
     200            timemarker_select_sig <= timemarker_select;
     201            tim_sel_state <= IDLE;
     202          end if;
     203       end case;
     204     end if;
     205  end process tim_sel_proc;
     206     
     207           
    191208  CLK_Clk_Cond <= clk_uwire_sig;
    192209
    193210  clk_50M_sig <= clk;
    194  -- start_config_sig <= start_config;
    195 
    196  --  start_config <= start_config_sig;     
    197 
    198 
     211 
     212  -- start_config_sig <= start_config;
     213  --  start_config <= start_config_sig;     
    199214  config_started <= config_started_sig;
    200215
    … …  
    233248  clk_cond_array_sig(14) <= cc_R15_sig;
    234249
    235 
    236250end Behavioral;
    237 
    238 
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