Index: firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd =================================================================== --- firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd (revision 10260) +++ firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd (revision 10639) @@ -20,4 +20,5 @@ -- modifications: February 21 2011 by Patrick Vogler -- March 23 2011 by Patrick Vogler +-- May 03 2011 by Patrick Vogler and Quirin Weitzel ---------------------------------------------------------------------------------- @@ -37,27 +38,25 @@ - entity Clock_cond_interface is port( - --- Clock -------------------------------------------------------------------------------- - clk : IN STD_LOGIC; -- 50 MHz system clock - - --- Clock conditioner LMK03000 -------------------------------------------------------------------------------- - CLK_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface clock - LE_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface latch enable - DATA_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface data - - SYNC_Clk_Cond : out STD_LOGIC; -- clock conditioner global clock synchronization - LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect - - --- Time Marker -------------------------------------------------------------------------------- - TIM_Sel : out STD_LOGIC; -- Time Marker selector + -- Clock + ------------------------------------------------------------------------------- + clk : IN STD_LOGIC; -- 50 MHz system clock + + + -- Clock conditioner LMK03000 + ------------------------------------------------------------------------------- + CLK_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface clock + LE_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface latch enable + DATA_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface data + + SYNC_Clk_Cond : out STD_LOGIC; -- clock conditioner global clock synchronization + LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect + + + -- Time Marker + ------------------------------------------------------------------------------- + TIM_Sel : out STD_LOGIC; -- Time Marker selector -- 1 = time marker from Clock conditioner -- for DRS timing calibration @@ -67,32 +66,29 @@ - --- FPGA intern clock conditioner configuration data -------------------------------------------------------------------------------- - cc_R0 : in std_logic_vector (31 downto 0) := (others => '0'); - cc_R1 : in std_logic_vector (31 downto 0) := (others => '0'); - cc_R8 : in std_logic_vector (31 downto 0) := (others => '0'); - cc_R9 : in std_logic_vector (31 downto 0) := (others => '0'); - cc_R11 : in std_logic_vector (31 downto 0) := (others => '0'); - cc_R13 : in std_logic_vector (31 downto 0) := (others => '0'); - cc_R14 : in std_logic_vector (31 downto 0) := (others => '0'); - cc_R15 : in std_logic_vector (31 downto 0) := (others => '0'); - - - - --- FPGA intern control signals -------------------------------------------------------------------------------- - start_config : in STD_LOGIC; -- load new configuration into the clock + -- FPGA intern clock conditioner configuration data + ------------------------------------------------------------------------------- + cc_R0 : in std_logic_vector (31 downto 0) := (others => '0'); + cc_R1 : in std_logic_vector (31 downto 0) := (others => '0'); + cc_R8 : in std_logic_vector (31 downto 0) := (others => '0'); + cc_R9 : in std_logic_vector (31 downto 0) := (others => '0'); + cc_R11 : in std_logic_vector (31 downto 0) := (others => '0'); + cc_R13 : in std_logic_vector (31 downto 0) := (others => '0'); + cc_R14 : in std_logic_vector (31 downto 0) := (others => '0'); + cc_R15 : in std_logic_vector (31 downto 0) := (others => '0'); + + + -- FPGA intern control signals + ------------------------------------------------------------------------------- + start_config : in STD_LOGIC; -- load new configuration into the clock -- conditioner - config_started : out STD_LOGIC; -- indicates that the new configuration + config_started : out STD_LOGIC; -- indicates that the new configuration -- is currently loaded into the clock conditioner - config_done : out STD_LOGIC; -- indicates that the configuration has + config_done : out STD_LOGIC; -- indicates that the configuration has -- been loaded and the clock conditioners -- PLL is locked - timemarker_select: in STD_LOGIC -- selects time marker source + timemarker_select: in STD_LOGIC -- selects time marker source -- -- 1 = time marker from Clock conditioner @@ -106,11 +102,9 @@ - - architecture Behavioral of Clock_cond_interface is -component microwire_interface IS - PORT( + component microwire_interface IS + PORT( clk : IN std_logic; clk_uwire : OUT std_logic; --- IN or OUT ? @@ -121,12 +115,10 @@ config_ready : OUT std_logic; config_started : OUT std_logic - ); -end component; - - + ); + end component; signal clk_50M_sig : STD_LOGIC; -- system clock --- signal start_config_sig : STD_LOGIC; + --signal start_config_sig : STD_LOGIC; signal config_ready_sig : STD_LOGIC; @@ -154,5 +146,8 @@ signal cc_R15_sig : std_logic_vector (31 downto 0); - + signal timemarker_select_sig : std_logic := '0'; + + type TIM_SEL_STATE_TYPE is (IDLE, CONFIG); + signal tim_sel_state : TIM_SEL_STATE_TYPE := IDLE; @@ -173,14 +168,14 @@ config_ready => config_ready_sig, config_started => config_started_sig - ); + ); - config_done <= config_ready_sig; -- indicates that the configuration + --config_done <= config_ready_sig; -- indicates that the configuration -- has been loaded - -- config_done <= (config_ready_sig AND LD_Clk_Cond); -- indicates that the configuration + config_done <= (config_ready_sig AND LD_Clk_Cond); -- indicates that the configuration -- has been loaded and -- the PLL is locked again @@ -188,13 +183,33 @@ - TIM_Sel <= timemarker_select; + --TIM_Sel <= timemarker_select; + + TIM_Sel <= timemarker_select_sig; + + tim_sel_proc : process (clk_uwire_sig) + begin + if rising_edge(clk_uwire_sig) then + case tim_sel_state is + when IDLE => + if start_config = '1' then + timemarker_select_sig <= '0'; + tim_sel_state <= CONFIG; + end if; + when CONFIG => + if config_ready_sig = '1' then + timemarker_select_sig <= timemarker_select; + tim_sel_state <= IDLE; + end if; + end case; + end if; + end process tim_sel_proc; + + CLK_Clk_Cond <= clk_uwire_sig; clk_50M_sig <= clk; - -- start_config_sig <= start_config; - - -- start_config <= start_config_sig; - - + + -- start_config_sig <= start_config; + -- start_config <= start_config_sig; config_started <= config_started_sig; @@ -233,6 +248,3 @@ clk_cond_array_sig(14) <= cc_R15_sig; - end Behavioral; - -