Index: /firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd =================================================================== --- /firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd (revision 10638) +++ /firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd (revision 10639) @@ -20,4 +20,5 @@ -- modifications: February 21 2011 by Patrick Vogler -- March 23 2011 by Patrick Vogler +-- May 03 2011 by Patrick Vogler and Quirin Weitzel ---------------------------------------------------------------------------------- @@ -37,27 +38,25 @@ - entity Clock_cond_interface is port( - --- Clock -------------------------------------------------------------------------------- - clk : IN STD_LOGIC; -- 50 MHz system clock - - --- Clock conditioner LMK03000 -------------------------------------------------------------------------------- - CLK_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface clock - LE_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface latch enable - DATA_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface data - - SYNC_Clk_Cond : out STD_LOGIC; -- clock conditioner global clock synchronization - LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect - - --- Time Marker -------------------------------------------------------------------------------- - TIM_Sel : out STD_LOGIC; -- Time Marker selector + -- Clock + ------------------------------------------------------------------------------- + clk : IN STD_LOGIC; -- 50 MHz system clock + + + -- Clock conditioner LMK03000 + ------------------------------------------------------------------------------- + CLK_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface clock + LE_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface latch enable + DATA_Clk_Cond : out STD_LOGIC; -- clock conditioner MICROWIRE interface data + + SYNC_Clk_Cond : out STD_LOGIC; -- clock conditioner global clock synchronization + LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect + + + -- Time Marker + ------------------------------------------------------------------------------- + TIM_Sel : out STD_LOGIC; -- Time Marker selector -- 1 = time marker from Clock conditioner -- for DRS timing calibration @@ -67,32 +66,29 @@ - --- FPGA intern clock conditioner configuration data -------------------------------------------------------------------------------- - cc_R0 : in std_logic_vector (31 downto 0) := (others => '0'); - cc_R1 : in std_logic_vector (31 downto 0) := (others => '0'); - cc_R8 : in std_logic_vector (31 downto 0) := (others => '0'); - cc_R9 : in std_logic_vector (31 downto 0) := (others => '0'); - cc_R11 : in std_logic_vector (31 downto 0) := (others => '0'); - cc_R13 : in std_logic_vector (31 downto 0) := (others => '0'); - cc_R14 : in std_logic_vector (31 downto 0) := (others => '0'); - cc_R15 : in std_logic_vector (31 downto 0) := (others => '0'); - - - - --- FPGA intern control signals -------------------------------------------------------------------------------- - start_config : in STD_LOGIC; -- load new configuration into the clock + -- FPGA intern clock conditioner configuration data + ------------------------------------------------------------------------------- + cc_R0 : in std_logic_vector (31 downto 0) := (others => '0'); + cc_R1 : in std_logic_vector (31 downto 0) := (others => '0'); + cc_R8 : in std_logic_vector (31 downto 0) := (others => '0'); + cc_R9 : in std_logic_vector (31 downto 0) := (others => '0'); + cc_R11 : in std_logic_vector (31 downto 0) := (others => '0'); + cc_R13 : in std_logic_vector (31 downto 0) := (others => '0'); + cc_R14 : in std_logic_vector (31 downto 0) := (others => '0'); + cc_R15 : in std_logic_vector (31 downto 0) := (others => '0'); + + + -- FPGA intern control signals + ------------------------------------------------------------------------------- + start_config : in STD_LOGIC; -- load new configuration into the clock -- conditioner - config_started : out STD_LOGIC; -- indicates that the new configuration + config_started : out STD_LOGIC; -- indicates that the new configuration -- is currently loaded into the clock conditioner - config_done : out STD_LOGIC; -- indicates that the configuration has + config_done : out STD_LOGIC; -- indicates that the configuration has -- been loaded and the clock conditioners -- PLL is locked - timemarker_select: in STD_LOGIC -- selects time marker source + timemarker_select: in STD_LOGIC -- selects time marker source -- -- 1 = time marker from Clock conditioner @@ -106,11 +102,9 @@ - - architecture Behavioral of Clock_cond_interface is -component microwire_interface IS - PORT( + component microwire_interface IS + PORT( clk : IN std_logic; clk_uwire : OUT std_logic; --- IN or OUT ? @@ -121,12 +115,10 @@ config_ready : OUT std_logic; config_started : OUT std_logic - ); -end component; - - + ); + end component; signal clk_50M_sig : STD_LOGIC; -- system clock --- signal start_config_sig : STD_LOGIC; + --signal start_config_sig : STD_LOGIC; signal config_ready_sig : STD_LOGIC; @@ -154,5 +146,8 @@ signal cc_R15_sig : std_logic_vector (31 downto 0); - + signal timemarker_select_sig : std_logic := '0'; + + type TIM_SEL_STATE_TYPE is (IDLE, CONFIG); + signal tim_sel_state : TIM_SEL_STATE_TYPE := IDLE; @@ -173,14 +168,14 @@ config_ready => config_ready_sig, config_started => config_started_sig - ); + ); - config_done <= config_ready_sig; -- indicates that the configuration + --config_done <= config_ready_sig; -- indicates that the configuration -- has been loaded - -- config_done <= (config_ready_sig AND LD_Clk_Cond); -- indicates that the configuration + config_done <= (config_ready_sig AND LD_Clk_Cond); -- indicates that the configuration -- has been loaded and -- the PLL is locked again @@ -188,13 +183,33 @@ - TIM_Sel <= timemarker_select; + --TIM_Sel <= timemarker_select; + + TIM_Sel <= timemarker_select_sig; + + tim_sel_proc : process (clk_uwire_sig) + begin + if rising_edge(clk_uwire_sig) then + case tim_sel_state is + when IDLE => + if start_config = '1' then + timemarker_select_sig <= '0'; + tim_sel_state <= CONFIG; + end if; + when CONFIG => + if config_ready_sig = '1' then + timemarker_select_sig <= timemarker_select; + tim_sel_state <= IDLE; + end if; + end case; + end if; + end process tim_sel_proc; + + CLK_Clk_Cond <= clk_uwire_sig; clk_50M_sig <= clk; - -- start_config_sig <= start_config; - - -- start_config <= start_config_sig; - - + + -- start_config_sig <= start_config; + -- start_config <= start_config_sig; config_started <= config_started_sig; @@ -233,6 +248,3 @@ clk_cond_array_sig(14) <= cc_R15_sig; - end Behavioral; - - Index: /firmware/FTM/FTM_central_control.vhd =================================================================== --- /firmware/FTM/FTM_central_control.vhd (revision 10638) +++ /firmware/FTM/FTM_central_control.vhd (revision 10639) @@ -80,5 +80,6 @@ start_run_num_events : IN std_logic_vector (31 DOWNTO 0); trigger_start : out std_logic := '0'; - trigger_stop : out std_logic := '1' + trigger_stop : out std_logic := '1'; + enable_ID_sending : out std_logic := '0' ); end FTM_central_control; @@ -248,4 +249,5 @@ trigger_start <= '1'; trigger_stop <= '0'; + enable_Id_sending <= '1'; if (new_config = '1') then config_started <= '1'; @@ -270,4 +272,5 @@ trigger_start <= '0'; trigger_stop <= '1'; + enable_Id_sending <= '0'; state_central_proc <= CP_RUNNING_02; end if; Index: /firmware/FTM/FTM_top.vhd =================================================================== --- /firmware/FTM/FTM_top.vhd (revision 10638) +++ /firmware/FTM/FTM_top.vhd (revision 10639) @@ -122,5 +122,5 @@ SYNC_Clk_Cond : out STD_LOGIC; -- global clock synchronization - LD_Clk_Cond : in STD_LOGIC; -- lock detect, should be checked for + LD_Clk_Cond : in STD_LOGIC; -- lock detect @@ -400,4 +400,6 @@ signal trigger_start_sig : std_logic; signal trigger_stop_sig : std_logic; + + signal enable_ID_sending_sig : std_logic; -- component FTM_clk_gen @@ -561,5 +563,6 @@ start_run_num_events : IN std_logic_vector (31 DOWNTO 0); trigger_start : out std_logic; - trigger_stop : out std_logic + trigger_stop : out std_logic; + enable_ID_sending : out std_logic ); end component; @@ -942,5 +945,6 @@ start_run_num_events => start_run_num_events_sig, trigger_start => trigger_start_sig, - trigger_stop => trigger_stop_sig + trigger_stop => trigger_stop_sig, + enable_ID_sending => enable_ID_sending_sig ); @@ -1009,5 +1013,7 @@ rx_d_3 => Bus2_RxD_3, tx_d_3 => Bus2_TxD_3, - enable_ID_sending => '1', + --enable_ID_sending => trigger_start_sig, + enable_ID_sending => enable_ID_sending_sig, + --enable_ID_sending => '1', TIM_source => general_settings_sig(0), LP_settings => "0000", Index: /firmware/FTM/ethernet/w5300_modul.vhd =================================================================== --- /firmware/FTM/ethernet/w5300_modul.vhd (revision 10638) +++ /firmware/FTM/ethernet/w5300_modul.vhd (revision 10639) @@ -18,5 +18,5 @@ -- ---------------------------------------------------------------------------------- --- hds interface_start + LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; @@ -117,8 +117,8 @@ type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA, INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, - SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, SEND_FTU_ERROR, + SI, SI0, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, SEND_FTU_ERROR, READ_DATA, WRITE_TO_SD_ADDR, READ_FTU_ERROR, READ_FROM_SD_ADDR, READ_FROM_DD_ADDR, READ_FROM_FL_ADDR, READ_FROM_HEADER_MODUL); type state_write_type is (WR_START, WR_LENGTH, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08, - WR_WRITE_START_DEL, WR_GET_HEADER, WR_GET_HEADER_WAIT, WR_FIFO_DATA, WR_FIFO_DATA_01, WR_FIFO_HEADER, WR_FIFO_HEADER_01, WR_WRITE_END_DEL); + WR_WRITE_START_DEL, WR_GET_HEADER, WR_GET_HEADER_WAIT, WR_SD_ADDR, WR_FIFO_DATA, WR_FIFO_DATA_01, WR_FIFO_HEADER, WR_FIFO_HEADER_01, WR_WRITE_END_DEL); type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04); type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06); @@ -179,4 +179,5 @@ signal cmd_array : cmd_array_type; signal internal_cmd : std_logic := '0'; + signal wait_for_data_flag : std_logic := '0'; signal autosend_flag : std_logic := '1'; @@ -461,4 +462,10 @@ par_data <= X"0101"; -- ALIGN, TCP state_init <= WRITE_REG; + next_state <= SI0; + -- keep alive + when SI0 => + par_addr <= W5300_S0_KPALVTR + socket_cnt * W5300_S_INC; + par_data <= X"0C00"; -- 12 * 5s = 60s + state_init <= WRITE_REG; next_state <= SI1; -- Sx Interrupt Mask @@ -520,4 +527,5 @@ ftu_error_send_ready <= '0'; led_int <= X"00"; + wait_for_data_flag <= '0'; -- -- -- else @@ -560,5 +568,5 @@ state_init <= READ_DATA; busy <= '1'; - elsif (dd_send = '1') then + elsif ((dd_send = '1') and (wait_for_data_flag = '0')) then internal_cmd <= '1'; dd_send_ack <= '1'; @@ -569,5 +577,5 @@ state_read_data <= RD_READ_DD_BLOCK; state_init <= READ_DATA; - elsif (ftu_error_send = '1') then + elsif ((ftu_error_send = '1') and (wait_for_data_flag = '0')) then ftu_error_send_ack <= '1'; ftu_error_send_ready <= '0'; @@ -697,4 +705,5 @@ when PAR_START_X_EVNTS => next_state_read_data <= RD_X_EVNTS; + wait_for_data_flag <= '1'; state_read_data <= RD_5; when others => @@ -721,10 +730,10 @@ -- write to address in static data block when PAR_WRITE_SD_ADDR => - new_config_flag <= '1'; + wait_for_data_flag <= '1'; next_state_read_data <= RD_WRITE_SD_ADDR; state_read_data <= RD_5; -- write static data block when PAR_WRITE_SD => - new_config_flag <= '1'; + wait_for_data_flag <= '1'; next_state_read_data <= RD_WRITE_SD_BLOCK; state_read_data <= RD_5; @@ -737,4 +746,5 @@ -- read from address in static data block when PAR_READ_SD_ADDR => + wait_for_data_flag <= '1'; next_state_read_data <= RD_READ_SD_ADDR; state_read_data <= RD_5; @@ -865,4 +875,5 @@ local_write_length <= '0' & X"0001"; -- one word will be written to ethernet next_state_read_data <= RD_CMD; + wait_for_data_flag <= '0'; next_state <= READ_DATA; state_init <= WRITE_DATA; @@ -879,4 +890,6 @@ if (next_packet_data_cnt = (SD_BLOCK_SIZE - 1)) then next_packet_data_cnt <= 0; + wait_for_data_flag <= '0'; + new_config_flag <= '1'; next_state_read_data <= RD_CMD; end if; @@ -891,4 +904,6 @@ local_sd_data <= data_read; next_packet_data_cnt <= 0; + wait_for_data_flag <= '0'; + new_config_flag <= '1'; next_state_read_data <= RD_CMD; next_state <= READ_DATA; @@ -907,4 +922,5 @@ start_run <= '0'; next_packet_data_cnt <= 0; + wait_for_data_flag <= '0'; next_state_read_data <= RD_CMD; state_read_data <= RD_5; @@ -1106,4 +1122,5 @@ -- Fill FIFO + -- write header when WR_FIFO_HEADER => state_init <= READ_FROM_HEADER_MODUL; @@ -1120,7 +1137,21 @@ state_write <= WR_FIFO_HEADER; else - state_write <= WR_FIFO_DATA; - end if; - + if (data_package_type = FTM_PACKAGE_TYPE_SD_WORD) then + state_write <= WR_SD_ADDR; + else + state_write <= WR_FIFO_DATA; + end if; + end if; + + -- write static data ram address (only for single address request) + when WR_SD_ADDR => + write_length_bytes <= write_length_bytes + 2; -- one extra word to write + par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; + par_data <= "0000" & local_sd_addr; + state_init <= WRITE_REG; + next_state <= WRITE_DATA; + state_write <= WR_FIFO_DATA; + + -- write data when WR_FIFO_DATA => state_init <= read_addr_state; Index: /firmware/FTM/ftm_definitions.vhd =================================================================== --- /firmware/FTM/ftm_definitions.vhd (revision 10638) +++ /firmware/FTM/ftm_definitions.vhd (revision 10639) @@ -46,4 +46,6 @@ -- changed FTM_HEADER_LENGTH to 0x0E -- kw 20.04.: added "package types", SD_SINGLE_WORD_SIZE +-- +-- kw 28.04.: changed SD_SINGLE_WORD_SIZE to X"002", added W5300_S0_KPALVTR (keep alive) -- ---------------------------------------------------------------------------------- @@ -189,4 +191,5 @@ constant W5300_S0_DPORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"12"; constant W5300_S0_DIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"14"; + constant W5300_S0_KPALVTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"1A"; constant W5300_S0_TX_WRSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"20"; constant W5300_S0_TX_FSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"24"; @@ -270,5 +273,5 @@ constant SD_FTU_ACTIVE_NUM : integer := 4; -- number of active FTU lists (cr0 to cr3) constant SD_BLOCK_SIZE : std_logic_vector (11 downto 0) := X"1B4"; -- total size of static data block - constant SD_SINGLE_WORD_SIZE : std_logic_vector := X"001"; + constant SD_SINGLE_WORD_SIZE : std_logic_vector := X"002"; -- dynamic data block