Index: /firmware/FSC/doc/FSC.aux =================================================================== --- /firmware/FSC/doc/FSC.aux (revision 10668) +++ /firmware/FSC/doc/FSC.aux (revision 10668) @@ -0,0 +1,32 @@ +\relax +\@writefile{toc}{\contentsline {section}{\numberline {1}Basic Facts and Purpose}{1}} +\@writefile{toc}{\contentsline {subsection}{\numberline {1.1}Measuring}{1}} +\newlabel{sec_measuring}{{1.1}{1}} +\@writefile{toc}{\contentsline {subsubsection}{\numberline {1.1.1}RTD switching}{2}} +\@writefile{toc}{\contentsline {subsection}{\numberline {1.2}The Telegram}{2}} +\@writefile{lot}{\contentsline {table}{\numberline {1}{\ignorespaces composition of FSC telegram}}{2}} +\newlabel{tbl_telegram}{{1}{2}} +\@writefile{lot}{\contentsline {table}{\numberline {2}{\ignorespaces composition of the sensor ID - ad exemplum}}{2}} +\newlabel{tdl_sensor_id}{{2}{2}} +\@writefile{toc}{\contentsline {subsection}{\numberline {1.3}Sensor Data}{2}} +\newlabel{sec_sensor_data}{{1.3}{2}} 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+\documentclass[a4paper]{article} + +\setlength{\topmargin}{0mm} %1 inch is always there! +\setlength{\oddsidemargin}{0mm} %1 inch is always there! +\setlength{\evensidemargin}{0mm} %1 inch is always there! + +\setlength{\textwidth}{16cm} +\setlength{\textheight}{25cm} + + +\setlength{\headheight}{0mm} +\setlength{\headsep}{0mm} + + + +%um die deutschen Umlaute eingeben zu können +% müssen diese 3 Pakete eingebunden werden. +% welches der Pakete was macht, weiss ich nicht. +\usepackage[T1]{fontenc} +\usepackage[latin1]{inputenc} +%\usepackage{ngerman} % nur wenn z.B. 'Inhaltsverzeichnis' auch deutsch sein soll. + +\usepackage{graphicx} % for pictures +\usepackage{float} % for figures with english descriptions + +\restylefloat{figure} % can nor force it with H +\restylefloat{table} % can nor force it with H + +\title{FSC - facts about the board} +\author{D. Neise} +\date{07.02.2011} + +\begin{document} + +%title page contains TOC +\maketitle +\tableofcontents +%\newpage + +%\listoffigures +%\listoftables + +\section{Basic Facts and Purpose} +% no pictures in SVN repos ... no space. +%\emph{picture here - 3D model of FSC} + +This document presents electronic facts and figures of FACTs FSC board. FSC stands for {\bf F}act {\bf S}low {\bf C}ontrol. The name is a bit misleading, since the boards sole purpose is to monitor slowly changing parameters, such as: +\begin{itemize} + \item up to 64 temperatures (RTD sensors, e.g. Pt1000 or Pt100), + \item up to 4 humidities (designed for Honeywell HIH-40xx family), + \item the DC levels of all 36 FACT low voltage supply channels, + \item the current consumption on each LV-channel (actually a dc-voltage\footnote{see FLV specs for further details}). +\end{itemize} + +FSC uses an 8MHz ATmega32L micro controller(MCU) to readout the muxed 24bit sigma delta ADC (AD7719) which is connected to the RTDs. In addition the ATmegas internal 10bit ADC is used to monitor the humidity, LV-voltages and LV-currents. +The muxers on FSC belong to analog devices ADG77xx family, and are controlled by the MCU. +The User has access to FSC via Ethernet Interface, provided by WIZNETs W5100, the younger brother of W5300, which is used on FACTs FAD boards. + +AD7719 and W5100 communicate with the MCU via an SPI bus, which results in the fact, that a lot of user interaction might slow down temperature measurement or vice versa. Additionally the user should be aware, that sigma delta ADCs have a prolonged settling time, when muxed. Redout of all 64 temperature channels takes about 13s, while one single channel might be readout with at a rate of 10Hz. In addition FSC runs a 32bit timer, counting miliseconds since timer init. The timer is initialized to zero, when FSC is powered. User may synchronize FSCs timer to Unix time. + +\subsection{Measuring} +\label{sec_measuring} +The user may send a command telling FSC, what to measure. FSC will measure it and return the result, right after the measurement was finished. It is possible to tell FSC to measure several sensors at a time. +Users may issue an 'activate' command (see table \ref{tbl_FSC_CMDS}), to specify which channel should be measured during the next measurement phase. In case one is not sure which channel was activated beforehand users may issue a 'status' command, to gather information about FSCs current status. Whenever the user completed the channel activation process the 'measure' commands may be issued. Since the high resolution ADC AD7719 used for resistance measurement and the 10bit ADC used for voltage measurement run independently on different time scales, different 'measure' commands are defined. 'measure resistances' will start a measurement possibly taking some seconds, while 'measure voltages' will be ready almost instantaneosly. +Since a measurement might take some time, FSC generates an answer, once the 'measure' command received, informing the user about the command reception. The results are then submitted in a single message to the user, which is called a telegram. +During a 'measure resistance' FSC is not checking for incoming commands. So incoming commands will pile up in W5100 input FIFO. Which means, sending a lot of on demand commands will delay FSCs reaction to the following commands consecutivly. +The W5100 transmission FIFO can recieve 4kbyte. I am not sure what happens in case this FIFO is completely full, but I guess W5100 will reject incoming TCP/IP packets and the user side PC will constantly keep on (re)sending them. Since a typical command consists of less than 10bytes it is necessary to send a lot of commands without receiving any answer before the FSC FIFO is full. +The theoretical limit for data readout from the W5100 FIFO into the ATmega microncontroller is about 98kbyte/s. + +\subsubsection{RTD switching} +FSCs high resolution ADC AD7719 only bears one single input channel. So the RTDs are beeing multiplexed during the resistance measurement. This multplexing includes the RTDs current supply of about $400\,{\mu}A$. In case the RTDs are near to FACTs G-APD signal lines, low frequency crosstalk might be induced due to these switching processes. +In case of FACT there might be two families of RTDs. About 30 pieces will be mounted next to the G-APDs, while a smaller number of sensors will be mounted in the electronics compartement, where this kind of noise will not contribute much. +Maybe this swithcing noise can be completely cancelled by parallel capacities of $C_P \approx 10\,{\mu}F$. + + +\subsection{The Telegram} +As previously outlined the results of a measurement will be submitted in a single message called telegram. The format of this telegram is given in table (\ref{tbl_telegram}). Despite the fact that the measurement of several RTDs might take several seconds, the storage and transmission of the time of each temperature measurement is regarded as too much overhead, hence the time of the last measurement taken for a telegram is submitted within. Subsequent all activated sensor measurement results are beeing transmitted. A result always consists of a sensor ID and the actual data. Detailed information about the composition of the sensor ID can be found in table (\ref{tdl_sensor_id}). The data might be either 3 byte in case of an RTD or 2 byte in case of all other sensors. For detailed information of sensor data see section \ref{sec_sensor_data}. +\begin{table}[htpb] +\begin{tabular}{|l|l|l|} +\hline +address & mnemonic & description \\ +\hline +byte 0 & 0x00 & special telegram header \\ +byte 1..2 & length & length of telegram in byte \\ +byte 3...6 & time & time, when measurement was finished.\\ +byte 7 & sensor ID 0 & \\ +byte 8..x & data 0 & data field is eigther 2 or 3 byte wide. \\ + & & depending of sensor type. \\ +\hline +byte ... & ... & sensor IDs and data until end.\\ +\hline +\end{tabular} +\caption{composition of FSC telegram} +\label{tbl_telegram} +\end{table} + +\begin{table}[htpb] +\begin{tabular}{|l|l|l|} +\hline +ID bits & meaning \\ +\hline +00pp.psss & temperatur sensor no. sss on port ppp \\ +01vv.vvvv & voltage sensor no. vvvvvv (between 0..35) \\ +10cc.cccc & current sensor no. cccccc (between 0..35)\\ +1100.0hhh & humidity sensor no. hhh \\ +&\\ +... & to be completed \\ +\hline +\end{tabular} +\caption{composition of the sensor ID - ad exemplum} +\label{tdl_sensor_id} +\end{table} + +\subsection{Sensor Data} +\label{sec_sensor_data} +FSC supports many different sensors. The first type is any resistive sensor, such as RTDs. The second type is any sensor outputting a voltage between 0VDC and 4.096VDC. In order to keep the firmware independent from the sensors and to keep it as simple as possible, the measured data is treated as less as possible before beeing output. + +Since the resistance measurement is perfomed in a ratiometric manner, the resistance is measured as a 24bit fraction of an onboard fix reference resistor of $\mathrm{R_{ref}} \approx 6.25 \mathrm{k\Omega}$ (see table \ref{tbl_REG_overview}). The value of $\mathrm{R_{ref}}$ is not stored as a constant value, so the user should measure its value once and submit it to the FSC. In case no value is submitted, $\mathrm{R_{ref}} = 6.25\,k\Omega$ is assumed. +FSC does not multiply the measured fraction with the reference resistance. Hence the resistance is unknown on FSC and cannot be transformed into a temperature. Similarly the current of the low voltage supply channels, which is converted into a voltage level and measured by FSC is not beeing treated in any way by the MCU but directly transmitted to the user via ethernet. +The format of each sensor data is given in table \ref{tbl_sensor_data_format}. +\begin{table}[htpb] +\begin{tabular}{|l|l|l|l|l|l|} +\hline +sensor name & actual physical value & resolution & width & format & unit \\ +\hline +temperature & resistance &24 or 16 bit & 24 & unsigned int & fraction of $\mathrm{R_{ref}}$ \\ +humidity & voltage & 10 bit & 16 & unsigned int & V \\ +voltage & voltage & 10 bit & 16 & unsigned int & V \\ +current & voltage & 10 bit & 16 & unsigned int & V \\ +\hline +\end{tabular} +\caption{sensor data format} +\label{tbl_sensor_data_format} +\end{table} + + + + +\section{Ethernet Interface} +FSC runs as a TCP/IP server, this means after W5100 was initialized, FSC will listen on a Port, but will not attempt to connect to any server. Since W5100 does not support DHCP, FSC has a fix IP\footnote{see FACT Elogbook / doc}. The Port is defined as 5000. +For simplicity of firmware coding, the UI is non human readable. Table (\ref{tbl_FSC_CMDS}) shows which commands are defined (so far). +Some commands need parameters others don't. Table (\ref{tbl_FSC_CMD_PACKAGE}) shows how a message containing a command is defined. +Since TCP/IP packages on the ethernet might be delayed up to minutes timescale it is handy to identify command packages by a (nearly-)unique ID instead of its time only. So when the user receives an answer of the FSC, it is possible to relate it to a specific command. +Generally FSC copies the package ID of a given command package into its answer. + +The following commands are defined: +\begin{table}[htpb] +\begin{tabular}{|l|l|l|} +\hline +command & function & description \\ +\hline +0x00 & -reserved- & -reserved- \\ +0x01 & status & returns entire FSC registers. see table (\ref{tbl_REG_overview}) \\ +0x02 & write reg(U8 addr, U8 data) & write data to register address \\ +0x03 & read reg(U8 addr) & return only specified register \\ +0x04 & measure active R-channels & see see \ref{sec_measuring} \\ +0x05 & measure active V-channels & see ... \\ +0x06 & measure all active channels & see ... \\ +0x07 & set timer(U32 data) & set internal timer \\ +0x08 & start timer & start timer after setting. see \ref{sec_time_register}\\ +0x09 & stop timer & stop timer before setting. \\ +&&\\ +... & ... & to be completed \\ +&& \\ +0xFF & reset & reset all internal registers and peripherals \\ +\hline +\end{tabular} +\caption{FSC commands} +\label{tbl_FSC_CMDS} +\end{table} + +\begin{table}[htpb] +\begin{tabular}{|l|l|l|} +\hline +address & mnemonic & description \\ +\hline +byte 0 & command & see table\ref{tbl_FSC_CMDS}\\ +byte 1 & package ID & (nearly-)unique package identifier \\ +byte 2 & length & length of data section - if apropriate\\ +byte 3..1k & data & parameters for command - if apropriate\\ +\hline +\end{tabular} +\caption{composition of FSC commands} +\label{tbl_FSC_CMD_PACKAGE} +\end{table} + +FSC answers with a short acknowledgement to any command. An acknowledgement contains the command in the first byte and the (nearly-)unique package ID of the command package in the second byte. +\begin{table}[htpb] +\begin{tabular}{|l|l|l|} +\hline +address & mnemonic & description \\ +\hline +byte 0 & command & command, which caused this acknowledgement \\ +byte 1 & package ID & package ID of the command package \\ +\hline +\end{tabular} +\caption{composition of FSCs acknowledgement} +\label{tbl_FSC_ACK} +\end{table} + +If the user issued a measurement command, a telegram is beeing send whenever the measurement is done. In case of free running mode even several telegrams will be submitted. In order to distinguish a telegram from a command acknowledgement, the first byte is always 0x00, see table (\ref{tbl_telegram}). + +%\newpage +\subsection{FSC Registers} +Table \ref{tbl_REG_overview} shows an overview of the FSC registers. Most registers may be read and written. Only the first two registers are readonly. Detailed descriptions of the register contents (will) follow. All registers are 8bit wide. +\begin{table}[htpb] +\begin{tabular}{|l|l|l|} +\hline +{\bf address} & {\bf name} & {\bf description } \\ +\hline +0x00 & status3 & status register. TBR \\ +0x01 & status2 & see \ref{sec_status_register} \\ +0x02 & status1 & \\ +0x03 & status0 & \\ +0x02 & time\_s3 & current time in secondsMSB\\ +0x03 & time\_s2 & see \ref{sec_time_register}\\ +0x04 & time\_s1 & \\ +0x05 & time\_s0 & current time in seconds LSB\\ +0x08 & time\_ms1 & current time, fraction of miliseconds MSB\\ +0x09 & time\_ms0 & -the same- LSB\\ +0x0A & FRperiod1 & time in seconds between two free running measurements MSB\\ +0x0B & FRperiod0 & -the same- LSB\\ +0x0C & RREF1 & reference resistor value in ohms (MSB) \\ +0x0D & RREF0 & reference resistor value in ohms (LSB) \\ +0x10 & TempEn7 & \\ +0x11 & TempEn6 & \\ +0x12 & TempEn5 & \\ +0x13 & TempEn4 & \\ +0x14 & TempEn3 & \\ +0x15 & TempEn2 & \\ +0x16 & TempEn1 & \\ +0x17 & TempEn0 & bitmap defining which channel \\ +0x18 & HumiEn0 & is activated\\ +0x19 & VoltEn4 & \\ +0x1A & VoltEn3 & \\ +0x1B & VoltEn2 & \\ +0x1C & VoltEn1 & \\ +0x1D & VoltEn0 & \\ +0x1E & CurrEn4 & \\ +0x1F & CurrEn3 & \\ +0x20 & CurrEn2 & \\ +0x21 & CurrEn1 & \\ +0x22 & CurrEn0 & \\ +0x30 & TempDone7 & \\ +0x31 & TempDone6 & \\ +0x32 & TempDone5 & \\ +0x33 & TempDone4 & \\ +0x34 & TempDone3 & \\ +0x35 & TempDone2 & \\ +0x36 & TempDone1 & \\ +0x37 & TempDone0 & bitmap defining which channel \\ +0x38 & HumiDone0 & is already measured\\ +0x39 & VoltDone4 & \\ +0x3A & VoltDone3 & \\ +0x3B & VoltDone2 & \\ +0x3C & VoltDone1 & \\ +0x3D & VoltDone0 & \\ +0x3E & CurrDone4 & \\ +0x3F & CurrDone3 & \\ +0x40 & CurrDone2 & \\ +0x41 & CurrDone1 & \\ +0x42 & CurrDone0 & \\ +... & ... & to be completed \\ + \hline +\end{tabular} +\caption{FSC registers} +\label{tbl_REG_overview} +\end{table} + +\subsubsection{Status Registers} +\label{sec_status_register} +Apart from the possibility of crosstalk due to RTD channel switching, it is of course possible to let FSC monitor all of its active channels an in case one channel exceeds a its threshold, a message is generated. +In this case these thresholds need to be stored and this modus needs to be switched on or off. +Some additional information might be stored here, such as: +\begin{itemize} +\item Timer enabled/disabled +\item SPI interface adjusted for: AD7719 / W5100 +\item ... +\end{itemize} + +\subsubsection{Time Registers} +\label{sec_time_register} +Here the current time is stored. Four registers are used to store the current time in seconds, so the current unix time might be +transfered to FSC after power up. Additionaly two registers store the current time in milisenconds. This register cannot be set by the user. +When the user wants to synchronize FSC to the current time, first the timer should be stopped by issuing the 'stop timer' command. Then the Time Registers should be written and finally the 'start timer' command should be sent, causing the milisecond registers to be reset as well. + +\subsubsection{The Enable Registers} +\label{sec_enable_registers} +Most probably not every input channel will be connected to a sensor. In order not to measure unconnected channels, the user may define, which sensor is active, by writing to the registers, TempEnx, HumiEnx, AcceEnx, VoltEnx and CurrEnx the apropriate bitpattern. + +\subsubsection{Ideas for more registers} +\label{sec_register_ideas} + +%\appendix +\end{document} Index: /firmware/FSC/doc/FSC.tex.backup =================================================================== --- /firmware/FSC/doc/FSC.tex.backup (revision 10668) +++ /firmware/FSC/doc/FSC.tex.backup (revision 10668) @@ -0,0 +1,170 @@ +\documentclass[a4paper]{article} + +%\setlength{\topmargin}{0mm} %1 inch is always there! +%\setlength{\oddsidemargin}{0mm} %1 inch is always there! +%\setlength{\evensidemargin}{0mm} %1 inch is always there! + +%\setlength{\textwidth}{16cm} + +% keine Kopfzeile? +%\setlength{\headheight}{0mm} +%\setlength{\headsep}{0mm} + + +%um die deutschen Umlaute eingeben zu können +% müssen diese 3 Pakete eingebunden werden. +% welches der Pakete was macht, weiss ich nicht. +\usepackage[T1]{fontenc} +\usepackage[latin1]{inputenc} +%\usepackage{ngerman} % nur wenn z.B. 'Inhaltsverzeichnis' auch deutsch sein soll. + +\usepackage{graphicx} % for pictures +\usepackage{float} % for figures with english descriptions + +\restylefloat{figure} % can nor force it with H +\restylefloat{table} % can nor force it with H + +\title{FSC - facts about the board} +\author{D. Neise} +\date{07.02.2011} + +\begin{document} + +%title page contains TOC +\maketitle +\tableofcontents +\newpage + +%\listoffigures +%\listoftables + +\section{Basic Facts and Purpose} +% no pictures in SVN repos ... no space. +%\emph{picture here - 3D model of FSC} + +This document presents electronic facts and figures of FACTs FSC board, which stands for {\bf F}act {\bf S}low {\bf C}ontrol. The name is a bit misleading, since the boards sole purpose is to monitor slowly changing parameters, such as: +\begin{itemize} + \item up to 64 temperatures (RTD like sensors, e.g. Pt1000 or Pt100), + \item up to 4 humidities (designed for Honeywell HIH-40xx family), + \item the DC levels of all FACT low voltage supply channels(32 ??? channels), + \item the current drawn from each of these channels (converted to a voltage inside LV-supply). +\end{itemize} + +FSC therefor brings an 8MHz ATmega32L micro controller(MCU), used to readout the muxed 24bit sigma delta ADC (AD7719) which is connected to the RTDs. In addition the ATmegas internal 10bit ADC is used to monitor the humidity, LV-voltages and LV-currents. The muxers on FSC belong to analog devices ADG77xx family, and are controlled by the MCU according to the users needs. The User has access to FSC via Ethernet Interface, comprised(?) by wiznets W5100, the younger brother of W5300, which is used on FACTs FAD boards. AD7719 and W5100 communicate with the MCU via an SPI bus, which results in the fact, that User interaction might slow down temperature measurement or vice versa. Additionally the user should be aware, that sigma delta ADCs have a long settling, when muxed. Redout of all 64 temperature channels takes about 13s, while the one channel might be readout with >10Hz. In addition FSC runs a 32bit timer, counting seconds since timer init. The timer is initialized to zero, when FSC is powered. User may synchronize FSCs timer to Unix time. \newline +We do not talk here about the accelerometer on the FSC, since this piece it not part of the original proposal. + +\subsection{measurement modes} +FSC knows two measurement modes. The first is \emph{on demand}. When FSC measures on demand, user may send a command telling FSC, what to measure. FSC will measure it and return the result, only after the measurement was finished. It is possible to tell FSC to measure several sensors at a time. +If the user asked for a temperature measurement and FSC had to change the muxer setting, this might take up to 300ms. +During a measurement on demand, FSC is not checking for incoming commands. So new commands will pile up in W5100 input FIFO. So sending a lot of on demand commands can easily delay FSC reaction a lot. + +The second mode is \emph{free running}. In free running mode FSC measures all activated sensors and stores the value and time tuples. Once all sensors were measured, FSC returns a measurement telegram. The user can define which sensors should be measured and which should be left out. Additionally one can tell FSC how often it should start a measurement cycle. +\section{Ethernet Interface} +FSC runs as a TCP/IP server, this means after W5100 was initialized, FSC will listen on one Port, but will not attempt to connect to any other server. Since W5100 does not support DHCP, FSC has a fix IP\footnote{see FACT Elogbook / doc}. The Port is not yet defined, but since FADs use Ports 5000-5007, there is a high probability, that you can access FSC via Port 5000 as well. +For simplicity of firmware coding, the UI is non human readable, commands from User to FCS may look like this. +\begin{table}[htpb] +\begin{tabular}{|l|l|l|} +\hline +address & mnemonic & description \\ +\hline +byte 0 & command & see reference to next subsection\\ +byte 1 & ticket no & number of commands - upcounting \\ +byte 2 & length & length of data section - if apropriate\\ +byte 3..1k & data & parameters for command - if apropriate\\ +\hline +\end{tabular} +\caption{composition of FSC commands} +\label{tbl_UserCommand} +\end{table} + +FSCs answers might be eigther a short acknowledgement, in case the user changed a just setting, or a measurement telegram. +An acknowledgement contains the number of the command, which caused the FSC to answer and looks like this. +\begin{table}[htpb] +\begin{tabular}{|l|l|l|} +\hline +address & mnemonic & description \\ +\hline +byte 0 & ticket no & number of the command, \\ + &&causing this answer: range: 0x01 .. 0xFF \\ +byte 1 & length & length of data section \\ +byte 2 & command & first byte in data section: repeated command \\ +byte 3..1k & data & parameters for command - repetition as well\\ +\hline +\end{tabular} +\caption{composition of FSCs answer - acknowledgement} +\label{tbl_FSC_ACK} +\end{table} + +If the user asked for a measurement on demand, the acknowledgement contains the measurement telegram inside the data section. +For a detailed description of the telegram refer to \emph{the right subsection}. +In case the FSC returns data measured, because it was switched to free running mode, the message looks slightly different. + +\begin{table}[htpb] +\begin{tabular}{|l|l|l|} +\hline +address & mnemonic & description \\ +\hline +byte 0 & free run code & 0x00 - is defined not to \\ +&&be a legal ticket number \\ +byte 1 & length & length of data section \\ +byte 2..1k & telegram & see \emph{the right subsection}\\ +\hline +\end{tabular} +\caption{composition of FSCs free running massage} +\label{tbl_FSC_MESS} +\end{table} + +\newpage +\subsection{FSC registers} + +FSC uses the following registers. +\begin{table}[htpb] +\begin{tabular}{|l|l|l|} +\hline +{\bf address} & {\bf name} & {\bf description } \\ +\hline +0x00 & status & stats register - TBR (e.g. mode; timer synched?; ) \\ +0x01 & error & error register - \\ +&& TBR (AD7719 found disconnected sensor, \\ +&&HUM or TEMP too high, V or I out of range)\\ +0x02 & timer3 & \\ +0x03 & timer2 & \\ +0x04 & timer1 & \\ +0x05 & timer0 & current time\\ +0x06 & TempEn7 & \\ +0x07 & TempEn6 & \\ +0x08 & TempEn5 & \\ +0x09 & TempEn4 & \\ +0x0A & TempEn3 & \\ +0x0B & TempEn2 & \\ +0x0C & TempEn1 & \\ +0x0D & TempEn0 & \\ +0x0E & HumiEn0 & \\ +0x0F & AcceEn0 & \\ +0x10 & VoltEn4 & \\ +0x11 & VoltEn3 & \\ +0x12 & VoltEn2 & \\ +0x13 & VoltEn1 & \\ +0x14 & VoltEn0 & \\ +0x15 & CurrEn4 & \\ +0x16 & CurrEn3 & \\ +0x17 & CurrEn2 & \\ +0x18 & CurrEn1 & \\ +0x19 & CurrEn0 & \\ +... & ... & to be completed \\ + \hline +\end{tabular} +\caption{FSC registers} +\label{tbl_REG_overview} +\end{table} + + +\subsection{getting out results - the telegram} +Most probably not every input channel will be connected to a sensor. In order not to measure unconnected channels, the user may define, which sensor is active. + + + + + +%\appendix +\end{document} Index: /firmware/FSC/doc/FSC.toc =================================================================== --- /firmware/FSC/doc/FSC.toc (revision 10668) +++ /firmware/FSC/doc/FSC.toc (revision 10668) @@ -0,0 +1,11 @@ +\contentsline {section}{\numberline {1}Basic Facts and Purpose}{1} +\contentsline {subsection}{\numberline {1.1}Measuring}{1} +\contentsline {subsubsection}{\numberline {1.1.1}RTD switching}{2} +\contentsline {subsection}{\numberline {1.2}The Telegram}{2} +\contentsline {subsection}{\numberline {1.3}Sensor Data}{2} +\contentsline {section}{\numberline {2}Ethernet Interface}{3} +\contentsline {subsection}{\numberline {2.1}FSC Registers}{4} +\contentsline {subsubsection}{\numberline {2.1.1}Status Registers}{4} +\contentsline {subsubsection}{\numberline {2.1.2}Time Registers}{4} +\contentsline {subsubsection}{\numberline {2.1.3}The Enable Registers}{4} +\contentsline {subsubsection}{\numberline {2.1.4}Ideas for more registers}{4} Index: /firmware/FSC/doc/FSC_for_me.tex =================================================================== --- /firmware/FSC/doc/FSC_for_me.tex (revision 10668) +++ /firmware/FSC/doc/FSC_for_me.tex (revision 10668) @@ -0,0 +1,298 @@ +\documentclass[a4paper]{article} + +\setlength{\topmargin}{0mm} %1 inch is always there! +\setlength{\oddsidemargin}{0mm} %1 inch is always there! +\setlength{\evensidemargin}{0mm} %1 inch is always there! + +\setlength{\textwidth}{16cm} +\setlength{\textheight}{25cm} + + +\setlength{\headheight}{0mm} +\setlength{\headsep}{0mm} + + + +%um die deutschen Umlaute eingeben zu können +% müssen diese 3 Pakete eingebunden werden. +% welches der Pakete was macht, weiss ich nicht. +\usepackage[T1]{fontenc} +\usepackage[latin1]{inputenc} +%\usepackage{ngerman} % nur wenn z.B. 'Inhaltsverzeichnis' auch deutsch sein soll. + +\usepackage{graphicx} % for pictures +\usepackage{float} % for figures with english descriptions + +\restylefloat{figure} % can nor force it with H +\restylefloat{table} % can nor force it with H + +\title{FSC - facts about the board} +\author{D. Neise} +\date{07.02.2011} + +\begin{document} + +%title page contains TOC +\maketitle +\tableofcontents +%\newpage + +%\listoffigures +%\listoftables + +\section{Basic Facts and Purpose} +% no pictures in SVN repos ... no space. +%\emph{picture here - 3D model of FSC} + +This document presents electronic facts and figures of FACTs FSC board. FSC stands for {\bf F}act {\bf S}low {\bf C}ontrol. The name is a bit misleading, since the boards sole purpose is to monitor slowly changing parameters, such as: +\begin{itemize} + \item up to 64 temperatures (RTD sensors, e.g. Pt1000 or Pt100), + \item up to 4 humidities (designed for Honeywell HIH-40xx family), + \item the DC levels of all 36 FACT low voltage supply channels, + \item the current consumption on each LV-channel (actually a dc-voltage\footnote{see FLV specs for further details}). +\end{itemize} + +FSC uses an 8MHz ATmega32L micro controller(MCU) to readout the muxed 24bit sigma delta ADC (AD7719) which is connected to the RTDs. In addition the ATmegas internal 10bit ADC is used to monitor the humidity, LV-voltages and LV-currents. +The muxers on FSC belong to analog devices ADG77xx family, and are controlled by the MCU. +The User has access to FSC via Ethernet Interface, provided by WIZNETs W5100, the younger brother of W5300, which is used on FACTs FAD boards. + +AD7719 and W5100 communicate with the MCU via an SPI bus, which results in the fact, that a lot of user interaction might slow down temperature measurement or vice versa. Additionally the user should be aware, that sigma delta ADCs have a prolonged settling time, when muxed. Redout of all 64 temperature channels takes about 13s, while one single channel might be readout with at a rate of 10Hz. In addition FSC runs a 32bit timer, counting miliseconds since timer init. The timer is initialized to zero, when FSC is powered. User may synchronize FSCs timer to Unix time. + +\subsection{Measuring} +\label{sec_measuring} +[This piece should not be published] +FSC knows two measurement modes ({\bf note:} \emph{free running} mode will not be implemented in the first firmware version). +The second mode is \emph{free running}. In free running mode FSC measures all activated sensors and stores their value and time tuples. Once all sensors were measured, FSC returns a measurement telegram. Additionally one can tell FSC how often it should start a measurement cycle. + + +The first is \emph{on demand}. When FSC measures on demand, user may send a command telling FSC, what to measure. FSC will measure it and return the result, right after the measurement was finished. It is possible to tell FSC to measure several sensors at a time. +Users may issue an 'activate' command (see table \ref{tbl_FSC_CMDS}), to specify which channel should be measured during the next measurement phase. In case one is not sure which channel was activated beforehand users may issue a 'status' command, to gather information about FSCs current status. When ever the user completed the channel activation process the 'measure' commands may be issued. Since the high resolution ADC AD7719 used for resistance measurement and the 10bit ADC used for voltage measurement run independently on different time scales, different 'measure' commands are defined. 'measure resistances' will start a measurement possibly taking some seconds, while 'measure voltages' will be ready almost instantaneosly. +Since a measurement might take some time, FSC generates an answer, once the 'measure' command received, informing the user about the command reception. The results are then submitted in a single message to the user, which is called a telegram. +During a 'measure resistance' FSC is not checking for incoming commands. So incoming commands will pile up in W5100 input FIFO. Which means, sending a lot of on demand commands will delay FSCs reaction to the following commannds consecutivly. + +\subsubsection{RTD switching} +FSCs high resolution ADC AD7719 only bears one single input channel. So the RTDs are beeing multiplexed during the resistance measurement. This multplexing includes the RTDs current supply of about $400\,{\mu}A$. In case the RTDs are near to FACTs G-APD signal lines, low frequency crosstalk might be induced due to these switching processes. +In case of FACT there might be two families of RTDs. About 30 pieces will be mounted next to the G-APDs, while a smaller number of sensors will be mounted in the electronics compartement, where this kind of noise will not contribute much. + + +\subsection{The Telegram} +As previously outlined the results of a measurement will be submitted in a single message called telegram. The format of this telegram is given in table (\ref{tbl_telegram}). Despite the fact that the measurement of several RTDs might take several seconds, the storage and transmission of the time of each temperature measurement is regarded as too much overhead, hence the time of the last measurement taken for a telegram is submitted within. Subsequent all activated sensor measurement results are beeing transmitted. A result always consists of a sensor ID and the actual data. Detailed information about the composition of the sensor ID can be found in table (\ref{tdl_sensor_id}). The data might be either 3 byte in case of an RTD or 2 byte in case of all other sensors. For detailed information of sensor data see section \ref{sec_sensor_data}. +\begin{table}[htpb] +\begin{tabular}{|l|l|l|} +\hline +address & mnemonic & description \\ +\hline +byte 0 & 0x00 & special telegram header \\ +byte 1..2 & length & length of telegram in byte \\ +byte 3...6 & time & time, when measurement was finished.\\ +byte 7 & sensor ID 0 & \\ +byte 8..x & data 0 & data field is eigther 2 or 3 byte wide. \\ + & & depending of sensor type. \\ +\hline +byte ... & ... & sensor IDs and data until end.\\ +\hline +\end{tabular} +\caption{composition of FSC telegram} +\label{tbl_telegram} +\end{table} + +\begin{table}[htpb] +\begin{tabular}{|l|l|l|} +\hline +ID bits & meaning \\ +\hline +00pp.psss & temperatur sensor no. sss on port ppp \\ +01vv.vvvv & voltage sensor no. vvvvvv (between 0..35) \\ +10cc.cccc & current sensor no. cccccc (between 0..35)\\ +1100.0hhh & humidity sensor no. hhh \\ +1110.00aa & accelerometer channel no. aa (x, y or z) \\ +&\\ +... & to be completed \\ +\hline +\end{tabular} +\caption{composition of the sensor ID - ad exemplum} +\label{tdl_sensor_id} +\end{table} + +\subsection{Sensor Data} +\label{sec_sensor_data} +FSC supports many different sensors. The first type is any resistive sensor, such as RTDs. The second type is any sensor outputting a voltage between 0VDC and 4.096VDC. In order to keep the firmware independent from the sensors and to keep it as simple as possible, the measured data is treated as less as possible before beeing output. + +Since the resistance measurement is perfomed in a ratiometric manner, the resistance is measured as a 24bit fraction of an onboard fix reference resistor of $\mathrm{R_{ref}} \approx 6.25 \mathrm{k\Omega}$ (see table \ref{tbl_REG_overview}). The value of $\mathrm{R_{ref}}$ is not stored as a constant value, so the user should measure its value once and submit it to the FSC. In case no value is submitted, $\mathrm{R_{ref}} = 6.25\,k\Omega$ is assumed. +FSC does not multiply the measured fraction with the reference resistance. Hence the resistance is unknown on FSC and cannot be transformed into a temperature. Similarly the current of the low voltage supply channels, which is converted into a voltage level and measured by FSC is not beeing treated in any way by the MCU but directly transmitted to the user via ethernet. +The format of each sensor data is given in table \ref{tbl_sensor_data_format}. +\begin{table}[htpb] +\begin{tabular}{|l|l|l|l|l|l|} +\hline +sensor name & actual physical value & resolution & width & format & unit \\ +\hline +temperature & resistance &24 or 16 bit & 24 & unsigned int & fraction of $\mathrm{R_{ref}}$ \\ +humidity & voltage & 10 bit & 16 & unsigned int & V \\ +voltage & voltage & 10 bit & 16 & unsigned int & V \\ +current & voltage & 10 bit & 16 & unsigned int & V \\ +accelerometer & acceleration & 24 bit & 24 & signed int & $\mathrm{mg} \approx 9.81 \frac{\mathrm{mm}}{\mathrm{s^2}}$ \\ +\hline +\end{tabular} +\caption{sensor data format} +\label{tbl_sensor_data_format} +\end{table} + + + + +\section{Ethernet Interface} +FSC runs as a TCP/IP server, this means after W5100 was initialized, FSC will listen on a Port, but will not attempt to connect to any server. Since W5100 does not support DHCP, FSC has a fix IP\footnote{see FACT Elogbook / doc}. The Port is defined as 5000. +For simplicity of firmware coding, the UI is non human readable. Table (\ref{tbl_FSC_CMDS}) shows which commands are defined (so far). +Some commands need parameters others don't. Table (\ref{tbl_FSC_CMD_PACKAGE}) shows how a message containing a command is defined. +Since TCP/IP packages on the ethernet might be delayed up to minutes timescale it is handy to identify command packages by a (nearly-)unique ID instead of its time only. So when the user receives an answer of the FSC, it is possible to relate it to a specific command. +Generally FSC copies the package ID of a given command package into its answer. + +The following commands are defined: +\begin{table}[htpb] +\begin{tabular}{|l|l|l|} +\hline +command & function & description \\ +\hline +0x00 & -reserved- & -reserved- \\ +0x01 & status & returns entire FSC registers. see table (\ref{tbl_REG_overview}) \\ +0x02 & write reg(U8 addr, U8 data) & write data to register address \\ +0x03 & read reg(U8 addr) & return only specified register \\ +0x?? & measure active R-channels & see see \ref{sec_measuring} \\ +0x?? & measure active V-channels & see ... \\ +0x?? & measure all active channels & see ... \\ +0x?? & set timer(U32 data) & set internal timer \\ +0x?? & start timer & start timer after setting. see \ref{sec_time_register}\\ +0x?? & stop timer & stop timer before setting. \\ +0x?? & FR mode & start free running mode \\ +&&\\ +... & ... & to be completed \\ +&& \\ +0xFF & reset & reset all internal registers and peripherals \\ +\hline +\end{tabular} +\caption{FSC commands} +\label{tbl_FSC_CMDS} +\end{table} + +\begin{table}[htpb] +\begin{tabular}{|l|l|l|} +\hline +address & mnemonic & description \\ +\hline +byte 0 & command & see table\ref{tbl_FSC_CMDS}\\ +byte 1 & package ID & (nearly-)unique package identifier \\ +byte 2 & length & length of data section - if apropriate\\ +byte 3..1k & data & parameters for command - if apropriate\\ +\hline +\end{tabular} +\caption{composition of FSC commands} +\label{tbl_FSC_CMD_PACKAGE} +\end{table} + +FSC answers with a short acknowledgement to any command. An acknowledgement contains the command in the first byte and the (nearly-)unique package ID of the command package in the second byte. +\begin{table}[htpb] +\begin{tabular}{|l|l|l|} +\hline +address & mnemonic & description \\ +\hline +byte 0 & command & command, which caused this acknowledgement \\ +byte 1 & package ID & package ID of the command package \\ +\hline +\end{tabular} +\caption{composition of FSCs acknowledgement} +\label{tbl_FSC_ACK} +\end{table} + +If the user issued a measurement command, a telegram is beeing send whenever the measurement is done. In case of free running mode even several telegrams will be submitted. In order to distinguish a telegram from a command acknowledgement, the first byte is always 0x00, see table (\ref{tbl_telegram}). + +%\newpage +\subsection{FSC Registers} +Table \ref{tbl_REG_overview} shows an overview of the FSC registers. Most registers may be read and written. Only the first two registers are readonly. Detailed descriptions of the register contents (will) follow. All registers are 8bit wide. +\begin{table}[htpb] +\begin{tabular}{|l|l|l|} +\hline +{\bf address} & {\bf name} & {\bf description } \\ +\hline +0x00 & status3 & status register. TBR \\ +0x01 & status2 & see \ref{sec_status_register} \\ +0x02 & status1 & \\ +0x03 & status0 & \\ +0x02 & time\_s3 & current time in secondsMSB\\ +0x03 & time\_s2 & see \ref{sec_time_register}\\ +0x04 & time\_s1 & \\ +0x05 & time\_s0 & current time in seconds LSB\\ +0x08 & time\_ms1 & current time, fraction of miliseconds MSB\\ +0x09 & time\_ms0 & -the same- LSB\\ +0x0A & FRperiod1 & time in seconds between two free running measurements MSB\\ +0x0B & FRperiod0 & -the same- LSB\\ +0x0C & RREF1 & reference resistor value in ohms (MSB) \\ +0x0D & RREF0 & reference resistor value in ohms (LSB) \\ +0x10 & TempEn7 & \\ +0x11 & TempEn6 & \\ +0x12 & TempEn5 & \\ +0x13 & TempEn4 & \\ +0x14 & TempEn3 & \\ +0x15 & TempEn2 & \\ +0x16 & TempEn1 & \\ +0x17 & TempEn0 & bitmap defining which channel \\ +0x18 & HumiEn0 & is activated\\ +0x19 & AcceEn0 & \\ +0x1a & VoltEn4 & \\ +0x1b & VoltEn3 & \\ +0x1c & VoltEn2 & \\ +0x1d & VoltEn1 & \\ +0x1e & VoltEn0 & \\ +0x1f & CurrEn4 & \\ +0x20 & CurrEn3 & \\ +0x21 & CurrEn2 & \\ +0x22 & CurrEn1 & \\ +0x23 & CurrEn0 & \\ +0x30 & TempDone7 & \\ +0x31 & TempDone6 & \\ +0x32 & TempDone5 & \\ +0x33 & TempDone4 & \\ +0x34 & TempDone3 & \\ +0x35 & TempDone2 & \\ +0x36 & TempDone1 & \\ +0x37 & TempDone0 & bitmap defining which channel \\ +0x38 & HumiDone0 & is already measured\\ +0x39 & AcceDone0 & \\ +0x3A & VoltDone4 & \\ +0x3B & VoltDone3 & \\ +0x3C & VoltDone2 & \\ +0x3D & VoltDone1 & \\ +0x3E & VoltDone0 & \\ +0x3F & CurrDone4 & \\ +0x40 & CurrDone3 & \\ +0x41 & CurrDone2 & \\ +0x42 & CurrDone1 & \\ +0x43 & CurrDone0 & \\ +... & ... & to be completed \\ + \hline +\end{tabular} +\caption{FSC registers} +\label{tbl_REG_overview} +\end{table} + +\subsubsection{Status Registers} +\label{sec_status_register} + + +\subsubsection{Time Registers} +\label{sec_time_register} +Here the current time is stored. Four registers are used to store the current time in seconds, so the current unix time might be +transfered to FSC after power up. Additionaly two registers store the current time in milisenconds. This register cannot be set by the user. +When the user wants to synchronize FSC to the current time, first the timer should be stopped by issuing the 'stop timer' command. Then the Time Registers should be written and finally the 'start timer' command should be sent, causing the milisecond registers to be reset as well. + +\subsubsection{The Enable Registers} +\label{sec_enable_registers} +Most probably not every input channel will be connected to a sensor. In order not to measure unconnected channels, the user may define, which sensor is active, by writing to the registers, TempEnx, HumiEnx, AcceEnx, VoltEnx and CurrEnx the apropriate bitpattern. + +\subsubsection{Free Running Period Register} +\label{sec_fr_period_register} + +\subsubsection{Ideas for more registers} +\label{sec_register_ideas} + +%\appendix +\end{document} Index: /firmware/FSC/test_projects/test_ethernet/default/Makefile =================================================================== --- /firmware/FSC/test_projects/test_ethernet/default/Makefile (revision 10668) +++ /firmware/FSC/test_projects/test_ethernet/default/Makefile (revision 10668) @@ -0,0 +1,110 @@ +############################################################################### +# Makefile for the project test_ethernet +############################################################################### + +## General Flags +PROJECT = test_ethernet +MCU = atmega32 +TARGET = test_ethernet.elf +CC = avr-gcc + +CPP = avr-g++ + +## Options common to compile, link and assembly rules +COMMON = -mmcu=$(MCU) + +## Compile options common for all C compilation units. +CFLAGS = $(COMMON) +CFLAGS += -Wall -gdwarf-2 -std=gnu99 -DF_CPU=8000000UL -Os -funsigned-char -funsigned-bitfields -fpack-struct -fshort-enums +CFLAGS += -MD -MP -MT $(*F).o -MF dep/$(@F).d + +## Assembly specific flags +ASMFLAGS = $(COMMON) +ASMFLAGS += $(CFLAGS) +ASMFLAGS += -x assembler-with-cpp -Wa,-gdwarf2 + +## Linker flags +LDFLAGS = $(COMMON) +LDFLAGS += -Wl,-Map=test_ethernet.map + + +## Intel Hex file production flags +HEX_FLASH_FLAGS = -R .eeprom -R .fuse -R .lock -R .signature + +HEX_EEPROM_FLAGS = -j .eeprom +HEX_EEPROM_FLAGS += --set-section-flags=.eeprom="alloc,load" +HEX_EEPROM_FLAGS += --change-section-lma .eeprom=0 --no-change-warnings + + +## Objects that must be built in order to link +OBJECTS = w5100_spi_interface.o ad7719_adc.o application.o atmega_adc.o interpol.o muxer_fsc.o output.o parser.o spi_master.o usart.o num_conversion.o FSC_test.o + +## Objects explicitly added by the user +LINKONLYOBJECTS = + +## Build +all: $(TARGET) test_ethernet.hex test_ethernet.eep test_ethernet.lss size + +## Compile +w5100_spi_interface.o: ../../../src/w5100_spi_interface.c + $(CC) $(INCLUDES) $(CFLAGS) -c $< + +ad7719_adc.o: ../../../src/ad7719_adc.c + $(CC) $(INCLUDES) $(CFLAGS) -c $< + +application.o: ../../../src/application.c + $(CC) $(INCLUDES) $(CFLAGS) -c $< + +atmega_adc.o: ../../../src/atmega_adc.c + $(CC) $(INCLUDES) $(CFLAGS) -c $< + +interpol.o: ../../../src/interpol.c + $(CC) $(INCLUDES) $(CFLAGS) -c $< + +muxer_fsc.o: ../../../src/muxer_fsc.c + $(CC) $(INCLUDES) $(CFLAGS) -c $< + +output.o: ../../../src/output.c + $(CC) $(INCLUDES) $(CFLAGS) -c $< + +parser.o: ../../../src/parser.c + $(CC) $(INCLUDES) $(CFLAGS) -c $< + +spi_master.o: ../../../src/spi_master.c + $(CC) $(INCLUDES) $(CFLAGS) -c $< + +usart.o: ../../../src/usart.c + $(CC) $(INCLUDES) $(CFLAGS) -c $< + +num_conversion.o: ../../../src/num_conversion.c + $(CC) $(INCLUDES) $(CFLAGS) -c $< + +FSC_test.o: ../../../src/FSC_test.c + $(CC) $(INCLUDES) $(CFLAGS) -c $< + +##Link +$(TARGET): $(OBJECTS) + $(CC) $(LDFLAGS) $(OBJECTS) $(LINKONLYOBJECTS) $(LIBDIRS) $(LIBS) -o $(TARGET) + +%.hex: $(TARGET) + avr-objcopy -O ihex $(HEX_FLASH_FLAGS) $< $@ + +%.eep: $(TARGET) + -avr-objcopy $(HEX_EEPROM_FLAGS) -O ihex $< $@ || exit 0 + +%.lss: $(TARGET) + avr-objdump -h -S $< > $@ + +size: ${TARGET} + @echo + @avr-size -C --mcu=${MCU} ${TARGET} + +## Clean target +.PHONY: clean +clean: + -rm -rf $(OBJECTS) test_ethernet.elf dep/* test_ethernet.hex test_ethernet.eep test_ethernet.lss test_ethernet.map + + +## Other dependencies +-include $(shell mkdir dep 2>/dev/null) $(wildcard dep/*) + Index: /firmware/FSC/test_projects/test_ethernet/default/dep/FSC_test.o.d =================================================================== --- /firmware/FSC/test_projects/test_ethernet/default/dep/FSC_test.o.d (revision 10668) +++ /firmware/FSC/test_projects/test_ethernet/default/dep/FSC_test.o.d (revision 10668) @@ -0,0 +1,99 @@ +FSC_test.o: ../../../src/FSC_test.c ../../../src/typedefs.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdio.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stdarg.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stddef.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdlib.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/string.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/ctype.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include-fixed/limits.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/util/delay.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/util/delay_basic.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom32.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/interrupt.h \ + ../../../src/macros.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/pgmspace.h \ + ../../../src/application.h ../../../src/spi_master.h \ + ../../../src/usart.h ../../../src/num_conversion.h \ + ../../../src/ad7719_adc.h ../../../src/atmega_adc.h \ + ../../../src/muxer_fsc.h ../../../src/output.h ../../../src/parser.h \ + ../../../src/interpol.h ../../../src/w5100_spi_interface.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/wdt.h + +../../../src/typedefs.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdio.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stdarg.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stddef.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdlib.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/string.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/ctype.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include-fixed/limits.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/util/delay.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/util/delay_basic.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom32.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/interrupt.h: + +../../../src/macros.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/pgmspace.h: + +../../../src/application.h: + +../../../src/spi_master.h: + +../../../src/usart.h: + +../../../src/num_conversion.h: + +../../../src/ad7719_adc.h: + +../../../src/atmega_adc.h: + +../../../src/muxer_fsc.h: + +../../../src/output.h: + +../../../src/parser.h: + +../../../src/interpol.h: + +../../../src/w5100_spi_interface.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/wdt.h: Index: /firmware/FSC/test_projects/test_ethernet/default/dep/ad7719_adc.o.d =================================================================== --- /firmware/FSC/test_projects/test_ethernet/default/dep/ad7719_adc.o.d (revision 10668) +++ /firmware/FSC/test_projects/test_ethernet/default/dep/ad7719_adc.o.d (revision 10668) @@ -0,0 +1,82 @@ +ad7719_adc.o: ../../../src/ad7719_adc.c ../../../src/ad7719_adc.h \ + ../../../src/typedefs.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdio.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stdarg.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stddef.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdlib.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/string.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/ctype.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include-fixed/limits.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/util/delay.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/util/delay_basic.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom32.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/interrupt.h \ + ../../../src/macros.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/pgmspace.h \ + ../../../src/application.h ../../../src/num_conversion.h \ + ../../../src/spi_master.h ../../../src/usart.h + +../../../src/ad7719_adc.h: + +../../../src/typedefs.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdio.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stdarg.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stddef.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdlib.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/string.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/ctype.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include-fixed/limits.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/util/delay.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/util/delay_basic.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom32.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/interrupt.h: + +../../../src/macros.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/pgmspace.h: + +../../../src/application.h: + +../../../src/num_conversion.h: + +../../../src/spi_master.h: + +../../../src/usart.h: Index: /firmware/FSC/test_projects/test_ethernet/default/dep/application.o.d =================================================================== --- /firmware/FSC/test_projects/test_ethernet/default/dep/application.o.d (revision 10668) +++ /firmware/FSC/test_projects/test_ethernet/default/dep/application.o.d (revision 10668) @@ -0,0 +1,80 @@ +application.o: ../../../src/application.c ../../../src/application.h \ + ../../../src/typedefs.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdio.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stdarg.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stddef.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdlib.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/string.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/ctype.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include-fixed/limits.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/util/delay.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/util/delay_basic.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom32.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/interrupt.h \ + ../../../src/macros.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/pgmspace.h \ + ../../../src/usart.h ../../../src/num_conversion.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/wdt.h + +../../../src/application.h: + +../../../src/typedefs.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdio.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stdarg.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stddef.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdlib.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/string.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/ctype.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include-fixed/limits.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/util/delay.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/util/delay_basic.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom32.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/interrupt.h: + +../../../src/macros.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/pgmspace.h: + +../../../src/usart.h: + +../../../src/num_conversion.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/wdt.h: Index: /firmware/FSC/test_projects/test_ethernet/default/dep/atmega_adc.o.d =================================================================== --- /firmware/FSC/test_projects/test_ethernet/default/dep/atmega_adc.o.d (revision 10668) +++ /firmware/FSC/test_projects/test_ethernet/default/dep/atmega_adc.o.d (revision 10668) @@ -0,0 +1,72 @@ +atmega_adc.o: ../../../src/atmega_adc.c ../../../src/atmega_adc.h \ + ../../../src/typedefs.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdio.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stdarg.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stddef.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdlib.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/string.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/ctype.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include-fixed/limits.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/util/delay.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/util/delay_basic.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom32.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/interrupt.h \ + ../../../src/macros.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/pgmspace.h + +../../../src/atmega_adc.h: + +../../../src/typedefs.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdio.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stdarg.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stddef.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdlib.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/string.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/ctype.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include-fixed/limits.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/util/delay.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/util/delay_basic.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom32.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/interrupt.h: + +../../../src/macros.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/pgmspace.h: Index: /firmware/FSC/test_projects/test_ethernet/default/dep/interpol.o.d =================================================================== --- /firmware/FSC/test_projects/test_ethernet/default/dep/interpol.o.d (revision 10668) +++ /firmware/FSC/test_projects/test_ethernet/default/dep/interpol.o.d (revision 10668) @@ -0,0 +1,82 @@ +interpol.o: ../../../src/interpol.c ../../../src/interpol.h \ + ../../../src/typedefs.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdio.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stdarg.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stddef.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdlib.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/string.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/ctype.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include-fixed/limits.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/util/delay.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/util/delay_basic.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom32.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/interrupt.h \ + ../../../src/macros.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/pgmspace.h \ + ../../../src/application.h ../../../src/num_conversion.h \ + ../../../src/usart.h ../../../src/ad7719_adc.h + +../../../src/interpol.h: + +../../../src/typedefs.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdio.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stdarg.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stddef.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdlib.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/string.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/ctype.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include-fixed/limits.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/util/delay.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/util/delay_basic.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom32.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/interrupt.h: + +../../../src/macros.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/pgmspace.h: + +../../../src/application.h: + +../../../src/num_conversion.h: + +../../../src/usart.h: + +../../../src/ad7719_adc.h: Index: /firmware/FSC/test_projects/test_ethernet/default/dep/muxer_fsc.o.d =================================================================== --- /firmware/FSC/test_projects/test_ethernet/default/dep/muxer_fsc.o.d (revision 10668) +++ /firmware/FSC/test_projects/test_ethernet/default/dep/muxer_fsc.o.d (revision 10668) @@ -0,0 +1,72 @@ +muxer_fsc.o: ../../../src/muxer_fsc.c ../../../src/muxer_fsc.h \ + ../../../src/typedefs.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdio.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stdarg.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stddef.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdlib.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/string.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/ctype.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include-fixed/limits.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/util/delay.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/util/delay_basic.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom32.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/interrupt.h \ + ../../../src/macros.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/pgmspace.h + +../../../src/muxer_fsc.h: + +../../../src/typedefs.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdio.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stdarg.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stddef.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdlib.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/string.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/ctype.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include-fixed/limits.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/util/delay.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/util/delay_basic.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom32.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/interrupt.h: + +../../../src/macros.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/pgmspace.h: Index: /firmware/FSC/test_projects/test_ethernet/default/dep/num_conversion.o.d =================================================================== --- /firmware/FSC/test_projects/test_ethernet/default/dep/num_conversion.o.d (revision 10668) +++ /firmware/FSC/test_projects/test_ethernet/default/dep/num_conversion.o.d (revision 10668) @@ -0,0 +1,72 @@ +num_conversion.o: ../../../src/num_conversion.c \ + ../../../src/num_conversion.h ../../../src/typedefs.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdio.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stdarg.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stddef.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdlib.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/string.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/ctype.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include-fixed/limits.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/util/delay.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/util/delay_basic.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom32.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/interrupt.h \ + ../../../src/macros.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/pgmspace.h + +../../../src/num_conversion.h: + +../../../src/typedefs.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdio.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stdarg.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stddef.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdlib.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/string.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/ctype.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include-fixed/limits.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/util/delay.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/util/delay_basic.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom32.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/interrupt.h: + +../../../src/macros.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/pgmspace.h: Index: /firmware/FSC/test_projects/test_ethernet/default/dep/output.o.d =================================================================== --- /firmware/FSC/test_projects/test_ethernet/default/dep/output.o.d (revision 10668) +++ /firmware/FSC/test_projects/test_ethernet/default/dep/output.o.d (revision 10668) @@ -0,0 +1,80 @@ +output.o: ../../../src/output.c ../../../src/output.h \ + ../../../src/typedefs.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdio.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stdarg.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stddef.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdlib.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/string.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/ctype.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include-fixed/limits.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/util/delay.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/util/delay_basic.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom32.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/interrupt.h \ + ../../../src/macros.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/pgmspace.h \ + ../../../src/usart.h ../../../src/application.h \ + ../../../src/num_conversion.h + +../../../src/output.h: + +../../../src/typedefs.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdio.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stdarg.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stddef.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdlib.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/string.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/ctype.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include-fixed/limits.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/util/delay.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/util/delay_basic.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom32.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/interrupt.h: + +../../../src/macros.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/pgmspace.h: + +../../../src/usart.h: + +../../../src/application.h: + +../../../src/num_conversion.h: Index: /firmware/FSC/test_projects/test_ethernet/default/dep/parser.o.d =================================================================== --- /firmware/FSC/test_projects/test_ethernet/default/dep/parser.o.d (revision 10668) +++ /firmware/FSC/test_projects/test_ethernet/default/dep/parser.o.d (revision 10668) @@ -0,0 +1,82 @@ +parser.o: ../../../src/parser.c ../../../src/parser.h \ + ../../../src/output.h ../../../src/typedefs.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdio.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stdarg.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stddef.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdlib.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/string.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/ctype.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include-fixed/limits.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/util/delay.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/util/delay_basic.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom32.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/interrupt.h \ + ../../../src/macros.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/pgmspace.h \ + ../../../src/application.h ../../../src/usart.h \ + ../../../src/num_conversion.h + +../../../src/parser.h: + +../../../src/output.h: + +../../../src/typedefs.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdio.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stdarg.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stddef.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdlib.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/string.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/ctype.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include-fixed/limits.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/util/delay.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/util/delay_basic.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom32.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/interrupt.h: + +../../../src/macros.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/pgmspace.h: + +../../../src/application.h: + +../../../src/usart.h: + +../../../src/num_conversion.h: Index: /firmware/FSC/test_projects/test_ethernet/default/dep/spi_master.o.d =================================================================== --- /firmware/FSC/test_projects/test_ethernet/default/dep/spi_master.o.d (revision 10668) +++ /firmware/FSC/test_projects/test_ethernet/default/dep/spi_master.o.d (revision 10668) @@ -0,0 +1,80 @@ +spi_master.o: ../../../src/spi_master.c ../../../src/spi_master.h \ + ../../../src/typedefs.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdio.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stdarg.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stddef.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdlib.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/string.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/ctype.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include-fixed/limits.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/util/delay.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/util/delay_basic.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom32.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/interrupt.h \ + ../../../src/macros.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/pgmspace.h \ + ../../../src/application.h ../../../src/usart.h \ + ../../../src/num_conversion.h + +../../../src/spi_master.h: + +../../../src/typedefs.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdio.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stdarg.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stddef.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdlib.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/string.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/ctype.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include-fixed/limits.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/util/delay.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/util/delay_basic.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom32.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/interrupt.h: + +../../../src/macros.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/pgmspace.h: + +../../../src/application.h: + +../../../src/usart.h: + +../../../src/num_conversion.h: Index: /firmware/FSC/test_projects/test_ethernet/default/dep/usart.o.d =================================================================== --- /firmware/FSC/test_projects/test_ethernet/default/dep/usart.o.d (revision 10668) +++ /firmware/FSC/test_projects/test_ethernet/default/dep/usart.o.d (revision 10668) @@ -0,0 +1,77 @@ +usart.o: ../../../src/usart.c ../../../src/usart.h \ + ../../../src/typedefs.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdio.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stdarg.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stddef.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdlib.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/string.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/ctype.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include-fixed/limits.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/util/delay.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/util/delay_basic.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom32.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/interrupt.h \ + ../../../src/macros.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/pgmspace.h \ + ../../../src/application.h ../../../src/num_conversion.h + +../../../src/usart.h: + +../../../src/typedefs.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdio.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stdarg.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stddef.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdlib.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/string.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/ctype.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include-fixed/limits.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/util/delay.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/util/delay_basic.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom32.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/interrupt.h: + +../../../src/macros.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/pgmspace.h: + +../../../src/application.h: + +../../../src/num_conversion.h: Index: /firmware/FSC/test_projects/test_ethernet/default/dep/w5100_spi_interface.o.d =================================================================== --- /firmware/FSC/test_projects/test_ethernet/default/dep/w5100_spi_interface.o.d (revision 10668) +++ /firmware/FSC/test_projects/test_ethernet/default/dep/w5100_spi_interface.o.d (revision 10668) @@ -0,0 +1,82 @@ +w5100_spi_interface.o: ../../../src/w5100_spi_interface.c \ + ../../../src/w5100_spi_interface.h ../../../src/typedefs.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdio.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stdarg.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stddef.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/stdlib.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/string.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/ctype.h \ + c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include-fixed/limits.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/util/delay.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/util/delay_basic.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom32.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/interrupt.h \ + ../../../src/macros.h \ + c:/winavr-20100110/lib/gcc/../../avr/include/avr/pgmspace.h \ + ../../../src/application.h ../../../src/num_conversion.h \ + ../../../src/spi_master.h ../../../src/usart.h + +../../../src/w5100_spi_interface.h: + +../../../src/typedefs.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdio.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/inttypes.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdint.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stdarg.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include/stddef.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/stdlib.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/string.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/ctype.h: + +c:\winavr-20100110\bin\../lib/gcc/avr/4.3.3/include-fixed/limits.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/util/delay.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/util/delay_basic.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/io.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/sfr_defs.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/iom32.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/portpins.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/common.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/version.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/fuse.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/lock.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/interrupt.h: + +../../../src/macros.h: + +c:/winavr-20100110/lib/gcc/../../avr/include/avr/pgmspace.h: + +../../../src/application.h: + +../../../src/num_conversion.h: + +../../../src/spi_master.h: + +../../../src/usart.h: Index: /firmware/FSC/test_projects/test_ethernet/default/test_ethernet.eep =================================================================== --- /firmware/FSC/test_projects/test_ethernet/default/test_ethernet.eep (revision 10668) +++ /firmware/FSC/test_projects/test_ethernet/default/test_ethernet.eep (revision 10668) @@ -0,0 +1,1 @@ +:00000001FF Index: /firmware/FSC/test_projects/test_ethernet/default/test_ethernet.hex =================================================================== --- /firmware/FSC/test_projects/test_ethernet/default/test_ethernet.hex (revision 10668) +++ /firmware/FSC/test_projects/test_ethernet/default/test_ethernet.hex (revision 10668) @@ -0,0 +1,930 @@ +:100000000C942A000C9447000C9447000C94470071 +:100010000C94B3100C9447000C9447000C944700C8 +:100020000C9447000C9447000C9447000C94470034 +:100030000C9447000C94070B0C9447000C94470059 +:100040000C9447000C9447000C9447000C94470014 +:100050000C94470011241FBECFE5D8E0DEBFCDBF12 +:1000600015E0A0E6B0E0E0EDF4E302C005900D92EB +:10007000A839B107D9F717E0A8E9B5E001C01D928A +:10008000AC3CB107E1F70E94D8100C94661A0C94AE +:1000900000002FE02093E6059093E7058093E805A4 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/firmware/FSC/test_projects/test_ethernet/default/test_ethernet.lss (revision 10668) @@ -0,0 +1,9053 @@ + +test_ethernet.elf: file format elf32-avr + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 000034d0 00000000 00000000 00000094 2**1 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .data 00000538 00800060 000034d0 00003564 2**0 + CONTENTS, ALLOC, LOAD, DATA + 2 .bss 00000234 00800598 00800598 00003a9c 2**0 + ALLOC + 3 .debug_aranges 00000320 00000000 00000000 00003a9c 2**0 + CONTENTS, READONLY, DEBUGGING + 4 .debug_pubnames 00000cc0 00000000 00000000 00003dbc 2**0 + CONTENTS, READONLY, DEBUGGING + 5 .debug_info 00004e47 00000000 00000000 00004a7c 2**0 + CONTENTS, READONLY, DEBUGGING + 6 .debug_abbrev 0000208a 00000000 00000000 000098c3 2**0 + CONTENTS, READONLY, DEBUGGING + 7 .debug_line 00003884 00000000 00000000 0000b94d 2**0 + CONTENTS, READONLY, DEBUGGING + 8 .debug_frame 000007b0 00000000 00000000 0000f1d4 2**2 + CONTENTS, READONLY, DEBUGGING + 9 .debug_str 00000fb1 00000000 00000000 0000f984 2**0 + CONTENTS, READONLY, DEBUGGING + 10 .debug_loc 000023f1 00000000 00000000 00010935 2**0 + CONTENTS, READONLY, DEBUGGING + 11 .debug_ranges 000001d0 00000000 00000000 00012d26 2**0 + CONTENTS, READONLY, DEBUGGING + +Disassembly of section .text: + +00000000 <__vectors>: + 0: 0c 94 2a 00 jmp 0x54 ; 0x54 <__ctors_end> + 4: 0c 94 47 00 jmp 0x8e ; 0x8e <__bad_interrupt> + 8: 0c 94 47 00 jmp 0x8e ; 0x8e <__bad_interrupt> + c: 0c 94 47 00 jmp 0x8e ; 0x8e <__bad_interrupt> + 10: 0c 94 b3 10 jmp 0x2166 ; 0x2166 <__vector_4> + 14: 0c 94 47 00 jmp 0x8e ; 0x8e <__bad_interrupt> + 18: 0c 94 47 00 jmp 0x8e ; 0x8e <__bad_interrupt> + 1c: 0c 94 47 00 jmp 0x8e ; 0x8e <__bad_interrupt> + 20: 0c 94 47 00 jmp 0x8e ; 0x8e <__bad_interrupt> + 24: 0c 94 47 00 jmp 0x8e ; 0x8e <__bad_interrupt> + 28: 0c 94 47 00 jmp 0x8e ; 0x8e <__bad_interrupt> + 2c: 0c 94 47 00 jmp 0x8e ; 0x8e <__bad_interrupt> + 30: 0c 94 47 00 jmp 0x8e ; 0x8e <__bad_interrupt> + 34: 0c 94 07 0b jmp 0x160e ; 0x160e <__vector_13> + 38: 0c 94 47 00 jmp 0x8e ; 0x8e <__bad_interrupt> + 3c: 0c 94 47 00 jmp 0x8e ; 0x8e <__bad_interrupt> + 40: 0c 94 47 00 jmp 0x8e ; 0x8e <__bad_interrupt> + 44: 0c 94 47 00 jmp 0x8e ; 0x8e <__bad_interrupt> + 48: 0c 94 47 00 jmp 0x8e ; 0x8e <__bad_interrupt> + 4c: 0c 94 47 00 jmp 0x8e ; 0x8e <__bad_interrupt> + 50: 0c 94 47 00 jmp 0x8e ; 0x8e <__bad_interrupt> + +00000054 <__ctors_end>: + 54: 11 24 eor r1, r1 + 56: 1f be out 0x3f, r1 ; 63 + 58: cf e5 ldi r28, 0x5F ; 95 + 5a: d8 e0 ldi r29, 0x08 ; 8 + 5c: de bf out 0x3e, r29 ; 62 + 5e: cd bf out 0x3d, r28 ; 61 + +00000060 <__do_copy_data>: + 60: 15 e0 ldi r17, 0x05 ; 5 + 62: a0 e6 ldi r26, 0x60 ; 96 + 64: b0 e0 ldi r27, 0x00 ; 0 + 66: e0 ed ldi r30, 0xD0 ; 208 + 68: f4 e3 ldi r31, 0x34 ; 52 + 6a: 02 c0 rjmp .+4 ; 0x70 <.do_copy_data_start> + +0000006c <.do_copy_data_loop>: + 6c: 05 90 lpm r0, Z+ + 6e: 0d 92 st X+, r0 + +00000070 <.do_copy_data_start>: + 70: a8 39 cpi r26, 0x98 ; 152 + 72: b1 07 cpc r27, r17 + 74: d9 f7 brne .-10 ; 0x6c <.do_copy_data_loop> + +00000076 <__do_clear_bss>: + 76: 17 e0 ldi r17, 0x07 ; 7 + 78: a8 e9 ldi r26, 0x98 ; 152 + 7a: b5 e0 ldi r27, 0x05 ; 5 + 7c: 01 c0 rjmp .+2 ; 0x80 <.do_clear_bss_start> + +0000007e <.do_clear_bss_loop>: + 7e: 1d 92 st X+, r1 + +00000080 <.do_clear_bss_start>: + 80: ac 3c cpi r26, 0xCC ; 204 + 82: b1 07 cpc r27, r17 + 84: e1 f7 brne .-8 ; 0x7e <.do_clear_bss_loop> + 86: 0e 94 d8 10 call 0x21b0 ; 0x21b0
+ 8a: 0c 94 66 1a jmp 0x34cc ; 0x34cc <_exit> + +0000008e <__bad_interrupt>: + 8e: 0c 94 00 00 jmp 0 ; 0x0 <__vectors> + +00000092 : +// spi_read_buffer should contain 0x00 0x01 0x02 and 0x03 ... nice check! +} + +U08 w5100_read( U16 addr) +{ +spi_write_buffer[0]=0x0F; + 92: 2f e0 ldi r18, 0x0F ; 15 + 94: 20 93 e6 05 sts 0x05E6, r18 +spi_write_buffer[1]=(U08)(addr>>8); + 98: 90 93 e7 05 sts 0x05E7, r25 +spi_write_buffer[2]=(U08)(addr); + 9c: 80 93 e8 05 sts 0x05E8, r24 +spi_write_buffer[3]=0x00; + a0: 10 92 e9 05 sts 0x05E9, r1 + +spi_transfer(4, 0); + a4: 84 e0 ldi r24, 0x04 ; 4 + a6: 60 e0 ldi r22, 0x00 ; 0 + a8: 0e 94 c5 09 call 0x138a ; 0x138a +return spi_read_buffer[3]; + ac: 80 91 fc 05 lds r24, 0x05FC +// spi_read_buffer should contain 0x00 0x01 0x02 and data ... nice check! +} + b0: 08 95 ret + +000000b2 : +return received_size; +} + +// S0_RX_RD +U16 get_S0_RX_RD() +{ + b2: 0f 93 push r16 + b4: 1f 93 push r17 +U16 readpointer; +readpointer=w5100_read(S0_RX_RD0); + b6: 88 e2 ldi r24, 0x28 ; 40 + b8: 94 e0 ldi r25, 0x04 ; 4 + ba: 0e 94 49 00 call 0x92 ; 0x92 +readpointer = readpointer << 8; + be: 18 2f mov r17, r24 + c0: 00 e0 ldi r16, 0x00 ; 0 +readpointer += w5100_read(S0_RX_RD1); + c2: 89 e2 ldi r24, 0x29 ; 41 + c4: 94 e0 ldi r25, 0x04 ; 4 + c6: 0e 94 49 00 call 0x92 ; 0x92 + ca: 08 0f add r16, r24 + cc: 11 1d adc r17, r1 +return readpointer; +} + ce: c8 01 movw r24, r16 + d0: 1f 91 pop r17 + d2: 0f 91 pop r16 + d4: 08 95 ret + +000000d6 : +return writepointer; +} + +// S0_RX_RSR +U16 get_S0_RX_RSR() +{ + d6: 0f 93 push r16 + d8: 1f 93 push r17 +U16 received_size; +received_size=w5100_read(S0_RX_RSR0); + da: 86 e2 ldi r24, 0x26 ; 38 + dc: 94 e0 ldi r25, 0x04 ; 4 + de: 0e 94 49 00 call 0x92 ; 0x92 +received_size = received_size << 8; + e2: 18 2f mov r17, r24 + e4: 00 e0 ldi r16, 0x00 ; 0 +received_size += w5100_read(S0_RX_RSR1); // S0_RX_RSR1 is the least significant byte ... + e6: 87 e2 ldi r24, 0x27 ; 39 + e8: 94 e0 ldi r25, 0x04 ; 4 + ea: 0e 94 49 00 call 0x92 ; 0x92 + ee: 08 0f add r16, r24 + f0: 11 1d adc r17, r1 +return received_size; +} + f2: c8 01 movw r24, r16 + f4: 1f 91 pop r17 + f6: 0f 91 pop r16 + f8: 08 95 ret + +000000fa : +return readpointer; +} + +// S0_TX_WR +U16 get_S0_TX_WR() +{ + fa: 0f 93 push r16 + fc: 1f 93 push r17 +U16 writepointer; +writepointer=w5100_read(S0_TX_WR0); + fe: 84 e2 ldi r24, 0x24 ; 36 + 100: 94 e0 ldi r25, 0x04 ; 4 + 102: 0e 94 49 00 call 0x92 ; 0x92 +writepointer = writepointer << 8; + 106: 18 2f mov r17, r24 + 108: 00 e0 ldi r16, 0x00 ; 0 +writepointer += w5100_read(S0_TX_WR1); + 10a: 85 e2 ldi r24, 0x25 ; 37 + 10c: 94 e0 ldi r25, 0x04 ; 4 + 10e: 0e 94 49 00 call 0x92 ; 0x92 + 112: 08 0f add r16, r24 + 114: 11 1d adc r17, r1 +return writepointer; +} + 116: c8 01 movw r24, r16 + 118: 1f 91 pop r17 + 11a: 0f 91 pop r16 + 11c: 08 95 ret + +0000011e : +return freesize; +} + +// S0_TX_RD +U16 get_S0_TX_RD() +{ + 11e: 0f 93 push r16 + 120: 1f 93 push r17 +U16 readpointer; +readpointer=w5100_read(S0_TX_RD0); + 122: 82 e2 ldi r24, 0x22 ; 34 + 124: 94 e0 ldi r25, 0x04 ; 4 + 126: 0e 94 49 00 call 0x92 ; 0x92 +readpointer = readpointer << 8; + 12a: 18 2f mov r17, r24 + 12c: 00 e0 ldi r16, 0x00 ; 0 +readpointer += w5100_read(S0_TX_RD1); + 12e: 83 e2 ldi r24, 0x23 ; 35 + 130: 94 e0 ldi r25, 0x04 ; 4 + 132: 0e 94 49 00 call 0x92 ; 0x92 + 136: 08 0f add r16, r24 + 138: 11 1d adc r17, r1 +return readpointer; +} + 13a: c8 01 movw r24, r16 + 13c: 1f 91 pop r17 + 13e: 0f 91 pop r16 + 140: 08 95 ret + +00000142 : + + +// getters of TX and RX registers +// S0_TX_FSR +U16 get_S0_TX_FSR() +{ + 142: 0f 93 push r16 + 144: 1f 93 push r17 +U16 freesize; +freesize=w5100_read(S0_TX_FSR0); + 146: 80 e2 ldi r24, 0x20 ; 32 + 148: 94 e0 ldi r25, 0x04 ; 4 + 14a: 0e 94 49 00 call 0x92 ; 0x92 +freesize = freesize << 8; + 14e: 18 2f mov r17, r24 + 150: 00 e0 ldi r16, 0x00 ; 0 +freesize += w5100_read(S0_TX_FSR1); + 152: 81 e2 ldi r24, 0x21 ; 33 + 154: 94 e0 ldi r25, 0x04 ; 4 + 156: 0e 94 49 00 call 0x92 ; 0x92 + 15a: 08 0f add r16, r24 + 15c: 11 1d adc r17, r1 +return freesize; +} + 15e: c8 01 movw r24, r16 + 160: 1f 91 pop r17 + 162: 0f 91 pop r16 + 164: 08 95 ret + +00000166 : + +} + +U08 w5100_sock_status() +{ + return w5100_read(S0_SR); + 166: 83 e0 ldi r24, 0x03 ; 3 + 168: 94 e0 ldi r25, 0x04 ; 4 + 16a: 0e 94 49 00 call 0x92 ; 0x92 +} + 16e: 08 95 ret + +00000170 : +} + + +BOOL w5100_is_established() +{ + if ( w5100_read(S0_SR) == SR_SOCK_ESTABLISHED ) + 170: 83 e0 ldi r24, 0x03 ; 3 + 172: 94 e0 ldi r25, 0x04 ; 4 + 174: 0e 94 49 00 call 0x92 ; 0x92 + 178: 87 31 cpi r24, 0x17 ; 23 + 17a: 21 f4 brne .+8 ; 0x184 + { + sock0_connection_established = true; + 17c: 81 e0 ldi r24, 0x01 ; 1 + 17e: 80 93 98 05 sts 0x0598, r24 + 182: 02 c0 rjmp .+4 ; 0x188 + } + else + { + sock0_connection_established = false; + 184: 10 92 98 05 sts 0x0598, r1 + } + return sock0_connection_established; + 188: 80 91 98 05 lds r24, 0x0598 + +} + 18c: 08 95 ret + +0000018e : + +//----------------------------------------------------------------------------- + +void w5100_write( U16 addr, U08 data) +{ +spi_write_buffer[0]=0xF0; + 18e: 20 ef ldi r18, 0xF0 ; 240 + 190: 20 93 e6 05 sts 0x05E6, r18 +spi_write_buffer[1]=(U08)(addr>>8); + 194: 90 93 e7 05 sts 0x05E7, r25 +spi_write_buffer[2]=(U08)(addr); + 198: 80 93 e8 05 sts 0x05E8, r24 +spi_write_buffer[3]=data; + 19c: 60 93 e9 05 sts 0x05E9, r22 + +spi_transfer(4, 0); + 1a0: 84 e0 ldi r24, 0x04 ; 4 + 1a2: 60 e0 ldi r22, 0x00 ; 0 + 1a4: 0e 94 c5 09 call 0x138a ; 0x138a +// spi_read_buffer should contain 0x00 0x01 0x02 and 0x03 ... nice check! +} + 1a8: 08 95 ret + +000001aa : +w5100_write(S0_TX_WR1, low_byte); +} + +// S0_TX_RD +void set_S0_RX_RD(U16 value) +{ + 1aa: 1f 93 push r17 + 1ac: 18 2f mov r17, r24 + 1ae: 69 2f mov r22, r25 +U08 high_byte = (value>>8); +U08 low_byte = value&0x00FF; + +w5100_write(S0_RX_RD0, high_byte); + 1b0: 88 e2 ldi r24, 0x28 ; 40 + 1b2: 94 e0 ldi r25, 0x04 ; 4 + 1b4: 0e 94 c7 00 call 0x18e ; 0x18e +w5100_write(S0_RX_RD1, low_byte); + 1b8: 89 e2 ldi r24, 0x29 ; 41 + 1ba: 94 e0 ldi r25, 0x04 ; 4 + 1bc: 61 2f mov r22, r17 + 1be: 0e 94 c7 00 call 0x18e ; 0x18e +} + 1c2: 1f 91 pop r17 + 1c4: 08 95 ret + +000001c6 : + +U08 w5100_get_RX(U08 NumBytes, BOOL send_ACK) +{ + 1c6: 4f 92 push r4 + 1c8: 5f 92 push r5 + 1ca: 7f 92 push r7 + 1cc: 8f 92 push r8 + 1ce: 9f 92 push r9 + 1d0: af 92 push r10 + 1d2: bf 92 push r11 + 1d4: cf 92 push r12 + 1d6: df 92 push r13 + 1d8: ef 92 push r14 + 1da: ff 92 push r15 + 1dc: 0f 93 push r16 + 1de: 1f 93 push r17 + 1e0: cf 93 push r28 + 1e2: df 93 push r29 + 1e4: 08 2f mov r16, r24 + U16 size = get_S0_RX_RSR(); + 1e6: 0e 94 6b 00 call 0xd6 ; 0xd6 + 1ea: 9c 01 movw r18, r24 + U16 upper_size, lower_size; + if (NumBytes > ETH_READ_BUFFER_SIZE) + { + NumBytes = ETH_READ_BUFFER_SIZE; + } + if (size == 0) + 1ec: 00 97 sbiw r24, 0x00 ; 0 + 1ee: 11 f4 brne .+4 ; 0x1f4 + 1f0: 77 24 eor r7, r7 + 1f2: ae c0 rjmp .+348 ; 0x350 + 1f4: 70 2e mov r7, r16 + 1f6: 80 e1 ldi r24, 0x10 ; 16 + 1f8: 80 17 cp r24, r16 + 1fa: 10 f4 brcc .+4 ; 0x200 + 1fc: 40 e1 ldi r20, 0x10 ; 16 + 1fe: 74 2e mov r7, r20 + { + return 0; + } + else if ( size < NumBytes ) + 200: 87 2d mov r24, r7 + 202: 90 e0 ldi r25, 0x00 ; 0 + 204: 28 17 cp r18, r24 + 206: 39 07 cpc r19, r25 + 208: 08 f4 brcc .+2 ; 0x20c + { + NumBytes = size; + 20a: 72 2e mov r7, r18 + } + + // now calculate the offset address + // calculated according to W5100 datasheet page: 43 + U16 last_RX_read_pointer = get_S0_RX_RD(); + 20c: 0e 94 59 00 call 0xb2 ; 0xb2 + 210: 4c 01 movw r8, r24 + U16 offset = last_RX_read_pointer & S0_RX_MASK; + 212: ec 01 movw r28, r24 + 214: df 70 andi r29, 0x0F ; 15 + U16 start_address = S0_RX_BASE + offset; + 216: c1 2c mov r12, r1 + 218: 90 e6 ldi r25, 0x60 ; 96 + 21a: d9 2e mov r13, r25 + 21c: cc 0e add r12, r28 + 21e: dd 1e adc r13, r29 + + usart_write_str("last_read_pointer:"); + 220: 80 e6 ldi r24, 0x60 ; 96 + 222: 90 e0 ldi r25, 0x00 ; 0 + 224: 0e 94 d6 0a call 0x15ac ; 0x15ac + usart_write_U16_hex(last_RX_read_pointer); + 228: c4 01 movw r24, r8 + 22a: 0e 94 69 0b call 0x16d2 ; 0x16d2 + usart_write_str("\noffset:"); + 22e: 83 e7 ldi r24, 0x73 ; 115 + 230: 90 e0 ldi r25, 0x00 ; 0 + 232: 0e 94 d6 0a call 0x15ac ; 0x15ac + usart_write_U16_hex(offset); + 236: ce 01 movw r24, r28 + 238: 0e 94 69 0b call 0x16d2 ; 0x16d2 + usart_write_str("\nstart_address:"); + 23c: 8c e7 ldi r24, 0x7C ; 124 + 23e: 90 e0 ldi r25, 0x00 ; 0 + 240: 0e 94 d6 0a call 0x15ac ; 0x15ac + usart_write_U16_hex(start_address); + 244: c6 01 movw r24, r12 + 246: 0e 94 69 0b call 0x16d2 ; 0x16d2 + usart_write_char('\n'); + 24a: 8a e0 ldi r24, 0x0A ; 10 + 24c: 0e 94 c9 0a call 0x1592 ; 0x1592 + + if ((offset + NumBytes) > (S0_RX_MASK + 1) ) // if data is turned over in RX-mem + 250: a7 2c mov r10, r7 + 252: bb 24 eor r11, r11 + 254: c5 01 movw r24, r10 + 256: 8c 0f add r24, r28 + 258: 9d 1f adc r25, r29 + 25a: 81 50 subi r24, 0x01 ; 1 + 25c: 90 41 sbci r25, 0x10 ; 16 + 25e: 18 f4 brcc .+6 ; 0x266 + 260: c0 e0 ldi r28, 0x00 ; 0 + 262: d0 e0 ldi r29, 0x00 ; 0 + 264: 37 c0 rjmp .+110 ; 0x2d4 + { + upper_size = (S0_RX_MASK + 1) - offset; + 266: e1 2c mov r14, r1 + 268: 80 e1 ldi r24, 0x10 ; 16 + 26a: f8 2e mov r15, r24 + 26c: ec 1a sub r14, r28 + 26e: fd 0a sbc r15, r29 + lower_size = NumBytes - upper_size; + 270: 25 01 movw r4, r10 + 272: 4e 18 sub r4, r14 + 274: 5f 08 sbc r5, r15 + 276: 00 e0 ldi r16, 0x00 ; 0 + 278: 09 c0 rjmp .+18 ; 0x28c + for (U08 i = 0; i < upper_size; ++i) + { + eth_read_buffer[i] = w5100_read(start_address + i); + 27a: ce 01 movw r24, r28 + 27c: 8c 0d add r24, r12 + 27e: 9d 1d adc r25, r13 + 280: 0e 94 49 00 call 0x92 ; 0x92 + 284: cd 53 subi r28, 0x3D ; 61 + 286: da 4f sbci r29, 0xFA ; 250 + 288: 88 83 st Y, r24 + + if ((offset + NumBytes) > (S0_RX_MASK + 1) ) // if data is turned over in RX-mem + { + upper_size = (S0_RX_MASK + 1) - offset; + lower_size = NumBytes - upper_size; + for (U08 i = 0; i < upper_size; ++i) + 28a: 0f 5f subi r16, 0xFF ; 255 + 28c: c0 2f mov r28, r16 + 28e: d0 e0 ldi r29, 0x00 ; 0 + 290: ce 15 cp r28, r14 + 292: df 05 cpc r29, r15 + 294: 90 f3 brcs .-28 ; 0x27a + 296: dd 24 eor r13, r13 + 298: 0c c0 rjmp .+24 ; 0x2b2 + { + eth_read_buffer[i] = w5100_read(start_address + i); + } + for (U08 i = 0; i < lower_size; ++i) + { + eth_read_buffer[upper_size + i] = w5100_read(S0_RX_BASE + i); + 29a: 8c 01 movw r16, r24 + 29c: 0e 0d add r16, r14 + 29e: 1f 1d adc r17, r15 + 2a0: 80 50 subi r24, 0x00 ; 0 + 2a2: 90 4a sbci r25, 0xA0 ; 160 + 2a4: 0e 94 49 00 call 0x92 ; 0x92 + 2a8: 0d 53 subi r16, 0x3D ; 61 + 2aa: 1a 4f sbci r17, 0xFA ; 250 + 2ac: f8 01 movw r30, r16 + 2ae: 80 83 st Z, r24 + lower_size = NumBytes - upper_size; + for (U08 i = 0; i < upper_size; ++i) + { + eth_read_buffer[i] = w5100_read(start_address + i); + } + for (U08 i = 0; i < lower_size; ++i) + 2b0: d3 94 inc r13 + 2b2: 8d 2d mov r24, r13 + 2b4: 90 e0 ldi r25, 0x00 ; 0 + 2b6: 84 15 cp r24, r4 + 2b8: 95 05 cpc r25, r5 + 2ba: 78 f3 brcs .-34 ; 0x29a + 2bc: 0d c0 rjmp .+26 ; 0x2d8 + } + else // if not data turn over in RX-mem + { + for (U08 i = 0; i < NumBytes; ++i) + { + eth_read_buffer[i] = w5100_read(start_address + i); + 2be: c6 01 movw r24, r12 + 2c0: 0e 94 49 00 call 0x92 ; 0x92 + 2c4: fe 01 movw r30, r28 + 2c6: ed 53 subi r30, 0x3D ; 61 + 2c8: fa 4f sbci r31, 0xFA ; 250 + 2ca: 80 83 st Z, r24 + 2cc: 21 96 adiw r28, 0x01 ; 1 + 2ce: 08 94 sec + 2d0: c1 1c adc r12, r1 + 2d2: d1 1c adc r13, r1 + eth_read_buffer[upper_size + i] = w5100_read(S0_RX_BASE + i); + } + } + else // if not data turn over in RX-mem + { + for (U08 i = 0; i < NumBytes; ++i) + 2d4: c7 15 cp r28, r7 + 2d6: 98 f3 brcs .-26 ; 0x2be + eth_read_buffer[i] = w5100_read(start_address + i); + } + } + + // inform W5100 about how much data was read out. + set_S0_RX_RD(last_RX_read_pointer + NumBytes); + 2d8: c5 01 movw r24, r10 + 2da: 88 0d add r24, r8 + 2dc: 99 1d adc r25, r9 + 2de: 0e 94 d5 00 call 0x1aa ; 0x1aa + w5100_write ( S0_CR, CR_RECV ); + 2e2: 81 e0 ldi r24, 0x01 ; 1 + 2e4: 94 e0 ldi r25, 0x04 ; 4 + 2e6: 60 e4 ldi r22, 0x40 ; 64 + 2e8: 0e 94 c7 00 call 0x18e ; 0x18e + + usart_write_U16_hex(get_S0_TX_FSR()); usart_write_char('\t'); usart_write_char('|'); + 2ec: 0e 94 a1 00 call 0x142 ; 0x142 + 2f0: 0e 94 69 0b call 0x16d2 ; 0x16d2 + 2f4: 89 e0 ldi r24, 0x09 ; 9 + 2f6: 0e 94 c9 0a call 0x1592 ; 0x1592 + 2fa: 8c e7 ldi r24, 0x7C ; 124 + 2fc: 0e 94 c9 0a call 0x1592 ; 0x1592 + usart_write_U16_hex(get_S0_TX_RD()); usart_write_char('\t'); usart_write_char('|'); + 300: 0e 94 8f 00 call 0x11e ; 0x11e + 304: 0e 94 69 0b call 0x16d2 ; 0x16d2 + 308: 89 e0 ldi r24, 0x09 ; 9 + 30a: 0e 94 c9 0a call 0x1592 ; 0x1592 + 30e: 8c e7 ldi r24, 0x7C ; 124 + 310: 0e 94 c9 0a call 0x1592 ; 0x1592 + usart_write_U16_hex(get_S0_TX_WR()); usart_write_char('\t'); usart_write_char('|'); + 314: 0e 94 7d 00 call 0xfa ; 0xfa + 318: 0e 94 69 0b call 0x16d2 ; 0x16d2 + 31c: 89 e0 ldi r24, 0x09 ; 9 + 31e: 0e 94 c9 0a call 0x1592 ; 0x1592 + 322: 8c e7 ldi r24, 0x7C ; 124 + 324: 0e 94 c9 0a call 0x1592 ; 0x1592 + usart_write_U16_hex(get_S0_RX_RSR()); usart_write_char('\t'); usart_write_char('|'); + 328: 0e 94 6b 00 call 0xd6 ; 0xd6 + 32c: 0e 94 69 0b call 0x16d2 ; 0x16d2 + 330: 89 e0 ldi r24, 0x09 ; 9 + 332: 0e 94 c9 0a call 0x1592 ; 0x1592 + 336: 8c e7 ldi r24, 0x7C ; 124 + 338: 0e 94 c9 0a call 0x1592 ; 0x1592 + usart_write_U16_hex(get_S0_RX_RD()); usart_write_char('\t'); usart_write_char('|'); + 33c: 0e 94 59 00 call 0xb2 ; 0xb2 + 340: 0e 94 69 0b call 0x16d2 ; 0x16d2 + 344: 89 e0 ldi r24, 0x09 ; 9 + 346: 0e 94 c9 0a call 0x1592 ; 0x1592 + 34a: 8c e7 ldi r24, 0x7C ; 124 + 34c: 0e 94 c9 0a call 0x1592 ; 0x1592 + { + //w5100_write ( S0_CR, CR_RECV ); + } + + return NumBytes; +} + 350: 87 2d mov r24, r7 + 352: df 91 pop r29 + 354: cf 91 pop r28 + 356: 1f 91 pop r17 + 358: 0f 91 pop r16 + 35a: ff 90 pop r15 + 35c: ef 90 pop r14 + 35e: df 90 pop r13 + 360: cf 90 pop r12 + 362: bf 90 pop r11 + 364: af 90 pop r10 + 366: 9f 90 pop r9 + 368: 8f 90 pop r8 + 36a: 7f 90 pop r7 + 36c: 5f 90 pop r5 + 36e: 4f 90 pop r4 + 370: 08 95 ret + +00000372 : +} + +// setters for some RX and TX registers +// S0_TX_WR +void set_S0_TX_WR(U16 value) +{ + 372: 1f 93 push r17 + 374: 18 2f mov r17, r24 + 376: 69 2f mov r22, r25 +U08 high_byte = (value>>8); +U08 low_byte = value&0x00FF; +w5100_write(S0_TX_WR0, high_byte); + 378: 84 e2 ldi r24, 0x24 ; 36 + 37a: 94 e0 ldi r25, 0x04 ; 4 + 37c: 0e 94 c7 00 call 0x18e ; 0x18e +w5100_write(S0_TX_WR1, low_byte); + 380: 85 e2 ldi r24, 0x25 ; 37 + 382: 94 e0 ldi r25, 0x04 ; 4 + 384: 61 2f mov r22, r17 + 386: 0e 94 c7 00 call 0x18e ; 0x18e +} + 38a: 1f 91 pop r17 + 38c: 08 95 ret + +0000038e : + + return NumBytes; +} + +// returns number of words, transmitted into TX - buffer. +U08 w5100_set_TX(U08 NumBytes) { + 38e: 8f 92 push r8 + 390: 9f 92 push r9 + 392: af 92 push r10 + 394: bf 92 push r11 + 396: cf 92 push r12 + 398: df 92 push r13 + 39a: ef 92 push r14 + 39c: ff 92 push r15 + 39e: 0f 93 push r16 + 3a0: 1f 93 push r17 + 3a2: cf 93 push r28 + 3a4: df 93 push r29 + 3a6: 18 2f mov r17, r24 + U16 freesize = get_S0_TX_FSR(); + 3a8: 0e 94 a1 00 call 0x142 ; 0x142 + 3ac: ec 01 movw r28, r24 + if (freesize == 0) + 3ae: 00 97 sbiw r24, 0x00 ; 0 + 3b0: 11 f4 brne .+4 ; 0x3b6 + 3b2: 00 e0 ldi r16, 0x00 ; 0 + 3b4: 60 c0 rjmp .+192 ; 0x476 + { + return 0; + } + + U16 last_TX_write_pointer = get_S0_TX_WR(); + 3b6: 0e 94 7d 00 call 0xfa ; 0xfa + 3ba: 4c 01 movw r8, r24 + U16 offset = last_TX_write_pointer & S0_TX_MASK; + 3bc: 9c 01 movw r18, r24 + 3be: 3f 70 andi r19, 0x0F ; 15 + U16 start_address = S0_TX_BASE + offset; + 3c0: e1 2c mov r14, r1 + 3c2: 50 e4 ldi r21, 0x40 ; 64 + 3c4: f5 2e mov r15, r21 + 3c6: e2 0e add r14, r18 + 3c8: f3 1e adc r15, r19 + 3ca: 01 2f mov r16, r17 + 3cc: 11 31 cpi r17, 0x11 ; 17 + 3ce: 08 f0 brcs .+2 ; 0x3d2 + 3d0: 00 e1 ldi r16, 0x10 ; 16 + } + if (freesize == 0) + { + return 0; + } + else if ( freesize < NumBytes ) + 3d2: 80 2f mov r24, r16 + 3d4: 90 e0 ldi r25, 0x00 ; 0 + 3d6: c8 17 cp r28, r24 + 3d8: d9 07 cpc r29, r25 + 3da: 08 f4 brcc .+2 ; 0x3de + { + NumBytes = freesize; + 3dc: 0c 2f mov r16, r28 + } + + // now calculate the offset address + // calculated according to W5100 datasheet page: 44 + + if ((offset + NumBytes) > (S0_RX_MASK + 1) ) // if data is turned over in RX-mem + 3de: c0 2e mov r12, r16 + 3e0: dd 24 eor r13, r13 + 3e2: c6 01 movw r24, r12 + 3e4: 82 0f add r24, r18 + 3e6: 93 1f adc r25, r19 + 3e8: 81 50 subi r24, 0x01 ; 1 + 3ea: 90 41 sbci r25, 0x10 ; 16 + 3ec: 18 f4 brcc .+6 ; 0x3f4 + 3ee: c0 e0 ldi r28, 0x00 ; 0 + 3f0: d0 e0 ldi r29, 0x00 ; 0 + 3f2: 35 c0 rjmp .+106 ; 0x45e + { + upper_size = (S0_RX_MASK + 1) - offset; + 3f4: c0 e0 ldi r28, 0x00 ; 0 + 3f6: d0 e1 ldi r29, 0x10 ; 16 + 3f8: c2 1b sub r28, r18 + 3fa: d3 0b sbc r29, r19 + lower_size = NumBytes - upper_size; + 3fc: 56 01 movw r10, r12 + 3fe: ac 1a sub r10, r28 + 400: bd 0a sbc r11, r29 + 402: 10 e0 ldi r17, 0x00 ; 0 + 404: 09 c0 rjmp .+18 ; 0x418 + for (U08 i = 0; i < upper_size; ++i) + { + w5100_write(start_address + i, eth_write_buffer[i]); + 406: fc 01 movw r30, r24 + 408: ed 52 subi r30, 0x2D ; 45 + 40a: fa 4f sbci r31, 0xFA ; 250 + 40c: 60 81 ld r22, Z + 40e: 8e 0d add r24, r14 + 410: 9f 1d adc r25, r15 + 412: 0e 94 c7 00 call 0x18e ; 0x18e + + if ((offset + NumBytes) > (S0_RX_MASK + 1) ) // if data is turned over in RX-mem + { + upper_size = (S0_RX_MASK + 1) - offset; + lower_size = NumBytes - upper_size; + for (U08 i = 0; i < upper_size; ++i) + 416: 1f 5f subi r17, 0xFF ; 255 + 418: 81 2f mov r24, r17 + 41a: 90 e0 ldi r25, 0x00 ; 0 + 41c: 8c 17 cp r24, r28 + 41e: 9d 07 cpc r25, r29 + 420: 90 f3 brcs .-28 ; 0x406 + 422: 10 e0 ldi r17, 0x00 ; 0 + 424: 0b c0 rjmp .+22 ; 0x43c + { + w5100_write(start_address + i, eth_write_buffer[i]); + } + for (U08 i = 0; i < lower_size; ++i) + { + w5100_write(S0_RX_BASE + i, eth_write_buffer[upper_size+i]); + 426: fc 01 movw r30, r24 + 428: ec 0f add r30, r28 + 42a: fd 1f adc r31, r29 + 42c: ed 52 subi r30, 0x2D ; 45 + 42e: fa 4f sbci r31, 0xFA ; 250 + 430: 60 81 ld r22, Z + 432: 80 50 subi r24, 0x00 ; 0 + 434: 90 4a sbci r25, 0xA0 ; 160 + 436: 0e 94 c7 00 call 0x18e ; 0x18e + lower_size = NumBytes - upper_size; + for (U08 i = 0; i < upper_size; ++i) + { + w5100_write(start_address + i, eth_write_buffer[i]); + } + for (U08 i = 0; i < lower_size; ++i) + 43a: 1f 5f subi r17, 0xFF ; 255 + 43c: 81 2f mov r24, r17 + 43e: 90 e0 ldi r25, 0x00 ; 0 + 440: 8a 15 cp r24, r10 + 442: 9b 05 cpc r25, r11 + 444: 80 f3 brcs .-32 ; 0x426 + 446: 0d c0 rjmp .+26 ; 0x462 + } + else // if not data turn over in RX-mem + { + for (U08 i = 0; i < NumBytes; ++i) + { + w5100_write(start_address + i, eth_write_buffer[i]); + 448: fe 01 movw r30, r28 + 44a: ed 52 subi r30, 0x2D ; 45 + 44c: fa 4f sbci r31, 0xFA ; 250 + 44e: 60 81 ld r22, Z + 450: c7 01 movw r24, r14 + 452: 0e 94 c7 00 call 0x18e ; 0x18e + 456: 21 96 adiw r28, 0x01 ; 1 + 458: 08 94 sec + 45a: e1 1c adc r14, r1 + 45c: f1 1c adc r15, r1 + w5100_write(S0_RX_BASE + i, eth_write_buffer[upper_size+i]); + } + } + else // if not data turn over in RX-mem + { + for (U08 i = 0; i < NumBytes; ++i) + 45e: c0 17 cp r28, r16 + 460: 98 f3 brcs .-26 ; 0x448 + w5100_write(start_address + i, eth_write_buffer[i]); + } + } + + // inform W5100 about how much data was read out. + set_S0_TX_WR(last_TX_write_pointer + NumBytes); + 462: c6 01 movw r24, r12 + 464: 88 0d add r24, r8 + 466: 99 1d adc r25, r9 + 468: 0e 94 b9 01 call 0x372 ; 0x372 + + // tell it to send now the data away + w5100_write( S0_CR, CR_SEND); + 46c: 81 e0 ldi r24, 0x01 ; 1 + 46e: 94 e0 ldi r25, 0x04 ; 4 + 470: 60 e2 ldi r22, 0x20 ; 32 + 472: 0e 94 c7 00 call 0x18e ; 0x18e + + return NumBytes; +} + 476: 80 2f mov r24, r16 + 478: df 91 pop r29 + 47a: cf 91 pop r28 + 47c: 1f 91 pop r17 + 47e: 0f 91 pop r16 + 480: ff 90 pop r15 + 482: ef 90 pop r14 + 484: df 90 pop r13 + 486: cf 90 pop r12 + 488: bf 90 pop r11 + 48a: af 90 pop r10 + 48c: 9f 90 pop r9 + 48e: 8f 90 pop r8 + 490: 08 95 ret + +00000492 : +return spi_read_buffer[3]; +// spi_read_buffer should contain 0x00 0x01 0x02 and data ... nice check! +} + +U08 w5100_init (void) +{ + 492: 1f 93 push r17 +U08 sock0_status = 0x00; + + // set FSCs MAC Address to value defined in w5100_spi_interface.h + w5100_write( CM_SHAR0, FSC_MAC_ADDRESS0 ); + 494: 89 e0 ldi r24, 0x09 ; 9 + 496: 90 e0 ldi r25, 0x00 ; 0 + 498: 6a ef ldi r22, 0xFA ; 250 + 49a: 0e 94 c7 00 call 0x18e ; 0x18e + w5100_write( CM_SHAR1, FSC_MAC_ADDRESS1 ); + 49e: 8a e0 ldi r24, 0x0A ; 10 + 4a0: 90 e0 ldi r25, 0x00 ; 0 + 4a2: 67 ec ldi r22, 0xC7 ; 199 + 4a4: 0e 94 c7 00 call 0x18e ; 0x18e + w5100_write( CM_SHAR2, FSC_MAC_ADDRESS2 ); + 4a8: 8b e0 ldi r24, 0x0B ; 11 + 4aa: 90 e0 ldi r25, 0x00 ; 0 + 4ac: 6f e0 ldi r22, 0x0F ; 15 + 4ae: 0e 94 c7 00 call 0x18e ; 0x18e + w5100_write( CM_SHAR3, FSC_MAC_ADDRESS3 ); + 4b2: 8c e0 ldi r24, 0x0C ; 12 + 4b4: 90 e0 ldi r25, 0x00 ; 0 + 4b6: 6d ea ldi r22, 0xAD ; 173 + 4b8: 0e 94 c7 00 call 0x18e ; 0x18e + w5100_write( CM_SHAR4, FSC_MAC_ADDRESS4 ); + 4bc: 8d e0 ldi r24, 0x0D ; 13 + 4be: 90 e0 ldi r25, 0x00 ; 0 + 4c0: 62 e2 ldi r22, 0x22 ; 34 + 4c2: 0e 94 c7 00 call 0x18e ; 0x18e + w5100_write( CM_SHAR5, FSC_MAC_ADDRESS5 ); + 4c6: 8e e0 ldi r24, 0x0E ; 14 + 4c8: 90 e0 ldi r25, 0x00 ; 0 + 4ca: 61 e0 ldi r22, 0x01 ; 1 + 4cc: 0e 94 c7 00 call 0x18e ; 0x18e + + //set IP + w5100_write( CM_SIPR0, FSC_IP_ADDRESS0 ); + 4d0: 8f e0 ldi r24, 0x0F ; 15 + 4d2: 90 e0 ldi r25, 0x00 ; 0 + 4d4: 60 ec ldi r22, 0xC0 ; 192 + 4d6: 0e 94 c7 00 call 0x18e ; 0x18e + w5100_write( CM_SIPR1, FSC_IP_ADDRESS1 ); + 4da: 80 e1 ldi r24, 0x10 ; 16 + 4dc: 90 e0 ldi r25, 0x00 ; 0 + 4de: 68 ea ldi r22, 0xA8 ; 168 + 4e0: 0e 94 c7 00 call 0x18e ; 0x18e + w5100_write( CM_SIPR2, FSC_IP_ADDRESS2 ); + 4e4: 81 e1 ldi r24, 0x11 ; 17 + 4e6: 90 e0 ldi r25, 0x00 ; 0 + 4e8: 60 e0 ldi r22, 0x00 ; 0 + 4ea: 0e 94 c7 00 call 0x18e ; 0x18e + w5100_write( CM_SIPR3, FSC_IP_ADDRESS3 ); + 4ee: 82 e1 ldi r24, 0x12 ; 18 + 4f0: 90 e0 ldi r25, 0x00 ; 0 + 4f2: 62 e0 ldi r22, 0x02 ; 2 + 4f4: 0e 94 c7 00 call 0x18e ; 0x18e + + // set subnet mask + w5100_write( CM_SUBR0, FSC_SUBNET_MASK0 ); + 4f8: 85 e0 ldi r24, 0x05 ; 5 + 4fa: 90 e0 ldi r25, 0x00 ; 0 + 4fc: 6f ef ldi r22, 0xFF ; 255 + 4fe: 0e 94 c7 00 call 0x18e ; 0x18e + w5100_write( CM_SUBR1, FSC_SUBNET_MASK1 ); + 502: 86 e0 ldi r24, 0x06 ; 6 + 504: 90 e0 ldi r25, 0x00 ; 0 + 506: 6f ef ldi r22, 0xFF ; 255 + 508: 0e 94 c7 00 call 0x18e ; 0x18e + w5100_write( CM_SUBR2, FSC_SUBNET_MASK2 ); + 50c: 87 e0 ldi r24, 0x07 ; 7 + 50e: 90 e0 ldi r25, 0x00 ; 0 + 510: 6f ef ldi r22, 0xFF ; 255 + 512: 0e 94 c7 00 call 0x18e ; 0x18e + w5100_write( CM_SUBR3, FSC_SUBNET_MASK3 ); + 516: 88 e0 ldi r24, 0x08 ; 8 + 518: 90 e0 ldi r25, 0x00 ; 0 + 51a: 60 e0 ldi r22, 0x00 ; 0 + 51c: 0e 94 c7 00 call 0x18e ; 0x18e + + // set IP of Gateway used by FSC + w5100_write( CM_GAR0, FSC_GATEWAY_ADDRESS0 ); + 520: 81 e0 ldi r24, 0x01 ; 1 + 522: 90 e0 ldi r25, 0x00 ; 0 + 524: 60 ec ldi r22, 0xC0 ; 192 + 526: 0e 94 c7 00 call 0x18e ; 0x18e + w5100_write( CM_GAR1, FSC_GATEWAY_ADDRESS1 ); + 52a: 82 e0 ldi r24, 0x02 ; 2 + 52c: 90 e0 ldi r25, 0x00 ; 0 + 52e: 61 e2 ldi r22, 0x21 ; 33 + 530: 0e 94 c7 00 call 0x18e ; 0x18e + w5100_write( CM_GAR2, FSC_GATEWAY_ADDRESS2 ); + 534: 83 e0 ldi r24, 0x03 ; 3 + 536: 90 e0 ldi r25, 0x00 ; 0 + 538: 60 e6 ldi r22, 0x60 ; 96 + 53a: 0e 94 c7 00 call 0x18e ; 0x18e + w5100_write( CM_GAR3, FSC_GATEWAY_ADDRESS3 ); + 53e: 84 e0 ldi r24, 0x04 ; 4 + 540: 90 e0 ldi r25, 0x00 ; 0 + 542: 61 e0 ldi r22, 0x01 ; 1 + 544: 0e 94 c7 00 call 0x18e ; 0x18e + + //set socket read and write fifo sizes + w5100_write( CM_RMSR, 0x0A); // --> 4k for socket 0 and 1 + 548: 8a e1 ldi r24, 0x1A ; 26 + 54a: 90 e0 ldi r25, 0x00 ; 0 + 54c: 6a e0 ldi r22, 0x0A ; 10 + 54e: 0e 94 c7 00 call 0x18e ; 0x18e + w5100_write( CM_TMSR, 0x0A); // --> 4k for socket 0 and 1 + 552: 8b e1 ldi r24, 0x1B ; 27 + 554: 90 e0 ldi r25, 0x00 ; 0 + 556: 6a e0 ldi r22, 0x0A ; 10 + 558: 0e 94 c7 00 call 0x18e ; 0x18e + + + w5100_write ( S0_MR, 0x01); // set Socket 0 as TCP + 55c: 80 e0 ldi r24, 0x00 ; 0 + 55e: 94 e0 ldi r25, 0x04 ; 4 + 560: 61 e0 ldi r22, 0x01 ; 1 + 562: 0e 94 c7 00 call 0x18e ; 0x18e + w5100_write ( S0_PORT0, 0x13 ); // Port 5000 -> 0x1388 + 566: 84 e0 ldi r24, 0x04 ; 4 + 568: 94 e0 ldi r25, 0x04 ; 4 + 56a: 63 e1 ldi r22, 0x13 ; 19 + 56c: 0e 94 c7 00 call 0x18e ; 0x18e + w5100_write ( S0_PORT1, 0x88 ); + 570: 85 e0 ldi r24, 0x05 ; 5 + 572: 94 e0 ldi r25, 0x04 ; 4 + 574: 68 e8 ldi r22, 0x88 ; 136 + 576: 0e 94 c7 00 call 0x18e ; 0x18e + usart_write_str((pU08)"Issuing Socket open command. NOW\n"); + 57a: 8c e8 ldi r24, 0x8C ; 140 + 57c: 90 e0 ldi r25, 0x00 ; 0 + 57e: 0e 94 d6 0a call 0x15ac ; 0x15ac + w5100_write ( S0_CR, CR_OPEN ); // issue Socket open command + 582: 81 e0 ldi r24, 0x01 ; 1 + 584: 94 e0 ldi r25, 0x04 ; 4 + 586: 61 e0 ldi r22, 0x01 ; 1 + 588: 0e 94 c7 00 call 0x18e ; 0x18e + while (sock0_status != SR_SOCK_INIT) { + sock0_status = w5100_read(S0_SR); // request socket 0 status + 58c: 83 e0 ldi r24, 0x03 ; 3 + 58e: 94 e0 ldi r25, 0x04 ; 4 + 590: 0e 94 49 00 call 0x92 ; 0x92 + 594: 18 2f mov r17, r24 + usart_write_str((pU08)"Socket 0 status is:"); + 596: 8e ea ldi r24, 0xAE ; 174 + 598: 90 e0 ldi r25, 0x00 ; 0 + 59a: 0e 94 d6 0a call 0x15ac ; 0x15ac + usart_write_U08_hex(sock0_status); + 59e: 81 2f mov r24, r17 + 5a0: 0e 94 7d 0b call 0x16fa ; 0x16fa + usart_write_char('\n'); + 5a4: 8a e0 ldi r24, 0x0A ; 10 + 5a6: 0e 94 c9 0a call 0x1592 ; 0x1592 + w5100_write ( S0_MR, 0x01); // set Socket 0 as TCP + w5100_write ( S0_PORT0, 0x13 ); // Port 5000 -> 0x1388 + w5100_write ( S0_PORT1, 0x88 ); + usart_write_str((pU08)"Issuing Socket open command. NOW\n"); + w5100_write ( S0_CR, CR_OPEN ); // issue Socket open command + while (sock0_status != SR_SOCK_INIT) { + 5aa: 13 31 cpi r17, 0x13 ; 19 + 5ac: 79 f7 brne .-34 ; 0x58c + usart_write_str((pU08)"Socket 0 status is:"); + usart_write_U08_hex(sock0_status); + usart_write_char('\n'); + } + + usart_write_str((pU08)"Issuing Socket LISTEN command. NOW\n"); + 5ae: 82 ec ldi r24, 0xC2 ; 194 + 5b0: 90 e0 ldi r25, 0x00 ; 0 + 5b2: 0e 94 d6 0a call 0x15ac ; 0x15ac + w5100_write ( S0_CR, CR_LISTEN ); // issue Socket listen command + 5b6: 81 e0 ldi r24, 0x01 ; 1 + 5b8: 94 e0 ldi r25, 0x04 ; 4 + 5ba: 62 e0 ldi r22, 0x02 ; 2 + 5bc: 0e 94 c7 00 call 0x18e ; 0x18e + + while (sock0_status != SR_SOCK_LISTEN) { + sock0_status = w5100_read(S0_SR); // request socket 0 status + 5c0: 83 e0 ldi r24, 0x03 ; 3 + 5c2: 94 e0 ldi r25, 0x04 ; 4 + 5c4: 0e 94 49 00 call 0x92 ; 0x92 + 5c8: 18 2f mov r17, r24 + usart_write_str((pU08)"Socket 0 status is:"); + 5ca: 8e ea ldi r24, 0xAE ; 174 + 5cc: 90 e0 ldi r25, 0x00 ; 0 + 5ce: 0e 94 d6 0a call 0x15ac ; 0x15ac + usart_write_U08_hex(sock0_status); + 5d2: 81 2f mov r24, r17 + 5d4: 0e 94 7d 0b call 0x16fa ; 0x16fa + usart_write_char('\n'); + 5d8: 8a e0 ldi r24, 0x0A ; 10 + 5da: 0e 94 c9 0a call 0x1592 ; 0x1592 + } + + usart_write_str((pU08)"Issuing Socket LISTEN command. NOW\n"); + w5100_write ( S0_CR, CR_LISTEN ); // issue Socket listen command + + while (sock0_status != SR_SOCK_LISTEN) { + 5de: 14 31 cpi r17, 0x14 ; 20 + 5e0: 79 f7 brne .-34 ; 0x5c0 + usart_write_str((pU08)"Socket 0 status is:"); + usart_write_U08_hex(sock0_status); + usart_write_char('\n'); + } + return sock0_status; +} + 5e2: 84 e1 ldi r24, 0x14 ; 20 + 5e4: 1f 91 pop r17 + 5e6: 08 95 ret + +000005e8 : + SET_BIT(PORTD,SPI_AD_CS); +} + + +U32 read_adc(void) +{ + 5e8: ef 92 push r14 + 5ea: ff 92 push r15 + 5ec: 0f 93 push r16 + 5ee: 1f 93 push r17 + CLR_BIT(PORTD,SPI_AD_CS); // Set CS low + 5f0: 93 98 cbi 0x12, 3 ; 18 + spi_transfer_byte(AD0DAT_RD); // Next Operation is read from Main ADC Data Register + 5f2: 85 e4 ldi r24, 0x45 ; 69 + 5f4: 0e 94 be 09 call 0x137c ; 0x137c + SET_BIT(PORTD,SPI_AD_CS); + 5f8: 93 9a sbi 0x12, 3 ; 18 + can be achieved. +*/ +void +_delay_loop_1(uint8_t __count) +{ + __asm__ volatile ( + 5fa: 85 e8 ldi r24, 0x85 ; 133 + 5fc: 8a 95 dec r24 + 5fe: f1 f7 brne .-4 ; 0x5fc + _delay_us(50); + + CLR_BIT(PORTD,SPI_AD_CS); + 600: 93 98 cbi 0x12, 3 ; 18 + U32 value=0; // actually a 24bit value is returned + value |= spi_transfer_byte(0) ; + 602: 80 e0 ldi r24, 0x00 ; 0 + 604: 0e 94 be 09 call 0x137c ; 0x137c + value =value<<8; + 608: e8 2e mov r14, r24 + 60a: ff 24 eor r15, r15 + 60c: 00 e0 ldi r16, 0x00 ; 0 + 60e: 10 e0 ldi r17, 0x00 ; 0 + 610: 10 2f mov r17, r16 + 612: 0f 2d mov r16, r15 + 614: fe 2c mov r15, r14 + 616: ee 24 eor r14, r14 + value |= spi_transfer_byte(0) ; + 618: 80 e0 ldi r24, 0x00 ; 0 + 61a: 0e 94 be 09 call 0x137c ; 0x137c + 61e: 90 e0 ldi r25, 0x00 ; 0 + 620: a0 e0 ldi r26, 0x00 ; 0 + 622: b0 e0 ldi r27, 0x00 ; 0 + 624: e8 2a or r14, r24 + 626: f9 2a or r15, r25 + 628: 0a 2b or r16, r26 + 62a: 1b 2b or r17, r27 + value =value<<8; + 62c: 10 2f mov r17, r16 + 62e: 0f 2d mov r16, r15 + 630: fe 2c mov r15, r14 + 632: ee 24 eor r14, r14 + value |= spi_transfer_byte(0) ; + 634: 80 e0 ldi r24, 0x00 ; 0 + 636: 0e 94 be 09 call 0x137c ; 0x137c + SET_BIT(PORTD,SPI_AD_CS); // Set CS high + 63a: 93 9a sbi 0x12, 3 ; 18 + 63c: 28 2f mov r18, r24 + 63e: 30 e0 ldi r19, 0x00 ; 0 + 640: 40 e0 ldi r20, 0x00 ; 0 + 642: 50 e0 ldi r21, 0x00 ; 0 + 644: 2e 29 or r18, r14 + 646: 3f 29 or r19, r15 + 648: 40 2b or r20, r16 + 64a: 51 2b or r21, r17 + return value; +} + 64c: b9 01 movw r22, r18 + 64e: ca 01 movw r24, r20 + 650: 1f 91 pop r17 + 652: 0f 91 pop r16 + 654: ff 90 pop r15 + 656: ef 90 pop r14 + 658: 08 95 ret + +0000065a : + SET_BIT(PORTD,SPI_AD_CS); +} + +void stopconv(void) +{ + CLR_BIT(PORTD,SPI_AD_CS); // Set CS low + 65a: 93 98 cbi 0x12, 3 ; 18 + spi_transfer_byte(MODE_WR); // Next Operation is write to Mode Register + 65c: 81 e0 ldi r24, 0x01 ; 1 + 65e: 0e 94 be 09 call 0x137c ; 0x137c + SET_BIT(PORTD,SPI_AD_CS); + 662: 93 9a sbi 0x12, 3 ; 18 + CLR_BIT(PORTD,SPI_AD_CS); + 664: 93 98 cbi 0x12, 3 ; 18 + spi_transfer_byte(MODE_IDLE); + 666: 81 e0 ldi r24, 0x01 ; 1 + 668: 0e 94 be 09 call 0x137c ; 0x137c + SET_BIT(PORTD,SPI_AD_CS); + 66c: 93 9a sbi 0x12, 3 ; 18 +} + 66e: 08 95 ret + +00000670 : + + +} + +void startconv(U08 continuous) +{ + 670: 1f 93 push r17 + 672: 18 2f mov r17, r24 + CLR_BIT(PORTD,SPI_AD_CS); // Set CS low + 674: 93 98 cbi 0x12, 3 ; 18 + spi_transfer_byte(MODE_WR); // Next Operation is write to Mode Register + 676: 81 e0 ldi r24, 0x01 ; 1 + 678: 0e 94 be 09 call 0x137c ; 0x137c + SET_BIT(PORTD,SPI_AD_CS); + 67c: 93 9a sbi 0x12, 3 ; 18 + CLR_BIT(PORTD,SPI_AD_CS); + 67e: 93 98 cbi 0x12, 3 ; 18 + if (continuous) spi_transfer_byte(MODE_SINGLE); // Start new A/D conversion + 680: 11 23 and r17, r17 + 682: 11 f0 breq .+4 ; 0x688 + 684: 82 e0 ldi r24, 0x02 ; 2 + 686: 01 c0 rjmp .+2 ; 0x68a + else spi_transfer_byte(MODE_CONT); // Start continous conversion mode + 688: 83 e0 ldi r24, 0x03 ; 3 + 68a: 0e 94 be 09 call 0x137c ; 0x137c + SET_BIT(PORTD,SPI_AD_CS); + 68e: 93 9a sbi 0x12, 3 ; 18 +} + 690: 1f 91 pop r17 + 692: 08 95 ret + +00000694 : +#include "spi_master.h" + +//----------------------------------------------------------------------------- + +void ad7719_init(void) +{ + 694: 1f 93 push r17 + // #WEN (inversed write enable) must be zero inorder to clock more bits into the SPI interface. + // R/#W (read / not write) must be zero if the next operation will be a WRITE. one if the next is READ. + // A3-A0 denote the address of the next register. + + + CLR_BIT(ADC_PRT,ADC_RST); // Reset ADC (active low) + 696: 97 98 cbi 0x12, 7 ; 18 + SET_BIT(ADC_PRT,ADC_RST); // Stop Reset ADC + 698: 97 9a sbi 0x12, 7 ; 18 + + + CLR_BIT(PORTD,SPI_AD_CS); // Set CS low + 69a: 93 98 cbi 0x12, 3 ; 18 + spi_transfer_byte(FILTER_RD); // Next Operation is write to IOCON + 69c: 84 e4 ldi r24, 0x44 ; 68 + 69e: 0e 94 be 09 call 0x137c ; 0x137c + SET_BIT(PORTD,SPI_AD_CS); + 6a2: 93 9a sbi 0x12, 3 ; 18 + 6a4: 15 e8 ldi r17, 0x85 ; 133 + 6a6: 81 2f mov r24, r17 + 6a8: 8a 95 dec r24 + 6aa: f1 f7 brne .-4 ; 0x6a8 + +_delay_us(50); + + CLR_BIT(PORTD,SPI_AD_CS); // Set CS low + 6ac: 93 98 cbi 0x12, 3 ; 18 + spi_transfer_byte(0); // Next Operation is write to IOCON + 6ae: 80 e0 ldi r24, 0x00 ; 0 + 6b0: 0e 94 be 09 call 0x137c ; 0x137c + SET_BIT(PORTD,SPI_AD_CS); + 6b4: 93 9a sbi 0x12, 3 ; 18 + 6b6: 81 2f mov r24, r17 + 6b8: 8a 95 dec r24 + 6ba: f1 f7 brne .-4 ; 0x6b8 + +_delay_us(50); + + CLR_BIT(PORTD,SPI_AD_CS); // Set CS low + 6bc: 93 98 cbi 0x12, 3 ; 18 + spi_transfer_byte(IOCON_WR); // Next Operation is write to IOCON + 6be: 87 e0 ldi r24, 0x07 ; 7 + 6c0: 0e 94 be 09 call 0x137c ; 0x137c + SET_BIT(PORTD,SPI_AD_CS); + 6c4: 93 9a sbi 0x12, 3 ; 18 + 6c6: 81 2f mov r24, r17 + 6c8: 8a 95 dec r24 + 6ca: f1 f7 brne .-4 ; 0x6c8 + + _delay_us(50); + + CLR_BIT(PORTD,SPI_AD_CS); + 6cc: 93 98 cbi 0x12, 3 ; 18 + spi_transfer_byte(IOCON_INIT_HIGH); // Write to IOCON1 + 6ce: 83 e0 ldi r24, 0x03 ; 3 + 6d0: 0e 94 be 09 call 0x137c ; 0x137c + SET_BIT(PORTD,SPI_AD_CS); + 6d4: 93 9a sbi 0x12, 3 ; 18 + 6d6: 81 2f mov r24, r17 + 6d8: 8a 95 dec r24 + 6da: f1 f7 brne .-4 ; 0x6d8 +_delay_us(50); + CLR_BIT(PORTD,SPI_AD_CS); + 6dc: 93 98 cbi 0x12, 3 ; 18 + spi_transfer_byte(IOCON_INIT_LOWBYTE); // Write to IOCON2 + 6de: 80 e0 ldi r24, 0x00 ; 0 + 6e0: 0e 94 be 09 call 0x137c ; 0x137c + SET_BIT(PORTD,SPI_AD_CS); // Set CS high + 6e4: 93 9a sbi 0x12, 3 ; 18 + 6e6: 81 2f mov r24, r17 + 6e8: 8a 95 dec r24 + 6ea: f1 f7 brne .-4 ; 0x6e8 + +_delay_us(50); + + CLR_BIT(PORTD,SPI_AD_CS); // Set CS low + 6ec: 93 98 cbi 0x12, 3 ; 18 + spi_transfer_byte(FILTER_WR); // Next Operation is write to FILTER Start SPI + 6ee: 84 e0 ldi r24, 0x04 ; 4 + 6f0: 0e 94 be 09 call 0x137c ; 0x137c + SET_BIT(PORTD,SPI_AD_CS); + 6f4: 93 9a sbi 0x12, 3 ; 18 + 6f6: 81 2f mov r24, r17 + 6f8: 8a 95 dec r24 + 6fa: f1 f7 brne .-4 ; 0x6f8 + +_delay_us(50); + CLR_BIT(PORTD,SPI_AD_CS); + 6fc: 93 98 cbi 0x12, 3 ; 18 + + spi_transfer_byte(FILTER_INIT); // Write to FILTER + 6fe: 82 e5 ldi r24, 0x52 ; 82 + 700: 0e 94 be 09 call 0x137c ; 0x137c + SET_BIT(PORTD,SPI_AD_CS); // Set CS high + 704: 93 9a sbi 0x12, 3 ; 18 + 706: 81 2f mov r24, r17 + 708: 8a 95 dec r24 + 70a: f1 f7 brne .-4 ; 0x708 +_delay_us(50); + CLR_BIT(PORTD,SPI_AD_CS); // Set CS low + 70c: 93 98 cbi 0x12, 3 ; 18 + spi_transfer_byte(AD1CON_WR); // Next Operation is write to AD1CON Start SPI + 70e: 83 e0 ldi r24, 0x03 ; 3 + 710: 0e 94 be 09 call 0x137c ; 0x137c + SET_BIT(PORTD,SPI_AD_CS); + 714: 93 9a sbi 0x12, 3 ; 18 + 716: 81 2f mov r24, r17 + 718: 8a 95 dec r24 + 71a: f1 f7 brne .-4 ; 0x718 + +_delay_us(50); + + CLR_BIT(PORTD,SPI_AD_CS); + 71c: 93 98 cbi 0x12, 3 ; 18 + spi_transfer_byte(AD1CON_INIT); // Write to AD1CON + 71e: 81 e3 ldi r24, 0x31 ; 49 + 720: 0e 94 be 09 call 0x137c ; 0x137c + SET_BIT(PORTD,SPI_AD_CS); // Set CS high + 724: 93 9a sbi 0x12, 3 ; 18 + 726: 81 2f mov r24, r17 + 728: 8a 95 dec r24 + 72a: f1 f7 brne .-4 ; 0x728 + +_delay_us(50); + + CLR_BIT(PORTD,SPI_AD_CS); // Set CS low + 72c: 93 98 cbi 0x12, 3 ; 18 + spi_transfer_byte(AD0CON_WR); // Next Operation is write to AD0CON Start SPI + 72e: 82 e0 ldi r24, 0x02 ; 2 + 730: 0e 94 be 09 call 0x137c ; 0x137c + SET_BIT(PORTD,SPI_AD_CS); + 734: 93 9a sbi 0x12, 3 ; 18 + 736: 81 2f mov r24, r17 + 738: 8a 95 dec r24 + 73a: f1 f7 brne .-4 ; 0x738 + +_delay_us(50); + + CLR_BIT(PORTD,SPI_AD_CS); + 73c: 93 98 cbi 0x12, 3 ; 18 + spi_transfer_byte(AD0CON_INIT); // Write to AD0CON + 73e: 8e e8 ldi r24, 0x8E ; 142 + 740: 0e 94 be 09 call 0x137c ; 0x137c + SET_BIT(PORTD,SPI_AD_CS); // Set CS high + 744: 93 9a sbi 0x12, 3 ; 18 + 746: 81 2f mov r24, r17 + 748: 8a 95 dec r24 + 74a: f1 f7 brne .-4 ; 0x748 + +_delay_us(50); + + CLR_BIT(PORTD,SPI_AD_CS); // Set CS low + 74c: 93 98 cbi 0x12, 3 ; 18 + spi_transfer_byte(MODE_WR); // Next Operation is write to MODE Start SPI + 74e: 81 e0 ldi r24, 0x01 ; 1 + 750: 0e 94 be 09 call 0x137c ; 0x137c + SET_BIT(PORTD,SPI_AD_CS); + 754: 93 9a sbi 0x12, 3 ; 18 + 756: 81 2f mov r24, r17 + 758: 8a 95 dec r24 + 75a: f1 f7 brne .-4 ; 0x758 + +_delay_us(50); + + CLR_BIT(PORTD,SPI_AD_CS); + 75c: 93 98 cbi 0x12, 3 ; 18 + spi_transfer_byte(MODE_CONT); // Write to MODE + 75e: 83 e0 ldi r24, 0x03 ; 3 + 760: 0e 94 be 09 call 0x137c ; 0x137c + SET_BIT(PORTD,SPI_AD_CS); // Set CS high + 764: 93 9a sbi 0x12, 3 ; 18 + 766: 81 2f mov r24, r17 + 768: 8a 95 dec r24 + 76a: f1 f7 brne .-4 ; 0x768 + +_delay_us(50); + + CLR_BIT(PORTD,SPI_AD_CS); // Set CS low + 76c: 93 98 cbi 0x12, 3 ; 18 + spi_transfer_byte(FILTER_RD); // Next Operation is write to IOCON + 76e: 84 e4 ldi r24, 0x44 ; 68 + 770: 0e 94 be 09 call 0x137c ; 0x137c + SET_BIT(PORTD,SPI_AD_CS); + 774: 93 9a sbi 0x12, 3 ; 18 + 776: 81 2f mov r24, r17 + 778: 8a 95 dec r24 + 77a: f1 f7 brne .-4 ; 0x778 + +_delay_us(50); + + CLR_BIT(PORTD,SPI_AD_CS); // Set CS low + 77c: 93 98 cbi 0x12, 3 ; 18 + spi_transfer_byte(0); // Next Operation is write to IOCON + 77e: 80 e0 ldi r24, 0x00 ; 0 + 780: 0e 94 be 09 call 0x137c ; 0x137c + SET_BIT(PORTD,SPI_AD_CS); + 784: 93 9a sbi 0x12, 3 ; 18 + 786: 1a 95 dec r17 + 788: f1 f7 brne .-4 ; 0x786 + +_delay_us(50); + + +} + 78a: 1f 91 pop r17 + 78c: 08 95 ret + +0000078e : + +volatile U08 app_reset_source; +//----------------------------------------------------------------------------- + +void app_init(void) { + app_reset_source = MCUSR; // Save last reset source + 78e: 84 b7 in r24, 0x34 ; 52 + 790: 80 93 e3 05 sts 0x05E3, r24 + MCUSR = 0x00; // Clear reset source for next reset cycle + 794: 14 be out 0x34, r1 ; 52 + WDTCSR = WDTOE | (1 << WDE); // Enable watchdog reset (~16ms) + #endif + + // define PORTS + // USART + DDRD &= ~(1< output + 7a6: 8a b3 in r24, 0x1a ; 26 + 7a8: 8f 63 ori r24, 0x3F ; 63 + 7aa: 8a bb out 0x1a, r24 ; 26 + DDRC |= 0x7F; // SB-pins -> output + 7ac: 84 b3 in r24, 0x14 ; 20 + 7ae: 8f 67 ori r24, 0x7F ; 127 + 7b0: 84 bb out 0x14, r24 ; 20 + + // SPI + // set all CS's: output + DDRB |= (1 << SPI_E_CS); + 7b2: bc 9a sbi 0x17, 4 ; 23 + DDRD |= (1 << SPI_AD_CS) |(1 << SPI_M_CS) |(1 << SPI_A_CS); + 7b4: 81 b3 in r24, 0x11 ; 17 + 7b6: 88 63 ori r24, 0x38 ; 56 + 7b8: 81 bb out 0x11, r24 ; 17 + + // set all Chips selects HIGH + PORTB |= (1 << SPI_E_CS); + 7ba: c4 9a sbi 0x18, 4 ; 24 + PORTD |= (1 << SPI_AD_CS) |(1 << SPI_M_CS) |(1 << SPI_A_CS); + 7bc: 82 b3 in r24, 0x12 ; 18 + 7be: 88 63 ori r24, 0x38 ; 56 + 7c0: 82 bb out 0x12, r24 ; 18 + + // set MOSI and SCK: output & // set MISO: input + SPI_DDR |= (1 << SPI_MOSI); + 7c2: bd 9a sbi 0x17, 5 ; 23 + SPI_DDR |= (1 << SPI_SCLK); + 7c4: bf 9a sbi 0x17, 7 ; 23 + SPI_DDR &= ~(1 << SPI_MISO); + 7c6: be 98 cbi 0x17, 6 ; 23 + + // set MOSI, SCK: HIGH. MISO leave alone. + SPI_PRT |= (1 << SPI_MOSI); + 7c8: c5 9a sbi 0x18, 5 ; 24 + SPI_PRT |= (1 << SPI_SCLK); + 7ca: c7 9a sbi 0x18, 7 ; 24 + //SPI_PRT |= (1 << SPI_MISO); + + // ADC + DDRD &= ~(1<: + +//----------------------------------------------------------------------------- + +void app_set_watchdog_prescaler(tWDT_PRESCALE wdt_prescale) // Set watchdog prescale +{ + U08 sreg_backup = SREG; // Copy status register to variable + 7d4: 2f b7 in r18, 0x3f ; 63 + U08 wdtcsr_value = WDE + wdt_prescale; // Set new prescale value to variable + 7d6: 8d 5f subi r24, 0xFD ; 253 + + cli(); // Disable interrups + 7d8: f8 94 cli + wdt_reset(); // Reset watchdog + 7da: a8 95 wdr + + WDTCR |= (1 << WDTOE) | (1 << WDE); // Unlock register access, 4 cycles to store new value + 7dc: 91 b5 in r25, 0x21 ; 33 + 7de: 98 61 ori r25, 0x18 ; 24 + 7e0: 91 bd out 0x21, r25 ; 33 + WDTCR = wdtcsr_value; // Set new watchdog prescaler + 7e2: 81 bd out 0x21, r24 ; 33 + SREG = sreg_backup; // Restore status register + 7e4: 2f bf out 0x3f, r18 ; 63 +} + 7e6: 08 95 ret + +000007e8 : +void set_adc_enable_register() { + // TODO + usart_write_str((pU08)"setting of ATmega internal ADC enable registers is not supported. yet.\n"); +} + +U08 increase_adc (U08 channel){ + 7e8: 0f 93 push r16 + 7ea: 1f 93 push r17 + 7ec: cf 93 push r28 + 7ee: df 93 push r29 + 7f0: 48 2f mov r20, r24 + 7f2: c0 e0 ldi r28, 0x00 ; 0 + 7f4: d0 e0 ldi r29, 0x00 ; 0 +U08 effective_channel; + for ( U08 increase = 1 ; increase <= V_CHANNELS + I_CHANNELS + H_CHANNELS; increase++) + { + effective_channel = (channel + increase) % (V_CHANNELS + I_CHANNELS + H_CHANNELS); + 7f6: 08 2f mov r16, r24 + 7f8: 10 e0 ldi r17, 0x00 ; 0 + 7fa: 0f 5f subi r16, 0xFF ; 255 + 7fc: 1f 4f sbci r17, 0xFF ; 255 + 7fe: c8 01 movw r24, r16 + 800: 8c 0f add r24, r28 + 802: 9d 1f adc r25, r29 + 804: 64 e5 ldi r22, 0x54 ; 84 + 806: 70 e0 ldi r23, 0x00 ; 0 + 808: 0e 94 fa 19 call 0x33f4 ; 0x33f4 <__divmodhi4> + 80c: 38 2f mov r19, r24 + if (adc_enables[effective_channel/8] & (1< + 826: 95 95 asr r25 + 828: 87 95 ror r24 + 82a: 2a 95 dec r18 + 82c: e2 f7 brpl .-8 ; 0x826 + 82e: 80 fd sbrc r24, 0 + 830: 05 c0 rjmp .+10 ; 0x83c + 832: 21 96 adiw r28, 0x01 ; 1 + usart_write_str((pU08)"setting of ATmega internal ADC enable registers is not supported. yet.\n"); +} + +U08 increase_adc (U08 channel){ +U08 effective_channel; + for ( U08 increase = 1 ; increase <= V_CHANNELS + I_CHANNELS + H_CHANNELS; increase++) + 834: c4 35 cpi r28, 0x54 ; 84 + 836: d1 05 cpc r29, r1 + 838: 11 f7 brne .-60 ; 0x7fe + 83a: 34 2f mov r19, r20 + effective_channel = (channel + increase) % (V_CHANNELS + I_CHANNELS + H_CHANNELS); + if (adc_enables[effective_channel/8] & (1<: + +U08 increase_ad7719 (U08 channel){ + 848: 58 2f mov r21, r24 + 84a: 48 2f mov r20, r24 + 84c: 4f 5f subi r20, 0xFF ; 255 +U08 effective_channel; + for ( U08 increase = 1 ; increase <= TEMP_CHANNELS; increase++) + 84e: 68 2f mov r22, r24 + 850: 6f 5b subi r22, 0xBF ; 191 + { + effective_channel = (channel + increase) % (TEMP_CHANNELS); + 852: 34 2f mov r19, r20 + 854: 3f 73 andi r19, 0x3F ; 63 + if (ad7719_enables[effective_channel/8] & (1< + 86e: 95 95 asr r25 + 870: 87 95 ror r24 + 872: 2a 95 dec r18 + 874: e2 f7 brpl .-8 ; 0x86e <__stack+0xf> + 876: 80 fd sbrc r24, 0 + 878: 04 c0 rjmp .+8 ; 0x882 <__stack+0x23> + 87a: 4f 5f subi r20, 0xFF ; 255 + return channel; +} // end if increase_adc; + +U08 increase_ad7719 (U08 channel){ +U08 effective_channel; + for ( U08 increase = 1 ; increase <= TEMP_CHANNELS; increase++) + 87c: 46 17 cp r20, r22 + 87e: 49 f7 brne .-46 ; 0x852 + 880: 35 2f mov r19, r21 + effective_channel = (channel + increase) % (TEMP_CHANNELS); + if (ad7719_enables[effective_channel/8] & (1<: + +void check_if_measured_all() { + adc_measured_all = true; + 886: 81 e0 ldi r24, 0x01 ; 1 + 888: 80 93 c1 05 sts 0x05C1, r24 + 88c: 20 e0 ldi r18, 0x00 ; 0 + 88e: 30 e0 ldi r19, 0x00 ; 0 + for ( U08 i=0; i + adc_measured_all = false; + 8a4: 10 92 c1 05 sts 0x05C1, r1 + 8a8: 05 c0 rjmp .+10 ; 0x8b4 + break; + 8aa: 2f 5f subi r18, 0xFF ; 255 + 8ac: 3f 4f sbci r19, 0xFF ; 255 + return channel; +} // end if increase_adc; + +void check_if_measured_all() { + adc_measured_all = true; + for ( U08 i=0; i + if ((adc_enables[i] ^ adc_channels_ready[i]) != 0x00) { + adc_measured_all = false; + break; + } + } + ad7719_measured_all = true; + 8b4: 81 e0 ldi r24, 0x01 ; 1 + 8b6: 80 93 bd 05 sts 0x05BD, r24 + 8ba: 20 e0 ldi r18, 0x00 ; 0 + 8bc: 30 e0 ldi r19, 0x00 ; 0 + for ( U08 i=0; i + ad7719_measured_all = false; + 8d2: 10 92 bd 05 sts 0x05BD, r1 + 8d6: 08 95 ret + break; + 8d8: 2f 5f subi r18, 0xFF ; 255 + 8da: 3f 4f sbci r19, 0xFF ; 255 + adc_measured_all = false; + break; + } + } + ad7719_measured_all = true; + for ( U08 i=0; i + 8e2: 08 95 ret + +000008e4 : + } +} + +void set_adc_enable_register() { + // TODO + usart_write_str((pU08)"setting of ATmega internal ADC enable registers is not supported. yet.\n"); + 8e4: 86 ee ldi r24, 0xE6 ; 230 + 8e6: 90 e0 ldi r25, 0x00 ; 0 + 8e8: 0e 94 d6 0a call 0x15ac ; 0x15ac +} + 8ec: 08 95 ret + +000008ee : + SREG = sreg_backup; // Restore status register +} + +void set_ad7719_enable_register() { + + usart_write_str((pU08)"\n set enable bits of AD7719 Port "); + 8ee: 8e e2 ldi r24, 0x2E ; 46 + 8f0: 91 e0 ldi r25, 0x01 ; 1 + 8f2: 0e 94 d6 0a call 0x15ac ; 0x15ac + if ((usart_received_chars>=5) && + 8f6: 80 91 09 06 lds r24, 0x0609 + 8fa: 85 30 cpi r24, 0x05 ; 5 + 8fc: 10 f1 brcs .+68 ; 0x942 + 8fe: 90 91 0c 06 lds r25, 0x060C + 902: 89 2f mov r24, r25 + 904: 81 54 subi r24, 0x41 ; 65 + 906: 88 30 cpi r24, 0x08 ; 8 + 908: e0 f4 brcc .+56 ; 0x942 + (usart_rx_buffer[2] >= 'A' && usart_rx_buffer[2] <= 'H')) + { + usart_write_char(usart_rx_buffer[2]); + 90a: 89 2f mov r24, r25 + 90c: 0e 94 c9 0a call 0x1592 ; 0x1592 + usart_write_str((pU08)" to "); + 910: 80 e5 ldi r24, 0x50 ; 80 + 912: 91 e0 ldi r25, 0x01 ; 1 + 914: 0e 94 d6 0a call 0x15ac ; 0x15ac + usart_write_U08_hex(usart_rx_buffer[4]); + 918: 80 91 0e 06 lds r24, 0x060E + 91c: 0e 94 7d 0b call 0x16fa ; 0x16fa + usart_write_char('\n'); + 920: 8a e0 ldi r24, 0x0A ; 10 + 922: 0e 94 c9 0a call 0x1592 ; 0x1592 + ad7719_enables[usart_rx_buffer[2]-'A']=usart_rx_buffer[4]; + 926: e0 91 0c 06 lds r30, 0x060C + 92a: f0 e0 ldi r31, 0x00 ; 0 + 92c: e1 54 subi r30, 0x41 ; 65 + 92e: f0 40 sbci r31, 0x00 ; 0 + 930: df 01 movw r26, r30 + 932: ad 59 subi r26, 0x9D ; 157 + 934: b8 4f sbci r27, 0xF8 ; 248 + 936: 80 91 0e 06 lds r24, 0x060E + 93a: 8c 93 st X, r24 + ad7719_channels_ready[usart_rx_buffer[2]-'A']=0x00; + 93c: ec 53 subi r30, 0x3C ; 60 + 93e: f8 4f sbci r31, 0xF8 ; 248 + 940: 2b c0 rjmp .+86 ; 0x998 + } + else if ((usart_received_chars=3) && + 942: 83 e0 ldi r24, 0x03 ; 3 + 944: 80 93 09 06 sts 0x0609, r24 + 948: 90 91 0b 06 lds r25, 0x060B + 94c: 89 2f mov r24, r25 + 94e: 81 54 subi r24, 0x41 ; 65 + 950: 88 30 cpi r24, 0x08 ; 8 + 952: 20 f5 brcc .+72 ; 0x99c + (usart_rx_buffer[1] >= 'A' && usart_rx_buffer[1] <= 'H')) + { + usart_write_char(usart_rx_buffer[1]); + 954: 89 2f mov r24, r25 + 956: 0e 94 c9 0a call 0x1592 ; 0x1592 + if (usart_rx_buffer[2]!='0') { + 95a: 80 91 0c 06 lds r24, 0x060C + 95e: 80 33 cpi r24, 0x30 ; 48 + 960: 61 f0 breq .+24 ; 0x97a + usart_write_str((pU08)" to 0xFF\n"); + 962: 85 e5 ldi r24, 0x55 ; 85 + 964: 91 e0 ldi r25, 0x01 ; 1 + 966: 0e 94 d6 0a call 0x15ac ; 0x15ac + ad7719_enables[usart_rx_buffer[1]-'A']=0xFF; + 96a: e0 91 0b 06 lds r30, 0x060B + 96e: f0 e0 ldi r31, 0x00 ; 0 + 970: ee 5d subi r30, 0xDE ; 222 + 972: f8 4f sbci r31, 0xF8 ; 248 + 974: 8f ef ldi r24, 0xFF ; 255 + 976: 80 83 st Z, r24 + 978: 0a c0 rjmp .+20 ; 0x98e + } else + { + usart_write_str((pU08)" to 0x00\n"); + 97a: 8f e5 ldi r24, 0x5F ; 95 + 97c: 91 e0 ldi r25, 0x01 ; 1 + 97e: 0e 94 d6 0a call 0x15ac ; 0x15ac + ad7719_enables[usart_rx_buffer[1]-'A']=0x00; + 982: e0 91 0b 06 lds r30, 0x060B + 986: f0 e0 ldi r31, 0x00 ; 0 + 988: ee 5d subi r30, 0xDE ; 222 + 98a: f8 4f sbci r31, 0xF8 ; 248 + 98c: 10 82 st Z, r1 + } + ad7719_channels_ready[usart_rx_buffer[1]-'A']=0x00; + 98e: e0 91 0b 06 lds r30, 0x060B + 992: f0 e0 ldi r31, 0x00 ; 0 + 994: ed 57 subi r30, 0x7D ; 125 + 996: f8 4f sbci r31, 0xF8 ; 248 + 998: 10 82 st Z, r1 + 99a: 08 95 ret + } + else + { + usart_write_str((pU08)"\n something wrong\n"); + 99c: 89 e6 ldi r24, 0x69 ; 105 + 99e: 91 e0 ldi r25, 0x01 ; 1 + 9a0: 0e 94 d6 0a call 0x15ac ; 0x15ac + usart_write_str((pU08)"usart_rx_buffer_index: "); + 9a4: 8c e7 ldi r24, 0x7C ; 124 + 9a6: 91 e0 ldi r25, 0x01 ; 1 + 9a8: 0e 94 d6 0a call 0x15ac ; 0x15ac + usart_write_U08(usart_received_chars, 3); + 9ac: 80 91 09 06 lds r24, 0x0609 + 9b0: 63 e0 ldi r22, 0x03 ; 3 + 9b2: 0e 94 87 0b call 0x170e ; 0x170e + usart_write_str((pU08)"\n usart_rx_buffer[2]: "); + 9b6: 84 e9 ldi r24, 0x94 ; 148 + 9b8: 91 e0 ldi r25, 0x01 ; 1 + 9ba: 0e 94 d6 0a call 0x15ac ; 0x15ac + usart_write_char(usart_rx_buffer[2]); + 9be: 80 91 0c 06 lds r24, 0x060C + 9c2: 0e 94 c9 0a call 0x1592 ; 0x1592 + usart_write_str((pU08)"\n usart_rx_buffer[4]: "); + 9c6: 8b ea ldi r24, 0xAB ; 171 + 9c8: 91 e0 ldi r25, 0x01 ; 1 + 9ca: 0e 94 d6 0a call 0x15ac ; 0x15ac + usart_write_U08_hex(usart_rx_buffer[4]); + 9ce: 80 91 0e 06 lds r24, 0x060E + 9d2: 0e 94 7d 0b call 0x16fa ; 0x16fa + usart_write_char('\n'); + 9d6: 8a e0 ldi r24, 0x0A ; 10 + 9d8: 0e 94 c9 0a call 0x1592 ; 0x1592 + 9dc: 08 95 ret + +000009de : +#include "typedefs.h" + +void atmega_adc_init(void) +{ +//ADC einschalten + ADCSRA |= (1< free running mode + 9e8: 80 b7 in r24, 0x30 ; 48 + 9ea: 8f 71 andi r24, 0x1F ; 31 + 9ec: 80 bf out 0x30, r24 ; 48 + ADCSRA |= (1< use external reference voltage. + 9f2: 3f 98 cbi 0x07, 7 ; 7 + ADMUX |= 1< left adjust ac result in ADCH register --> 8bit resolution only. + 9f4: 3d 9a sbi 0x07, 5 ; 7 + ADMUX |= (0x1F & 0x06); //MUX = 0x06 --> Pin ADC6 = PA6 is used as ADC input pin. + 9f6: 87 b1 in r24, 0x07 ; 7 + 9f8: 86 60 ori r24, 0x06 ; 6 + 9fa: 87 b9 out 0x07, r24 ; 7 + + ADCSRA |= (1<: + return resistance; // in kilo-ohms +} + +U32 getadc(void) +{ +return read_adc(); + a00: 0e 94 f4 02 call 0x5e8 ; 0x5e8 +} + a04: 08 95 ret + +00000a06 : +{ + + U32 adcword=0; + float resistance; + const float R_REF=6.25; // kilo-ohms + adcword = read_adc(); + a06: 0e 94 f4 02 call 0x5e8 ; 0x5e8 + a0a: 0e 94 6c 17 call 0x2ed8 ; 0x2ed8 <__floatunsisf> + a0e: 2f ef ldi r18, 0xFF ; 255 + a10: 3f ef ldi r19, 0xFF ; 255 + a12: 4f e7 ldi r20, 0x7F ; 127 + a14: 5b e4 ldi r21, 0x4B ; 75 + a16: 0e 94 ae 15 call 0x2b5c ; 0x2b5c <__divsf3> + a1a: 20 e0 ldi r18, 0x00 ; 0 + a1c: 30 e0 ldi r19, 0x00 ; 0 + a1e: 40 e0 ldi r20, 0x00 ; 0 + a20: 5f e3 ldi r21, 0x3F ; 63 + a22: 0e 94 b4 14 call 0x2968 ; 0x2968 <__mulsf3> + a26: 20 e0 ldi r18, 0x00 ; 0 + a28: 30 e0 ldi r19, 0x00 ; 0 + a2a: 48 ec ldi r20, 0xC8 ; 200 + a2c: 50 e4 ldi r21, 0x40 ; 64 + a2e: 0e 94 b4 14 call 0x2968 ; 0x2968 <__mulsf3> + U32 fullscale = 16777215L; //2^24 -1 + + resistance = ((float)adcword / (float)fullscale) /2.0 * R_REF; // divide through 2.0 because of PGA in ADC. + + return resistance; // in kilo-ohms +} + a32: 08 95 ret + +00000a34 : + float temp=-3.14; // should be initialized in a proper way, but I dont know how :-) + const U32 min = 0x404054; + const U32 max = 0x8CAF50; + const U32 s = 0x4C6F0; //(max-min)/16 = s(lice) + + adcword = read_adc(); + a34: 0e 94 f4 02 call 0x5e8 ; 0x5e8 + + if (adcword >= (min + 8*s)) + a38: 64 3d cpi r22, 0xD4 ; 212 + a3a: 27 e7 ldi r18, 0x77 ; 119 + a3c: 72 07 cpc r23, r18 + a3e: 26 e6 ldi r18, 0x66 ; 102 + a40: 82 07 cpc r24, r18 + a42: 20 e0 ldi r18, 0x00 ; 0 + a44: 92 07 cpc r25, r18 + a46: 08 f4 brcc .+2 ; 0xa4a + a48: 49 c0 rjmp .+146 ; 0xadc + { + if (adcword >= (min + 12*s)) + a4a: 64 39 cpi r22, 0x94 ; 148 + a4c: 23 e9 ldi r18, 0x93 ; 147 + a4e: 72 07 cpc r23, r18 + a50: 29 e7 ldi r18, 0x79 ; 121 + a52: 82 07 cpc r24, r18 + a54: 20 e0 ldi r18, 0x00 ; 0 + a56: 92 07 cpc r25, r18 + a58: 28 f1 brcs .+74 ; 0xaa4 + { + if (adcword >= (min + 14*s)) + a5a: 64 37 cpi r22, 0x74 ; 116 + a5c: 21 e2 ldi r18, 0x21 ; 33 + a5e: 72 07 cpc r23, r18 + a60: 23 e8 ldi r18, 0x83 ; 131 + a62: 82 07 cpc r24, r18 + a64: 20 e0 ldi r18, 0x00 ; 0 + a66: 92 07 cpc r25, r18 + a68: 98 f0 brcs .+38 ; 0xa90 + { + if (adcword >= (min + 15*s)) + a6a: 64 36 cpi r22, 0x64 ; 100 + a6c: 28 ee ldi r18, 0xE8 ; 232 + a6e: 72 07 cpc r23, r18 + a70: 27 e8 ldi r18, 0x87 ; 135 + a72: 82 07 cpc r24, r18 + a74: 20 e0 ldi r18, 0x00 ; 0 + a76: 92 07 cpc r25, r18 + a78: 08 f4 brcc .+2 ; 0xa7c + a7a: 11 c1 rjmp .+546 ; 0xc9e + { + if (adcword < max) + a7c: 60 35 cpi r22, 0x50 ; 80 + a7e: 2f ea ldi r18, 0xAF ; 175 + a80: 72 07 cpc r23, r18 + a82: 2c e8 ldi r18, 0x8C ; 140 + a84: 82 07 cpc r24, r18 + a86: 20 e0 ldi r18, 0x00 ; 0 + a88: 92 07 cpc r25, r18 + a8a: 08 f4 brcc .+2 ; 0xa8e + a8c: 15 c1 rjmp .+554 ; 0xcb8 + a8e: 21 c1 rjmp .+578 ; 0xcd2 + temprange = 15; + } + } + else + { + if (adcword >= (min + 13*s)) + a90: 64 38 cpi r22, 0x84 ; 132 + a92: 2a e5 ldi r18, 0x5A ; 90 + a94: 72 07 cpc r23, r18 + a96: 2e e7 ldi r18, 0x7E ; 126 + a98: 82 07 cpc r24, r18 + a9a: 20 e0 ldi r18, 0x00 ; 0 + a9c: 92 07 cpc r25, r18 + a9e: 08 f0 brcs .+2 ; 0xaa2 + aa0: f1 c0 rjmp .+482 ; 0xc84 + aa2: e3 c0 rjmp .+454 ; 0xc6a + } + } + } + else + { + if (adcword >= (min + 10*s)) + aa4: 64 3b cpi r22, 0xB4 ; 180 + aa6: 25 e0 ldi r18, 0x05 ; 5 + aa8: 72 07 cpc r23, r18 + aaa: 20 e7 ldi r18, 0x70 ; 112 + aac: 82 07 cpc r24, r18 + aae: 20 e0 ldi r18, 0x00 ; 0 + ab0: 92 07 cpc r25, r18 + ab2: 50 f0 brcs .+20 ; 0xac8 + { + if (adcword >= (min + 11*s)) + ab4: 64 3a cpi r22, 0xA4 ; 164 + ab6: 2c ec ldi r18, 0xCC ; 204 + ab8: 72 07 cpc r23, r18 + aba: 24 e7 ldi r18, 0x74 ; 116 + abc: 82 07 cpc r24, r18 + abe: 20 e0 ldi r18, 0x00 ; 0 + ac0: 92 07 cpc r25, r18 + ac2: 08 f0 brcs .+2 ; 0xac6 + ac4: c5 c0 rjmp .+394 ; 0xc50 + ac6: 52 c0 rjmp .+164 ; 0xb6c + temprange = 11; + } + } + else + { + if (adcword >= (min + 9*s)) + ac8: 64 3c cpi r22, 0xC4 ; 196 + aca: 2e e3 ldi r18, 0x3E ; 62 + acc: 72 07 cpc r23, r18 + ace: 2b e6 ldi r18, 0x6B ; 107 + ad0: 82 07 cpc r24, r18 + ad2: 20 e0 ldi r18, 0x00 ; 0 + ad4: 92 07 cpc r25, r18 + ad6: 08 f0 brcs .+2 ; 0xada + ad8: ae c0 rjmp .+348 ; 0xc36 + ada: a0 c0 rjmp .+320 ; 0xc1c + } + } + } + else + { + if (adcword >= (min + 4*s)) + adc: 64 31 cpi r22, 0x14 ; 20 + ade: 2c e5 ldi r18, 0x5C ; 92 + ae0: 72 07 cpc r23, r18 + ae2: 23 e5 ldi r18, 0x53 ; 83 + ae4: 82 07 cpc r24, r18 + ae6: 20 e0 ldi r18, 0x00 ; 0 + ae8: 92 07 cpc r25, r18 + aea: e0 f0 brcs .+56 ; 0xb24 + { + if (adcword >= (min + 6*s)) + aec: 64 3f cpi r22, 0xF4 ; 244 + aee: 29 ee ldi r18, 0xE9 ; 233 + af0: 72 07 cpc r23, r18 + af2: 2c e5 ldi r18, 0x5C ; 92 + af4: 82 07 cpc r24, r18 + af6: 20 e0 ldi r18, 0x00 ; 0 + af8: 92 07 cpc r25, r18 + afa: 50 f0 brcs .+20 ; 0xb10 + { + if (adcword >= (min + 7*s)) + afc: 64 3e cpi r22, 0xE4 ; 228 + afe: 20 eb ldi r18, 0xB0 ; 176 + b00: 72 07 cpc r23, r18 + b02: 21 e6 ldi r18, 0x61 ; 97 + b04: 82 07 cpc r24, r18 + b06: 20 e0 ldi r18, 0x00 ; 0 + b08: 92 07 cpc r25, r18 + b0a: 08 f0 brcs .+2 ; 0xb0e + b0c: 7a c0 rjmp .+244 ; 0xc02 + b0e: 6c c0 rjmp .+216 ; 0xbe8 + temprange = 7; + } + } + else + { + if (adcword >= (min + 5*s)) + b10: 64 30 cpi r22, 0x04 ; 4 + b12: 23 e2 ldi r18, 0x23 ; 35 + b14: 72 07 cpc r23, r18 + b16: 28 e5 ldi r18, 0x58 ; 88 + b18: 82 07 cpc r24, r18 + b1a: 20 e0 ldi r18, 0x00 ; 0 + b1c: 92 07 cpc r25, r18 + b1e: 08 f0 brcs .+2 ; 0xb22 + b20: 56 c0 rjmp .+172 ; 0xbce + b22: 48 c0 rjmp .+144 ; 0xbb4 + } + } + } + else + { + if (adcword >= (min + 2*s)) + b24: 64 33 cpi r22, 0x34 ; 52 + b26: 2e ec ldi r18, 0xCE ; 206 + b28: 72 07 cpc r23, r18 + b2a: 29 e4 ldi r18, 0x49 ; 73 + b2c: 82 07 cpc r24, r18 + b2e: 20 e0 ldi r18, 0x00 ; 0 + b30: 92 07 cpc r25, r18 + b32: 48 f0 brcs .+18 ; 0xb46 + { + if (adcword >= (min + 3*s)) + b34: 64 32 cpi r22, 0x24 ; 36 + b36: 25 e9 ldi r18, 0x95 ; 149 + b38: 72 07 cpc r23, r18 + b3a: 2e e4 ldi r18, 0x4E ; 78 + b3c: 82 07 cpc r24, r18 + b3e: 20 e0 ldi r18, 0x00 ; 0 + b40: 92 07 cpc r25, r18 + b42: 58 f5 brcc .+86 ; 0xb9a + b44: e6 c0 rjmp .+460 ; 0xd12 + temprange = 3; + } + } + else + { + if (adcword >= (min + s)) + b46: 64 34 cpi r22, 0x44 ; 68 + b48: 27 e0 ldi r18, 0x07 ; 7 + b4a: 72 07 cpc r23, r18 + b4c: 25 e4 ldi r18, 0x45 ; 69 + b4e: 82 07 cpc r24, r18 + b50: 20 e0 ldi r18, 0x00 ; 0 + b52: 92 07 cpc r25, r18 + b54: 08 f0 brcs .+2 ; 0xb58 + b56: d0 c0 rjmp .+416 ; 0xcf8 + { + temprange = 2; + } + else + { + if (adcword > min) + b58: 65 35 cpi r22, 0x55 ; 85 + b5a: 20 e4 ldi r18, 0x40 ; 64 + b5c: 72 07 cpc r23, r18 + b5e: 20 e4 ldi r18, 0x40 ; 64 + b60: 82 07 cpc r24, r18 + b62: 20 e0 ldi r18, 0x00 ; 0 + b64: 92 07 cpc r25, r18 + b66: 08 f0 brcs .+2 ; 0xb6a + b68: ba c0 rjmp .+372 ; 0xcde + b6a: b3 c0 rjmp .+358 ; 0xcd2 + temp = ((float)adcword / 19894.657024 - 265.0037); //19894.657024 - 265.0037 + } + break; + + case 11:{ // Temp. Range [106.25°C , 121.875°C] + temp = ((float)adcword / 19800.039424 - 266.7778); //19800.039424 - 266.7778 + b6c: 0e 94 6c 17 call 0x2ed8 ; 0x2ed8 <__floatunsisf> + b70: 24 e1 ldi r18, 0x14 ; 20 + b72: 30 eb ldi r19, 0xB0 ; 176 + b74: 4a e9 ldi r20, 0x9A ; 154 + b76: 56 e4 ldi r21, 0x46 ; 70 + b78: 0e 94 ae 15 call 0x2b5c ; 0x2b5c <__divsf3> + b7c: 2f e8 ldi r18, 0x8F ; 143 + b7e: 33 e6 ldi r19, 0x63 ; 99 + b80: 45 e8 ldi r20, 0x85 ; 133 + b82: 53 e4 ldi r21, 0x43 ; 67 + b84: 0e 94 56 14 call 0x28ac ; 0x28ac <__subsf3> + b88: e6 2f mov r30, r22 + b8a: 69 2f mov r22, r25 + PORTC = (PORTC | 0x04); + } + }// end of switch case statement + return temp; + + } + b8c: 2e 2f mov r18, r30 + b8e: 37 2f mov r19, r23 + b90: 48 2f mov r20, r24 + b92: 56 2f mov r21, r22 + b94: b9 01 movw r22, r18 + b96: ca 01 movw r24, r20 + b98: 08 95 ret + temp = ((float)adcword / 20557.997603 - 255.0436); //20557.997603 - 255.0436 + } + break; + + case 4:{ // Temp. Range [-3.125°C , 12.5°C] + temp = ((float)adcword / 20462.362624 - 256.2209); //20462.362624 - 256.2209 + b9a: 0e 94 6c 17 call 0x2ed8 ; 0x2ed8 <__floatunsisf> + b9e: 2a eb ldi r18, 0xBA ; 186 + ba0: 3c ed ldi r19, 0xDC ; 220 + ba2: 4f e9 ldi r20, 0x9F ; 159 + ba4: 56 e4 ldi r21, 0x46 ; 70 + ba6: 0e 94 ae 15 call 0x2b5c ; 0x2b5c <__divsf3> + baa: 26 e4 ldi r18, 0x46 ; 70 + bac: 3c e1 ldi r19, 0x1C ; 28 + bae: 40 e8 ldi r20, 0x80 ; 128 + bb0: 53 e4 ldi r21, 0x43 ; 67 + bb2: e8 cf rjmp .-48 ; 0xb84 + } + break; + + case 5:{ // Temp. Range [12.5°C , 28.125°C] + temp = ((float)adcword / 20367.745024 - 257.4692); //20367.745024 - 257.4692 + bb4: 0e 94 6c 17 call 0x2ed8 ; 0x2ed8 <__floatunsisf> + bb8: 2d e7 ldi r18, 0x7D ; 125 + bba: 3f e1 ldi r19, 0x1F ; 31 + bbc: 4f e9 ldi r20, 0x9F ; 159 + bbe: 56 e4 ldi r21, 0x46 ; 70 + bc0: 0e 94 ae 15 call 0x2b5c ; 0x2b5c <__divsf3> + bc4: 2f e0 ldi r18, 0x0F ; 15 + bc6: 3c eb ldi r19, 0xBC ; 188 + bc8: 40 e8 ldi r20, 0x80 ; 128 + bca: 53 e4 ldi r21, 0x43 ; 67 + bcc: db cf rjmp .-74 ; 0xb84 + } + break; + + case 6:{ // Temp. Range [28.125°C , 43.75°C] + temp = ((float)adcword / 20273.127424 - 258.8021); //20273.127424 - 258.8021 + bce: 0e 94 6c 17 call 0x2ed8 ; 0x2ed8 <__floatunsisf> + bd2: 21 e4 ldi r18, 0x41 ; 65 + bd4: 32 e6 ldi r19, 0x62 ; 98 + bd6: 4e e9 ldi r20, 0x9E ; 158 + bd8: 56 e4 ldi r21, 0x46 ; 70 + bda: 0e 94 ae 15 call 0x2b5c ; 0x2b5c <__divsf3> + bde: 2b ea ldi r18, 0xAB ; 171 + be0: 36 e6 ldi r19, 0x66 ; 102 + be2: 41 e8 ldi r20, 0x81 ; 129 + be4: 53 e4 ldi r21, 0x43 ; 67 + be6: ce cf rjmp .-100 ; 0xb84 + } + break; + + case 7:{ // Temp. Range [43.75°C , 59.375°C] + temp = ((float)adcword / 20178.509824 - 260.2208); //20178.509824 - 260.2208 + be8: 0e 94 6c 17 call 0x2ed8 ; 0x2ed8 <__floatunsisf> + bec: 25 e0 ldi r18, 0x05 ; 5 + bee: 35 ea ldi r19, 0xA5 ; 165 + bf0: 4d e9 ldi r20, 0x9D ; 157 + bf2: 56 e4 ldi r21, 0x46 ; 70 + bf4: 0e 94 ae 15 call 0x2b5c ; 0x2b5c <__divsf3> + bf8: 23 e4 ldi r18, 0x43 ; 67 + bfa: 3c e1 ldi r19, 0x1C ; 28 + bfc: 42 e8 ldi r20, 0x82 ; 130 + bfe: 53 e4 ldi r21, 0x43 ; 67 + c00: c1 cf rjmp .-126 ; 0xb84 + } + break; + + case 8:{ // Temp. Range [59.375°C , 75°C] + temp = ((float)adcword / 20083.892224 - 261.7265); //20083.892224 - 261.7265 + c02: 0e 94 6c 17 call 0x2ed8 ; 0x2ed8 <__floatunsisf> + c06: 29 ec ldi r18, 0xC9 ; 201 + c08: 37 ee ldi r19, 0xE7 ; 231 + c0a: 4c e9 ldi r20, 0x9C ; 156 + c0c: 56 e4 ldi r21, 0x46 ; 70 + c0e: 0e 94 ae 15 call 0x2b5c ; 0x2b5c <__divsf3> + c12: 2e ef ldi r18, 0xFE ; 254 + c14: 3c ed ldi r19, 0xDC ; 220 + c16: 42 e8 ldi r20, 0x82 ; 130 + c18: 53 e4 ldi r21, 0x43 ; 67 + c1a: b4 cf rjmp .-152 ; 0xb84 + } + break; + + case 9:{ // Temp. Range [75°C , 90.625°C] + temp = ((float)adcword / 19989.274624 - 263.3203); //19989.274624 - 263.3203 + c1c: 0e 94 6c 17 call 0x2ed8 ; 0x2ed8 <__floatunsisf> + c20: 2d e8 ldi r18, 0x8D ; 141 + c22: 3a e2 ldi r19, 0x2A ; 42 + c24: 4c e9 ldi r20, 0x9C ; 156 + c26: 56 e4 ldi r21, 0x46 ; 70 + c28: 0e 94 ae 15 call 0x2b5c ; 0x2b5c <__divsf3> + c2c: 20 e0 ldi r18, 0x00 ; 0 + c2e: 39 ea ldi r19, 0xA9 ; 169 + c30: 43 e8 ldi r20, 0x83 ; 131 + c32: 53 e4 ldi r21, 0x43 ; 67 + c34: a7 cf rjmp .-178 ; 0xb84 + } + break; + + case 10:{ // Temp. Range [90.625°C , 106.25°C] + temp = ((float)adcword / 19894.657024 - 265.0037); //19894.657024 - 265.0037 + c36: 0e 94 6c 17 call 0x2ed8 ; 0x2ed8 <__floatunsisf> + c3a: 20 e5 ldi r18, 0x50 ; 80 + c3c: 3d e6 ldi r19, 0x6D ; 109 + c3e: 4b e9 ldi r20, 0x9B ; 155 + c40: 56 e4 ldi r21, 0x46 ; 70 + c42: 0e 94 ae 15 call 0x2b5c ; 0x2b5c <__divsf3> + c46: 29 e7 ldi r18, 0x79 ; 121 + c48: 30 e8 ldi r19, 0x80 ; 128 + c4a: 44 e8 ldi r20, 0x84 ; 132 + c4c: 53 e4 ldi r21, 0x43 ; 67 + c4e: 9a cf rjmp .-204 ; 0xb84 + temp = ((float)adcword / 19800.039424 - 266.7778); //19800.039424 - 266.7778 + } + break; + + case 12:{ // Temp. Range [121.875°C , 137.5°C] + temp = ((float)adcword / 19705.421824 - 268.6439); //19705.421824 - 268.6439 + c50: 0e 94 6c 17 call 0x2ed8 ; 0x2ed8 <__floatunsisf> + c54: 28 ed ldi r18, 0xD8 ; 216 + c56: 32 ef ldi r19, 0xF2 ; 242 + c58: 49 e9 ldi r20, 0x99 ; 153 + c5a: 56 e4 ldi r21, 0x46 ; 70 + c5c: 0e 94 ae 15 call 0x2b5c ; 0x2b5c <__divsf3> + c60: 2b e6 ldi r18, 0x6B ; 107 + c62: 32 e5 ldi r19, 0x52 ; 82 + c64: 46 e8 ldi r20, 0x86 ; 134 + c66: 53 e4 ldi r21, 0x43 ; 67 + c68: 8d cf rjmp .-230 ; 0xb84 + } + break; + + case 13:{ // Temp. Range [137.5°C , 153.125°C] + temp = ((float)adcword / 19610.804224 - 270.6035); //19610.804224 - 270.6035 + c6a: 0e 94 6c 17 call 0x2ed8 ; 0x2ed8 <__floatunsisf> + c6e: 2c e9 ldi r18, 0x9C ; 156 + c70: 35 e3 ldi r19, 0x35 ; 53 + c72: 49 e9 ldi r20, 0x99 ; 153 + c74: 56 e4 ldi r21, 0x46 ; 70 + c76: 0e 94 ae 15 call 0x2b5c ; 0x2b5c <__divsf3> + c7a: 2f e3 ldi r18, 0x3F ; 63 + c7c: 3d e4 ldi r19, 0x4D ; 77 + c7e: 47 e8 ldi r20, 0x87 ; 135 + c80: 53 e4 ldi r21, 0x43 ; 67 + c82: 80 cf rjmp .-256 ; 0xb84 + } + break; + + case 14:{ // Temp. Range [153.125°C , 168.75°C] + temp = ((float)adcword / 19516.186624 - 272.6578); //19516.186624 - 272.6578 + c84: 0e 94 6c 17 call 0x2ed8 ; 0x2ed8 <__floatunsisf> + c88: 20 e6 ldi r18, 0x60 ; 96 + c8a: 38 e7 ldi r19, 0x78 ; 120 + c8c: 48 e9 ldi r20, 0x98 ; 152 + c8e: 56 e4 ldi r21, 0x46 ; 70 + c90: 0e 94 ae 15 call 0x2b5c ; 0x2b5c <__divsf3> + c94: 23 e3 ldi r18, 0x33 ; 51 + c96: 34 e5 ldi r19, 0x54 ; 84 + c98: 48 e8 ldi r20, 0x88 ; 136 + c9a: 53 e4 ldi r21, 0x43 ; 67 + c9c: 73 cf rjmp .-282 ; 0xb84 + } + break; + + case 15:{ // Temp. Range [168.75°C , 184.375°C] + temp = ((float)adcword / 19421.569024 - 274.8082); //19421.569024 - 274.8082 + c9e: 0e 94 6c 17 call 0x2ed8 ; 0x2ed8 <__floatunsisf> + ca2: 23 e2 ldi r18, 0x23 ; 35 + ca4: 3b eb ldi r19, 0xBB ; 187 + ca6: 47 e9 ldi r20, 0x97 ; 151 + ca8: 56 e4 ldi r21, 0x46 ; 70 + caa: 0e 94 ae 15 call 0x2b5c ; 0x2b5c <__divsf3> + cae: 23 e7 ldi r18, 0x73 ; 115 + cb0: 37 e6 ldi r19, 0x67 ; 103 + cb2: 49 e8 ldi r20, 0x89 ; 137 + cb4: 53 e4 ldi r21, 0x43 ; 67 + cb6: 66 cf rjmp .-308 ; 0xb84 + } + break; + + case 16:{ // Temp. Range [184.375°C , 200°C] + temp = ((float)adcword / 19326.951424 - 277.0562); //19326.951424 - 277.0562 + cb8: 0e 94 6c 17 call 0x2ed8 ; 0x2ed8 <__floatunsisf> + cbc: 27 ee ldi r18, 0xE7 ; 231 + cbe: 3d ef ldi r19, 0xFD ; 253 + cc0: 46 e9 ldi r20, 0x96 ; 150 + cc2: 56 e4 ldi r21, 0x46 ; 70 + cc4: 0e 94 ae 15 call 0x2b5c ; 0x2b5c <__divsf3> + cc8: 22 e3 ldi r18, 0x32 ; 50 + cca: 37 e8 ldi r19, 0x87 ; 135 + ccc: 4a e8 ldi r20, 0x8A ; 138 + cce: 53 e4 ldi r21, 0x43 ; 67 + cd0: 59 cf rjmp .-334 ; 0xb84 + } + break; + default:{ // Temp. Range beyond [-50C , 200C] + PORTC = (PORTC | 0x04); + cd2: aa 9a sbi 0x15, 2 ; 21 + cd4: e3 ec ldi r30, 0xC3 ; 195 + cd6: 75 ef ldi r23, 0xF5 ; 245 + cd8: 88 e4 ldi r24, 0x48 ; 72 + cda: 60 ec ldi r22, 0xC0 ; 192 + cdc: 57 cf rjmp .-338 ; 0xb8c + + + switch (temprange) + { + case 1:{ // Temp. Range [-50°C , -34.375°C[ + temp = ((float)adcword / 20764.727846 - 252.7721); //20764.727846 - 252.7721 + cde: 0e 94 6c 17 call 0x2ed8 ; 0x2ed8 <__floatunsisf> + ce2: 25 e7 ldi r18, 0x75 ; 117 + ce4: 39 e3 ldi r19, 0x39 ; 57 + ce6: 42 ea ldi r20, 0xA2 ; 162 + ce8: 56 e4 ldi r21, 0x46 ; 70 + cea: 0e 94 ae 15 call 0x2b5c ; 0x2b5c <__divsf3> + cee: 28 ea ldi r18, 0xA8 ; 168 + cf0: 35 ec ldi r19, 0xC5 ; 197 + cf2: 4c e7 ldi r20, 0x7C ; 124 + cf4: 53 e4 ldi r21, 0x43 ; 67 + cf6: 46 cf rjmp .-372 ; 0xb84 + } + break; + + case 2:{ // Temp. Range [-34.375°C , -18.75°C[ + temp = ((float)adcword / 20658.049789 - 253.8995); //20658.049789 - 253.8995 + cf8: 0e 94 6c 17 call 0x2ed8 ; 0x2ed8 <__floatunsisf> + cfc: 29 e1 ldi r18, 0x19 ; 25 + cfe: 34 e6 ldi r19, 0x64 ; 100 + d00: 41 ea ldi r20, 0xA1 ; 161 + d02: 56 e4 ldi r21, 0x46 ; 70 + d04: 0e 94 ae 15 call 0x2b5c ; 0x2b5c <__divsf3> + d08: 26 e4 ldi r18, 0x46 ; 70 + d0a: 36 ee ldi r19, 0xE6 ; 230 + d0c: 4d e7 ldi r20, 0x7D ; 125 + d0e: 53 e4 ldi r21, 0x43 ; 67 + d10: 39 cf rjmp .-398 ; 0xb84 + } + break; + + case 3:{ // Temp. Range [-18.75°C , -3.125°C[ + temp = ((float)adcword / 20557.997603 - 255.0436); //20557.997603 - 255.0436 + d12: 0e 94 6c 17 call 0x2ed8 ; 0x2ed8 <__floatunsisf> + d16: 2f ef ldi r18, 0xFF ; 255 + d18: 3b e9 ldi r19, 0x9B ; 155 + d1a: 40 ea ldi r20, 0xA0 ; 160 + d1c: 56 e4 ldi r21, 0x46 ; 70 + d1e: 0e 94 ae 15 call 0x2b5c ; 0x2b5c <__divsf3> + d22: 29 e2 ldi r18, 0x29 ; 41 + d24: 3b e0 ldi r19, 0x0B ; 11 + d26: 4f e7 ldi r20, 0x7F ; 127 + d28: 53 e4 ldi r21, 0x43 ; 67 + d2a: 2c cf rjmp .-424 ; 0xb84 + +00000d2c : + void readandsendpress(void) + { + U32 adcword=0; + float press; + + adcword = read_adc(); + d2c: 0e 94 f4 02 call 0x5e8 ; 0x5e8 + d30: 9b 01 movw r18, r22 + d32: ac 01 movw r20, r24 + + if ( (adcword > 0x253332) && (adcword < 0xF80000) ) // Press. Range is [0Bar , 250Bar] + d34: dc 01 movw r26, r24 + d36: cb 01 movw r24, r22 + d38: 83 53 subi r24, 0x33 ; 51 + d3a: 93 43 sbci r25, 0x33 ; 51 + d3c: a5 42 sbci r26, 0x25 ; 37 + d3e: b0 40 sbci r27, 0x00 ; 0 + d40: 8d 5c subi r24, 0xCD ; 205 + d42: 9c 4c sbci r25, 0xCC ; 204 + d44: a2 4d sbci r26, 0xD2 ; 210 + d46: b0 40 sbci r27, 0x00 ; 0 + d48: c8 f4 brcc .+50 ; 0xd7c + { + press = ((float)adcword / (62 * 836.658790402)) - 63.0091; // 62 Ohm + usart_write_float(press,2,5); + d4a: ca 01 movw r24, r20 + d4c: b9 01 movw r22, r18 + d4e: 0e 94 6c 17 call 0x2ed8 ; 0x2ed8 <__floatunsisf> + d52: 29 ed ldi r18, 0xD9 ; 217 + d54: 30 ea ldi r19, 0xA0 ; 160 + d56: 4a e4 ldi r20, 0x4A ; 74 + d58: 57 e4 ldi r21, 0x47 ; 71 + d5a: 0e 94 ae 15 call 0x2b5c ; 0x2b5c <__divsf3> + d5e: 22 e5 ldi r18, 0x52 ; 82 + d60: 39 e0 ldi r19, 0x09 ; 9 + d62: 4c e7 ldi r20, 0x7C ; 124 + d64: 52 e4 ldi r21, 0x42 ; 66 + d66: 0e 94 56 14 call 0x28ac ; 0x28ac <__subsf3> + d6a: 42 e0 ldi r20, 0x02 ; 2 + d6c: 25 e0 ldi r18, 0x05 ; 5 + d6e: 0e 94 55 0b call 0x16aa ; 0x16aa + usart_write_flash_str(space_STR); + d72: 82 ec ldi r24, 0xC2 ; 194 + d74: 91 e0 ldi r25, 0x01 ; 1 + d76: 0e 94 e0 0a call 0x15c0 ; 0x15c0 + d7a: 08 95 ret + } + else + { + usart_write_flash_str(OoR_STR); // Press. is beyond [0Bar , 250Bar] + d7c: 86 ec ldi r24, 0xC6 ; 198 + d7e: 91 e0 ldi r25, 0x01 ; 1 + d80: 0e 94 e0 0a call 0x15c0 ; 0x15c0 + PORTC = (PORTC | 0x04); + d84: aa 9a sbi 0x15, 2 ; 21 + d86: 08 95 ret + +00000d88 : +// channel 40..79 --> looking at the current channels +// channel 80..83 --> looking at the humidities +void Set_V_Muxer (U08 channel){ +U08 SB = 0; + // voltages + if (channel < 40) { + d88: 88 32 cpi r24, 0x28 ; 40 + d8a: 48 f4 brcc .+18 ; 0xd9e + d8c: 28 2f mov r18, r24 + d8e: 30 e0 ldi r19, 0x00 ; 0 + if (channel < 36) + d90: 84 32 cpi r24, 0x24 ; 36 + d92: 10 f0 brcs .+4 ; 0xd98 + SB = channel*2; + else + SB = (channel+1)*2; + d94: 2f 5f subi r18, 0xFF ; 255 + d96: 3f 4f sbci r19, 0xFF ; 255 + d98: 92 2f mov r25, r18 + d9a: 99 0f add r25, r25 + d9c: 1f c0 rjmp .+62 ; 0xddc + } + // currents + else if (channel < 80) { + d9e: 80 35 cpi r24, 0x50 ; 80 + da0: 60 f4 brcc .+24 ; 0xdba + channel -= 40; + da2: 88 52 subi r24, 0x28 ; 40 + da4: 28 2f mov r18, r24 + da6: 30 e0 ldi r19, 0x00 ; 0 + if (channel < 36) + da8: 84 32 cpi r24, 0x24 ; 36 + daa: 10 f0 brcs .+4 ; 0xdb0 + SB = channel*2+1; + else + SB = (channel+1)*2+1; + dac: 2f 5f subi r18, 0xFF ; 255 + dae: 3f 4f sbci r19, 0xFF ; 255 + db0: 22 0f add r18, r18 + db2: 33 1f adc r19, r19 + db4: 92 2f mov r25, r18 + db6: 9f 5f subi r25, 0xFF ; 255 + db8: 11 c0 rjmp .+34 ; 0xddc + } + // humidities + else if (channel < 84) { + dba: 84 35 cpi r24, 0x54 ; 84 + dbc: 60 f4 brcc .+24 ; 0xdd6 + channel -= 80; + switch (channel) { + dbe: 80 55 subi r24, 0x50 ; 80 + dc0: 81 30 cpi r24, 0x01 ; 1 + dc2: 39 f0 breq .+14 ; 0xdd2 + dc4: 81 30 cpi r24, 0x01 ; 1 + dc6: 18 f0 brcs .+6 ; 0xdce + dc8: 84 30 cpi r24, 0x04 ; 4 + dca: 28 f4 brcc .+10 ; 0xdd6 + dcc: 06 c0 rjmp .+12 ; 0xdda + dce: 98 e4 ldi r25, 0x48 ; 72 + dd0: 05 c0 rjmp .+10 ; 0xddc + dd2: 99 e4 ldi r25, 0x49 ; 73 + dd4: 03 c0 rjmp .+6 ; 0xddc + case 0: + SB = 0x48; //0100.1000 + break; + case 1: + SB = 0x49; //0100.1001 + break; + dd6: 90 e0 ldi r25, 0x00 ; 0 + dd8: 01 c0 rjmp .+2 ; 0xddc + dda: 98 e5 ldi r25, 0x58 ; 88 + SB = 0x58; //0101.0011 + break; + } // end of switch-case + } // end of if (channel < some_number) + + PORTC = (PORTC & 0x80) | (0x7F & SB); // Here the muxer is switched. + ddc: 85 b3 in r24, 0x15 ; 21 + dde: 9f 77 andi r25, 0x7F ; 127 + de0: 80 78 andi r24, 0x80 ; 128 + de2: 98 2b or r25, r24 + de4: 95 bb out 0x15, r25 ; 21 +} + de6: 08 95 ret + +00000de8 : + +void Set_T_Muxer(U08 channel) { + de8: 28 2f mov r18, r24 +U08 SA = 0x00; + + switch (channel/16) { + dea: 82 95 swap r24 + dec: 8f 70 andi r24, 0x0F ; 15 + dee: 82 30 cpi r24, 0x02 ; 2 + df0: 41 f0 breq .+16 ; 0xe02 + df2: 83 30 cpi r24, 0x03 ; 3 + df4: 41 f0 breq .+16 ; 0xe06 + df6: 88 23 and r24, r24 + df8: 11 f4 brne .+4 ; 0xdfe + dfa: 90 e1 ldi r25, 0x10 ; 16 + dfc: 05 c0 rjmp .+10 ; 0xe08 + dfe: 90 e0 ldi r25, 0x00 ; 0 + e00: 03 c0 rjmp .+6 ; 0xe08 + e02: 90 e3 ldi r25, 0x30 ; 48 + e04: 01 c0 rjmp .+2 ; 0xe08 + break; + case 1: + break; // 0000.0000 + case 2: + SA |= (1<<4)|(1<<5); // 0011.0000 + break; + e06: 90 e2 ldi r25, 0x20 ; 32 + break; + } + + SA = SA | (channel%16); + + PORTA = (PORTA & 0xC0) | (0x3F & SA); // Here the muxer is switched. + e08: 8b b3 in r24, 0x1b ; 27 + e0a: 2f 70 andi r18, 0x0F ; 15 + e0c: 92 2b or r25, r18 + e0e: 80 7c andi r24, 0xC0 ; 192 + e10: 98 2b or r25, r24 + e12: 9b bb out 0x1b, r25 ; 27 +} + e14: 08 95 ret + +00000e16 : + //usart_write_U32_hex(data); //data + + +} + +void adc_output(U08 channel, U08 data) { + e16: 0f 93 push r16 + e18: 1f 93 push r17 + e1a: 18 2f mov r17, r24 + e1c: 06 2f mov r16, r22 +// else if (channel < 80) +// usart_write_str((pU08)"I:"); +// else if (channel < 84) +// usart_write_str((pU08)"H:"); + + if (channel <80) + e1e: 80 35 cpi r24, 0x50 ; 80 + e20: 08 f5 brcc .+66 ; 0xe64 + { + switch ((channel%40)/4) { + e22: 68 e2 ldi r22, 0x28 ; 40 + e24: 0e 94 da 19 call 0x33b4 ; 0x33b4 <__udivmodqi4> + e28: 96 95 lsr r25 + e2a: 96 95 lsr r25 + e2c: 96 30 cpi r25, 0x06 ; 6 + e2e: 28 f4 brcc .+10 ; 0xe3a + e30: 94 30 cpi r25, 0x04 ; 4 + e32: 70 f4 brcc .+28 ; 0xe50 + e34: 92 30 cpi r25, 0x02 ; 2 + e36: 40 f0 brcs .+16 ; 0xe48 + e38: 09 c0 rjmp .+18 ; 0xe4c + e3a: 98 30 cpi r25, 0x08 ; 8 + e3c: 69 f0 breq .+26 ; 0xe58 + e3e: 98 30 cpi r25, 0x08 ; 8 + e40: 48 f0 brcs .+18 ; 0xe54 + e42: 99 30 cpi r25, 0x09 ; 9 + e44: 69 f4 brne .+26 ; 0xe60 + e46: 0a c0 rjmp .+20 ; 0xe5c + case 0: + case 1: + usart_write_char('A'); + e48: 81 e4 ldi r24, 0x41 ; 65 + e4a: 0d c0 rjmp .+26 ; 0xe66 + break; + case 2: + case 3: + usart_write_char('B'); + e4c: 82 e4 ldi r24, 0x42 ; 66 + e4e: 0b c0 rjmp .+22 ; 0xe66 + break; + case 4: + case 5: + usart_write_char('C'); + e50: 83 e4 ldi r24, 0x43 ; 67 + e52: 09 c0 rjmp .+18 ; 0xe66 + break; + case 6: + case 7: + usart_write_char('D'); + e54: 84 e4 ldi r24, 0x44 ; 68 + e56: 07 c0 rjmp .+14 ; 0xe66 + break; + case 8: + usart_write_char('E'); + e58: 85 e4 ldi r24, 0x45 ; 69 + e5a: 05 c0 rjmp .+10 ; 0xe66 + break; + case 9: + usart_write_char('F'); + e5c: 86 e4 ldi r24, 0x46 ; 70 + e5e: 03 c0 rjmp .+6 ; 0xe66 + break; + default: + usart_write_char('?'); + e60: 8f e3 ldi r24, 0x3F ; 63 + e62: 01 c0 rjmp .+2 ; 0xe66 + break; + } + } + else // channel 80..83 + { + usart_write_char('H'); + e64: 88 e4 ldi r24, 0x48 ; 72 + e66: 0e 94 c9 0a call 0x1592 ; 0x1592 + } + //usart_write_char(' '); + + if ( (channel%40)/4 == 9) + e6a: 81 2f mov r24, r17 + e6c: 68 e2 ldi r22, 0x28 ; 40 + e6e: 0e 94 da 19 call 0x33b4 ; 0x33b4 <__udivmodqi4> + e72: 94 52 subi r25, 0x24 ; 36 + e74: 94 30 cpi r25, 0x04 ; 4 + e76: 10 f4 brcc .+4 ; 0xe7c + usart_write_U08((channel)%4+1,1); // Numbers 1...4 + e78: 13 70 andi r17, 0x03 ; 3 + e7a: 01 c0 rjmp .+2 ; 0xe7e + else + usart_write_U08((channel)%8+1,1); // Numbers 1...8 + e7c: 17 70 andi r17, 0x07 ; 7 + e7e: 81 2f mov r24, r17 + e80: 8f 5f subi r24, 0xFF ; 255 + e82: 61 e0 ldi r22, 0x01 ; 1 + e84: 0e 94 87 0b call 0x170e ; 0x170e + + + //usart_write_U08(channel,2); // Numbers 1...8 + usart_write_char(':'); + e88: 8a e3 ldi r24, 0x3A ; 58 + e8a: 0e 94 c9 0a call 0x1592 ; 0x1592 + usart_write_U16((U16)data*16, 4); //data + e8e: 80 2f mov r24, r16 + e90: 90 e0 ldi r25, 0x00 ; 0 + e92: 24 e0 ldi r18, 0x04 ; 4 + e94: 88 0f add r24, r24 + e96: 99 1f adc r25, r25 + e98: 2a 95 dec r18 + e9a: e1 f7 brne .-8 ; 0xe94 + e9c: 64 e0 ldi r22, 0x04 ; 4 + e9e: 0e 94 73 0b call 0x16e6 ; 0x16e6 +} + ea2: 1f 91 pop r17 + ea4: 0f 91 pop r16 + ea6: 08 95 ret + +00000ea8 : + usart_write_str((pU08)"ad7719 current channel:"); + usart_write_U08(ad7719_current_channel,2); + usart_write_char('\n'); + +} +void print_adc_nicely() { + ea8: 1f 93 push r17 + eaa: cf 93 push r28 + eac: df 93 push r29 + usart_write_str((pU08)"\n printing voltages in mV:\n"); + eae: 8f ec ldi r24, 0xCF ; 207 + eb0: 91 e0 ldi r25, 0x01 ; 1 + eb2: 0e 94 d6 0a call 0x15ac ; 0x15ac + eb6: c0 e0 ldi r28, 0x00 ; 0 + eb8: d0 e0 ldi r29, 0x00 ; 0 + eba: 1c 2f mov r17, r28 + // output: U08 adc_values[V_CHANNELS + I_CHANNELS + H_CHANNELS]; + for (U08 i=0; i< V_CHANNELS + I_CHANNELS + H_CHANNELS;++i) { + if (i%8 == 0) usart_write_char('\n'); + ebc: ce 01 movw r24, r28 + ebe: 87 70 andi r24, 0x07 ; 7 + ec0: 90 70 andi r25, 0x00 ; 0 + ec2: 89 2b or r24, r25 + ec4: 19 f4 brne .+6 ; 0xecc + ec6: 8a e0 ldi r24, 0x0A ; 10 + ec8: 0e 94 c9 0a call 0x1592 ; 0x1592 + adc_output(i, adc_values[i]); + ecc: fe 01 movw r30, r28 + ece: e0 59 subi r30, 0x90 ; 144 + ed0: f8 4f sbci r31, 0xF8 ; 248 + ed2: 81 2f mov r24, r17 + ed4: 60 81 ld r22, Z + ed6: 0e 94 0b 07 call 0xe16 ; 0xe16 + usart_write_str((pU08)" "); + eda: 8b ee ldi r24, 0xEB ; 235 + edc: 91 e0 ldi r25, 0x01 ; 1 + ede: 0e 94 d6 0a call 0x15ac ; 0x15ac + ee2: 21 96 adiw r28, 0x01 ; 1 + +} +void print_adc_nicely() { + usart_write_str((pU08)"\n printing voltages in mV:\n"); + // output: U08 adc_values[V_CHANNELS + I_CHANNELS + H_CHANNELS]; + for (U08 i=0; i< V_CHANNELS + I_CHANNELS + H_CHANNELS;++i) { + ee4: c4 35 cpi r28, 0x54 ; 84 + ee6: d1 05 cpc r29, r1 + ee8: 41 f7 brne .-48 ; 0xeba + if (i%8 == 0) usart_write_char('\n'); + adc_output(i, adc_values[i]); + usart_write_str((pU08)" "); + } + usart_write_char('\n'); + eea: 8a e0 ldi r24, 0x0A ; 10 + eec: 0e 94 c9 0a call 0x1592 ; 0x1592 +} + ef0: df 91 pop r29 + ef2: cf 91 pop r28 + ef4: 1f 91 pop r17 + ef6: 08 95 ret + +00000ef8 : + } + //usart_write_char('\n'); + } +} + +void ad7719_output(U08 channel, U32 data) { + ef8: cf 92 push r12 + efa: df 92 push r13 + efc: ef 92 push r14 + efe: ff 92 push r15 + f00: 1f 93 push r17 + f02: 18 2f mov r17, r24 + f04: 6a 01 movw r12, r20 + f06: 7b 01 movw r14, r22 +float value = 0; + usart_write_str((pU08)"R:"); //R for resistance + f08: 8f ee ldi r24, 0xEF ; 239 + f0a: 91 e0 ldi r25, 0x01 ; 1 + f0c: 0e 94 d6 0a call 0x15ac ; 0x15ac + usart_write_char('A'+channel/8); // Letters A,B,C,D,E,F,G,H + f10: 81 2f mov r24, r17 + f12: 86 95 lsr r24 + f14: 86 95 lsr r24 + f16: 86 95 lsr r24 + f18: 8f 5b subi r24, 0xBF ; 191 + f1a: 0e 94 c9 0a call 0x1592 ; 0x1592 + //usart_write_char(' '); + usart_write_U08(channel%8+1,1); // Numbers 1...8 + f1e: 17 70 andi r17, 0x07 ; 7 + f20: 81 2f mov r24, r17 + f22: 8f 5f subi r24, 0xFF ; 255 + f24: 61 e0 ldi r22, 0x01 ; 1 + f26: 0e 94 87 0b call 0x170e ; 0x170e + usart_write_char(':'); + f2a: 8a e3 ldi r24, 0x3A ; 58 + f2c: 0e 94 c9 0a call 0x1592 ; 0x1592 + + + value = (6.25 * data) / ((U32)1 << 25); + usart_write_float(value, 3,6); + f30: c7 01 movw r24, r14 + f32: b6 01 movw r22, r12 + f34: 0e 94 6c 17 call 0x2ed8 ; 0x2ed8 <__floatunsisf> + f38: 20 e0 ldi r18, 0x00 ; 0 + f3a: 30 e0 ldi r19, 0x00 ; 0 + f3c: 48 ec ldi r20, 0xC8 ; 200 + f3e: 50 e4 ldi r21, 0x40 ; 64 + f40: 0e 94 b4 14 call 0x2968 ; 0x2968 <__mulsf3> + f44: 20 e0 ldi r18, 0x00 ; 0 + f46: 30 e0 ldi r19, 0x00 ; 0 + f48: 40 e0 ldi r20, 0x00 ; 0 + f4a: 53 e3 ldi r21, 0x33 ; 51 + f4c: 0e 94 b4 14 call 0x2968 ; 0x2968 <__mulsf3> + f50: 43 e0 ldi r20, 0x03 ; 3 + f52: 26 e0 ldi r18, 0x06 ; 6 + f54: 0e 94 55 0b call 0x16aa ; 0x16aa + //usart_write_U32_hex(data); //data + + +} + f58: 1f 91 pop r17 + f5a: ff 90 pop r15 + f5c: ef 90 pop r14 + f5e: df 90 pop r13 + f60: cf 90 pop r12 + f62: 08 95 ret + +00000f64 : + usart_write_char('\n'); +} + + +void print_ad7719_nicely() +{ + f64: cf 92 push r12 + f66: df 92 push r13 + f68: ef 92 push r14 + f6a: ff 92 push r15 + f6c: 0f 93 push r16 + f6e: 1f 93 push r17 + f70: cf 93 push r28 + f72: df 93 push r29 + float value; + + usart_write_str((pU08)"\n printing measured resistance in kohms:\n"); + f74: 82 ef ldi r24, 0xF2 ; 242 + f76: 91 e0 ldi r25, 0x01 ; 1 + f78: 0e 94 d6 0a call 0x15ac ; 0x15ac + f7c: 43 e6 ldi r20, 0x63 ; 99 + f7e: e4 2e mov r14, r20 + f80: 46 e0 ldi r20, 0x06 ; 6 + f82: f4 2e mov r15, r20 + f84: c0 e0 ldi r28, 0x00 ; 0 + f86: d0 e0 ldi r29, 0x00 ; 0 + f88: 1c 2f mov r17, r28 + + for (U08 i=0; i< TEMP_CHANNELS;++i) { + if (i%8 == 0) usart_write_char('\n'); + f8a: 37 e0 ldi r19, 0x07 ; 7 + f8c: c3 2e mov r12, r19 + f8e: d1 2c mov r13, r1 + f90: cc 22 and r12, r28 + f92: dd 22 and r13, r29 + f94: c1 14 cp r12, r1 + f96: d1 04 cpc r13, r1 + f98: 19 f4 brne .+6 ; 0xfa0 + f9a: 8a e0 ldi r24, 0x0A ; 10 + f9c: 0e 94 c9 0a call 0x1592 ; 0x1592 + + // print channel name: + usart_write_str((pU08)"R:"); //R for resistance + fa0: 8f ee ldi r24, 0xEF ; 239 + fa2: 91 e0 ldi r25, 0x01 ; 1 + fa4: 0e 94 d6 0a call 0x15ac ; 0x15ac + usart_write_char('A'+i/8); // Letters A,B,C,D,E,F,G,H + fa8: 01 2f mov r16, r17 + faa: 06 95 lsr r16 + fac: 06 95 lsr r16 + fae: 06 95 lsr r16 + fb0: 80 2f mov r24, r16 + fb2: 8f 5b subi r24, 0xBF ; 191 + fb4: 0e 94 c9 0a call 0x1592 ; 0x1592 + //usart_write_char(' '); + usart_write_U08(i%8+1,1); // Numbers 1...8 + fb8: 17 70 andi r17, 0x07 ; 7 + fba: 81 2f mov r24, r17 + fbc: 8f 5f subi r24, 0xFF ; 255 + fbe: 61 e0 ldi r22, 0x01 ; 1 + fc0: 0e 94 87 0b call 0x170e ; 0x170e + usart_write_char(':'); + fc4: 8a e3 ldi r24, 0x3A ; 58 + fc6: 0e 94 c9 0a call 0x1592 ; 0x1592 + + // check if this channel is enabled in the bitmap + if (ad7719_enables[i/8] & (1< + fd8: 95 95 asr r25 + fda: 87 95 ror r24 + fdc: ca 94 dec r12 + fde: e2 f7 brpl .-8 ; 0xfd8 + fe0: 80 ff sbrs r24, 0 + fe2: 1a c0 rjmp .+52 ; 0x1018 + { + value = (6.25 * 1.024 * ad7719_values[i]) / ((U32)1 << 25); + usart_write_float(value, 3,6); + fe4: f7 01 movw r30, r14 + fe6: 60 81 ld r22, Z + fe8: 71 81 ldd r23, Z+1 ; 0x01 + fea: 82 81 ldd r24, Z+2 ; 0x02 + fec: 93 81 ldd r25, Z+3 ; 0x03 + fee: 0e 94 6c 17 call 0x2ed8 ; 0x2ed8 <__floatunsisf> + ff2: 2d ec ldi r18, 0xCD ; 205 + ff4: 3c ec ldi r19, 0xCC ; 204 + ff6: 4c ec ldi r20, 0xCC ; 204 + ff8: 50 e4 ldi r21, 0x40 ; 64 + ffa: 0e 94 b4 14 call 0x2968 ; 0x2968 <__mulsf3> + ffe: 20 e0 ldi r18, 0x00 ; 0 + 1000: 30 e0 ldi r19, 0x00 ; 0 + 1002: 40 e0 ldi r20, 0x00 ; 0 + 1004: 53 e3 ldi r21, 0x33 ; 51 + 1006: 0e 94 b4 14 call 0x2968 ; 0x2968 <__mulsf3> + 100a: 43 e0 ldi r20, 0x03 ; 3 + 100c: 26 e0 ldi r18, 0x06 ; 6 + 100e: 0e 94 55 0b call 0x16aa ; 0x16aa + //usart_write_U32(ad7719_values[i],8); + //usart_write_U32_hex(data); //data + usart_write_str((pU08)" "); + 1012: 8c e1 ldi r24, 0x1C ; 28 + 1014: 92 e0 ldi r25, 0x02 ; 2 + 1016: 02 c0 rjmp .+4 ; 0x101c + } else { + usart_write_str((pU08)" "); + 1018: 8e e1 ldi r24, 0x1E ; 30 + 101a: 92 e0 ldi r25, 0x02 ; 2 + 101c: 0e 94 d6 0a call 0x15ac ; 0x15ac + 1020: 21 96 adiw r28, 0x01 ; 1 + 1022: 84 e0 ldi r24, 0x04 ; 4 + 1024: 90 e0 ldi r25, 0x00 ; 0 + 1026: e8 0e add r14, r24 + 1028: f9 1e adc r15, r25 +{ + float value; + + usart_write_str((pU08)"\n printing measured resistance in kohms:\n"); + + for (U08 i=0; i< TEMP_CHANNELS;++i) { + 102a: c0 34 cpi r28, 0x40 ; 64 + 102c: d1 05 cpc r29, r1 + 102e: 09 f0 breq .+2 ; 0x1032 + 1030: ab cf rjmp .-170 ; 0xf88 + } else { + usart_write_str((pU08)" "); + } + //usart_write_char('\n'); + } +} + 1032: df 91 pop r29 + 1034: cf 91 pop r28 + 1036: 1f 91 pop r17 + 1038: 0f 91 pop r16 + 103a: ff 90 pop r15 + 103c: ef 90 pop r14 + 103e: df 90 pop r13 + 1040: cf 90 pop r12 + 1042: 08 95 ret + +00001044 : + usart_write_U16((U16)data*16, 4); //data +} + + +void adc_output_all() { + print_adc_nicely(); + 1044: 0e 94 54 07 call 0xea8 ; 0xea8 + print_ad7719_nicely(); + 1048: 0e 94 b2 07 call 0xf64 ; 0xf64 +} + 104c: 08 95 ret + +0000104e : +#include "output.h" +#include "usart.h" +#include "application.h" + +void print_status() { + 104e: cf 93 push r28 + 1050: df 93 push r29 + usart_write_str((pU08)"adc status:\n"); + 1052: 88 e2 ldi r24, 0x28 ; 40 + 1054: 92 e0 ldi r25, 0x02 ; 2 + 1056: 0e 94 d6 0a call 0x15ac ; 0x15ac + 105a: c7 e5 ldi r28, 0x57 ; 87 + 105c: d6 e0 ldi r29, 0x06 ; 6 + for (U08 i=0; i< V_BITMAP + I_BITMAP + H_BITMAP;++i) { + usart_write_U08_bin(adc_enables[i]); + 105e: 89 91 ld r24, Y+ + 1060: 0e 94 78 0b call 0x16f0 ; 0x16f0 + usart_write_char(' '); + 1064: 80 e2 ldi r24, 0x20 ; 32 + 1066: 0e 94 c9 0a call 0x1592 ; 0x1592 +#include "usart.h" +#include "application.h" + +void print_status() { + usart_write_str((pU08)"adc status:\n"); + for (U08 i=0; i< V_BITMAP + I_BITMAP + H_BITMAP;++i) { + 106a: 86 e0 ldi r24, 0x06 ; 6 + 106c: c2 36 cpi r28, 0x62 ; 98 + 106e: d8 07 cpc r29, r24 + 1070: b1 f7 brne .-20 ; 0x105e + usart_write_U08_bin(adc_enables[i]); + usart_write_char(' '); + } + usart_write_char('\n'); + 1072: 8a e0 ldi r24, 0x0A ; 10 + 1074: 0e 94 c9 0a call 0x1592 ; 0x1592 + 1078: cb e4 ldi r28, 0x4B ; 75 + 107a: d6 e0 ldi r29, 0x06 ; 6 + for (U08 i=0; i< V_BITMAP + I_BITMAP + H_BITMAP;++i){ + usart_write_U08_bin(adc_channels_ready[i]); + 107c: 89 91 ld r24, Y+ + 107e: 0e 94 78 0b call 0x16f0 ; 0x16f0 + usart_write_char(' '); + 1082: 80 e2 ldi r24, 0x20 ; 32 + 1084: 0e 94 c9 0a call 0x1592 ; 0x1592 + for (U08 i=0; i< V_BITMAP + I_BITMAP + H_BITMAP;++i) { + usart_write_U08_bin(adc_enables[i]); + usart_write_char(' '); + } + usart_write_char('\n'); + for (U08 i=0; i< V_BITMAP + I_BITMAP + H_BITMAP;++i){ + 1088: 86 e0 ldi r24, 0x06 ; 6 + 108a: c6 35 cpi r28, 0x56 ; 86 + 108c: d8 07 cpc r29, r24 + 108e: b1 f7 brne .-20 ; 0x107c + usart_write_U08_bin(adc_channels_ready[i]); + usart_write_char(' '); + } + usart_write_char('\n'); + 1090: 8a e0 ldi r24, 0x0A ; 10 + 1092: 0e 94 c9 0a call 0x1592 ; 0x1592 + + usart_write_str((pU08)"ad7719 status:\n"); + 1096: 85 e3 ldi r24, 0x35 ; 53 + 1098: 92 e0 ldi r25, 0x02 ; 2 + 109a: 0e 94 d6 0a call 0x15ac ; 0x15ac + 109e: c3 e6 ldi r28, 0x63 ; 99 + 10a0: d7 e0 ldi r29, 0x07 ; 7 + for (U08 i=0; i< CHANNEL_BITMAP;++i) { + usart_write_U08_bin(ad7719_enables[i]); + 10a2: 89 91 ld r24, Y+ + 10a4: 0e 94 78 0b call 0x16f0 ; 0x16f0 + usart_write_char(' '); + 10a8: 80 e2 ldi r24, 0x20 ; 32 + 10aa: 0e 94 c9 0a call 0x1592 ; 0x1592 + usart_write_char(' '); + } + usart_write_char('\n'); + + usart_write_str((pU08)"ad7719 status:\n"); + for (U08 i=0; i< CHANNEL_BITMAP;++i) { + 10ae: 87 e0 ldi r24, 0x07 ; 7 + 10b0: cb 36 cpi r28, 0x6B ; 107 + 10b2: d8 07 cpc r29, r24 + 10b4: b1 f7 brne .-20 ; 0x10a2 + usart_write_U08_bin(ad7719_enables[i]); + usart_write_char(' '); + } + usart_write_char('\n'); + 10b6: 8a e0 ldi r24, 0x0A ; 10 + 10b8: 0e 94 c9 0a call 0x1592 ; 0x1592 + 10bc: c4 ec ldi r28, 0xC4 ; 196 + 10be: d7 e0 ldi r29, 0x07 ; 7 + for (U08 i=0; i< CHANNEL_BITMAP;++i){ + usart_write_U08_bin(ad7719_channels_ready[i]); + 10c0: 89 91 ld r24, Y+ + 10c2: 0e 94 78 0b call 0x16f0 ; 0x16f0 + usart_write_char(' '); + 10c6: 80 e2 ldi r24, 0x20 ; 32 + 10c8: 0e 94 c9 0a call 0x1592 ; 0x1592 + for (U08 i=0; i< CHANNEL_BITMAP;++i) { + usart_write_U08_bin(ad7719_enables[i]); + usart_write_char(' '); + } + usart_write_char('\n'); + for (U08 i=0; i< CHANNEL_BITMAP;++i){ + 10cc: 87 e0 ldi r24, 0x07 ; 7 + 10ce: cc 3c cpi r28, 0xCC ; 204 + 10d0: d8 07 cpc r29, r24 + 10d2: b1 f7 brne .-20 ; 0x10c0 + usart_write_U08_bin(ad7719_channels_ready[i]); + usart_write_char(' '); + } + usart_write_char('\n'); + 10d4: 8a e0 ldi r24, 0x0A ; 10 + 10d6: 0e 94 c9 0a call 0x1592 ; 0x1592 + + usart_write_str((pU08)"time:"); + 10da: 85 e4 ldi r24, 0x45 ; 69 + 10dc: 92 e0 ldi r25, 0x02 ; 2 + 10de: 0e 94 d6 0a call 0x15ac ; 0x15ac + usart_write_float((float)local_ms/1000 , 1,7); + 10e2: 60 91 b3 05 lds r22, 0x05B3 + 10e6: 70 91 b4 05 lds r23, 0x05B4 + 10ea: 80 91 b5 05 lds r24, 0x05B5 + 10ee: 90 91 b6 05 lds r25, 0x05B6 + 10f2: 0e 94 6c 17 call 0x2ed8 ; 0x2ed8 <__floatunsisf> + 10f6: 20 e0 ldi r18, 0x00 ; 0 + 10f8: 30 e0 ldi r19, 0x00 ; 0 + 10fa: 4a e7 ldi r20, 0x7A ; 122 + 10fc: 54 e4 ldi r21, 0x44 ; 68 + 10fe: 0e 94 ae 15 call 0x2b5c ; 0x2b5c <__divsf3> + 1102: 41 e0 ldi r20, 0x01 ; 1 + 1104: 27 e0 ldi r18, 0x07 ; 7 + 1106: 0e 94 55 0b call 0x16aa ; 0x16aa + usart_write_str((pU08)" sec.\n"); + 110a: 8b e4 ldi r24, 0x4B ; 75 + 110c: 92 e0 ldi r25, 0x02 ; 2 + 110e: 0e 94 d6 0a call 0x15ac ; 0x15ac + + usart_write_str((pU08)"adc measured all: "); + 1112: 82 e5 ldi r24, 0x52 ; 82 + 1114: 92 e0 ldi r25, 0x02 ; 2 + 1116: 0e 94 d6 0a call 0x15ac ; 0x15ac + if (adc_measured_all) + 111a: 80 91 c1 05 lds r24, 0x05C1 + 111e: 88 23 and r24, r24 + 1120: 19 f0 breq .+6 ; 0x1128 + usart_write_str((pU08)" true\n"); + 1122: 85 e6 ldi r24, 0x65 ; 101 + 1124: 92 e0 ldi r25, 0x02 ; 2 + 1126: 02 c0 rjmp .+4 ; 0x112c + else + usart_write_str((pU08)"false\n"); + 1128: 8c e6 ldi r24, 0x6C ; 108 + 112a: 92 e0 ldi r25, 0x02 ; 2 + 112c: 0e 94 d6 0a call 0x15ac ; 0x15ac + + usart_write_str((pU08)"ad7719 measured all: "); + 1130: 83 e7 ldi r24, 0x73 ; 115 + 1132: 92 e0 ldi r25, 0x02 ; 2 + 1134: 0e 94 d6 0a call 0x15ac ; 0x15ac + if (ad7719_measured_all) + 1138: 80 91 bd 05 lds r24, 0x05BD + 113c: 88 23 and r24, r24 + 113e: 19 f0 breq .+6 ; 0x1146 + usart_write_str((pU08)" true\n"); + 1140: 85 e6 ldi r24, 0x65 ; 101 + 1142: 92 e0 ldi r25, 0x02 ; 2 + 1144: 02 c0 rjmp .+4 ; 0x114a + else + usart_write_str((pU08)"false\n"); + 1146: 8c e6 ldi r24, 0x6C ; 108 + 1148: 92 e0 ldi r25, 0x02 ; 2 + 114a: 0e 94 d6 0a call 0x15ac ; 0x15ac + + usart_write_str((pU08)"adc current channel:"); + 114e: 89 e8 ldi r24, 0x89 ; 137 + 1150: 92 e0 ldi r25, 0x02 ; 2 + 1152: 0e 94 d6 0a call 0x15ac ; 0x15ac + usart_write_U08(adc_current_channel,2); + 1156: 80 91 bf 05 lds r24, 0x05BF + 115a: 62 e0 ldi r22, 0x02 ; 2 + 115c: 0e 94 87 0b call 0x170e ; 0x170e + usart_write_char('\n'); + 1160: 8a e0 ldi r24, 0x0A ; 10 + 1162: 0e 94 c9 0a call 0x1592 ; 0x1592 + + usart_write_str((pU08)"ad7719 current channel:"); + 1166: 8e e9 ldi r24, 0x9E ; 158 + 1168: 92 e0 ldi r25, 0x02 ; 2 + 116a: 0e 94 d6 0a call 0x15ac ; 0x15ac + usart_write_U08(ad7719_current_channel,2); + 116e: 80 91 b8 05 lds r24, 0x05B8 + 1172: 62 e0 ldi r22, 0x02 ; 2 + 1174: 0e 94 87 0b call 0x170e ; 0x170e + usart_write_char('\n'); + 1178: 8a e0 ldi r24, 0x0A ; 10 + 117a: 0e 94 c9 0a call 0x1592 ; 0x1592 + +} + 117e: df 91 pop r29 + 1180: cf 91 pop r28 + 1182: 08 95 ret + +00001184 : +} + +void parse_non_human_readable_input() { + + +} + 1184: 08 95 ret + +00001186 : +// to be discarded, because something went wrong, and the bytemade no sense... +// the end of a commmand, and so the 'real parser' may do his work. + +void incoming_byte_parser() { + static bool receiving_command = false; + U08 current_byte = UDR; + 1186: 9c b1 in r25, 0x0c ; 12 + + if (!receiving_command) { + 1188: 80 91 99 05 lds r24, 0x0599 + 118c: 88 23 and r24, r24 + 118e: 21 f4 brne .+8 ; 0x1198 + switch (current_byte) { + 1190: 91 30 cpi r25, 0x01 ; 1 + 1192: 11 f4 brne .+4 ; 0x1198 + case 0x01: + receiving_command = true; + 1194: 90 93 99 05 sts 0x0599, r25 + break; + } + } + + if (receiving_command) + 1198: 80 91 99 05 lds r24, 0x0599 + 119c: 88 23 and r24, r24 + 119e: 61 f0 breq .+24 ; 0x11b8 + { + usart_rx_buffer[usart_received_chars] = usart_last_char; + 11a0: 80 91 09 06 lds r24, 0x0609 + 11a4: e8 2f mov r30, r24 + 11a6: f0 e0 ldi r31, 0x00 ; 0 + 11a8: e6 5f subi r30, 0xF6 ; 246 + 11aa: f9 4f sbci r31, 0xF9 ; 249 + 11ac: 90 91 62 06 lds r25, 0x0662 + 11b0: 90 83 st Z, r25 + usart_received_chars++; + 11b2: 8f 5f subi r24, 0xFF ; 255 + 11b4: 80 93 09 06 sts 0x0609, r24 + 11b8: 08 95 ret + +000011ba : +#include "usart.h" +// this method parses the data, +// which came in via USART +// later it might as well parse the data from ethernet. +void parse_ascii() { + usart_rx_buffer[USART_RX_BUFFER_SIZE-1] = 0; + 11ba: 10 92 29 06 sts 0x0629, r1 + usart_write_str((pU08)"got:"); + 11be: 86 eb ldi r24, 0xB6 ; 182 + 11c0: 92 e0 ldi r25, 0x02 ; 2 + 11c2: 0e 94 d6 0a call 0x15ac ; 0x15ac + usart_write_str(usart_rx_buffer); + 11c6: 8a e0 ldi r24, 0x0A ; 10 + 11c8: 96 e0 ldi r25, 0x06 ; 6 + 11ca: 0e 94 d6 0a call 0x15ac ; 0x15ac + +// look at first byte +// I hope, I can manage to use one byte commands + switch (usart_rx_buffer[0]) { + 11ce: 80 91 0a 06 lds r24, 0x060A + 11d2: 85 36 cpi r24, 0x65 ; 101 + 11d4: 09 f1 breq .+66 ; 0x1218 + 11d6: 86 36 cpi r24, 0x66 ; 102 + 11d8: 70 f4 brcc .+28 ; 0x11f6 + 11da: 87 34 cpi r24, 0x47 ; 71 + 11dc: 71 f1 breq .+92 ; 0x123a + 11de: 88 34 cpi r24, 0x48 ; 72 + 11e0: 20 f4 brcc .+8 ; 0x11ea + 11e2: 85 34 cpi r24, 0x45 ; 69 + 11e4: 09 f0 breq .+2 ; 0x11e8 + 11e6: 5a c0 rjmp .+180 ; 0x129c + 11e8: 14 c0 rjmp .+40 ; 0x1212 + 11ea: 80 35 cpi r24, 0x50 ; 80 + 11ec: d1 f1 breq .+116 ; 0x1262 + 11ee: 84 36 cpi r24, 0x64 ; 100 + 11f0: 09 f0 breq .+2 ; 0x11f4 + 11f2: 54 c0 rjmp .+168 ; 0x129c + 11f4: 3f c0 rjmp .+126 ; 0x1274 + 11f6: 88 36 cpi r24, 0x68 ; 104 + 11f8: 91 f0 breq .+36 ; 0x121e + 11fa: 89 36 cpi r24, 0x69 ; 105 + 11fc: 20 f4 brcc .+8 ; 0x1206 + 11fe: 87 36 cpi r24, 0x67 ; 103 + 1200: 09 f0 breq .+2 ; 0x1204 + 1202: 4c c0 rjmp .+152 ; 0x129c + 1204: 24 c0 rjmp .+72 ; 0x124e + 1206: 80 37 cpi r24, 0x70 ; 112 + 1208: 79 f1 breq .+94 ; 0x1268 + 120a: 83 37 cpi r24, 0x73 ; 115 + 120c: 09 f0 breq .+2 ; 0x1210 + 120e: 46 c0 rjmp .+140 ; 0x129c + 1210: 2e c0 rjmp .+92 ; 0x126e + case 'E': // AD7719 enable bitmaps may be set + set_ad7719_enable_register(); + 1212: 0e 94 77 04 call 0x8ee ; 0x8ee + 1216: 42 c0 rjmp .+132 ; 0x129c + break; + case 'e': // ATmega internal ADC enable bitmaps may be set + // not supported yet. + set_adc_enable_register(); + 1218: 0e 94 72 04 call 0x8e4 ; 0x8e4 + 121c: 3f c0 rjmp .+126 ; 0x129c + break; + case 'h': + usart_write_str((pU08)"\nheartbeat "); + 121e: 8b eb ldi r24, 0xBB ; 187 + 1220: 92 e0 ldi r25, 0x02 ; 2 + 1222: 0e 94 d6 0a call 0x15ac ; 0x15ac + heartbeat_enable = true; + 1226: 81 e0 ldi r24, 0x01 ; 1 + 1228: 80 93 56 06 sts 0x0656, r24 + if (usart_rx_buffer[1] == '0'){ + 122c: 80 91 0b 06 lds r24, 0x060B + 1230: 80 33 cpi r24, 0x30 ; 48 + 1232: 81 f5 brne .+96 ; 0x1294 + heartbeat_enable = false; + 1234: 10 92 56 06 sts 0x0656, r1 + 1238: 2a c0 rjmp .+84 ; 0x128e + } else { + usart_write_str((pU08)"on\n"); + } + break; + case 'G': // GET the Temperature channels, which are enabled + once_told_you = false; + 123a: 10 92 8e 04 sts 0x048E, r1 + 123e: e4 ec ldi r30, 0xC4 ; 196 + 1240: f7 e0 ldi r31, 0x07 ; 7 + for ( U08 i=0; i + 124c: 27 c0 rjmp .+78 ; 0x129c + ad7719_channels_ready[i]=0; + } + break; + + case 'g': // GET the voltage/current/humidity channels, which are enabled + once_told_you = false; + 124e: 10 92 8e 04 sts 0x048E, r1 + 1252: eb e4 ldi r30, 0x4B ; 75 + 1254: f6 e0 ldi r31, 0x06 ; 6 + for ( U08 i=0; i + 1260: 1d c0 rjmp .+58 ; 0x129c + adc_channels_ready[i]=0; + } + break; + + case 'P': + print_ad7719_nicely(); + 1262: 0e 94 b2 07 call 0xf64 ; 0xf64 + 1266: 1a c0 rjmp .+52 ; 0x129c + break; + + case 'p': + print_adc_nicely(); + 1268: 0e 94 54 07 call 0xea8 ; 0xea8 + 126c: 17 c0 rjmp .+46 ; 0x129c + break; + + case 's': + print_status(); + 126e: 0e 94 27 08 call 0x104e ; 0x104e + 1272: 14 c0 rjmp .+40 ; 0x129c + break; + + case 'd': + usart_write_str((pU08)"\ndebug mode "); + 1274: 80 ed ldi r24, 0xD0 ; 208 + 1276: 92 e0 ldi r25, 0x02 ; 2 + 1278: 0e 94 d6 0a call 0x15ac ; 0x15ac + debug_mode = true; + 127c: 81 e0 ldi r24, 0x01 ; 1 + 127e: 80 93 c2 05 sts 0x05C2, r24 + if (usart_rx_buffer[1] == '0'){ + 1282: 80 91 0b 06 lds r24, 0x060B + 1286: 80 33 cpi r24, 0x30 ; 48 + 1288: 29 f4 brne .+10 ; 0x1294 + debug_mode = false; + 128a: 10 92 c2 05 sts 0x05C2, r1 + usart_write_str((pU08)"off\n"); + 128e: 87 ec ldi r24, 0xC7 ; 199 + 1290: 92 e0 ldi r25, 0x02 ; 2 + 1292: 02 c0 rjmp .+4 ; 0x1298 + } else { + usart_write_str((pU08)"on\n"); + 1294: 8c ec ldi r24, 0xCC ; 204 + 1296: 92 e0 ldi r25, 0x02 ; 2 + 1298: 0e 94 d6 0a call 0x15ac ; 0x15ac + } + break; + } + + + usart_write_str((pU08)"\nready?"); + 129c: 8d ed ldi r24, 0xDD ; 221 + 129e: 92 e0 ldi r25, 0x02 ; 2 + 12a0: 0e 94 d6 0a call 0x15ac ; 0x15ac + 12a4: ea e0 ldi r30, 0x0A ; 10 + 12a6: f6 e0 ldi r31, 0x06 ; 6 + for (U08 i=0; i + usart_rx_buffer[i] = 0; +} + 12b2: 08 95 ret + +000012b4 : +} +//----------------------------------------------------------------------------- +void spi_setup(void) +{ + // Disable SPI, clear all flags + SPCR = 0; + 12b4: 1d b8 out 0x0d, r1 ; 13 + + // Set/Clear bits DORD, CPOL and CPHA in SPI Control Register + spi_dord & 0x01 ? (SPCR |= (1 << DORD)) : (SPCR &= ~(1 << DORD)); + 12b6: 80 91 f8 05 lds r24, 0x05F8 + 12ba: 80 ff sbrs r24, 0 + 12bc: 02 c0 rjmp .+4 ; 0x12c2 + 12be: 6d 9a sbi 0x0d, 5 ; 13 + 12c0: 01 c0 rjmp .+2 ; 0x12c4 + 12c2: 6d 98 cbi 0x0d, 5 ; 13 + 12c4: 8d b1 in r24, 0x0d ; 13 + spi_cpol & 0x01 ? (SPCR |= (1 << CPOL)) : (SPCR &= ~(1 << CPOL)); + 12c6: 80 91 e5 05 lds r24, 0x05E5 + 12ca: 80 ff sbrs r24, 0 + 12cc: 02 c0 rjmp .+4 ; 0x12d2 + 12ce: 6b 9a sbi 0x0d, 3 ; 13 + 12d0: 01 c0 rjmp .+2 ; 0x12d4 + 12d2: 6b 98 cbi 0x0d, 3 ; 13 + 12d4: 8d b1 in r24, 0x0d ; 13 + spi_cpha & 0x01 ? (SPCR |= (1 << CPHA)) : (SPCR &= ~(1 << CPHA)); + 12d6: 80 91 f6 05 lds r24, 0x05F6 + 12da: 80 ff sbrs r24, 0 + 12dc: 02 c0 rjmp .+4 ; 0x12e2 + 12de: 6a 9a sbi 0x0d, 2 ; 13 + 12e0: 01 c0 rjmp .+2 ; 0x12e4 + 12e2: 6a 98 cbi 0x0d, 2 ; 13 + 12e4: 8d b1 in r24, 0x0d ; 13 + + switch (spi_clock_index) + 12e6: 80 91 f7 05 lds r24, 0x05F7 + 12ea: 83 30 cpi r24, 0x03 ; 3 + 12ec: 91 f0 breq .+36 ; 0x1312 + 12ee: 84 30 cpi r24, 0x04 ; 4 + 12f0: 28 f4 brcc .+10 ; 0x12fc + 12f2: 81 30 cpi r24, 0x01 ; 1 + 12f4: 51 f0 breq .+20 ; 0x130a + 12f6: 82 30 cpi r24, 0x02 ; 2 + 12f8: 50 f4 brcc .+20 ; 0x130e + 12fa: 10 c0 rjmp .+32 ; 0x131c + 12fc: 85 30 cpi r24, 0x05 ; 5 + 12fe: 89 f0 breq .+34 ; 0x1322 + 1300: 85 30 cpi r24, 0x05 ; 5 + 1302: 48 f0 brcs .+18 ; 0x1316 + 1304: 86 30 cpi r24, 0x06 ; 6 + 1306: 51 f4 brne .+20 ; 0x131c + 1308: 07 c0 rjmp .+14 ; 0x1318 + SPSR &= ~(1 < + SPSR &= ~(1 << SPI2X); + } + break; + + case 2:{ // F_CPU / 32 + SPCR |= (1 << SPR1); + 130e: 69 9a sbi 0x0d, 1 ; 13 + 1310: 03 c0 rjmp .+6 ; 0x1318 + SPSR |= (1 << SPI2X); + } + break; + + case 3:{ // F_CPU / 16 + SPCR |= (1 << SPR0); + 1312: 68 9a sbi 0x0d, 0 ; 13 + 1314: 06 c0 rjmp .+12 ; 0x1322 + SPSR &= ~(1 << SPI2X); + } + break; + + case 4:{ // F_CPU / 8 + SPCR |= (1 << SPR0); + 1316: 68 9a sbi 0x0d, 0 ; 13 + case 5: // F_CPU / 4 + SPSR &= ~(1 << SPI2X); + break; + + case 6: // F_CPU / 2 + SPSR |= (1 << SPI2X); + 1318: 70 9a sbi 0x0e, 0 ; 14 + 131a: 04 c0 rjmp .+8 ; 0x1324 + break; + + default:{ // F_CPU / 128 + SPCR |= (1 << SPR1) | (1 << SPR0); + 131c: 8d b1 in r24, 0x0d ; 13 + 131e: 83 60 ori r24, 0x03 ; 3 + 1320: 8d b9 out 0x0d, r24 ; 13 + SPSR &= ~(1 << SPI2X); + 1322: 70 98 cbi 0x0e, 0 ; 14 + } + } + + // Enable SPI in Master Mode + SPCR |= (1 << SPE) | (1 << MSTR); + 1324: 8d b1 in r24, 0x0d ; 13 + 1326: 80 65 ori r24, 0x50 ; 80 + 1328: 8d b9 out 0x0d, r24 ; 13 +} + 132a: 08 95 ret + +0000132c : + + // fastes SPI CLK frequency can be --> F_CPU/2 = 4MHz + // slowest can be --> F_CPU/128 = 62.5KHz + + // Lets try with the fastest! + spi_clock_index = 0; // Set Clockindex for lowest clock speed (F_CPU / 128) + 132c: 10 92 f7 05 sts 0x05F7, r1 + + spi_dord = 0; // Data Order MSB first dord = 0 --> good for all devices + 1330: 10 92 f8 05 sts 0x05F8, r1 + spi_cpol = 0; spi_cpha = 0; // SPI mode=0 good for ethernet. + 1334: 10 92 e5 05 sts 0x05E5, r1 + 1338: 10 92 f6 05 sts 0x05F6, r1 + spi_setup(); // Setup SPI bits and clock speed + 133c: 0e 94 5a 09 call 0x12b4 ; 0x12b4 + +} + 1340: 08 95 ret + +00001342 : +} + +//----------------------------------------------------------------------------- + +void spi_set_clock_index(U08 clock_index) +{ + 1342: 87 30 cpi r24, 0x07 ; 7 + 1344: 08 f0 brcs .+2 ; 0x1348 + 1346: 86 e0 ldi r24, 0x06 ; 6 + if (clock_index > SPI_MAX_CLOCK_INDEX) + { + clock_index = SPI_MAX_CLOCK_INDEX; + } + + spi_clock_index = clock_index; + 1348: 80 93 f7 05 sts 0x05F7, r24 + + spi_setup(); // Setup SPI bits and clock speed + 134c: 0e 94 5a 09 call 0x12b4 ; 0x12b4 +} + 1350: 08 95 ret + +00001352 : +//----------------------------------------------------------------------------- + +void spi_set_dord(U08 dord) +{ + 1352: 81 11 cpse r24, r1 + 1354: 81 e0 ldi r24, 0x01 ; 1 + if (dord > 1) + { + dord = 1; + } + + spi_dord = dord; + 1356: 80 93 f8 05 sts 0x05F8, r24 + + spi_setup(); // Setup SPI bits and clock speed + 135a: 0e 94 5a 09 call 0x12b4 ; 0x12b4 +} + 135e: 08 95 ret + +00001360 : +//----------------------------------------------------------------------------- + +void spi_set_cpol(U08 cpol) +{ + 1360: 81 11 cpse r24, r1 + 1362: 81 e0 ldi r24, 0x01 ; 1 + if (cpol > 1) + { + cpol = 1; + } + + spi_cpol = cpol; + 1364: 80 93 e5 05 sts 0x05E5, r24 + + spi_setup(); // Setup SPI bits and clock speed + 1368: 0e 94 5a 09 call 0x12b4 ; 0x12b4 +} + 136c: 08 95 ret + +0000136e : +//----------------------------------------------------------------------------- + +void spi_set_cpha(U08 cpha) +{ + 136e: 81 11 cpse r24, r1 + 1370: 81 e0 ldi r24, 0x01 ; 1 + if (cpha > 1) + { + cpha = 1; + } + + spi_cpha = cpha; + 1372: 80 93 f6 05 sts 0x05F6, r24 + + spi_setup(); // Setup SPI bits and clock speed + 1376: 0e 94 5a 09 call 0x12b4 ; 0x12b4 +} + 137a: 08 95 ret + +0000137c : +//----------------------------------------------------------------------------- + +U08 spi_transfer_byte(U08 data) +{ + // Start SPI Transfer + if (!(SPCR & (1< + { + } + + // Return result of transfer + return SPDR; + 1386: 8f b1 in r24, 0x0f ; 15 +} + 1388: 08 95 ret + +0000138a : +} + +//----------------------------------------------------------------------------- + +void spi_transfer(U08 bytes, U08 device) +{ + 138a: af 92 push r10 + 138c: bf 92 push r11 + 138e: cf 92 push r12 + 1390: df 92 push r13 + 1392: ef 92 push r14 + 1394: ff 92 push r15 + 1396: 0f 93 push r16 + 1398: 1f 93 push r17 + 139a: cf 93 push r28 + 139c: df 93 push r29 + 139e: c8 2e mov r12, r24 + 13a0: d6 2e mov r13, r22 + 13a2: ee 24 eor r14, r14 + 13a4: ff 24 eor r15, r15 + U08 n; + // Transfer requested bytes + for (n = 0; n < bytes; n++) + { + // Check for active slave select level + if (SPI_DEVICE_ACTIVE_HIGH[device]) + 13a6: 86 2f mov r24, r22 + 13a8: 90 e0 ldi r25, 0x00 ; 0 + 13aa: 2a e9 ldi r18, 0x9A ; 154 + 13ac: a2 2e mov r10, r18 + 13ae: 25 e0 ldi r18, 0x05 ; 5 + 13b0: b2 2e mov r11, r18 + 13b2: a8 0e add r10, r24 + 13b4: b9 1e adc r11, r25 + 13b6: ec 01 movw r28, r24 + 13b8: cb 51 subi r28, 0x1B ; 27 + 13ba: dd 4f sbci r29, 0xFD ; 253 + else + { + if (device == 0) { + PORTB &= ~(1 << SPI_DEVICE_SS[device]); // Set Slave Select low + } else { + PORTD &= ~(1 << SPI_DEVICE_SS[device]); // Set Slave Select low + 13bc: 01 e0 ldi r16, 0x01 ; 1 + 13be: 10 e0 ldi r17, 0x00 ; 0 + 13c0: 7b c0 rjmp .+246 ; 0x14b8 + U08 n; + // Transfer requested bytes + for (n = 0; n < bytes; n++) + { + // Check for active slave select level + if (SPI_DEVICE_ACTIVE_HIGH[device]) + 13c2: f5 01 movw r30, r10 + 13c4: 80 81 ld r24, Z + 13c6: 88 23 and r24, r24 + 13c8: c1 f0 breq .+48 ; 0x13fa + { + if (device == 0) { + 13ca: dd 20 and r13, r13 + 13cc: 59 f4 brne .+22 ; 0x13e4 + PORTB |= (1 << SPI_DEVICE_SS[device]); // Set Slave Select high + 13ce: 28 b3 in r18, 0x18 ; 24 + 13d0: 88 81 ld r24, Y + 13d2: a8 01 movw r20, r16 + 13d4: 02 c0 rjmp .+4 ; 0x13da + 13d6: 44 0f add r20, r20 + 13d8: 55 1f adc r21, r21 + 13da: 8a 95 dec r24 + 13dc: e2 f7 brpl .-8 ; 0x13d6 + 13de: 24 2b or r18, r20 + 13e0: 28 bb out 0x18, r18 ; 24 + 13e2: 26 c0 rjmp .+76 ; 0x1430 + } else { + PORTD |= (1 << SPI_DEVICE_SS[device]); // Set Slave Select high + 13e4: 22 b3 in r18, 0x12 ; 18 + 13e6: 88 81 ld r24, Y + 13e8: f8 01 movw r30, r16 + 13ea: 02 c0 rjmp .+4 ; 0x13f0 + 13ec: ee 0f add r30, r30 + 13ee: ff 1f adc r31, r31 + 13f0: 8a 95 dec r24 + 13f2: e2 f7 brpl .-8 ; 0x13ec + 13f4: 2e 2b or r18, r30 + 13f6: 22 bb out 0x12, r18 ; 18 + 13f8: 1b c0 rjmp .+54 ; 0x1430 + } + } + else + { + if (device == 0) { + 13fa: dd 20 and r13, r13 + 13fc: 69 f4 brne .+26 ; 0x1418 + PORTB &= ~(1 << SPI_DEVICE_SS[device]); // Set Slave Select low + 13fe: 28 b3 in r18, 0x18 ; 24 + 1400: 88 81 ld r24, Y + 1402: a8 01 movw r20, r16 + 1404: 02 c0 rjmp .+4 ; 0x140a + 1406: 44 0f add r20, r20 + 1408: 55 1f adc r21, r21 + 140a: 8a 95 dec r24 + 140c: e2 f7 brpl .-8 ; 0x1406 + 140e: ca 01 movw r24, r20 + 1410: 80 95 com r24 + 1412: 82 23 and r24, r18 + 1414: 88 bb out 0x18, r24 ; 24 + 1416: 0c c0 rjmp .+24 ; 0x1430 + } else { + PORTD &= ~(1 << SPI_DEVICE_SS[device]); // Set Slave Select low + 1418: 22 b3 in r18, 0x12 ; 18 + 141a: 88 81 ld r24, Y + 141c: f8 01 movw r30, r16 + 141e: 02 c0 rjmp .+4 ; 0x1424 + 1420: ee 0f add r30, r30 + 1422: ff 1f adc r31, r31 + 1424: 8a 95 dec r24 + 1426: e2 f7 brpl .-8 ; 0x1420 + 1428: cf 01 movw r24, r30 + 142a: 80 95 com r24 + 142c: 82 23 and r24, r18 + 142e: 82 bb out 0x12, r24 ; 18 + } + } + + + spi_read_buffer[n] = spi_transfer_byte(spi_write_buffer[n]); + 1430: f7 01 movw r30, r14 + 1432: ea 51 subi r30, 0x1A ; 26 + 1434: fa 4f sbci r31, 0xFA ; 250 + 1436: 80 81 ld r24, Z + 1438: 0e 94 be 09 call 0x137c ; 0x137c + 143c: f7 01 movw r30, r14 + 143e: e7 50 subi r30, 0x07 ; 7 + 1440: fa 4f sbci r31, 0xFA ; 250 + 1442: 80 83 st Z, r24 + + + // Check for inactive slave select level + if (SPI_DEVICE_ACTIVE_HIGH[device]) + 1444: f5 01 movw r30, r10 + 1446: 80 81 ld r24, Z + 1448: 88 23 and r24, r24 + 144a: e1 f0 breq .+56 ; 0x1484 + { + if (device == 0) { + 144c: dd 20 and r13, r13 + 144e: 69 f4 brne .+26 ; 0x146a + PORTB &= ~(1 << SPI_DEVICE_SS[device]); // Set Slave Select low + 1450: 28 b3 in r18, 0x18 ; 24 + 1452: 88 81 ld r24, Y + 1454: a8 01 movw r20, r16 + 1456: 02 c0 rjmp .+4 ; 0x145c + 1458: 44 0f add r20, r20 + 145a: 55 1f adc r21, r21 + 145c: 8a 95 dec r24 + 145e: e2 f7 brpl .-8 ; 0x1458 + 1460: ca 01 movw r24, r20 + 1462: 80 95 com r24 + 1464: 82 23 and r24, r18 + 1466: 88 bb out 0x18, r24 ; 24 + 1468: 24 c0 rjmp .+72 ; 0x14b2 + } else { + PORTD &= ~(1 << SPI_DEVICE_SS[device]); // Set Slave Select low + 146a: 22 b3 in r18, 0x12 ; 18 + 146c: 88 81 ld r24, Y + 146e: f8 01 movw r30, r16 + 1470: 02 c0 rjmp .+4 ; 0x1476 + 1472: ee 0f add r30, r30 + 1474: ff 1f adc r31, r31 + 1476: 8a 95 dec r24 + 1478: e2 f7 brpl .-8 ; 0x1472 + 147a: cf 01 movw r24, r30 + 147c: 80 95 com r24 + 147e: 82 23 and r24, r18 + 1480: 82 bb out 0x12, r24 ; 18 + 1482: 17 c0 rjmp .+46 ; 0x14b2 + } + } + else + { + if (device == 0) { + 1484: dd 20 and r13, r13 + 1486: 59 f4 brne .+22 ; 0x149e + PORTB |= (1 << SPI_DEVICE_SS[device]); // Set Slave Select high + 1488: 28 b3 in r18, 0x18 ; 24 + 148a: 88 81 ld r24, Y + 148c: a8 01 movw r20, r16 + 148e: 02 c0 rjmp .+4 ; 0x1494 + 1490: 44 0f add r20, r20 + 1492: 55 1f adc r21, r21 + 1494: 8a 95 dec r24 + 1496: e2 f7 brpl .-8 ; 0x1490 + 1498: 24 2b or r18, r20 + 149a: 28 bb out 0x18, r18 ; 24 + 149c: 0a c0 rjmp .+20 ; 0x14b2 + } else { + PORTD |= (1 << SPI_DEVICE_SS[device]); // Set Slave Select high + 149e: 22 b3 in r18, 0x12 ; 18 + 14a0: 88 81 ld r24, Y + 14a2: f8 01 movw r30, r16 + 14a4: 02 c0 rjmp .+4 ; 0x14aa + 14a6: ee 0f add r30, r30 + 14a8: ff 1f adc r31, r31 + 14aa: 8a 95 dec r24 + 14ac: e2 f7 brpl .-8 ; 0x14a6 + 14ae: 2e 2b or r18, r30 + 14b0: 22 bb out 0x12, r18 ; 18 + 14b2: 08 94 sec + 14b4: e1 1c adc r14, r1 + 14b6: f1 1c adc r15, r1 +#define SPI_M_CS PD4 //device 2 +#define SPI_A_CS PD5 //device 3 +*/ + U08 n; + // Transfer requested bytes + for (n = 0; n < bytes; n++) + 14b8: ec 14 cp r14, r12 + 14ba: 08 f4 brcc .+2 ; 0x14be + 14bc: 82 cf rjmp .-252 ; 0x13c2 + PORTD |= (1 << SPI_DEVICE_SS[device]); // Set Slave Select high + } + } + + } +} + 14be: df 91 pop r29 + 14c0: cf 91 pop r28 + 14c2: 1f 91 pop r17 + 14c4: 0f 91 pop r16 + 14c6: ff 90 pop r15 + 14c8: ef 90 pop r14 + 14ca: df 90 pop r13 + 14cc: cf 90 pop r12 + 14ce: bf 90 pop r11 + 14d0: af 90 pop r10 + 14d2: 08 95 ret + +000014d4 : + return SPDR; +} + +//----------------------------------------------------------------------------- +void spi_transfer_string(U08 length, U08* addr, U08 device) +{ + 14d4: ff 92 push r15 + 14d6: 0f 93 push r16 + 14d8: 1f 93 push r17 + 14da: cf 93 push r28 + 14dc: df 93 push r29 + 14de: f8 2e mov r15, r24 + 14e0: 04 2f mov r16, r20 +#define SPI_A_CS PD5 //device 3 +*/ + U08 n; + + // I assume the CS line is in "not enable"-state; + if ( device == 0 ){ + 14e2: 44 23 and r20, r20 + 14e4: 79 f4 brne .+30 ; 0x1504 + TGL_BIT(PORTB, SPI_DEVICE_SS[device]); // I toggle the line + 14e6: 88 b3 in r24, 0x18 ; 24 + 14e8: 90 91 e5 02 lds r25, 0x02E5 + 14ec: 21 e0 ldi r18, 0x01 ; 1 + 14ee: 30 e0 ldi r19, 0x00 ; 0 + 14f0: 02 c0 rjmp .+4 ; 0x14f6 + 14f2: 22 0f add r18, r18 + 14f4: 33 1f adc r19, r19 + 14f6: 9a 95 dec r25 + 14f8: e2 f7 brpl .-8 ; 0x14f2 + 14fa: 82 27 eor r24, r18 + 14fc: 88 bb out 0x18, r24 ; 24 + 14fe: eb 01 movw r28, r22 + 1500: 10 e0 ldi r17, 0x00 ; 0 + 1502: 14 c0 rjmp .+40 ; 0x152c + } else { + TGL_BIT(PORTD, SPI_DEVICE_SS[device]); // I toggle the line + 1504: 22 b3 in r18, 0x12 ; 18 + 1506: e4 2f mov r30, r20 + 1508: f0 e0 ldi r31, 0x00 ; 0 + 150a: eb 51 subi r30, 0x1B ; 27 + 150c: fd 4f sbci r31, 0xFD ; 253 + 150e: 30 81 ld r19, Z + 1510: 81 e0 ldi r24, 0x01 ; 1 + 1512: 90 e0 ldi r25, 0x00 ; 0 + 1514: 02 c0 rjmp .+4 ; 0x151a + 1516: 88 0f add r24, r24 + 1518: 99 1f adc r25, r25 + 151a: 3a 95 dec r19 + 151c: e2 f7 brpl .-8 ; 0x1516 + 151e: 28 27 eor r18, r24 + 1520: 22 bb out 0x12, r18 ; 18 + 1522: ed cf rjmp .-38 ; 0x14fe + + + // Transfer requested bytes + for (n = 0; n < length; n++) + { + spi_transfer_byte(addr[n]); + 1524: 89 91 ld r24, Y+ + 1526: 0e 94 be 09 call 0x137c ; 0x137c + } + // now the line is in "enable"-state + + + // Transfer requested bytes + for (n = 0; n < length; n++) + 152a: 1f 5f subi r17, 0xFF ; 255 + 152c: 1f 15 cp r17, r15 + 152e: d0 f3 brcs .-12 ; 0x1524 + { + spi_transfer_byte(addr[n]); + } + + if ( device == 0 ){ + 1530: 00 23 and r16, r16 + 1532: 69 f4 brne .+26 ; 0x154e + TGL_BIT(PORTB, SPI_DEVICE_SS[device]); // I toggle the line + 1534: 88 b3 in r24, 0x18 ; 24 + 1536: 90 91 e5 02 lds r25, 0x02E5 + 153a: 21 e0 ldi r18, 0x01 ; 1 + 153c: 30 e0 ldi r19, 0x00 ; 0 + 153e: 02 c0 rjmp .+4 ; 0x1544 + 1540: 22 0f add r18, r18 + 1542: 33 1f adc r19, r19 + 1544: 9a 95 dec r25 + 1546: e2 f7 brpl .-8 ; 0x1540 + 1548: 82 27 eor r24, r18 + 154a: 88 bb out 0x18, r24 ; 24 + 154c: 0f c0 rjmp .+30 ; 0x156c + } else { + TGL_BIT(PORTD, SPI_DEVICE_SS[device]); // I toggle the line + 154e: 22 b3 in r18, 0x12 ; 18 + 1550: e0 2f mov r30, r16 + 1552: f0 e0 ldi r31, 0x00 ; 0 + 1554: eb 51 subi r30, 0x1B ; 27 + 1556: fd 4f sbci r31, 0xFD ; 253 + 1558: 30 81 ld r19, Z + 155a: 81 e0 ldi r24, 0x01 ; 1 + 155c: 90 e0 ldi r25, 0x00 ; 0 + 155e: 02 c0 rjmp .+4 ; 0x1564 + 1560: 88 0f add r24, r24 + 1562: 99 1f adc r25, r25 + 1564: 3a 95 dec r19 + 1566: e2 f7 brpl .-8 ; 0x1560 + 1568: 28 27 eor r18, r24 + 156a: 22 bb out 0x12, r18 ; 18 + } + +} + 156c: df 91 pop r29 + 156e: cf 91 pop r28 + 1570: 1f 91 pop r17 + 1572: 0f 91 pop r16 + 1574: ff 90 pop r15 + 1576: 08 95 ret + +00001578 : +#endif +//----------------------------------------------------------------------------- + +void usart_init(void) +{ + USART_SET_BAUDRATE(USART_BAUDRATE); + 1578: 10 bc out 0x20, r1 ; 32 + 157a: 83 e3 ldi r24, 0x33 ; 51 + 157c: 89 b9 out 0x09, r24 ; 9 + + UCSRA = 0x00; + 157e: 1b b8 out 0x0b, r1 ; 11 + + UCSRB = 0x00; // Disable receiver and transmitter and interrupts + 1580: 1a b8 out 0x0a, r1 ; 10 + +#ifdef USART_USE_RX + UCSRB |= (1 << RXEN); // Turn on receiver + 1582: 54 9a sbi 0x0a, 4 ; 10 + DDRD &= ~(1<: +//----------------------------------------------------------------------------- + +void usart_write_char(U08 data) +{ + while (!(UCSRA & (1 << UDRE))) ; // Wait until tx register is empty + 1592: 5d 9b sbis 0x0b, 5 ; 11 + 1594: fe cf rjmp .-4 ; 0x1592 + UDR = data; + 1596: 8c b9 out 0x0c, r24 ; 12 +// usart_tx_buffer[usart_tx_buffer_index] = data; +// ++usart_tx_buffer_index; +// } else { +// usart_tx_buffer_overflow = true; +// } +} + 1598: 08 95 ret + +0000159a : +} +//----------------------------------------------------------------------------- + +void usart_write_char(U08 data) +{ + while (!(UCSRA & (1 << UDRE))) ; // Wait until tx register is empty + 159a: 5d 9b sbis 0x0b, 5 ; 11 + 159c: fe cf rjmp .-4 ; 0x159a + UDR = data; + 159e: 8d e0 ldi r24, 0x0D ; 13 + 15a0: 8c b9 out 0x0c, r24 ; 12 +} +//----------------------------------------------------------------------------- + +void usart_write_char(U08 data) +{ + while (!(UCSRA & (1 << UDRE))) ; // Wait until tx register is empty + 15a2: 5d 9b sbis 0x0b, 5 ; 11 + 15a4: fe cf rjmp .-4 ; 0x15a2 + UDR = data; + 15a6: 8a e0 ldi r24, 0x0A ; 10 + 15a8: 8c b9 out 0x0c, r24 ; 12 + +void usart_write_crlf(void) +{ + usart_write_char(USART_CHAR_CR); + usart_write_char(USART_CHAR_LF); +} + 15aa: 08 95 ret + +000015ac : +//----------------------------------------------------------------------------- + +void usart_write_str(pU08 str) +{ + 15ac: fc 01 movw r30, r24 + 15ae: 04 c0 rjmp .+8 ; 0x15b8 +} +//----------------------------------------------------------------------------- + +void usart_write_char(U08 data) +{ + while (!(UCSRA & (1 << UDRE))) ; // Wait until tx register is empty + 15b0: 5d 9b sbis 0x0b, 5 ; 11 + 15b2: fe cf rjmp .-4 ; 0x15b0 + +void usart_write_str(pU08 str) +{ + while (*str) + { + usart_write_char(*str++); + 15b4: 31 96 adiw r30, 0x01 ; 1 +//----------------------------------------------------------------------------- + +void usart_write_char(U08 data) +{ + while (!(UCSRA & (1 << UDRE))) ; // Wait until tx register is empty + UDR = data; + 15b6: 8c b9 out 0x0c, r24 ; 12 +} +//----------------------------------------------------------------------------- + +void usart_write_str(pU08 str) +{ + while (*str) + 15b8: 80 81 ld r24, Z + 15ba: 88 23 and r24, r24 + 15bc: c9 f7 brne .-14 ; 0x15b0 + { + usart_write_char(*str++); + } +} + 15be: 08 95 ret + +000015c0 : +//----------------------------------------------------------------------------- + +void usart_write_flash_str(fpU08 str) +{ + 15c0: fc 01 movw r30, r24 + 15c2: 04 c0 rjmp .+8 ; 0x15cc +} +//----------------------------------------------------------------------------- + +void usart_write_char(U08 data) +{ + while (!(UCSRA & (1 << UDRE))) ; // Wait until tx register is empty + 15c4: 5d 9b sbis 0x0b, 5 ; 11 + 15c6: fe cf rjmp .-4 ; 0x15c4 + +void usart_write_flash_str(fpU08 str) +{ + while (*str) + { + usart_write_char(*str++); + 15c8: 31 96 adiw r30, 0x01 ; 1 +//----------------------------------------------------------------------------- + +void usart_write_char(U08 data) +{ + while (!(UCSRA & (1 << UDRE))) ; // Wait until tx register is empty + UDR = data; + 15ca: 8c b9 out 0x0c, r24 ; 12 +} +//----------------------------------------------------------------------------- + +void usart_write_flash_str(fpU08 str) +{ + while (*str) + 15cc: 80 81 ld r24, Z + 15ce: 88 23 and r24, r24 + 15d0: c9 f7 brne .-14 ; 0x15c4 + { + usart_write_char(*str++); + } +} + 15d2: 08 95 ret + +000015d4 : +//----------------------------------------------------------------------------- + +void usart_writeln_flash_str(fpU08 str) +{ + 15d4: fc 01 movw r30, r24 + 15d6: 04 c0 rjmp .+8 ; 0x15e0 +} +//----------------------------------------------------------------------------- + +void usart_write_char(U08 data) +{ + while (!(UCSRA & (1 << UDRE))) ; // Wait until tx register is empty + 15d8: 5d 9b sbis 0x0b, 5 ; 11 + 15da: fe cf rjmp .-4 ; 0x15d8 + +void usart_writeln_flash_str(fpU08 str) +{ + while (*str) + { + usart_write_char(*str++); + 15dc: 31 96 adiw r30, 0x01 ; 1 +//----------------------------------------------------------------------------- + +void usart_write_char(U08 data) +{ + while (!(UCSRA & (1 << UDRE))) ; // Wait until tx register is empty + UDR = data; + 15de: 8c b9 out 0x0c, r24 ; 12 +} +//----------------------------------------------------------------------------- + +void usart_writeln_flash_str(fpU08 str) +{ + while (*str) + 15e0: 80 81 ld r24, Z + 15e2: 88 23 and r24, r24 + 15e4: c9 f7 brne .-14 ; 0x15d8 +} +//----------------------------------------------------------------------------- + +void usart_write_char(U08 data) +{ + while (!(UCSRA & (1 << UDRE))) ; // Wait until tx register is empty + 15e6: 5d 9b sbis 0x0b, 5 ; 11 + 15e8: fe cf rjmp .-4 ; 0x15e6 + UDR = data; + 15ea: 8d e0 ldi r24, 0x0D ; 13 + 15ec: 8c b9 out 0x0c, r24 ; 12 +} +//----------------------------------------------------------------------------- + +void usart_write_char(U08 data) +{ + while (!(UCSRA & (1 << UDRE))) ; // Wait until tx register is empty + 15ee: 5d 9b sbis 0x0b, 5 ; 11 + 15f0: fe cf rjmp .-4 ; 0x15ee + UDR = data; + 15f2: 8a e0 ldi r24, 0x0A ; 10 + 15f4: 8c b9 out 0x0c, r24 ; 12 + usart_write_char(*str++); + } + + usart_write_char(USART_CHAR_CR); + usart_write_char(USART_CHAR_LF); +} + 15f6: 08 95 ret + +000015f8 : +//----------------------------------------------------------------------------- + +void usart_writeln_str(pU08 str) +{ + usart_write_str(str); + 15f8: 0e 94 d6 0a call 0x15ac ; 0x15ac +} +//----------------------------------------------------------------------------- + +void usart_write_char(U08 data) +{ + while (!(UCSRA & (1 << UDRE))) ; // Wait until tx register is empty + 15fc: 5d 9b sbis 0x0b, 5 ; 11 + 15fe: fe cf rjmp .-4 ; 0x15fc + UDR = data; + 1600: 8d e0 ldi r24, 0x0D ; 13 + 1602: 8c b9 out 0x0c, r24 ; 12 +} +//----------------------------------------------------------------------------- + +void usart_write_char(U08 data) +{ + while (!(UCSRA & (1 << UDRE))) ; // Wait until tx register is empty + 1604: 5d 9b sbis 0x0b, 5 ; 11 + 1606: fe cf rjmp .-4 ; 0x1604 + UDR = data; + 1608: 8a e0 ldi r24, 0x0A ; 10 + 160a: 8c b9 out 0x0c, r24 ; 12 +void usart_writeln_str(pU08 str) +{ + usart_write_str(str); + usart_write_char(USART_CHAR_CR); + usart_write_char(USART_CHAR_LF); +} + 160c: 08 95 ret + +0000160e <__vector_13>: +//----------------------------------------------------------------------------- + +#ifdef USART_USE_RX_IRQ + +ISR(SIG_USART_RECV) +{ + 160e: 1f 92 push r1 + 1610: 0f 92 push r0 + 1612: 0f b6 in r0, 0x3f ; 63 + 1614: 0f 92 push r0 + 1616: 11 24 eor r1, r1 + 1618: 8f 93 push r24 + 161a: 9f 93 push r25 + 161c: ef 93 push r30 + 161e: ff 93 push r31 + usart_receive_char = UDR; + 1620: 9c b1 in r25, 0x0c ; 12 + 1622: 90 93 a1 05 sts 0x05A1, r25 + + if (usart_rx_ready) // Exit if ready flag is still set + 1626: 80 91 9e 05 lds r24, 0x059E + 162a: 88 23 and r24, r24 + 162c: a9 f5 brne .+106 ; 0x1698 <__vector_13+0x8a> + { + return; + } + + // If CR received, then set ready flag + if (usart_receive_char == USART_CHAR_CR) + 162e: 9d 30 cpi r25, 0x0D ; 13 + 1630: 89 f4 brne .+34 ; 0x1654 <__vector_13+0x46> + { + usart_rx_buffer[usart_rx_buffer_index] = 0; // Terminate input string + 1632: 80 91 9f 05 lds r24, 0x059F + 1636: e8 2f mov r30, r24 + 1638: f0 e0 ldi r31, 0x00 ; 0 + 163a: e6 5f subi r30, 0xF6 ; 246 + 163c: f9 4f sbci r31, 0xF9 ; 249 + 163e: 10 82 st Z, r1 + usart_received_chars = usart_rx_buffer_index; + 1640: 80 93 09 06 sts 0x0609, r24 + usart_rx_buffer_index = 0; + 1644: 10 92 9f 05 sts 0x059F, r1 + usart_receive_suspended = false; + 1648: 10 92 a0 05 sts 0x05A0, r1 + usart_rx_ready = TRUE; + 164c: 81 e0 ldi r24, 0x01 ; 1 + 164e: 80 93 9e 05 sts 0x059E, r24 + 1652: 22 c0 rjmp .+68 ; 0x1698 <__vector_13+0x8a> + return; + } + + // Ignore all characters till next CR + if (usart_receive_suspended) + 1654: 80 91 a0 05 lds r24, 0x05A0 + 1658: 88 23 and r24, r24 + 165a: f1 f4 brne .+60 ; 0x1698 <__vector_13+0x8a> + { + return; + } + + // Check for underscore or comment + if (usart_receive_char == '_' || usart_receive_char == ';') + 165c: 9f 35 cpi r25, 0x5F ; 95 + 165e: 11 f0 breq .+4 ; 0x1664 <__vector_13+0x56> + 1660: 9b 33 cpi r25, 0x3B ; 59 + 1662: 21 f4 brne .+8 ; 0x166c <__vector_13+0x5e> + { + usart_receive_suspended = true; + 1664: 81 e0 ldi r24, 0x01 ; 1 + 1666: 80 93 a0 05 sts 0x05A0, r24 + 166a: 16 c0 rjmp .+44 ; 0x1698 <__vector_13+0x8a> + + return; + } + + // If Backspace received, then delete last character + if (usart_receive_char == USART_CHAR_BS && usart_rx_buffer_index) + 166c: 98 30 cpi r25, 0x08 ; 8 + 166e: 31 f4 brne .+12 ; 0x167c <__vector_13+0x6e> + 1670: 80 91 9f 05 lds r24, 0x059F + 1674: 88 23 and r24, r24 + 1676: 81 f0 breq .+32 ; 0x1698 <__vector_13+0x8a> + { + usart_rx_buffer_index--; + 1678: 81 50 subi r24, 0x01 ; 1 + 167a: 0c c0 rjmp .+24 ; 0x1694 <__vector_13+0x86> + + return; + } + + // Ignore invalid characters + if (usart_receive_char < USART_CHAR_SPC) + 167c: 90 32 cpi r25, 0x20 ; 32 + 167e: 60 f0 brcs .+24 ; 0x1698 <__vector_13+0x8a> + { + usart_receive_char -= 32; + } +#endif + + if (usart_rx_buffer_index < USART_RX_BUFFER_SIZE - 1) // Store character + 1680: 80 91 9f 05 lds r24, 0x059F + 1684: 8f 31 cpi r24, 0x1F ; 31 + 1686: 40 f4 brcc .+16 ; 0x1698 <__vector_13+0x8a> + { + usart_rx_buffer[usart_rx_buffer_index++] = usart_receive_char; + 1688: e8 2f mov r30, r24 + 168a: f0 e0 ldi r31, 0x00 ; 0 + 168c: e6 5f subi r30, 0xF6 ; 246 + 168e: f9 4f sbci r31, 0xF9 ; 249 + 1690: 90 83 st Z, r25 + 1692: 8f 5f subi r24, 0xFF ; 255 + 1694: 80 93 9f 05 sts 0x059F, r24 + //usart_writeln_str(usart_rx_buffer); + //usart_write_char(usart_rx_buffer[1,2]); + //usart_write_char(usart_rx_buffer[usart_rx_buffer_index]); + //usart_writeln_flash_str(*usart_rx_buffer); + //usart_write_char(usart_rx_buffer); +} + 1698: ff 91 pop r31 + 169a: ef 91 pop r30 + 169c: 9f 91 pop r25 + 169e: 8f 91 pop r24 + 16a0: 0f 90 pop r0 + 16a2: 0f be out 0x3f, r0 ; 63 + 16a4: 0f 90 pop r0 + 16a6: 1f 90 pop r1 + 16a8: 18 95 reti + +000016aa : +} +//----------------------------------------------------------------------------- + +void usart_write_float(float value,U08 decimals,U08 digits) +{ + usart_write_str(nc_float_to_str(value,decimals,digits)); + 16aa: 0e 94 4b 0c call 0x1896 ; 0x1896 + 16ae: 0e 94 d6 0a call 0x15ac ; 0x15ac +} + 16b2: 08 95 ret + +000016b4 : +} +//----------------------------------------------------------------------------- + +void usart_write_U32_hex(U32 value) +{ + usart_write_str(nc_U32_to_hex(value)); + 16b4: 0e 94 e4 0b call 0x17c8 ; 0x17c8 + 16b8: 0e 94 d6 0a call 0x15ac ; 0x15ac +} + 16bc: 08 95 ret + +000016be : +} +//----------------------------------------------------------------------------- + +void usart_write_S32(S32 value,U08 digits) +{ + usart_write_str(nc_S32_to_str(value,digits)); + 16be: 0e 94 42 0d call 0x1a84 ; 0x1a84 + 16c2: 0e 94 d6 0a call 0x15ac ; 0x15ac +} + 16c6: 08 95 ret + +000016c8 : +} +//----------------------------------------------------------------------------- + +void usart_write_U32(U32 value,U08 digits) +{ + usart_write_str(nc_U32_to_str(value,digits)); + 16c8: 0e 94 5f 0e call 0x1cbe ; 0x1cbe + 16cc: 0e 94 d6 0a call 0x15ac ; 0x15ac +} + 16d0: 08 95 ret + +000016d2 : +} +//----------------------------------------------------------------------------- + +void usart_write_U16_hex(U16 value) +{ + usart_write_str(nc_U16_to_hex(value)); + 16d2: 0e 94 be 0b call 0x177c ; 0x177c + 16d6: 0e 94 d6 0a call 0x15ac ; 0x15ac +} + 16da: 08 95 ret + +000016dc : +} +//----------------------------------------------------------------------------- + +void usart_write_S16(S16 value,U08 digits) +{ + usart_write_str(nc_S16_to_str(value,digits)); + 16dc: 0e 94 7b 0f call 0x1ef6 ; 0x1ef6 + 16e0: 0e 94 d6 0a call 0x15ac ; 0x15ac +} + 16e4: 08 95 ret + +000016e6 : +} +//----------------------------------------------------------------------------- + +void usart_write_U16(U16 value,U08 digits) +{ + usart_write_str(nc_U16_to_str(value,digits)); + 16e6: 0e 94 de 0f call 0x1fbc ; 0x1fbc + 16ea: 0e 94 d6 0a call 0x15ac ; 0x15ac +} + 16ee: 08 95 ret + +000016f0 : +} +//----------------------------------------------------------------------------- + +void usart_write_U08_bin(U08 value) +{ + usart_write_str(nc_U08_to_bin(value)); + 16f0: 0e 94 a2 0b call 0x1744 ; 0x1744 + 16f4: 0e 94 d6 0a call 0x15ac ; 0x15ac +} + 16f8: 08 95 ret + +000016fa : +} +//----------------------------------------------------------------------------- + +void usart_write_U08_hex(U08 value) +{ + usart_write_str(nc_U08_to_hex(value)); + 16fa: 0e 94 8c 0b call 0x1718 ; 0x1718 + 16fe: 0e 94 d6 0a call 0x15ac ; 0x15ac +} + 1702: 08 95 ret + +00001704 : +} +//----------------------------------------------------------------------------- + +void usart_write_S08(S08 value,U08 digits) +{ + usart_write_str(nc_S08_to_str(value,digits)); + 1704: 0e 94 3a 10 call 0x2074 ; 0x2074 + 1708: 0e 94 d6 0a call 0x15ac ; 0x15ac +} + 170c: 08 95 ret + +0000170e : +} +//----------------------------------------------------------------------------- + +void usart_write_U08(U08 value,U08 digits) +{ + usart_write_str(nc_U08_to_str(value,digits)); + 170e: 0e 94 78 10 call 0x20f0 ; 0x20f0 + 1712: 0e 94 d6 0a call 0x15ac ; 0x15ac +} + 1716: 08 95 ret + +00001718 : + +pU08 nc_U08_to_hex(U08 value) +{ + pU08 pstr = nc_buffer; + + *pstr++ = NC_HEX_ARRAY[value >> 4]; + 1718: 98 2f mov r25, r24 + 171a: 92 95 swap r25 + 171c: 9f 70 andi r25, 0x0F ; 15 + 171e: a9 ee ldi r26, 0xE9 ; 233 + 1720: b2 e0 ldi r27, 0x02 ; 2 + 1722: fd 01 movw r30, r26 + 1724: e9 0f add r30, r25 + 1726: f1 1d adc r31, r1 + 1728: 90 81 ld r25, Z + 172a: 90 93 2a 06 sts 0x062A, r25 + *pstr++ = NC_HEX_ARRAY[value & 0x0F]; + 172e: 8f 70 andi r24, 0x0F ; 15 + 1730: a8 0f add r26, r24 + 1732: b1 1d adc r27, r1 + 1734: 8c 91 ld r24, X + 1736: 80 93 2b 06 sts 0x062B, r24 + *pstr = 0; + 173a: 10 92 2c 06 sts 0x062C, r1 + + return (nc_buffer); +} + 173e: 8a e2 ldi r24, 0x2A ; 42 + 1740: 96 e0 ldi r25, 0x06 ; 6 + 1742: 08 95 ret + +00001744 : +//----------------------------------------------------------------------------- + +pU08 nc_U08_to_bin(U08 value) +{ + 1744: ea e2 ldi r30, 0x2A ; 42 + 1746: f6 e0 ldi r31, 0x06 ; 6 + 1748: 27 e0 ldi r18, 0x07 ; 7 + pU08 pstr = nc_buffer; + U08 n; + + for (n = 7; n < 8; n--) + { + if (value & (1 << n)) + 174a: 48 2f mov r20, r24 + 174c: 50 e0 ldi r21, 0x00 ; 0 + { + *pstr++ = '1'; + } + else + { + *pstr++ = '0'; + 174e: 60 e3 ldi r22, 0x30 ; 48 + + for (n = 7; n < 8; n--) + { + if (value & (1 << n)) + { + *pstr++ = '1'; + 1750: 31 e3 ldi r19, 0x31 ; 49 + pU08 pstr = nc_buffer; + U08 n; + + for (n = 7; n < 8; n--) + { + if (value & (1 << n)) + 1752: ca 01 movw r24, r20 + 1754: 02 2e mov r0, r18 + 1756: 02 c0 rjmp .+4 ; 0x175c + 1758: 95 95 asr r25 + 175a: 87 95 ror r24 + 175c: 0a 94 dec r0 + 175e: e2 f7 brpl .-8 ; 0x1758 + 1760: df 01 movw r26, r30 + 1762: 11 96 adiw r26, 0x01 ; 1 + 1764: 80 ff sbrs r24, 0 + 1766: 02 c0 rjmp .+4 ; 0x176c + { + *pstr++ = '1'; + 1768: 30 83 st Z, r19 + 176a: 01 c0 rjmp .+2 ; 0x176e + } + else + { + *pstr++ = '0'; + 176c: 60 83 st Z, r22 + 176e: fd 01 movw r30, r26 +pU08 nc_U08_to_bin(U08 value) +{ + pU08 pstr = nc_buffer; + U08 n; + + for (n = 7; n < 8; n--) + 1770: 21 50 subi r18, 0x01 ; 1 + 1772: 78 f7 brcc .-34 ; 0x1752 + { + *pstr++ = '0'; + } + } + + *pstr = 0; + 1774: 1c 92 st X, r1 + + return (nc_buffer); +} + 1776: 8a e2 ldi r24, 0x2A ; 42 + 1778: 96 e0 ldi r25, 0x06 ; 6 + 177a: 08 95 ret + +0000177c : + pU08 pstr = nc_buffer; + tMEM16 data; + + data.word = value; + + *pstr++ = NC_HEX_ARRAY[(data.byte[1]) >> 4]; + 177c: 29 2f mov r18, r25 + 177e: 22 95 swap r18 + 1780: 2f 70 andi r18, 0x0F ; 15 + 1782: a9 ee ldi r26, 0xE9 ; 233 + 1784: b2 e0 ldi r27, 0x02 ; 2 + 1786: fd 01 movw r30, r26 + 1788: e2 0f add r30, r18 + 178a: f1 1d adc r31, r1 + 178c: 20 81 ld r18, Z + 178e: 20 93 2a 06 sts 0x062A, r18 + *pstr++ = NC_HEX_ARRAY[(data.byte[1]) & 0x0F]; + 1792: 9f 70 andi r25, 0x0F ; 15 + 1794: fd 01 movw r30, r26 + 1796: e9 0f add r30, r25 + 1798: f1 1d adc r31, r1 + 179a: 90 81 ld r25, Z + 179c: 90 93 2b 06 sts 0x062B, r25 + + *pstr++ = NC_HEX_ARRAY[(data.byte[0]) >> 4]; + 17a0: 98 2f mov r25, r24 + 17a2: 92 95 swap r25 + 17a4: 9f 70 andi r25, 0x0F ; 15 + 17a6: fd 01 movw r30, r26 + 17a8: e9 0f add r30, r25 + 17aa: f1 1d adc r31, r1 + 17ac: 90 81 ld r25, Z + 17ae: 90 93 2c 06 sts 0x062C, r25 + *pstr++ = NC_HEX_ARRAY[(data.byte[0]) & 0x0F]; + 17b2: 8f 70 andi r24, 0x0F ; 15 + 17b4: a8 0f add r26, r24 + 17b6: b1 1d adc r27, r1 + 17b8: 8c 91 ld r24, X + 17ba: 80 93 2d 06 sts 0x062D, r24 + + *pstr = 0; + 17be: 10 92 2e 06 sts 0x062E, r1 + + return (nc_buffer); +} + 17c2: 8a e2 ldi r24, 0x2A ; 42 + 17c4: 96 e0 ldi r25, 0x06 ; 6 + 17c6: 08 95 ret + +000017c8 : + pU08 pstr = nc_buffer; + tMEM32 data; + + data.dword = value; + + *pstr++ = NC_HEX_ARRAY[(data.byte[3]) >> 4]; + 17c8: 29 2f mov r18, r25 + 17ca: 22 95 swap r18 + 17cc: 2f 70 andi r18, 0x0F ; 15 + 17ce: a9 ee ldi r26, 0xE9 ; 233 + 17d0: b2 e0 ldi r27, 0x02 ; 2 + 17d2: fd 01 movw r30, r26 + 17d4: e2 0f add r30, r18 + 17d6: f1 1d adc r31, r1 + 17d8: 20 81 ld r18, Z + 17da: 20 93 2a 06 sts 0x062A, r18 + *pstr++ = NC_HEX_ARRAY[(data.byte[3]) & 0x0F]; + 17de: 9f 70 andi r25, 0x0F ; 15 + 17e0: fd 01 movw r30, r26 + 17e2: e9 0f add r30, r25 + 17e4: f1 1d adc r31, r1 + 17e6: 90 81 ld r25, Z + 17e8: 90 93 2b 06 sts 0x062B, r25 + + *pstr++ = NC_HEX_ARRAY[(data.byte[2]) >> 4]; + 17ec: 98 2f mov r25, r24 + 17ee: 92 95 swap r25 + 17f0: 9f 70 andi r25, 0x0F ; 15 + 17f2: fd 01 movw r30, r26 + 17f4: e9 0f add r30, r25 + 17f6: f1 1d adc r31, r1 + 17f8: 90 81 ld r25, Z + 17fa: 90 93 2c 06 sts 0x062C, r25 + *pstr++ = NC_HEX_ARRAY[(data.byte[2]) & 0x0F]; + 17fe: 8f 70 andi r24, 0x0F ; 15 + 1800: fd 01 movw r30, r26 + 1802: e8 0f add r30, r24 + 1804: f1 1d adc r31, r1 + 1806: 80 81 ld r24, Z + 1808: 80 93 2d 06 sts 0x062D, r24 + + *pstr++ = NC_HEX_ARRAY[(data.byte[1]) >> 4]; + 180c: 87 2f mov r24, r23 + 180e: 82 95 swap r24 + 1810: 8f 70 andi r24, 0x0F ; 15 + 1812: fd 01 movw r30, r26 + 1814: e8 0f add r30, r24 + 1816: f1 1d adc r31, r1 + 1818: 80 81 ld r24, Z + 181a: 80 93 2e 06 sts 0x062E, r24 + *pstr++ = NC_HEX_ARRAY[(data.byte[1]) & 0x0F]; + 181e: 7f 70 andi r23, 0x0F ; 15 + 1820: fd 01 movw r30, r26 + 1822: e7 0f add r30, r23 + 1824: f1 1d adc r31, r1 + 1826: 80 81 ld r24, Z + 1828: 80 93 2f 06 sts 0x062F, r24 + + *pstr++ = NC_HEX_ARRAY[(data.byte[0]) >> 4]; + 182c: 86 2f mov r24, r22 + 182e: 82 95 swap r24 + 1830: 8f 70 andi r24, 0x0F ; 15 + 1832: fd 01 movw r30, r26 + 1834: e8 0f add r30, r24 + 1836: f1 1d adc r31, r1 + 1838: 80 81 ld r24, Z + 183a: 80 93 30 06 sts 0x0630, r24 + *pstr++ = NC_HEX_ARRAY[(data.byte[0]) & 0x0F]; + 183e: 6f 70 andi r22, 0x0F ; 15 + 1840: a6 0f add r26, r22 + 1842: b1 1d adc r27, r1 + 1844: 8c 91 ld r24, X + 1846: 80 93 31 06 sts 0x0631, r24 + + *pstr = 0; + 184a: 10 92 32 06 sts 0x0632, r1 + + return (nc_buffer); +} + 184e: 8a e2 ldi r24, 0x2A ; 42 + 1850: 96 e0 ldi r25, 0x06 ; 6 + 1852: 08 95 ret + +00001854 : +static U08 nc_int_digits[8]; +static U08 nc_dec_digits[6]; +//----------------------------------------------------------------------------- + +pU08 nc_format(pU08 source_ptr,U08 digits) +{ + 1854: cf 93 push r28 + 1856: df 93 push r29 + 1858: ec 01 movw r28, r24 + U08 len = strlen((const char *)source_ptr); + 185a: fc 01 movw r30, r24 + 185c: 01 90 ld r0, Z+ + 185e: 00 20 and r0, r0 + 1860: e9 f7 brne .-6 ; 0x185c + 1862: 31 97 sbiw r30, 0x01 ; 1 + 1864: e8 1b sub r30, r24 + 1866: aa e3 ldi r26, 0x3A ; 58 + 1868: b6 e0 ldi r27, 0x06 ; 6 + pU08 dest_ptr = (pU08)&nc_format_buffer; + + // Fillup loop + while (digits-- > len) + { + *dest_ptr++ = NC_FILL_CHAR; + 186a: 80 e2 ldi r24, 0x20 ; 32 + 186c: 02 c0 rjmp .+4 ; 0x1872 + 186e: 8d 93 st X+, r24 + 1870: 61 50 subi r22, 0x01 ; 1 +{ + U08 len = strlen((const char *)source_ptr); + pU08 dest_ptr = (pU08)&nc_format_buffer; + + // Fillup loop + while (digits-- > len) + 1872: e6 17 cp r30, r22 + 1874: e0 f3 brcs .-8 ; 0x186e + { + *dest_ptr++ = NC_FILL_CHAR; + } + + // Copy loop + while (len--) + 1876: cd 01 movw r24, r26 + 1878: 8e 0f add r24, r30 + 187a: 91 1d adc r25, r1 + 187c: fc 01 movw r30, r24 + 187e: 02 c0 rjmp .+4 ; 0x1884 + { + *dest_ptr++ = *source_ptr++; + 1880: 89 91 ld r24, Y+ + 1882: 8d 93 st X+, r24 + { + *dest_ptr++ = NC_FILL_CHAR; + } + + // Copy loop + while (len--) + 1884: ae 17 cp r26, r30 + 1886: bf 07 cpc r27, r31 + 1888: d9 f7 brne .-10 ; 0x1880 + { + *dest_ptr++ = *source_ptr++; + } + + *dest_ptr = 0; // Terminate format string + 188a: 1c 92 st X, r1 + + return (pU08)&nc_format_buffer; +} + 188c: 8a e3 ldi r24, 0x3A ; 58 + 188e: 96 e0 ldi r25, 0x06 ; 6 + 1890: df 91 pop r29 + 1892: cf 91 pop r28 + 1894: 08 95 ret + +00001896 : + return (nc_buffer); +} +//----------------------------------------------------------------------------- + +pU08 nc_float_to_str(float value,U08 decimals,U08 digits) +{ + 1896: 2f 92 push r2 + 1898: 3f 92 push r3 + 189a: 4f 92 push r4 + 189c: 5f 92 push r5 + 189e: 6f 92 push r6 + 18a0: 7f 92 push r7 + 18a2: 8f 92 push r8 + 18a4: 9f 92 push r9 + 18a6: af 92 push r10 + 18a8: bf 92 push r11 + 18aa: cf 92 push r12 + 18ac: df 92 push r13 + 18ae: ef 92 push r14 + 18b0: ff 92 push r15 + 18b2: 0f 93 push r16 + 18b4: 1f 93 push r17 + 18b6: df 93 push r29 + 18b8: cf 93 push r28 + 18ba: 0f 92 push r0 + 18bc: cd b7 in r28, 0x3d ; 61 + 18be: de b7 in r29, 0x3e ; 62 + 18c0: 3b 01 movw r6, r22 + 18c2: 4c 01 movw r8, r24 + 18c4: 29 83 std Y+1, r18 ; 0x01 + 18c6: 24 2e mov r2, r20 + 18c8: 85 e0 ldi r24, 0x05 ; 5 + 18ca: 84 17 cp r24, r20 + 18cc: 10 f4 brcc .+4 ; 0x18d2 + 18ce: 35 e0 ldi r19, 0x05 ; 5 + 18d0: 23 2e mov r2, r19 + if (decimals > 5) + { + decimals = 5; + } + + if (value < 0.0) + 18d2: c4 01 movw r24, r8 + 18d4: b3 01 movw r22, r6 + 18d6: 20 e0 ldi r18, 0x00 ; 0 + 18d8: 30 e0 ldi r19, 0x00 ; 0 + 18da: 40 e0 ldi r20, 0x00 ; 0 + 18dc: 50 e0 ldi r21, 0x00 ; 0 + 18de: 0e 94 8a 16 call 0x2d14 ; 0x2d14 <__ltsf2> + 18e2: 87 fd sbrc r24, 7 + 18e4: 05 c0 rjmp .+10 ; 0x18f0 + 18e6: 2a e2 ldi r18, 0x2A ; 42 + 18e8: 42 2e mov r4, r18 + 18ea: 26 e0 ldi r18, 0x06 ; 6 + 18ec: 52 2e mov r5, r18 + 18ee: 0b c0 rjmp .+22 ; 0x1906 + { + *pstr++ = '-'; + 18f0: 8d e2 ldi r24, 0x2D ; 45 + 18f2: 80 93 2a 06 sts 0x062A, r24 + value = -value; + 18f6: 97 fa bst r9, 7 + 18f8: 90 94 com r9 + 18fa: 97 f8 bld r9, 7 + 18fc: 90 94 com r9 + 18fe: 9b e2 ldi r25, 0x2B ; 43 + 1900: 49 2e mov r4, r25 + 1902: 96 e0 ldi r25, 0x06 ; 6 + 1904: 59 2e mov r5, r25 + } + + int_part = value; + 1906: c4 01 movw r24, r8 + 1908: b3 01 movw r22, r6 + 190a: 0e 94 de 12 call 0x25bc ; 0x25bc <__fixunssfsi> + 190e: 5b 01 movw r10, r22 + 1910: 6c 01 movw r12, r24 + dec_part = value - int_part; + int_count = 0; + dec_count = 0; + + if (int_part == 0) + 1912: 61 15 cp r22, r1 + 1914: 71 05 cpc r23, r1 + 1916: 81 05 cpc r24, r1 + 1918: 91 05 cpc r25, r1 + 191a: 21 f4 brne .+8 ; 0x1924 + { + *pstr++ = '0'; + 191c: 80 e3 ldi r24, 0x30 ; 48 + 191e: d2 01 movw r26, r4 + 1920: 8d 93 st X+, r24 + 1922: 2d 01 movw r4, r26 + 1924: 86 01 movw r16, r12 + 1926: 75 01 movw r14, r10 + 1928: 33 24 eor r3, r3 + 192a: 23 c0 rjmp .+70 ; 0x1972 + } + + while (int_part > 0) + { + nc_int_digits[int_count] = int_part % 10; + 192c: c8 01 movw r24, r16 + 192e: b7 01 movw r22, r14 + 1930: 2a e0 ldi r18, 0x0A ; 10 + 1932: 30 e0 ldi r19, 0x00 ; 0 + 1934: 40 e0 ldi r20, 0x00 ; 0 + 1936: 50 e0 ldi r21, 0x00 ; 0 + 1938: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 193c: e3 2d mov r30, r3 + 193e: f0 e0 ldi r31, 0x00 ; 0 + 1940: ee 55 subi r30, 0x5E ; 94 + 1942: fa 4f sbci r31, 0xFA ; 250 + 1944: 60 83 st Z, r22 + int_part = int_part - nc_int_digits[int_count]; + 1946: e6 1a sub r14, r22 + 1948: f1 08 sbc r15, r1 + 194a: 01 09 sbc r16, r1 + 194c: 11 09 sbc r17, r1 + + if (int_part > 0) + 194e: e1 14 cp r14, r1 + 1950: f1 04 cpc r15, r1 + 1952: 01 05 cpc r16, r1 + 1954: 11 05 cpc r17, r1 + 1956: 61 f0 breq .+24 ; 0x1970 + { + int_part = int_part / 10; + 1958: c8 01 movw r24, r16 + 195a: b7 01 movw r22, r14 + 195c: 2a e0 ldi r18, 0x0A ; 10 + 195e: 30 e0 ldi r19, 0x00 ; 0 + 1960: 40 e0 ldi r20, 0x00 ; 0 + 1962: 50 e0 ldi r21, 0x00 ; 0 + 1964: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1968: c9 01 movw r24, r18 + 196a: da 01 movw r26, r20 + 196c: 7c 01 movw r14, r24 + 196e: 8d 01 movw r16, r26 + } + + int_count++; // go to the next digit + 1970: 33 94 inc r3 + if (int_part == 0) + { + *pstr++ = '0'; + } + + while (int_part > 0) + 1972: e1 14 cp r14, r1 + 1974: f1 04 cpc r15, r1 + 1976: 01 05 cpc r16, r1 + 1978: 11 05 cpc r17, r1 + 197a: c1 f6 brne .-80 ; 0x192c + *pstr++ = '-'; + value = -value; + } + + int_part = value; + dec_part = value - int_part; + 197c: c6 01 movw r24, r12 + 197e: b5 01 movw r22, r10 + 1980: 0e 94 6c 17 call 0x2ed8 ; 0x2ed8 <__floatunsisf> + 1984: 9b 01 movw r18, r22 + 1986: ac 01 movw r20, r24 + 1988: c4 01 movw r24, r8 + 198a: b3 01 movw r22, r6 + 198c: 0e 94 56 14 call 0x28ac ; 0x28ac <__subsf3> + 1990: 7b 01 movw r14, r22 + 1992: 8c 01 movw r16, r24 + 1994: 8a ea ldi r24, 0xAA ; 170 + 1996: a8 2e mov r10, r24 + 1998: 85 e0 ldi r24, 0x05 ; 5 + 199a: b8 2e mov r11, r24 + 199c: 65 01 movw r12, r10 + return (nc_buffer); +} +//----------------------------------------------------------------------------- + +pU08 nc_float_to_str(float value,U08 decimals,U08 digits) +{ + 199e: 82 2c mov r8, r2 + 19a0: 99 24 eor r9, r9 + } + + int_count++; // go to the next digit + } + + while (dec_count < decimals) + 19a2: 35 01 movw r6, r10 + 19a4: 68 0c add r6, r8 + 19a6: 79 1c adc r7, r9 + 19a8: 22 c0 rjmp .+68 ; 0x19ee + { + dec_part = dec_part * 10.0; + 19aa: c8 01 movw r24, r16 + 19ac: b7 01 movw r22, r14 + 19ae: 20 e0 ldi r18, 0x00 ; 0 + 19b0: 30 e0 ldi r19, 0x00 ; 0 + 19b2: 40 e2 ldi r20, 0x20 ; 32 + 19b4: 51 e4 ldi r21, 0x41 ; 65 + 19b6: 0e 94 b4 14 call 0x2968 ; 0x2968 <__mulsf3> + 19ba: 7b 01 movw r14, r22 + 19bc: 8c 01 movw r16, r24 + nc_dec_digits[dec_count] = dec_part; + 19be: 0e 94 de 12 call 0x25bc ; 0x25bc <__fixunssfsi> + 19c2: f6 01 movw r30, r12 + 19c4: 60 83 st Z, r22 + + if (nc_dec_digits[dec_count] > 0) + 19c6: 66 23 and r22, r22 + 19c8: 79 f0 breq .+30 ; 0x19e8 + { + dec_part = dec_part - nc_dec_digits[dec_count]; + 19ca: 70 e0 ldi r23, 0x00 ; 0 + 19cc: 88 27 eor r24, r24 + 19ce: 77 fd sbrc r23, 7 + 19d0: 80 95 com r24 + 19d2: 98 2f mov r25, r24 + 19d4: 0e 94 ba 16 call 0x2d74 ; 0x2d74 <__floatsisf> + 19d8: 9b 01 movw r18, r22 + 19da: ac 01 movw r20, r24 + 19dc: c8 01 movw r24, r16 + 19de: b7 01 movw r22, r14 + 19e0: 0e 94 56 14 call 0x28ac ; 0x28ac <__subsf3> + 19e4: 7b 01 movw r14, r22 + 19e6: 8c 01 movw r16, r24 + 19e8: 08 94 sec + 19ea: c1 1c adc r12, r1 + 19ec: d1 1c adc r13, r1 + } + + int_count++; // go to the next digit + } + + while (dec_count < decimals) + 19ee: c6 14 cp r12, r6 + 19f0: d7 04 cpc r13, r7 + 19f2: d9 f6 brne .-74 ; 0x19aa + } + + dec_count++; + } + + for (n = int_count - 1; n > -1; n--) + 19f4: 93 2d mov r25, r3 + 19f6: 91 50 subi r25, 0x01 ; 1 + 19f8: a9 2f mov r26, r25 + 19fa: bb 27 eor r27, r27 + 19fc: a7 fd sbrc r26, 7 + 19fe: b0 95 com r27 + 1a00: ae 55 subi r26, 0x5E ; 94 + 1a02: ba 4f sbci r27, 0xFA ; 250 + 1a04: 07 c0 rjmp .+14 ; 0x1a14 + { + *pstr++ = 48 + nc_int_digits[n]; + 1a06: 8c 91 ld r24, X + 1a08: 80 5d subi r24, 0xD0 ; 208 + 1a0a: f2 01 movw r30, r4 + 1a0c: 80 83 st Z, r24 + 1a0e: 29 01 movw r4, r18 + } + + dec_count++; + } + + for (n = int_count - 1; n > -1; n--) + 1a10: 91 50 subi r25, 0x01 ; 1 + 1a12: 11 97 sbiw r26, 0x01 ; 1 + 1a14: 92 01 movw r18, r4 + 1a16: 2f 5f subi r18, 0xFF ; 255 + 1a18: 3f 4f sbci r19, 0xFF ; 255 + 1a1a: 97 ff sbrs r25, 7 + 1a1c: f4 cf rjmp .-24 ; 0x1a06 + { + *pstr++ = 48 + nc_int_digits[n]; + } + + *pstr++ = '.'; + 1a1e: 8e e2 ldi r24, 0x2E ; 46 + 1a20: d2 01 movw r26, r4 + 1a22: 8c 93 st X, r24 + 1a24: f2 01 movw r30, r4 + 1a26: 05 c0 rjmp .+10 ; 0x1a32 + + for (n = 0; n < dec_count; n++) + { + *pstr++ = 48 + nc_dec_digits[n]; + 1a28: d5 01 movw r26, r10 + 1a2a: 8d 91 ld r24, X+ + 1a2c: 5d 01 movw r10, r26 + 1a2e: 80 5d subi r24, 0xD0 ; 208 + 1a30: 80 83 st Z, r24 + 1a32: 31 96 adiw r30, 0x01 ; 1 + *pstr++ = 48 + nc_int_digits[n]; + } + + *pstr++ = '.'; + + for (n = 0; n < dec_count; n++) + 1a34: ac 14 cp r10, r12 + 1a36: bd 04 cpc r11, r13 + 1a38: b9 f7 brne .-18 ; 0x1a28 + { + *pstr++ = 48 + nc_dec_digits[n]; + } + + // Terminate string + *pstr = 0; + 1a3a: 28 0d add r18, r8 + 1a3c: 39 1d adc r19, r9 + 1a3e: f9 01 movw r30, r18 + 1a40: 10 82 st Z, r1 + + if (!digits) // If digits = 0, then return buffer start + 1a42: f9 81 ldd r31, Y+1 ; 0x01 + 1a44: ff 23 and r31, r31 + 1a46: 19 f4 brne .+6 ; 0x1a4e + 1a48: 2a e2 ldi r18, 0x2A ; 42 + 1a4a: 36 e0 ldi r19, 0x06 ; 6 + 1a4c: 06 c0 rjmp .+12 ; 0x1a5a + { + return nc_buffer; + } + else // Do formatted output + { + return nc_format(nc_buffer,digits); + 1a4e: 8a e2 ldi r24, 0x2A ; 42 + 1a50: 96 e0 ldi r25, 0x06 ; 6 + 1a52: 69 81 ldd r22, Y+1 ; 0x01 + 1a54: 0e 94 2a 0c call 0x1854 ; 0x1854 + 1a58: 9c 01 movw r18, r24 + } +} + 1a5a: c9 01 movw r24, r18 + 1a5c: 0f 90 pop r0 + 1a5e: cf 91 pop r28 + 1a60: df 91 pop r29 + 1a62: 1f 91 pop r17 + 1a64: 0f 91 pop r16 + 1a66: ff 90 pop r15 + 1a68: ef 90 pop r14 + 1a6a: df 90 pop r13 + 1a6c: cf 90 pop r12 + 1a6e: bf 90 pop r11 + 1a70: af 90 pop r10 + 1a72: 9f 90 pop r9 + 1a74: 8f 90 pop r8 + 1a76: 7f 90 pop r7 + 1a78: 6f 90 pop r6 + 1a7a: 5f 90 pop r5 + 1a7c: 4f 90 pop r4 + 1a7e: 3f 90 pop r3 + 1a80: 2f 90 pop r2 + 1a82: 08 95 ret + +00001a84 : + } +} +//----------------------------------------------------------------------------- + +pU08 nc_S32_to_str(S32 signed_value,U08 digits) +{ + 1a84: bf 92 push r11 + 1a86: cf 92 push r12 + 1a88: df 92 push r13 + 1a8a: ef 92 push r14 + 1a8c: ff 92 push r15 + 1a8e: 0f 93 push r16 + 1a90: 1f 93 push r17 + 1a92: cf 93 push r28 + 1a94: df 93 push r29 + 1a96: 8b 01 movw r16, r22 + 1a98: 9c 01 movw r18, r24 + 1a9a: b4 2e mov r11, r20 + pU08 pstr = nc_buffer; + U32 value; + + if (signed_value < 0) + 1a9c: 97 ff sbrs r25, 7 + 1a9e: 0d c0 rjmp .+26 ; 0x1aba + { + *pstr++ = '-'; + 1aa0: 8d e2 ldi r24, 0x2D ; 45 + 1aa2: 80 93 2a 06 sts 0x062A, r24 + value = -signed_value; + 1aa6: cc 24 eor r12, r12 + 1aa8: dd 24 eor r13, r13 + 1aaa: 76 01 movw r14, r12 + 1aac: c0 1a sub r12, r16 + 1aae: d1 0a sbc r13, r17 + 1ab0: e2 0a sbc r14, r18 + 1ab2: f3 0a sbc r15, r19 + 1ab4: cb e2 ldi r28, 0x2B ; 43 + 1ab6: d6 e0 ldi r29, 0x06 ; 6 + 1ab8: 04 c0 rjmp .+8 ; 0x1ac2 + } + else + { + value = signed_value; + 1aba: 6b 01 movw r12, r22 + 1abc: 7c 01 movw r14, r24 + 1abe: ca e2 ldi r28, 0x2A ; 42 + 1ac0: d6 e0 ldi r29, 0x06 ; 6 + } + + if (value >= 1000000000) *pstr++ = ('0' + (value / 1000000000)); + 1ac2: 80 e0 ldi r24, 0x00 ; 0 + 1ac4: c8 16 cp r12, r24 + 1ac6: 8a ec ldi r24, 0xCA ; 202 + 1ac8: d8 06 cpc r13, r24 + 1aca: 8a e9 ldi r24, 0x9A ; 154 + 1acc: e8 06 cpc r14, r24 + 1ace: 8b e3 ldi r24, 0x3B ; 59 + 1ad0: f8 06 cpc r15, r24 + 1ad2: 58 f0 brcs .+22 ; 0x1aea + 1ad4: c7 01 movw r24, r14 + 1ad6: b6 01 movw r22, r12 + 1ad8: 20 e0 ldi r18, 0x00 ; 0 + 1ada: 3a ec ldi r19, 0xCA ; 202 + 1adc: 4a e9 ldi r20, 0x9A ; 154 + 1ade: 5b e3 ldi r21, 0x3B ; 59 + 1ae0: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1ae4: 20 5d subi r18, 0xD0 ; 208 + 1ae6: 29 93 st Y+, r18 + 1ae8: 09 c0 rjmp .+18 ; 0x1afc + if (value >= 100000000) *pstr++ = ('0' + (value % 1000000000 / 100000000)); + 1aea: 80 e0 ldi r24, 0x00 ; 0 + 1aec: c8 16 cp r12, r24 + 1aee: 81 ee ldi r24, 0xE1 ; 225 + 1af0: d8 06 cpc r13, r24 + 1af2: 85 ef ldi r24, 0xF5 ; 245 + 1af4: e8 06 cpc r14, r24 + 1af6: 85 e0 ldi r24, 0x05 ; 5 + 1af8: f8 06 cpc r15, r24 + 1afa: 88 f0 brcs .+34 ; 0x1b1e + 1afc: c7 01 movw r24, r14 + 1afe: b6 01 movw r22, r12 + 1b00: 20 e0 ldi r18, 0x00 ; 0 + 1b02: 3a ec ldi r19, 0xCA ; 202 + 1b04: 4a e9 ldi r20, 0x9A ; 154 + 1b06: 5b e3 ldi r21, 0x3B ; 59 + 1b08: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1b0c: 20 e0 ldi r18, 0x00 ; 0 + 1b0e: 31 ee ldi r19, 0xE1 ; 225 + 1b10: 45 ef ldi r20, 0xF5 ; 245 + 1b12: 55 e0 ldi r21, 0x05 ; 5 + 1b14: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1b18: 20 5d subi r18, 0xD0 ; 208 + 1b1a: 29 93 st Y+, r18 + 1b1c: 09 c0 rjmp .+18 ; 0x1b30 + if (value >= 10000000) *pstr++ = ('0' + (value % 100000000 / 10000000)); + 1b1e: 80 e8 ldi r24, 0x80 ; 128 + 1b20: c8 16 cp r12, r24 + 1b22: 86 e9 ldi r24, 0x96 ; 150 + 1b24: d8 06 cpc r13, r24 + 1b26: 88 e9 ldi r24, 0x98 ; 152 + 1b28: e8 06 cpc r14, r24 + 1b2a: 80 e0 ldi r24, 0x00 ; 0 + 1b2c: f8 06 cpc r15, r24 + 1b2e: 88 f0 brcs .+34 ; 0x1b52 + 1b30: c7 01 movw r24, r14 + 1b32: b6 01 movw r22, r12 + 1b34: 20 e0 ldi r18, 0x00 ; 0 + 1b36: 31 ee ldi r19, 0xE1 ; 225 + 1b38: 45 ef ldi r20, 0xF5 ; 245 + 1b3a: 55 e0 ldi r21, 0x05 ; 5 + 1b3c: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1b40: 20 e8 ldi r18, 0x80 ; 128 + 1b42: 36 e9 ldi r19, 0x96 ; 150 + 1b44: 48 e9 ldi r20, 0x98 ; 152 + 1b46: 50 e0 ldi r21, 0x00 ; 0 + 1b48: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1b4c: 20 5d subi r18, 0xD0 ; 208 + 1b4e: 29 93 st Y+, r18 + 1b50: 09 c0 rjmp .+18 ; 0x1b64 + if (value >= 1000000) *pstr++ = ('0' + (value % 10000000 / 1000000)); + 1b52: 80 e4 ldi r24, 0x40 ; 64 + 1b54: c8 16 cp r12, r24 + 1b56: 82 e4 ldi r24, 0x42 ; 66 + 1b58: d8 06 cpc r13, r24 + 1b5a: 8f e0 ldi r24, 0x0F ; 15 + 1b5c: e8 06 cpc r14, r24 + 1b5e: 80 e0 ldi r24, 0x00 ; 0 + 1b60: f8 06 cpc r15, r24 + 1b62: 88 f0 brcs .+34 ; 0x1b86 + 1b64: c7 01 movw r24, r14 + 1b66: b6 01 movw r22, r12 + 1b68: 20 e8 ldi r18, 0x80 ; 128 + 1b6a: 36 e9 ldi r19, 0x96 ; 150 + 1b6c: 48 e9 ldi r20, 0x98 ; 152 + 1b6e: 50 e0 ldi r21, 0x00 ; 0 + 1b70: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1b74: 20 e4 ldi r18, 0x40 ; 64 + 1b76: 32 e4 ldi r19, 0x42 ; 66 + 1b78: 4f e0 ldi r20, 0x0F ; 15 + 1b7a: 50 e0 ldi r21, 0x00 ; 0 + 1b7c: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1b80: 20 5d subi r18, 0xD0 ; 208 + 1b82: 29 93 st Y+, r18 + 1b84: 09 c0 rjmp .+18 ; 0x1b98 + if (value >= 100000) *pstr++ = ('0' + (value % 1000000 / 100000)); + 1b86: 80 ea ldi r24, 0xA0 ; 160 + 1b88: c8 16 cp r12, r24 + 1b8a: 86 e8 ldi r24, 0x86 ; 134 + 1b8c: d8 06 cpc r13, r24 + 1b8e: 81 e0 ldi r24, 0x01 ; 1 + 1b90: e8 06 cpc r14, r24 + 1b92: 80 e0 ldi r24, 0x00 ; 0 + 1b94: f8 06 cpc r15, r24 + 1b96: 88 f0 brcs .+34 ; 0x1bba + 1b98: c7 01 movw r24, r14 + 1b9a: b6 01 movw r22, r12 + 1b9c: 20 e4 ldi r18, 0x40 ; 64 + 1b9e: 32 e4 ldi r19, 0x42 ; 66 + 1ba0: 4f e0 ldi r20, 0x0F ; 15 + 1ba2: 50 e0 ldi r21, 0x00 ; 0 + 1ba4: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1ba8: 20 ea ldi r18, 0xA0 ; 160 + 1baa: 36 e8 ldi r19, 0x86 ; 134 + 1bac: 41 e0 ldi r20, 0x01 ; 1 + 1bae: 50 e0 ldi r21, 0x00 ; 0 + 1bb0: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1bb4: 20 5d subi r18, 0xD0 ; 208 + 1bb6: 29 93 st Y+, r18 + 1bb8: 09 c0 rjmp .+18 ; 0x1bcc + if (value >= 10000) *pstr++ = ('0' + (value % 100000 / 10000)); + 1bba: 80 e1 ldi r24, 0x10 ; 16 + 1bbc: c8 16 cp r12, r24 + 1bbe: 87 e2 ldi r24, 0x27 ; 39 + 1bc0: d8 06 cpc r13, r24 + 1bc2: 80 e0 ldi r24, 0x00 ; 0 + 1bc4: e8 06 cpc r14, r24 + 1bc6: 80 e0 ldi r24, 0x00 ; 0 + 1bc8: f8 06 cpc r15, r24 + 1bca: 88 f0 brcs .+34 ; 0x1bee + 1bcc: c7 01 movw r24, r14 + 1bce: b6 01 movw r22, r12 + 1bd0: 20 ea ldi r18, 0xA0 ; 160 + 1bd2: 36 e8 ldi r19, 0x86 ; 134 + 1bd4: 41 e0 ldi r20, 0x01 ; 1 + 1bd6: 50 e0 ldi r21, 0x00 ; 0 + 1bd8: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1bdc: 20 e1 ldi r18, 0x10 ; 16 + 1bde: 37 e2 ldi r19, 0x27 ; 39 + 1be0: 40 e0 ldi r20, 0x00 ; 0 + 1be2: 50 e0 ldi r21, 0x00 ; 0 + 1be4: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1be8: 20 5d subi r18, 0xD0 ; 208 + 1bea: 29 93 st Y+, r18 + 1bec: 09 c0 rjmp .+18 ; 0x1c00 + if (value >= 1000) *pstr++ = ('0' + (value % 10000 / 1000)); + 1bee: 88 ee ldi r24, 0xE8 ; 232 + 1bf0: c8 16 cp r12, r24 + 1bf2: 83 e0 ldi r24, 0x03 ; 3 + 1bf4: d8 06 cpc r13, r24 + 1bf6: 80 e0 ldi r24, 0x00 ; 0 + 1bf8: e8 06 cpc r14, r24 + 1bfa: 80 e0 ldi r24, 0x00 ; 0 + 1bfc: f8 06 cpc r15, r24 + 1bfe: 88 f0 brcs .+34 ; 0x1c22 + 1c00: c7 01 movw r24, r14 + 1c02: b6 01 movw r22, r12 + 1c04: 20 e1 ldi r18, 0x10 ; 16 + 1c06: 37 e2 ldi r19, 0x27 ; 39 + 1c08: 40 e0 ldi r20, 0x00 ; 0 + 1c0a: 50 e0 ldi r21, 0x00 ; 0 + 1c0c: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1c10: 28 ee ldi r18, 0xE8 ; 232 + 1c12: 33 e0 ldi r19, 0x03 ; 3 + 1c14: 40 e0 ldi r20, 0x00 ; 0 + 1c16: 50 e0 ldi r21, 0x00 ; 0 + 1c18: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1c1c: 20 5d subi r18, 0xD0 ; 208 + 1c1e: 29 93 st Y+, r18 + 1c20: 06 c0 rjmp .+12 ; 0x1c2e + if (value >= 100) *pstr++ = ('0' + (value % 1000 / 100)); + 1c22: 84 e6 ldi r24, 0x64 ; 100 + 1c24: c8 16 cp r12, r24 + 1c26: d1 04 cpc r13, r1 + 1c28: e1 04 cpc r14, r1 + 1c2a: f1 04 cpc r15, r1 + 1c2c: 88 f0 brcs .+34 ; 0x1c50 + 1c2e: c7 01 movw r24, r14 + 1c30: b6 01 movw r22, r12 + 1c32: 28 ee ldi r18, 0xE8 ; 232 + 1c34: 33 e0 ldi r19, 0x03 ; 3 + 1c36: 40 e0 ldi r20, 0x00 ; 0 + 1c38: 50 e0 ldi r21, 0x00 ; 0 + 1c3a: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1c3e: 24 e6 ldi r18, 0x64 ; 100 + 1c40: 30 e0 ldi r19, 0x00 ; 0 + 1c42: 40 e0 ldi r20, 0x00 ; 0 + 1c44: 50 e0 ldi r21, 0x00 ; 0 + 1c46: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1c4a: 20 5d subi r18, 0xD0 ; 208 + 1c4c: 29 93 st Y+, r18 + 1c4e: 06 c0 rjmp .+12 ; 0x1c5c + if (value >= 10) *pstr++ = ('0' + (value % 100 / 10)); + 1c50: 8a e0 ldi r24, 0x0A ; 10 + 1c52: c8 16 cp r12, r24 + 1c54: d1 04 cpc r13, r1 + 1c56: e1 04 cpc r14, r1 + 1c58: f1 04 cpc r15, r1 + 1c5a: 80 f0 brcs .+32 ; 0x1c7c + 1c5c: c7 01 movw r24, r14 + 1c5e: b6 01 movw r22, r12 + 1c60: 24 e6 ldi r18, 0x64 ; 100 + 1c62: 30 e0 ldi r19, 0x00 ; 0 + 1c64: 40 e0 ldi r20, 0x00 ; 0 + 1c66: 50 e0 ldi r21, 0x00 ; 0 + 1c68: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1c6c: 2a e0 ldi r18, 0x0A ; 10 + 1c6e: 30 e0 ldi r19, 0x00 ; 0 + 1c70: 40 e0 ldi r20, 0x00 ; 0 + 1c72: 50 e0 ldi r21, 0x00 ; 0 + 1c74: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1c78: 20 5d subi r18, 0xD0 ; 208 + 1c7a: 29 93 st Y+, r18 + + *pstr++ = ('0' + (value % 10)); + 1c7c: c7 01 movw r24, r14 + 1c7e: b6 01 movw r22, r12 + 1c80: 2a e0 ldi r18, 0x0A ; 10 + 1c82: 30 e0 ldi r19, 0x00 ; 0 + 1c84: 40 e0 ldi r20, 0x00 ; 0 + 1c86: 50 e0 ldi r21, 0x00 ; 0 + 1c88: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1c8c: 60 5d subi r22, 0xD0 ; 208 + 1c8e: 68 83 st Y, r22 + *pstr = 0; + 1c90: 19 82 std Y+1, r1 ; 0x01 + + if (!digits) // If digits = 0, then return buffer start + 1c92: bb 20 and r11, r11 + 1c94: 19 f4 brne .+6 ; 0x1c9c + 1c96: 2a e2 ldi r18, 0x2A ; 42 + 1c98: 36 e0 ldi r19, 0x06 ; 6 + 1c9a: 06 c0 rjmp .+12 ; 0x1ca8 + { + return nc_buffer; + } + else // Do formatted output + { + return nc_format(nc_buffer,digits); + 1c9c: 8a e2 ldi r24, 0x2A ; 42 + 1c9e: 96 e0 ldi r25, 0x06 ; 6 + 1ca0: 6b 2d mov r22, r11 + 1ca2: 0e 94 2a 0c call 0x1854 ; 0x1854 + 1ca6: 9c 01 movw r18, r24 + } +} + 1ca8: c9 01 movw r24, r18 + 1caa: df 91 pop r29 + 1cac: cf 91 pop r28 + 1cae: 1f 91 pop r17 + 1cb0: 0f 91 pop r16 + 1cb2: ff 90 pop r15 + 1cb4: ef 90 pop r14 + 1cb6: df 90 pop r13 + 1cb8: cf 90 pop r12 + 1cba: bf 90 pop r11 + 1cbc: 08 95 ret + +00001cbe : + return (nc_buffer); +} +//----------------------------------------------------------------------------- + +pU08 nc_U32_to_str(U32 value,U08 digits) +{ + 1cbe: df 92 push r13 + 1cc0: ef 92 push r14 + 1cc2: ff 92 push r15 + 1cc4: 0f 93 push r16 + 1cc6: 1f 93 push r17 + 1cc8: cf 93 push r28 + 1cca: df 93 push r29 + 1ccc: 7b 01 movw r14, r22 + 1cce: 8c 01 movw r16, r24 + 1cd0: d4 2e mov r13, r20 + pU08 pstr = nc_buffer; + + if (value >= 1000000000) *pstr++ = ('0' + (value / 1000000000)); + 1cd2: 80 e0 ldi r24, 0x00 ; 0 + 1cd4: e8 16 cp r14, r24 + 1cd6: 8a ec ldi r24, 0xCA ; 202 + 1cd8: f8 06 cpc r15, r24 + 1cda: 8a e9 ldi r24, 0x9A ; 154 + 1cdc: 08 07 cpc r16, r24 + 1cde: 8b e3 ldi r24, 0x3B ; 59 + 1ce0: 18 07 cpc r17, r24 + 1ce2: 70 f0 brcs .+28 ; 0x1d00 + 1ce4: c8 01 movw r24, r16 + 1ce6: b7 01 movw r22, r14 + 1ce8: 20 e0 ldi r18, 0x00 ; 0 + 1cea: 3a ec ldi r19, 0xCA ; 202 + 1cec: 4a e9 ldi r20, 0x9A ; 154 + 1cee: 5b e3 ldi r21, 0x3B ; 59 + 1cf0: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1cf4: 20 5d subi r18, 0xD0 ; 208 + 1cf6: 20 93 2a 06 sts 0x062A, r18 + 1cfa: cb e2 ldi r28, 0x2B ; 43 + 1cfc: d6 e0 ldi r29, 0x06 ; 6 + 1cfe: 0b c0 rjmp .+22 ; 0x1d16 + if (value >= 100000000) *pstr++ = ('0' + (value % 1000000000 / 100000000)); + 1d00: 80 e0 ldi r24, 0x00 ; 0 + 1d02: e8 16 cp r14, r24 + 1d04: 81 ee ldi r24, 0xE1 ; 225 + 1d06: f8 06 cpc r15, r24 + 1d08: 85 ef ldi r24, 0xF5 ; 245 + 1d0a: 08 07 cpc r16, r24 + 1d0c: 85 e0 ldi r24, 0x05 ; 5 + 1d0e: 18 07 cpc r17, r24 + 1d10: 98 f0 brcs .+38 ; 0x1d38 + 1d12: ca e2 ldi r28, 0x2A ; 42 + 1d14: d6 e0 ldi r29, 0x06 ; 6 + 1d16: c8 01 movw r24, r16 + 1d18: b7 01 movw r22, r14 + 1d1a: 20 e0 ldi r18, 0x00 ; 0 + 1d1c: 3a ec ldi r19, 0xCA ; 202 + 1d1e: 4a e9 ldi r20, 0x9A ; 154 + 1d20: 5b e3 ldi r21, 0x3B ; 59 + 1d22: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1d26: 20 e0 ldi r18, 0x00 ; 0 + 1d28: 31 ee ldi r19, 0xE1 ; 225 + 1d2a: 45 ef ldi r20, 0xF5 ; 245 + 1d2c: 55 e0 ldi r21, 0x05 ; 5 + 1d2e: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1d32: 20 5d subi r18, 0xD0 ; 208 + 1d34: 29 93 st Y+, r18 + 1d36: 0b c0 rjmp .+22 ; 0x1d4e + if (value >= 10000000) *pstr++ = ('0' + (value % 100000000 / 10000000)); + 1d38: 80 e8 ldi r24, 0x80 ; 128 + 1d3a: e8 16 cp r14, r24 + 1d3c: 86 e9 ldi r24, 0x96 ; 150 + 1d3e: f8 06 cpc r15, r24 + 1d40: 88 e9 ldi r24, 0x98 ; 152 + 1d42: 08 07 cpc r16, r24 + 1d44: 80 e0 ldi r24, 0x00 ; 0 + 1d46: 18 07 cpc r17, r24 + 1d48: 98 f0 brcs .+38 ; 0x1d70 + 1d4a: ca e2 ldi r28, 0x2A ; 42 + 1d4c: d6 e0 ldi r29, 0x06 ; 6 + 1d4e: c8 01 movw r24, r16 + 1d50: b7 01 movw r22, r14 + 1d52: 20 e0 ldi r18, 0x00 ; 0 + 1d54: 31 ee ldi r19, 0xE1 ; 225 + 1d56: 45 ef ldi r20, 0xF5 ; 245 + 1d58: 55 e0 ldi r21, 0x05 ; 5 + 1d5a: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1d5e: 20 e8 ldi r18, 0x80 ; 128 + 1d60: 36 e9 ldi r19, 0x96 ; 150 + 1d62: 48 e9 ldi r20, 0x98 ; 152 + 1d64: 50 e0 ldi r21, 0x00 ; 0 + 1d66: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1d6a: 20 5d subi r18, 0xD0 ; 208 + 1d6c: 29 93 st Y+, r18 + 1d6e: 0b c0 rjmp .+22 ; 0x1d86 + if (value >= 1000000) *pstr++ = ('0' + (value % 10000000 / 1000000)); + 1d70: 80 e4 ldi r24, 0x40 ; 64 + 1d72: e8 16 cp r14, r24 + 1d74: 82 e4 ldi r24, 0x42 ; 66 + 1d76: f8 06 cpc r15, r24 + 1d78: 8f e0 ldi r24, 0x0F ; 15 + 1d7a: 08 07 cpc r16, r24 + 1d7c: 80 e0 ldi r24, 0x00 ; 0 + 1d7e: 18 07 cpc r17, r24 + 1d80: 98 f0 brcs .+38 ; 0x1da8 + 1d82: ca e2 ldi r28, 0x2A ; 42 + 1d84: d6 e0 ldi r29, 0x06 ; 6 + 1d86: c8 01 movw r24, r16 + 1d88: b7 01 movw r22, r14 + 1d8a: 20 e8 ldi r18, 0x80 ; 128 + 1d8c: 36 e9 ldi r19, 0x96 ; 150 + 1d8e: 48 e9 ldi r20, 0x98 ; 152 + 1d90: 50 e0 ldi r21, 0x00 ; 0 + 1d92: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1d96: 20 e4 ldi r18, 0x40 ; 64 + 1d98: 32 e4 ldi r19, 0x42 ; 66 + 1d9a: 4f e0 ldi r20, 0x0F ; 15 + 1d9c: 50 e0 ldi r21, 0x00 ; 0 + 1d9e: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1da2: 20 5d subi r18, 0xD0 ; 208 + 1da4: 29 93 st Y+, r18 + 1da6: 0b c0 rjmp .+22 ; 0x1dbe + if (value >= 100000) *pstr++ = ('0' + (value % 1000000 / 100000)); + 1da8: 80 ea ldi r24, 0xA0 ; 160 + 1daa: e8 16 cp r14, r24 + 1dac: 86 e8 ldi r24, 0x86 ; 134 + 1dae: f8 06 cpc r15, r24 + 1db0: 81 e0 ldi r24, 0x01 ; 1 + 1db2: 08 07 cpc r16, r24 + 1db4: 80 e0 ldi r24, 0x00 ; 0 + 1db6: 18 07 cpc r17, r24 + 1db8: 98 f0 brcs .+38 ; 0x1de0 + 1dba: ca e2 ldi r28, 0x2A ; 42 + 1dbc: d6 e0 ldi r29, 0x06 ; 6 + 1dbe: c8 01 movw r24, r16 + 1dc0: b7 01 movw r22, r14 + 1dc2: 20 e4 ldi r18, 0x40 ; 64 + 1dc4: 32 e4 ldi r19, 0x42 ; 66 + 1dc6: 4f e0 ldi r20, 0x0F ; 15 + 1dc8: 50 e0 ldi r21, 0x00 ; 0 + 1dca: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1dce: 20 ea ldi r18, 0xA0 ; 160 + 1dd0: 36 e8 ldi r19, 0x86 ; 134 + 1dd2: 41 e0 ldi r20, 0x01 ; 1 + 1dd4: 50 e0 ldi r21, 0x00 ; 0 + 1dd6: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1dda: 20 5d subi r18, 0xD0 ; 208 + 1ddc: 29 93 st Y+, r18 + 1dde: 0b c0 rjmp .+22 ; 0x1df6 + if (value >= 10000) *pstr++ = ('0' + (value % 100000 / 10000)); + 1de0: 80 e1 ldi r24, 0x10 ; 16 + 1de2: e8 16 cp r14, r24 + 1de4: 87 e2 ldi r24, 0x27 ; 39 + 1de6: f8 06 cpc r15, r24 + 1de8: 80 e0 ldi r24, 0x00 ; 0 + 1dea: 08 07 cpc r16, r24 + 1dec: 80 e0 ldi r24, 0x00 ; 0 + 1dee: 18 07 cpc r17, r24 + 1df0: 98 f0 brcs .+38 ; 0x1e18 + 1df2: ca e2 ldi r28, 0x2A ; 42 + 1df4: d6 e0 ldi r29, 0x06 ; 6 + 1df6: c8 01 movw r24, r16 + 1df8: b7 01 movw r22, r14 + 1dfa: 20 ea ldi r18, 0xA0 ; 160 + 1dfc: 36 e8 ldi r19, 0x86 ; 134 + 1dfe: 41 e0 ldi r20, 0x01 ; 1 + 1e00: 50 e0 ldi r21, 0x00 ; 0 + 1e02: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1e06: 20 e1 ldi r18, 0x10 ; 16 + 1e08: 37 e2 ldi r19, 0x27 ; 39 + 1e0a: 40 e0 ldi r20, 0x00 ; 0 + 1e0c: 50 e0 ldi r21, 0x00 ; 0 + 1e0e: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1e12: 20 5d subi r18, 0xD0 ; 208 + 1e14: 29 93 st Y+, r18 + 1e16: 0b c0 rjmp .+22 ; 0x1e2e + if (value >= 1000) *pstr++ = ('0' + (value % 10000 / 1000)); + 1e18: 88 ee ldi r24, 0xE8 ; 232 + 1e1a: e8 16 cp r14, r24 + 1e1c: 83 e0 ldi r24, 0x03 ; 3 + 1e1e: f8 06 cpc r15, r24 + 1e20: 80 e0 ldi r24, 0x00 ; 0 + 1e22: 08 07 cpc r16, r24 + 1e24: 80 e0 ldi r24, 0x00 ; 0 + 1e26: 18 07 cpc r17, r24 + 1e28: 98 f0 brcs .+38 ; 0x1e50 + 1e2a: ca e2 ldi r28, 0x2A ; 42 + 1e2c: d6 e0 ldi r29, 0x06 ; 6 + 1e2e: c8 01 movw r24, r16 + 1e30: b7 01 movw r22, r14 + 1e32: 20 e1 ldi r18, 0x10 ; 16 + 1e34: 37 e2 ldi r19, 0x27 ; 39 + 1e36: 40 e0 ldi r20, 0x00 ; 0 + 1e38: 50 e0 ldi r21, 0x00 ; 0 + 1e3a: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1e3e: 28 ee ldi r18, 0xE8 ; 232 + 1e40: 33 e0 ldi r19, 0x03 ; 3 + 1e42: 40 e0 ldi r20, 0x00 ; 0 + 1e44: 50 e0 ldi r21, 0x00 ; 0 + 1e46: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1e4a: 20 5d subi r18, 0xD0 ; 208 + 1e4c: 29 93 st Y+, r18 + 1e4e: 08 c0 rjmp .+16 ; 0x1e60 + if (value >= 100) *pstr++ = ('0' + (value % 1000 / 100)); + 1e50: 84 e6 ldi r24, 0x64 ; 100 + 1e52: e8 16 cp r14, r24 + 1e54: f1 04 cpc r15, r1 + 1e56: 01 05 cpc r16, r1 + 1e58: 11 05 cpc r17, r1 + 1e5a: 98 f0 brcs .+38 ; 0x1e82 + 1e5c: ca e2 ldi r28, 0x2A ; 42 + 1e5e: d6 e0 ldi r29, 0x06 ; 6 + 1e60: c8 01 movw r24, r16 + 1e62: b7 01 movw r22, r14 + 1e64: 28 ee ldi r18, 0xE8 ; 232 + 1e66: 33 e0 ldi r19, 0x03 ; 3 + 1e68: 40 e0 ldi r20, 0x00 ; 0 + 1e6a: 50 e0 ldi r21, 0x00 ; 0 + 1e6c: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1e70: 24 e6 ldi r18, 0x64 ; 100 + 1e72: 30 e0 ldi r19, 0x00 ; 0 + 1e74: 40 e0 ldi r20, 0x00 ; 0 + 1e76: 50 e0 ldi r21, 0x00 ; 0 + 1e78: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1e7c: 20 5d subi r18, 0xD0 ; 208 + 1e7e: 29 93 st Y+, r18 + 1e80: 0b c0 rjmp .+22 ; 0x1e98 + if (value >= 10) *pstr++ = ('0' + (value % 100 / 10)); + 1e82: 8a e0 ldi r24, 0x0A ; 10 + 1e84: e8 16 cp r14, r24 + 1e86: f1 04 cpc r15, r1 + 1e88: 01 05 cpc r16, r1 + 1e8a: 11 05 cpc r17, r1 + 1e8c: 18 f4 brcc .+6 ; 0x1e94 + 1e8e: ca e2 ldi r28, 0x2A ; 42 + 1e90: d6 e0 ldi r29, 0x06 ; 6 + 1e92: 12 c0 rjmp .+36 ; 0x1eb8 + 1e94: ca e2 ldi r28, 0x2A ; 42 + 1e96: d6 e0 ldi r29, 0x06 ; 6 + 1e98: c8 01 movw r24, r16 + 1e9a: b7 01 movw r22, r14 + 1e9c: 24 e6 ldi r18, 0x64 ; 100 + 1e9e: 30 e0 ldi r19, 0x00 ; 0 + 1ea0: 40 e0 ldi r20, 0x00 ; 0 + 1ea2: 50 e0 ldi r21, 0x00 ; 0 + 1ea4: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1ea8: 2a e0 ldi r18, 0x0A ; 10 + 1eaa: 30 e0 ldi r19, 0x00 ; 0 + 1eac: 40 e0 ldi r20, 0x00 ; 0 + 1eae: 50 e0 ldi r21, 0x00 ; 0 + 1eb0: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1eb4: 20 5d subi r18, 0xD0 ; 208 + 1eb6: 29 93 st Y+, r18 + + *pstr++ = ('0' + (value % 10)); + 1eb8: c8 01 movw r24, r16 + 1eba: b7 01 movw r22, r14 + 1ebc: 2a e0 ldi r18, 0x0A ; 10 + 1ebe: 30 e0 ldi r19, 0x00 ; 0 + 1ec0: 40 e0 ldi r20, 0x00 ; 0 + 1ec2: 50 e0 ldi r21, 0x00 ; 0 + 1ec4: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 1ec8: 60 5d subi r22, 0xD0 ; 208 + 1eca: 68 83 st Y, r22 + *pstr = 0; + 1ecc: 19 82 std Y+1, r1 ; 0x01 + + if (!digits) // If digits = 0, then return buffer start + 1ece: dd 20 and r13, r13 + 1ed0: 19 f4 brne .+6 ; 0x1ed8 + 1ed2: 2a e2 ldi r18, 0x2A ; 42 + 1ed4: 36 e0 ldi r19, 0x06 ; 6 + 1ed6: 06 c0 rjmp .+12 ; 0x1ee4 + { + return nc_buffer; + } + else // Do formatted output + { + return nc_format(nc_buffer,digits); + 1ed8: 8a e2 ldi r24, 0x2A ; 42 + 1eda: 96 e0 ldi r25, 0x06 ; 6 + 1edc: 6d 2d mov r22, r13 + 1ede: 0e 94 2a 0c call 0x1854 ; 0x1854 + 1ee2: 9c 01 movw r18, r24 + } +} + 1ee4: c9 01 movw r24, r18 + 1ee6: df 91 pop r29 + 1ee8: cf 91 pop r28 + 1eea: 1f 91 pop r17 + 1eec: 0f 91 pop r16 + 1eee: ff 90 pop r15 + 1ef0: ef 90 pop r14 + 1ef2: df 90 pop r13 + 1ef4: 08 95 ret + +00001ef6 : + } +} +//----------------------------------------------------------------------------- + +pU08 nc_S16_to_str(S16 signed_value,U08 digits) +{ + 1ef6: cf 93 push r28 + 1ef8: df 93 push r29 + 1efa: 9c 01 movw r18, r24 + 1efc: 46 2f mov r20, r22 + pU08 pstr = nc_buffer; + U16 value; + + if (signed_value < 0) + 1efe: 97 ff sbrs r25, 7 + 1f00: 0a c0 rjmp .+20 ; 0x1f16 + { + *pstr++ = '-'; + 1f02: 8d e2 ldi r24, 0x2D ; 45 + 1f04: 80 93 2a 06 sts 0x062A, r24 + value = -signed_value; + 1f08: ee 27 eor r30, r30 + 1f0a: ff 27 eor r31, r31 + 1f0c: e2 1b sub r30, r18 + 1f0e: f3 0b sbc r31, r19 + 1f10: cb e2 ldi r28, 0x2B ; 43 + 1f12: d6 e0 ldi r29, 0x06 ; 6 + 1f14: 03 c0 rjmp .+6 ; 0x1f1c + } + else + { + value = signed_value; + 1f16: fc 01 movw r30, r24 + 1f18: ca e2 ldi r28, 0x2A ; 42 + 1f1a: d6 e0 ldi r29, 0x06 ; 6 + } + + if (value >= 10000) *pstr++ = ('0' + (value / 10000)); + 1f1c: 87 e2 ldi r24, 0x27 ; 39 + 1f1e: e0 31 cpi r30, 0x10 ; 16 + 1f20: f8 07 cpc r31, r24 + 1f22: 40 f0 brcs .+16 ; 0x1f34 + 1f24: cf 01 movw r24, r30 + 1f26: 60 e1 ldi r22, 0x10 ; 16 + 1f28: 77 e2 ldi r23, 0x27 ; 39 + 1f2a: 0e 94 e6 19 call 0x33cc ; 0x33cc <__udivmodhi4> + 1f2e: 60 5d subi r22, 0xD0 ; 208 + 1f30: 69 93 st Y+, r22 + 1f32: 04 c0 rjmp .+8 ; 0x1f3c + if (value >= 1000) *pstr++ = ('0' + (value % 10000 / 1000)); + 1f34: 83 e0 ldi r24, 0x03 ; 3 + 1f36: e8 3e cpi r30, 0xE8 ; 232 + 1f38: f8 07 cpc r31, r24 + 1f3a: 60 f0 brcs .+24 ; 0x1f54 + 1f3c: cf 01 movw r24, r30 + 1f3e: 60 e1 ldi r22, 0x10 ; 16 + 1f40: 77 e2 ldi r23, 0x27 ; 39 + 1f42: 0e 94 e6 19 call 0x33cc ; 0x33cc <__udivmodhi4> + 1f46: 68 ee ldi r22, 0xE8 ; 232 + 1f48: 73 e0 ldi r23, 0x03 ; 3 + 1f4a: 0e 94 e6 19 call 0x33cc ; 0x33cc <__udivmodhi4> + 1f4e: 60 5d subi r22, 0xD0 ; 208 + 1f50: 69 93 st Y+, r22 + 1f52: 03 c0 rjmp .+6 ; 0x1f5a + if (value >= 100) *pstr++ = ('0' + (value % 1000 / 100)); + 1f54: e4 36 cpi r30, 0x64 ; 100 + 1f56: f1 05 cpc r31, r1 + 1f58: 60 f0 brcs .+24 ; 0x1f72 + 1f5a: cf 01 movw r24, r30 + 1f5c: 68 ee ldi r22, 0xE8 ; 232 + 1f5e: 73 e0 ldi r23, 0x03 ; 3 + 1f60: 0e 94 e6 19 call 0x33cc ; 0x33cc <__udivmodhi4> + 1f64: 64 e6 ldi r22, 0x64 ; 100 + 1f66: 70 e0 ldi r23, 0x00 ; 0 + 1f68: 0e 94 e6 19 call 0x33cc ; 0x33cc <__udivmodhi4> + 1f6c: 60 5d subi r22, 0xD0 ; 208 + 1f6e: 69 93 st Y+, r22 + 1f70: 03 c0 rjmp .+6 ; 0x1f78 + if (value >= 10) *pstr++ = ('0' + (value % 100 / 10)); + 1f72: ea 30 cpi r30, 0x0A ; 10 + 1f74: f1 05 cpc r31, r1 + 1f76: 58 f0 brcs .+22 ; 0x1f8e + 1f78: cf 01 movw r24, r30 + 1f7a: 64 e6 ldi r22, 0x64 ; 100 + 1f7c: 70 e0 ldi r23, 0x00 ; 0 + 1f7e: 0e 94 e6 19 call 0x33cc ; 0x33cc <__udivmodhi4> + 1f82: 6a e0 ldi r22, 0x0A ; 10 + 1f84: 70 e0 ldi r23, 0x00 ; 0 + 1f86: 0e 94 e6 19 call 0x33cc ; 0x33cc <__udivmodhi4> + 1f8a: 60 5d subi r22, 0xD0 ; 208 + 1f8c: 69 93 st Y+, r22 + *pstr++ = ('0' + (value % 10)); + 1f8e: cf 01 movw r24, r30 + 1f90: 6a e0 ldi r22, 0x0A ; 10 + 1f92: 70 e0 ldi r23, 0x00 ; 0 + 1f94: 0e 94 e6 19 call 0x33cc ; 0x33cc <__udivmodhi4> + 1f98: 80 5d subi r24, 0xD0 ; 208 + 1f9a: 88 83 st Y, r24 + *pstr = 0; + 1f9c: 19 82 std Y+1, r1 ; 0x01 + + if (!digits) // If digits = 0, then return buffer start + 1f9e: 44 23 and r20, r20 + 1fa0: 19 f4 brne .+6 ; 0x1fa8 + 1fa2: 2a e2 ldi r18, 0x2A ; 42 + 1fa4: 36 e0 ldi r19, 0x06 ; 6 + 1fa6: 06 c0 rjmp .+12 ; 0x1fb4 + { + return nc_buffer; + } + else // Do formatted output + { + return nc_format(nc_buffer,digits); + 1fa8: 8a e2 ldi r24, 0x2A ; 42 + 1faa: 96 e0 ldi r25, 0x06 ; 6 + 1fac: 64 2f mov r22, r20 + 1fae: 0e 94 2a 0c call 0x1854 ; 0x1854 + 1fb2: 9c 01 movw r18, r24 + } +} + 1fb4: c9 01 movw r24, r18 + 1fb6: df 91 pop r29 + 1fb8: cf 91 pop r28 + 1fba: 08 95 ret + +00001fbc : + return (nc_buffer); +} +//----------------------------------------------------------------------------- + +pU08 nc_U16_to_str(U16 value,U08 digits) +{ + 1fbc: 9c 01 movw r18, r24 + 1fbe: 46 2f mov r20, r22 + pU08 pstr = nc_buffer; + + if (value >= 10000) *pstr++ = ('0' + (value / 10000)); + 1fc0: 87 e2 ldi r24, 0x27 ; 39 + 1fc2: 20 31 cpi r18, 0x10 ; 16 + 1fc4: 38 07 cpc r19, r24 + 1fc6: 58 f0 brcs .+22 ; 0x1fde + 1fc8: c9 01 movw r24, r18 + 1fca: 60 e1 ldi r22, 0x10 ; 16 + 1fcc: 77 e2 ldi r23, 0x27 ; 39 + 1fce: 0e 94 e6 19 call 0x33cc ; 0x33cc <__udivmodhi4> + 1fd2: 60 5d subi r22, 0xD0 ; 208 + 1fd4: 60 93 2a 06 sts 0x062A, r22 + 1fd8: eb e2 ldi r30, 0x2B ; 43 + 1fda: f6 e0 ldi r31, 0x06 ; 6 + 1fdc: 06 c0 rjmp .+12 ; 0x1fea + if (value >= 1000) *pstr++ = ('0' + (value % 10000 / 1000)); + 1fde: 83 e0 ldi r24, 0x03 ; 3 + 1fe0: 28 3e cpi r18, 0xE8 ; 232 + 1fe2: 38 07 cpc r19, r24 + 1fe4: 70 f0 brcs .+28 ; 0x2002 + 1fe6: ea e2 ldi r30, 0x2A ; 42 + 1fe8: f6 e0 ldi r31, 0x06 ; 6 + 1fea: c9 01 movw r24, r18 + 1fec: 60 e1 ldi r22, 0x10 ; 16 + 1fee: 77 e2 ldi r23, 0x27 ; 39 + 1ff0: 0e 94 e6 19 call 0x33cc ; 0x33cc <__udivmodhi4> + 1ff4: 68 ee ldi r22, 0xE8 ; 232 + 1ff6: 73 e0 ldi r23, 0x03 ; 3 + 1ff8: 0e 94 e6 19 call 0x33cc ; 0x33cc <__udivmodhi4> + 1ffc: 60 5d subi r22, 0xD0 ; 208 + 1ffe: 61 93 st Z+, r22 + 2000: 05 c0 rjmp .+10 ; 0x200c + if (value >= 100) *pstr++ = ('0' + (value % 1000 / 100)); + 2002: 24 36 cpi r18, 0x64 ; 100 + 2004: 31 05 cpc r19, r1 + 2006: 70 f0 brcs .+28 ; 0x2024 + 2008: ea e2 ldi r30, 0x2A ; 42 + 200a: f6 e0 ldi r31, 0x06 ; 6 + 200c: c9 01 movw r24, r18 + 200e: 68 ee ldi r22, 0xE8 ; 232 + 2010: 73 e0 ldi r23, 0x03 ; 3 + 2012: 0e 94 e6 19 call 0x33cc ; 0x33cc <__udivmodhi4> + 2016: 64 e6 ldi r22, 0x64 ; 100 + 2018: 70 e0 ldi r23, 0x00 ; 0 + 201a: 0e 94 e6 19 call 0x33cc ; 0x33cc <__udivmodhi4> + 201e: 60 5d subi r22, 0xD0 ; 208 + 2020: 61 93 st Z+, r22 + 2022: 08 c0 rjmp .+16 ; 0x2034 + if (value >= 10)*pstr++ = ('0' + (value % 100 / 10)); + 2024: 2a 30 cpi r18, 0x0A ; 10 + 2026: 31 05 cpc r19, r1 + 2028: 18 f4 brcc .+6 ; 0x2030 + 202a: ea e2 ldi r30, 0x2A ; 42 + 202c: f6 e0 ldi r31, 0x06 ; 6 + 202e: 0d c0 rjmp .+26 ; 0x204a + 2030: ea e2 ldi r30, 0x2A ; 42 + 2032: f6 e0 ldi r31, 0x06 ; 6 + 2034: c9 01 movw r24, r18 + 2036: 64 e6 ldi r22, 0x64 ; 100 + 2038: 70 e0 ldi r23, 0x00 ; 0 + 203a: 0e 94 e6 19 call 0x33cc ; 0x33cc <__udivmodhi4> + 203e: 6a e0 ldi r22, 0x0A ; 10 + 2040: 70 e0 ldi r23, 0x00 ; 0 + 2042: 0e 94 e6 19 call 0x33cc ; 0x33cc <__udivmodhi4> + 2046: 60 5d subi r22, 0xD0 ; 208 + 2048: 61 93 st Z+, r22 + *pstr++ = ('0' + (value % 10)); + 204a: c9 01 movw r24, r18 + 204c: 6a e0 ldi r22, 0x0A ; 10 + 204e: 70 e0 ldi r23, 0x00 ; 0 + 2050: 0e 94 e6 19 call 0x33cc ; 0x33cc <__udivmodhi4> + 2054: 80 5d subi r24, 0xD0 ; 208 + 2056: 80 83 st Z, r24 + *pstr = 0; + 2058: 11 82 std Z+1, r1 ; 0x01 + + if (!digits) // If digits = 0, then return buffer start + 205a: 44 23 and r20, r20 + 205c: 19 f4 brne .+6 ; 0x2064 + 205e: 2a e2 ldi r18, 0x2A ; 42 + 2060: 36 e0 ldi r19, 0x06 ; 6 + 2062: 06 c0 rjmp .+12 ; 0x2070 + { + return nc_buffer; + } + else // Do formatted output + { + return nc_format(nc_buffer,digits); + 2064: 8a e2 ldi r24, 0x2A ; 42 + 2066: 96 e0 ldi r25, 0x06 ; 6 + 2068: 64 2f mov r22, r20 + 206a: 0e 94 2a 0c call 0x1854 ; 0x1854 + 206e: 9c 01 movw r18, r24 + } +} + 2070: c9 01 movw r24, r18 + 2072: 08 95 ret + +00002074 : + } +} +//----------------------------------------------------------------------------- + +pU08 nc_S08_to_str(S08 signed_value,U08 digits) +{ + 2074: 98 2f mov r25, r24 + 2076: 36 2f mov r19, r22 + pU08 pstr = nc_buffer; + U08 value; + + if (signed_value < 0) + 2078: 87 ff sbrs r24, 7 + 207a: 08 c0 rjmp .+16 ; 0x208c + { + *pstr++ = '-'; + 207c: 8d e2 ldi r24, 0x2D ; 45 + 207e: 80 93 2a 06 sts 0x062A, r24 + value = -signed_value; + 2082: 29 2f mov r18, r25 + 2084: 21 95 neg r18 + 2086: eb e2 ldi r30, 0x2B ; 43 + 2088: f6 e0 ldi r31, 0x06 ; 6 + 208a: 03 c0 rjmp .+6 ; 0x2092 + } + else + { + value = signed_value; + 208c: 28 2f mov r18, r24 + 208e: ea e2 ldi r30, 0x2A ; 42 + 2090: f6 e0 ldi r31, 0x06 ; 6 + } + + if (value >= 100) *pstr++ = ('0' + (value % 1000 / 100)); + 2092: 24 36 cpi r18, 0x64 ; 100 + 2094: 68 f0 brcs .+26 ; 0x20b0 + 2096: 82 2f mov r24, r18 + 2098: 90 e0 ldi r25, 0x00 ; 0 + 209a: 68 ee ldi r22, 0xE8 ; 232 + 209c: 73 e0 ldi r23, 0x03 ; 3 + 209e: 0e 94 fa 19 call 0x33f4 ; 0x33f4 <__divmodhi4> + 20a2: 64 e6 ldi r22, 0x64 ; 100 + 20a4: 70 e0 ldi r23, 0x00 ; 0 + 20a6: 0e 94 fa 19 call 0x33f4 ; 0x33f4 <__divmodhi4> + 20aa: 60 5d subi r22, 0xD0 ; 208 + 20ac: 61 93 st Z+, r22 + 20ae: 02 c0 rjmp .+4 ; 0x20b4 + if (value >= 10) *pstr++ = ('0' + (value % 100 / 10)); + 20b0: 2a 30 cpi r18, 0x0A ; 10 + 20b2: 50 f0 brcs .+20 ; 0x20c8 + 20b4: 82 2f mov r24, r18 + 20b6: 64 e6 ldi r22, 0x64 ; 100 + 20b8: 0e 94 da 19 call 0x33b4 ; 0x33b4 <__udivmodqi4> + 20bc: 89 2f mov r24, r25 + 20be: 6a e0 ldi r22, 0x0A ; 10 + 20c0: 0e 94 da 19 call 0x33b4 ; 0x33b4 <__udivmodqi4> + 20c4: 80 5d subi r24, 0xD0 ; 208 + 20c6: 81 93 st Z+, r24 + *pstr++ = ('0' + (value % 10)); + 20c8: 82 2f mov r24, r18 + 20ca: 6a e0 ldi r22, 0x0A ; 10 + 20cc: 0e 94 da 19 call 0x33b4 ; 0x33b4 <__udivmodqi4> + 20d0: 90 5d subi r25, 0xD0 ; 208 + 20d2: 90 83 st Z, r25 + *pstr = 0; + 20d4: 11 82 std Z+1, r1 ; 0x01 + + if (!digits) // If digits = 0, then return buffer start + 20d6: 33 23 and r19, r19 + 20d8: 19 f4 brne .+6 ; 0x20e0 + 20da: 2a e2 ldi r18, 0x2A ; 42 + 20dc: 36 e0 ldi r19, 0x06 ; 6 + 20de: 06 c0 rjmp .+12 ; 0x20ec + { + return nc_buffer; + } + else // Do formatted output + { + return nc_format(nc_buffer,digits); + 20e0: 8a e2 ldi r24, 0x2A ; 42 + 20e2: 96 e0 ldi r25, 0x06 ; 6 + 20e4: 63 2f mov r22, r19 + 20e6: 0e 94 2a 0c call 0x1854 ; 0x1854 + 20ea: 9c 01 movw r18, r24 + } +} + 20ec: c9 01 movw r24, r18 + 20ee: 08 95 ret + +000020f0 : + return (pU08)&nc_format_buffer; +} +//----------------------------------------------------------------------------- + +pU08 nc_U08_to_str(U08 value,U08 digits) +{ + 20f0: 1f 93 push r17 + 20f2: 48 2f mov r20, r24 + 20f4: 16 2f mov r17, r22 + pU08 pstr = nc_buffer; + + if (value >= 100) *pstr++ = ('0' + (value % 1000 / 100)); + 20f6: 84 36 cpi r24, 0x64 ; 100 + 20f8: 78 f0 brcs .+30 ; 0x2118 + 20fa: 90 e0 ldi r25, 0x00 ; 0 + 20fc: 68 ee ldi r22, 0xE8 ; 232 + 20fe: 73 e0 ldi r23, 0x03 ; 3 + 2100: 0e 94 fa 19 call 0x33f4 ; 0x33f4 <__divmodhi4> + 2104: 64 e6 ldi r22, 0x64 ; 100 + 2106: 70 e0 ldi r23, 0x00 ; 0 + 2108: 0e 94 fa 19 call 0x33f4 ; 0x33f4 <__divmodhi4> + 210c: 60 5d subi r22, 0xD0 ; 208 + 210e: 60 93 2a 06 sts 0x062A, r22 + 2112: 2b e2 ldi r18, 0x2B ; 43 + 2114: 36 e0 ldi r19, 0x06 ; 6 + 2116: 07 c0 rjmp .+14 ; 0x2126 + if (value >= 10) *pstr++ = ('0' + (value % 100 / 10)); + 2118: 8a 30 cpi r24, 0x0A ; 10 + 211a: 18 f4 brcc .+6 ; 0x2122 + 211c: ea e2 ldi r30, 0x2A ; 42 + 211e: f6 e0 ldi r31, 0x06 ; 6 + 2120: 0d c0 rjmp .+26 ; 0x213c + 2122: 2a e2 ldi r18, 0x2A ; 42 + 2124: 36 e0 ldi r19, 0x06 ; 6 + 2126: 84 2f mov r24, r20 + 2128: 64 e6 ldi r22, 0x64 ; 100 + 212a: 0e 94 da 19 call 0x33b4 ; 0x33b4 <__udivmodqi4> + 212e: 89 2f mov r24, r25 + 2130: 6a e0 ldi r22, 0x0A ; 10 + 2132: 0e 94 da 19 call 0x33b4 ; 0x33b4 <__udivmodqi4> + 2136: 80 5d subi r24, 0xD0 ; 208 + 2138: f9 01 movw r30, r18 + 213a: 81 93 st Z+, r24 + *pstr++ = ('0' + (value % 10)); + 213c: 84 2f mov r24, r20 + 213e: 6a e0 ldi r22, 0x0A ; 10 + 2140: 0e 94 da 19 call 0x33b4 ; 0x33b4 <__udivmodqi4> + 2144: 90 5d subi r25, 0xD0 ; 208 + 2146: 90 83 st Z, r25 + *pstr = 0; + 2148: 11 82 std Z+1, r1 ; 0x01 + + if (!digits) // If digits = 0, then return buffer start + 214a: 11 23 and r17, r17 + 214c: 19 f4 brne .+6 ; 0x2154 + 214e: 2a e2 ldi r18, 0x2A ; 42 + 2150: 36 e0 ldi r19, 0x06 ; 6 + 2152: 06 c0 rjmp .+12 ; 0x2160 + { + return nc_buffer; + } + else // Do formatted output + { + return nc_format(nc_buffer,digits); + 2154: 8a e2 ldi r24, 0x2A ; 42 + 2156: 96 e0 ldi r25, 0x06 ; 6 + 2158: 61 2f mov r22, r17 + 215a: 0e 94 2a 0c call 0x1854 ; 0x1854 + 215e: 9c 01 movw r18, r24 + } +} + 2160: c9 01 movw r24, r18 + 2162: 1f 91 pop r17 + 2164: 08 95 ret + +00002166 <__vector_4>: +*/ + + + +ISR (TIMER2_COMP_vect) +{ + 2166: 1f 92 push r1 + 2168: 0f 92 push r0 + 216a: 0f b6 in r0, 0x3f ; 63 + 216c: 0f 92 push r0 + 216e: 11 24 eor r1, r1 + 2170: 8f 93 push r24 + 2172: 9f 93 push r25 + 2174: af 93 push r26 + 2176: bf 93 push r27 + ++local_ms; + 2178: 80 91 b3 05 lds r24, 0x05B3 + 217c: 90 91 b4 05 lds r25, 0x05B4 + 2180: a0 91 b5 05 lds r26, 0x05B5 + 2184: b0 91 b6 05 lds r27, 0x05B6 + 2188: 01 96 adiw r24, 0x01 ; 1 + 218a: a1 1d adc r26, r1 + 218c: b1 1d adc r27, r1 + 218e: 80 93 b3 05 sts 0x05B3, r24 + 2192: 90 93 b4 05 sts 0x05B4, r25 + 2196: a0 93 b5 05 sts 0x05B5, r26 + 219a: b0 93 b6 05 sts 0x05B6, r27 +} + 219e: bf 91 pop r27 + 21a0: af 91 pop r26 + 21a2: 9f 91 pop r25 + 21a4: 8f 91 pop r24 + 21a6: 0f 90 pop r0 + 21a8: 0f be out 0x3f, r0 ; 63 + 21aa: 0f 90 pop r0 + 21ac: 1f 90 pop r1 + 21ae: 18 95 reti + +000021b0
: + +//----------------------------------------------------------------------------- +// M A I N --- M A I N --- M A I N --- M A I N --- M A I N +//----------------------------------------------------------------------------- +int main(void) +{ + 21b0: cf 92 push r12 + 21b2: df 92 push r13 + 21b4: ef 92 push r14 + 21b6: ff 92 push r15 + 21b8: 1f 93 push r17 + 21ba: cf 93 push r28 + 21bc: df 93 push r29 + + app_init(); // Setup: Watchdog and I/Os + 21be: 0e 94 c7 03 call 0x78e ; 0x78e + usart_init(); + 21c2: 0e 94 bc 0a call 0x1578 ; 0x1578 + spi_init(); // Initialize SPI interface as master + 21c6: 0e 94 96 09 call 0x132c ; 0x132c + +// TIMER2 is used as local clock: +// configure timer 2 + TCCR2 = (1< counts up every 8us + 21ce: 85 b5 in r24, 0x25 ; 37 + 21d0: 83 60 ori r24, 0x03 ; 3 + 21d2: 85 bd out 0x25, r24 ; 37 + OCR2 = 125-1; // --> output compare interrupt occurs every 125 x 8us = 1ms + 21d4: 8c e7 ldi r24, 0x7C ; 124 + 21d6: 83 bd out 0x23, r24 ; 35 + // Compare Interrupt erlauben + TIMSK |= (1< + if (local_ms % 10000 == 0) { + 21e8: 60 91 b3 05 lds r22, 0x05B3 + 21ec: 70 91 b4 05 lds r23, 0x05B4 + 21f0: 80 91 b5 05 lds r24, 0x05B5 + 21f4: 90 91 b6 05 lds r25, 0x05B6 + 21f8: 20 e1 ldi r18, 0x10 ; 16 + 21fa: 37 e2 ldi r19, 0x27 ; 39 + 21fc: 40 e0 ldi r20, 0x00 ; 0 + 21fe: 50 e0 ldi r21, 0x00 ; 0 + 2200: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 2204: 61 15 cp r22, r1 + 2206: 71 05 cpc r23, r1 + 2208: 81 05 cpc r24, r1 + 220a: 91 05 cpc r25, r1 + 220c: d9 f4 brne .+54 ; 0x2244 + usart_write_str((pU08)"time: "); + 220e: 82 e2 ldi r24, 0x22 ; 34 + 2210: 93 e0 ldi r25, 0x03 ; 3 + 2212: 0e 94 d6 0a call 0x15ac ; 0x15ac + usart_write_U32(local_ms/1000,6); + 2216: 60 91 b3 05 lds r22, 0x05B3 + 221a: 70 91 b4 05 lds r23, 0x05B4 + 221e: 80 91 b5 05 lds r24, 0x05B5 + 2222: 90 91 b6 05 lds r25, 0x05B6 + 2226: 28 ee ldi r18, 0xE8 ; 232 + 2228: 33 e0 ldi r19, 0x03 ; 3 + 222a: 40 e0 ldi r20, 0x00 ; 0 + 222c: 50 e0 ldi r21, 0x00 ; 0 + 222e: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 2232: ca 01 movw r24, r20 + 2234: b9 01 movw r22, r18 + 2236: 46 e0 ldi r20, 0x06 ; 6 + 2238: 0e 94 64 0b call 0x16c8 ; 0x16c8 + usart_write_str((pU08)"sec.\n"); + 223c: 89 e2 ldi r24, 0x29 ; 41 + 223e: 93 e0 ldi r25, 0x03 ; 3 + 2240: 0e 94 d6 0a call 0x15ac ; 0x15ac + } + + PORTB &= ~(1< W5100 is in reset ... + 2244: c2 98 cbi 0x18, 2 ; 24 + 2246: 84 ef ldi r24, 0xF4 ; 244 + 2248: 91 e0 ldi r25, 0x01 ; 1 + milliseconds can be achieved. + */ +void +_delay_loop_2(uint16_t __count) +{ + __asm__ volatile ( + 224a: 28 ec ldi r18, 0xC8 ; 200 + 224c: 30 e0 ldi r19, 0x00 ; 0 + 224e: f9 01 movw r30, r18 + 2250: 31 97 sbiw r30, 0x01 ; 1 + 2252: f1 f7 brne .-4 ; 0x2250 + __ticks = (uint16_t) (__ms * 10.0); + while(__ticks) + { + // wait 1/10 ms + _delay_loop_2(((F_CPU) / 4e3) / 10); + __ticks --; + 2254: 01 97 sbiw r24, 0x01 ; 1 + __ticks = 1; + else if (__tmp > 65535) + { + // __ticks = requested delay in 1/10 ms + __ticks = (uint16_t) (__ms * 10.0); + while(__ticks) + 2256: d9 f7 brne .-10 ; 0x224e + _delay_ms(50); //reset + + PORTB |= 1< W5100 is active + 2258: c2 9a sbi 0x18, 2 ; 24 + 225a: 80 e1 ldi r24, 0x10 ; 16 + 225c: 97 e2 ldi r25, 0x27 ; 39 + 225e: 01 97 sbiw r24, 0x01 ; 1 + 2260: f1 f7 brne .-4 ; 0x225e + } + } + enter_received = false; +*/ + + usart_write_str((pU08)"W5300 init begins at:"); + 2262: 8f e2 ldi r24, 0x2F ; 47 + 2264: 93 e0 ldi r25, 0x03 ; 3 + 2266: 0e 94 d6 0a call 0x15ac ; 0x15ac + usart_write_U32(local_ms,10); + 226a: 60 91 b3 05 lds r22, 0x05B3 + 226e: 70 91 b4 05 lds r23, 0x05B4 + 2272: 80 91 b5 05 lds r24, 0x05B5 + 2276: 90 91 b6 05 lds r25, 0x05B6 + 227a: 4a e0 ldi r20, 0x0A ; 10 + 227c: 0e 94 64 0b call 0x16c8 ; 0x16c8 + usart_write_str((pU08)"ms.\n"); + 2280: 85 e4 ldi r24, 0x45 ; 69 + 2282: 93 e0 ldi r25, 0x03 ; 3 + 2284: 0e 94 d6 0a call 0x15ac ; 0x15ac + + w5100_init(); + 2288: 0e 94 49 02 call 0x492 ; 0x492 + + usart_write_str((pU08)"W5300 init finished at:"); + 228c: 8a e4 ldi r24, 0x4A ; 74 + 228e: 93 e0 ldi r25, 0x03 ; 3 + 2290: 0e 94 d6 0a call 0x15ac ; 0x15ac + usart_write_U32(local_ms,10); + 2294: 60 91 b3 05 lds r22, 0x05B3 + 2298: 70 91 b4 05 lds r23, 0x05B4 + 229c: 80 91 b5 05 lds r24, 0x05B5 + 22a0: 90 91 b6 05 lds r25, 0x05B6 + 22a4: 4a e0 ldi r20, 0x0A ; 10 + 22a6: 0e 94 64 0b call 0x16c8 ; 0x16c8 + usart_write_str((pU08)"ms.\n"); + 22aa: 85 e4 ldi r24, 0x45 ; 69 + 22ac: 93 e0 ldi r25, 0x03 ; 3 + 22ae: 0e 94 d6 0a call 0x15ac ; 0x15ac + + usart_write_str((pU08)"Wait for PC to connect to FSC..."); + 22b2: 82 e6 ldi r24, 0x62 ; 98 + 22b4: 93 e0 ldi r25, 0x03 ; 3 + 22b6: 0e 94 d6 0a call 0x15ac ; 0x15ac + 22ba: c8 ec ldi r28, 0xC8 ; 200 + 22bc: d0 e0 ldi r29, 0x00 ; 0 + 22be: 12 c0 rjmp .+36 ; 0x22e4 + while (!w5100_is_established()) { + usart_write_str((pU08)"Socket status is:"); + 22c0: 83 e8 ldi r24, 0x83 ; 131 + 22c2: 93 e0 ldi r25, 0x03 ; 3 + 22c4: 0e 94 d6 0a call 0x15ac ; 0x15ac + usart_write_U08_hex(w5100_sock_status()); + 22c8: 0e 94 b3 00 call 0x166 ; 0x166 + 22cc: 0e 94 7d 0b call 0x16fa ; 0x16fa + usart_write_char('\n'); + 22d0: 8a e0 ldi r24, 0x0A ; 10 + 22d2: 0e 94 c9 0a call 0x1592 ; 0x1592 + 22d6: 82 e0 ldi r24, 0x02 ; 2 + 22d8: 9d e0 ldi r25, 0x0D ; 13 + 22da: fe 01 movw r30, r28 + 22dc: 31 97 sbiw r30, 0x01 ; 1 + 22de: f1 f7 brne .-4 ; 0x22dc + { + // wait 1/10 ms + _delay_loop_2(((F_CPU) / 4e3) / 10); + __ticks --; + 22e0: 01 97 sbiw r24, 0x01 ; 1 + __ticks = 1; + else if (__tmp > 65535) + { + // __ticks = requested delay in 1/10 ms + __ticks = (uint16_t) (__ms * 10.0); + while(__ticks) + 22e2: d9 f7 brne .-10 ; 0x22da + usart_write_str((pU08)"W5300 init finished at:"); + usart_write_U32(local_ms,10); + usart_write_str((pU08)"ms.\n"); + + usart_write_str((pU08)"Wait for PC to connect to FSC..."); + while (!w5100_is_established()) { + 22e4: 0e 94 b8 00 call 0x170 ; 0x170 + 22e8: 88 23 and r24, r24 + 22ea: 51 f3 breq .-44 ; 0x22c0 + usart_write_U08_hex(w5100_sock_status()); + usart_write_char('\n'); + _delay_ms(333); + } + + usart_write_str((pU08)"connection to PC established at:"); + 22ec: 85 e9 ldi r24, 0x95 ; 149 + 22ee: 93 e0 ldi r25, 0x03 ; 3 + 22f0: 0e 94 d6 0a call 0x15ac ; 0x15ac + usart_write_U32(local_ms/1000,6); + 22f4: 60 91 b3 05 lds r22, 0x05B3 + 22f8: 70 91 b4 05 lds r23, 0x05B4 + 22fc: 80 91 b5 05 lds r24, 0x05B5 + 2300: 90 91 b6 05 lds r25, 0x05B6 + 2304: 28 ee ldi r18, 0xE8 ; 232 + 2306: 33 e0 ldi r19, 0x03 ; 3 + 2308: 40 e0 ldi r20, 0x00 ; 0 + 230a: 50 e0 ldi r21, 0x00 ; 0 + 230c: 0e 94 0d 1a call 0x341a ; 0x341a <__udivmodsi4> + 2310: ca 01 movw r24, r20 + 2312: b9 01 movw r22, r18 + 2314: 46 e0 ldi r20, 0x06 ; 6 + 2316: 0e 94 64 0b call 0x16c8 ; 0x16c8 + usart_write_str((pU08)"sec.\n"); + 231a: 89 e2 ldi r24, 0x29 ; 41 + 231c: 93 e0 ldi r25, 0x03 ; 3 + 231e: 0e 94 d6 0a call 0x15ac ; 0x15ac + + usart_write_str((pU08)"Ready to investigate, what's happening next? - HIT ENTER - \n"); + 2322: 86 eb ldi r24, 0xB6 ; 182 + 2324: 93 e0 ldi r25, 0x03 ; 3 + 2326: 0e 94 d6 0a call 0x15ac ; 0x15ac + 232a: 20 e2 ldi r18, 0x20 ; 32 + 232c: 3e e4 ldi r19, 0x4E ; 78 + 232e: 03 c0 rjmp .+6 ; 0x2336 + 2330: c9 01 movw r24, r18 + 2332: 01 97 sbiw r24, 0x01 ; 1 + 2334: f1 f7 brne .-4 ; 0x2332 + while(!usart_rx_ready){ + 2336: 80 91 9e 05 lds r24, 0x059E + 233a: 88 23 and r24, r24 + 233c: c9 f3 breq .-14 ; 0x2330 + _delay_ms(10); + } + usart_rx_ready = false; + 233e: 10 92 9e 05 sts 0x059E, r1 + + + usart_write_str((pU08)"S0_TX_FSR\t|S0_TX_RD\t|S0_TX_WR\t|S0_RX_RSR\t|S0_RX_RD\t| 0x0426 | 0x0427 |\n"); + 2342: 83 ef ldi r24, 0xF3 ; 243 + 2344: 93 e0 ldi r25, 0x03 ; 3 + 2346: 0e 94 d6 0a call 0x15ac ; 0x15ac + 234a: c8 ec ldi r28, 0xC8 ; 200 + 234c: d0 e0 ldi r29, 0x00 ; 0 + 234e: 5b c0 rjmp .+182 ; 0x2406 + while(!usart_rx_ready){ + + usart_write_U16_hex(get_S0_TX_FSR()); usart_write_char('\t'); usart_write_char('|'); + 2350: 0e 94 a1 00 call 0x142 ; 0x142 + 2354: 0e 94 69 0b call 0x16d2 ; 0x16d2 + 2358: 89 e0 ldi r24, 0x09 ; 9 + 235a: 0e 94 c9 0a call 0x1592 ; 0x1592 + 235e: 8c e7 ldi r24, 0x7C ; 124 + 2360: 0e 94 c9 0a call 0x1592 ; 0x1592 + usart_write_U16_hex(get_S0_TX_RD()); usart_write_char('\t'); usart_write_char('|'); + 2364: 0e 94 8f 00 call 0x11e ; 0x11e + 2368: 0e 94 69 0b call 0x16d2 ; 0x16d2 + 236c: 89 e0 ldi r24, 0x09 ; 9 + 236e: 0e 94 c9 0a call 0x1592 ; 0x1592 + 2372: 8c e7 ldi r24, 0x7C ; 124 + 2374: 0e 94 c9 0a call 0x1592 ; 0x1592 + usart_write_U16_hex(get_S0_TX_WR()); usart_write_char('\t'); usart_write_char('|'); + 2378: 0e 94 7d 00 call 0xfa ; 0xfa + 237c: 0e 94 69 0b call 0x16d2 ; 0x16d2 + 2380: 89 e0 ldi r24, 0x09 ; 9 + 2382: 0e 94 c9 0a call 0x1592 ; 0x1592 + 2386: 8c e7 ldi r24, 0x7C ; 124 + 2388: 0e 94 c9 0a call 0x1592 ; 0x1592 + usart_write_U16_hex(get_S0_RX_RSR()); usart_write_char('\t'); usart_write_char('|'); + 238c: 0e 94 6b 00 call 0xd6 ; 0xd6 + 2390: 0e 94 69 0b call 0x16d2 ; 0x16d2 + 2394: 89 e0 ldi r24, 0x09 ; 9 + 2396: 0e 94 c9 0a call 0x1592 ; 0x1592 + 239a: 8c e7 ldi r24, 0x7C ; 124 + 239c: 0e 94 c9 0a call 0x1592 ; 0x1592 + usart_write_U16_hex(get_S0_RX_RD()); usart_write_char('\t'); usart_write_char('|'); + 23a0: 0e 94 59 00 call 0xb2 ; 0xb2 + 23a4: 0e 94 69 0b call 0x16d2 ; 0x16d2 + 23a8: 89 e0 ldi r24, 0x09 ; 9 + 23aa: 0e 94 c9 0a call 0x1592 ; 0x1592 + 23ae: 8c e7 ldi r24, 0x7C ; 124 + 23b0: 0e 94 c9 0a call 0x1592 ; 0x1592 + usart_write_U08_hex( w5100_read(0x0426) ); usart_write_char('\t'); usart_write_char('|'); + 23b4: 86 e2 ldi r24, 0x26 ; 38 + 23b6: 94 e0 ldi r25, 0x04 ; 4 + 23b8: 0e 94 49 00 call 0x92 ; 0x92 + 23bc: 0e 94 7d 0b call 0x16fa ; 0x16fa + 23c0: 89 e0 ldi r24, 0x09 ; 9 + 23c2: 0e 94 c9 0a call 0x1592 ; 0x1592 + 23c6: 8c e7 ldi r24, 0x7C ; 124 + 23c8: 0e 94 c9 0a call 0x1592 ; 0x1592 + usart_write_U08_hex( w5100_read(0x0427) ); usart_write_char('\t'); usart_write_char('|'); + 23cc: 87 e2 ldi r24, 0x27 ; 39 + 23ce: 94 e0 ldi r25, 0x04 ; 4 + 23d0: 0e 94 49 00 call 0x92 ; 0x92 + 23d4: 0e 94 7d 0b call 0x16fa ; 0x16fa + 23d8: 89 e0 ldi r24, 0x09 ; 9 + 23da: 0e 94 c9 0a call 0x1592 ; 0x1592 + 23de: 8c e7 ldi r24, 0x7C ; 124 + 23e0: 0e 94 c9 0a call 0x1592 ; 0x1592 + + usart_write_char('\n'); + 23e4: 8a e0 ldi r24, 0x0A ; 10 + 23e6: 0e 94 c9 0a call 0x1592 ; 0x1592 + 23ea: 80 ea ldi r24, 0xA0 ; 160 + 23ec: 9f e0 ldi r25, 0x0F ; 15 + 23ee: fe 01 movw r30, r28 + 23f0: 31 97 sbiw r30, 0x01 ; 1 + 23f2: f1 f7 brne .-4 ; 0x23f0 + { + // wait 1/10 ms + _delay_loop_2(((F_CPU) / 4e3) / 10); + __ticks --; + 23f4: 01 97 sbiw r24, 0x01 ; 1 + __ticks = 1; + else if (__tmp > 65535) + { + // __ticks = requested delay in 1/10 ms + __ticks = (uint16_t) (__ms * 10.0); + while(__ticks) + 23f6: d9 f7 brne .-10 ; 0x23ee + 23f8: 80 ea ldi r24, 0xA0 ; 160 + 23fa: 9f e0 ldi r25, 0x0F ; 15 + 23fc: fe 01 movw r30, r28 + 23fe: 31 97 sbiw r30, 0x01 ; 1 + 2400: f1 f7 brne .-4 ; 0x23fe + { + // wait 1/10 ms + _delay_loop_2(((F_CPU) / 4e3) / 10); + __ticks --; + 2402: 01 97 sbiw r24, 0x01 ; 1 + __ticks = 1; + else if (__tmp > 65535) + { + // __ticks = requested delay in 1/10 ms + __ticks = (uint16_t) (__ms * 10.0); + while(__ticks) + 2404: d9 f7 brne .-10 ; 0x23fc + } + usart_rx_ready = false; + + + usart_write_str((pU08)"S0_TX_FSR\t|S0_TX_RD\t|S0_TX_WR\t|S0_RX_RSR\t|S0_RX_RD\t| 0x0426 | 0x0427 |\n"); + while(!usart_rx_ready){ + 2406: 80 91 9e 05 lds r24, 0x059E + 240a: 88 23 and r24, r24 + 240c: 09 f4 brne .+2 ; 0x2410 + 240e: a0 cf rjmp .-192 ; 0x2350 + usart_write_char('\n'); + + _delay_ms(400); + _delay_ms(400); + } + usart_rx_ready = false; + 2410: 10 92 9e 05 sts 0x059E, r1 + 2414: 88 ec ldi r24, 0xC8 ; 200 + 2416: c8 2e mov r12, r24 + 2418: d1 2c mov r13, r1 + 241a: 89 c0 rjmp .+274 ; 0x252e + + U16 received_bytes; + U08 really_downloaded_bytes; + while(!usart_rx_ready){ + received_bytes = get_S0_RX_RSR(); + 241c: 0e 94 6b 00 call 0xd6 ; 0xd6 + 2420: 7c 01 movw r14, r24 + + usart_write_U16_hex(get_S0_TX_FSR()); usart_write_char('\t'); usart_write_char('|'); + 2422: 0e 94 a1 00 call 0x142 ; 0x142 + 2426: 0e 94 69 0b call 0x16d2 ; 0x16d2 + 242a: 89 e0 ldi r24, 0x09 ; 9 + 242c: 0e 94 c9 0a call 0x1592 ; 0x1592 + 2430: 8c e7 ldi r24, 0x7C ; 124 + 2432: 0e 94 c9 0a call 0x1592 ; 0x1592 + usart_write_U16_hex(get_S0_TX_RD()); usart_write_char('\t'); usart_write_char('|'); + 2436: 0e 94 8f 00 call 0x11e ; 0x11e + 243a: 0e 94 69 0b call 0x16d2 ; 0x16d2 + 243e: 89 e0 ldi r24, 0x09 ; 9 + 2440: 0e 94 c9 0a call 0x1592 ; 0x1592 + 2444: 8c e7 ldi r24, 0x7C ; 124 + 2446: 0e 94 c9 0a call 0x1592 ; 0x1592 + usart_write_U16_hex(get_S0_TX_WR()); usart_write_char('\t'); usart_write_char('|'); + 244a: 0e 94 7d 00 call 0xfa ; 0xfa + 244e: 0e 94 69 0b call 0x16d2 ; 0x16d2 + 2452: 89 e0 ldi r24, 0x09 ; 9 + 2454: 0e 94 c9 0a call 0x1592 ; 0x1592 + 2458: 8c e7 ldi r24, 0x7C ; 124 + 245a: 0e 94 c9 0a call 0x1592 ; 0x1592 + usart_write_U16_hex(get_S0_RX_RSR()); usart_write_char('\t'); usart_write_char('|'); + 245e: 0e 94 6b 00 call 0xd6 ; 0xd6 + 2462: 0e 94 69 0b call 0x16d2 ; 0x16d2 + 2466: 89 e0 ldi r24, 0x09 ; 9 + 2468: 0e 94 c9 0a call 0x1592 ; 0x1592 + 246c: 8c e7 ldi r24, 0x7C ; 124 + 246e: 0e 94 c9 0a call 0x1592 ; 0x1592 + usart_write_U16_hex(get_S0_RX_RD()); usart_write_char('\t'); usart_write_char('|'); + 2472: 0e 94 59 00 call 0xb2 ; 0xb2 + 2476: 0e 94 69 0b call 0x16d2 ; 0x16d2 + 247a: 89 e0 ldi r24, 0x09 ; 9 + 247c: 0e 94 c9 0a call 0x1592 ; 0x1592 + 2480: 8c e7 ldi r24, 0x7C ; 124 + 2482: 0e 94 c9 0a call 0x1592 ; 0x1592 + + + if (get_S0_RX_RSR() != 0) { // we have something to read + 2486: 0e 94 6b 00 call 0xd6 ; 0xd6 + 248a: 89 2b or r24, r25 + 248c: 89 f1 breq .+98 ; 0x24f0 + usart_write_str((pU08)"\nReading "); + 248e: 8b e3 ldi r24, 0x3B ; 59 + 2490: 94 e0 ldi r25, 0x04 ; 4 + 2492: 0e 94 d6 0a call 0x15ac ; 0x15ac + usart_write_U16(get_S0_RX_RSR(), 6); + 2496: 0e 94 6b 00 call 0xd6 ; 0xd6 + 249a: 66 e0 ldi r22, 0x06 ; 6 + 249c: 0e 94 73 0b call 0x16e6 ; 0x16e6 + usart_write_str((pU08)" b from W5100\n"); + 24a0: 85 e4 ldi r24, 0x45 ; 69 + 24a2: 94 e0 ldi r25, 0x04 ; 4 + 24a4: 0e 94 d6 0a call 0x15ac ; 0x15ac + 24a8: 20 c0 rjmp .+64 ; 0x24ea + + while (received_bytes != 0) { + really_downloaded_bytes = w5100_get_RX(16, true); + 24aa: 80 e1 ldi r24, 0x10 ; 16 + 24ac: 61 e0 ldi r22, 0x01 ; 1 + 24ae: 0e 94 e3 00 call 0x1c6 ; 0x1c6 + 24b2: 18 2f mov r17, r24 + usart_write_char('!'); + 24b4: 81 e2 ldi r24, 0x21 ; 33 + 24b6: 0e 94 c9 0a call 0x1592 ; 0x1592 + usart_write_U08(really_downloaded_bytes,4); + 24ba: 81 2f mov r24, r17 + 24bc: 64 e0 ldi r22, 0x04 ; 4 + 24be: 0e 94 87 0b call 0x170e ; 0x170e + usart_write_char('\n'); + 24c2: 8a e0 ldi r24, 0x0A ; 10 + 24c4: 0e 94 c9 0a call 0x1592 ; 0x1592 + 24c8: c0 e0 ldi r28, 0x00 ; 0 + 24ca: d0 e0 ldi r29, 0x00 ; 0 + 24cc: 0a c0 rjmp .+20 ; 0x24e2 + for (U08 i=0; i + usart_write_char(' '); + 24da: 80 e2 ldi r24, 0x20 ; 32 + 24dc: 0e 94 c9 0a call 0x1592 ; 0x1592 + 24e0: 21 96 adiw r28, 0x01 ; 1 + while (received_bytes != 0) { + really_downloaded_bytes = w5100_get_RX(16, true); + usart_write_char('!'); + usart_write_U08(really_downloaded_bytes,4); + usart_write_char('\n'); + for (U08 i=0; i + usart_write_U08_hex(eth_read_buffer[i]); + usart_write_char(' '); + } + received_bytes -= really_downloaded_bytes; + 24e6: e1 1a sub r14, r17 + 24e8: f1 08 sbc r15, r1 + if (get_S0_RX_RSR() != 0) { // we have something to read + usart_write_str((pU08)"\nReading "); + usart_write_U16(get_S0_RX_RSR(), 6); + usart_write_str((pU08)" b from W5100\n"); + + while (received_bytes != 0) { + 24ea: e1 14 cp r14, r1 + 24ec: f1 04 cpc r15, r1 + 24ee: e9 f6 brne .-70 ; 0x24aa + usart_write_char(' '); + } + received_bytes -= really_downloaded_bytes; + } + } + usart_write_char('\n'); + 24f0: 8a e0 ldi r24, 0x0A ; 10 + 24f2: 0e 94 c9 0a call 0x1592 ; 0x1592 + 24f6: 80 ea ldi r24, 0xA0 ; 160 + 24f8: 9f e0 ldi r25, 0x0F ; 15 + 24fa: f6 01 movw r30, r12 + 24fc: 31 97 sbiw r30, 0x01 ; 1 + 24fe: f1 f7 brne .-4 ; 0x24fc + { + // wait 1/10 ms + _delay_loop_2(((F_CPU) / 4e3) / 10); + __ticks --; + 2500: 01 97 sbiw r24, 0x01 ; 1 + __ticks = 1; + else if (__tmp > 65535) + { + // __ticks = requested delay in 1/10 ms + __ticks = (uint16_t) (__ms * 10.0); + while(__ticks) + 2502: d9 f7 brne .-10 ; 0x24fa + 2504: 80 ea ldi r24, 0xA0 ; 160 + 2506: 9f e0 ldi r25, 0x0F ; 15 + 2508: f6 01 movw r30, r12 + 250a: 31 97 sbiw r30, 0x01 ; 1 + 250c: f1 f7 brne .-4 ; 0x250a + { + // wait 1/10 ms + _delay_loop_2(((F_CPU) / 4e3) / 10); + __ticks --; + 250e: 01 97 sbiw r24, 0x01 ; 1 + __ticks = 1; + else if (__tmp > 65535) + { + // __ticks = requested delay in 1/10 ms + __ticks = (uint16_t) (__ms * 10.0); + while(__ticks) + 2510: d9 f7 brne .-10 ; 0x2508 + 2512: 80 ea ldi r24, 0xA0 ; 160 + 2514: 9f e0 ldi r25, 0x0F ; 15 + 2516: f6 01 movw r30, r12 + 2518: 31 97 sbiw r30, 0x01 ; 1 + 251a: f1 f7 brne .-4 ; 0x2518 + { + // wait 1/10 ms + _delay_loop_2(((F_CPU) / 4e3) / 10); + __ticks --; + 251c: 01 97 sbiw r24, 0x01 ; 1 + __ticks = 1; + else if (__tmp > 65535) + { + // __ticks = requested delay in 1/10 ms + __ticks = (uint16_t) (__ms * 10.0); + while(__ticks) + 251e: d9 f7 brne .-10 ; 0x2516 + 2520: 80 ea ldi r24, 0xA0 ; 160 + 2522: 9f e0 ldi r25, 0x0F ; 15 + 2524: f6 01 movw r30, r12 + 2526: 31 97 sbiw r30, 0x01 ; 1 + 2528: f1 f7 brne .-4 ; 0x2526 + { + // wait 1/10 ms + _delay_loop_2(((F_CPU) / 4e3) / 10); + __ticks --; + 252a: 01 97 sbiw r24, 0x01 ; 1 + __ticks = 1; + else if (__tmp > 65535) + { + // __ticks = requested delay in 1/10 ms + __ticks = (uint16_t) (__ms * 10.0); + while(__ticks) + 252c: d9 f7 brne .-10 ; 0x2524 + } + usart_rx_ready = false; + + U16 received_bytes; + U08 really_downloaded_bytes; + while(!usart_rx_ready){ + 252e: 80 91 9e 05 lds r24, 0x059E + 2532: 88 23 and r24, r24 + 2534: 09 f4 brne .+2 ; 0x2538 + 2536: 72 cf rjmp .-284 ; 0x241c + _delay_ms(400); + _delay_ms(400); + _delay_ms(400); + _delay_ms(400); + } + usart_rx_ready = false; + 2538: 10 92 9e 05 sts 0x059E, r1 + 253c: c8 ec ldi r28, 0xC8 ; 200 + 253e: d0 e0 ldi r29, 0x00 ; 0 + + bool quit = false; + while (!quit) { + usart_write_str((pU08)"Enter the string to send to PC or \"XXX\" in order to quit\n"); + 2540: 84 e5 ldi r24, 0x54 ; 84 + 2542: 94 e0 ldi r25, 0x04 ; 4 + 2544: 0e 94 d6 0a call 0x15ac ; 0x15ac + 2548: 07 c0 rjmp .+14 ; 0x2558 + while(!usart_rx_ready){ + 254a: 88 ee ldi r24, 0xE8 ; 232 + 254c: 93 e0 ldi r25, 0x03 ; 3 + 254e: fe 01 movw r30, r28 + 2550: 31 97 sbiw r30, 0x01 ; 1 + 2552: f1 f7 brne .-4 ; 0x2550 + { + // wait 1/10 ms + _delay_loop_2(((F_CPU) / 4e3) / 10); + __ticks --; + 2554: 01 97 sbiw r24, 0x01 ; 1 + __ticks = 1; + else if (__tmp > 65535) + { + // __ticks = requested delay in 1/10 ms + __ticks = (uint16_t) (__ms * 10.0); + while(__ticks) + 2556: d9 f7 brne .-10 ; 0x254e + 2558: 80 91 9e 05 lds r24, 0x059E + 255c: 88 23 and r24, r24 + 255e: a9 f3 breq .-22 ; 0x254a + _delay_ms(100); + } + usart_rx_ready = false; + 2560: 10 92 9e 05 sts 0x059E, r1 + + if ( (usart_rx_buffer[0]=='X') && (usart_rx_buffer[1]=='X') && (usart_rx_buffer[2]=='X') ) + 2564: 80 91 0a 06 lds r24, 0x060A + 2568: 88 35 cpi r24, 0x58 ; 88 + 256a: 21 f4 brne .+8 ; 0x2574 + 256c: 80 91 0b 06 lds r24, 0x060B + 2570: 88 35 cpi r24, 0x58 ; 88 + 2572: 29 f0 breq .+10 ; 0x257e + quit = true; + else { + // copy string to W5100 TX buffer and issue 'SEND' command. + for (U08 i =0; i + while(!usart_rx_ready){ + _delay_ms(100); + } + usart_rx_ready = false; + + if ( (usart_rx_buffer[0]=='X') && (usart_rx_buffer[1]=='X') && (usart_rx_buffer[2]=='X') ) + 257e: 80 91 0c 06 lds r24, 0x060C + 2582: 88 35 cpi r24, 0x58 ; 88 + 2584: b9 f7 brne .-18 ; 0x2574 + 2586: 10 c0 rjmp .+32 ; 0x25a8 + quit = true; + else { + // copy string to W5100 TX buffer and issue 'SEND' command. + for (U08 i =0; i + eth_write_buffer[i]=usart_rx_buffer[i]; + } + + w5100_set_TX(usart_received_chars); + 25a0: 89 2f mov r24, r25 + 25a2: 0e 94 c7 01 call 0x38e ; 0x38e + 25a6: cc cf rjmp .-104 ; 0x2540 + } + + + } + +} // end of main() + 25a8: 80 e0 ldi r24, 0x00 ; 0 + 25aa: 90 e0 ldi r25, 0x00 ; 0 + 25ac: df 91 pop r29 + 25ae: cf 91 pop r28 + 25b0: 1f 91 pop r17 + 25b2: ff 90 pop r15 + 25b4: ef 90 pop r14 + 25b6: df 90 pop r13 + 25b8: cf 90 pop r12 + 25ba: 08 95 ret + +000025bc <__fixunssfsi>: + 25bc: ef 92 push r14 + 25be: ff 92 push r15 + 25c0: 0f 93 push r16 + 25c2: 1f 93 push r17 + 25c4: 7b 01 movw r14, r22 + 25c6: 8c 01 movw r16, r24 + 25c8: 20 e0 ldi r18, 0x00 ; 0 + 25ca: 30 e0 ldi r19, 0x00 ; 0 + 25cc: 40 e0 ldi r20, 0x00 ; 0 + 25ce: 5f e4 ldi r21, 0x4F ; 79 + 25d0: 0e 94 5a 16 call 0x2cb4 ; 0x2cb4 <__gesf2> + 25d4: 88 23 and r24, r24 + 25d6: 8c f0 brlt .+34 ; 0x25fa <__fixunssfsi+0x3e> + 25d8: c8 01 movw r24, r16 + 25da: b7 01 movw r22, r14 + 25dc: 20 e0 ldi r18, 0x00 ; 0 + 25de: 30 e0 ldi r19, 0x00 ; 0 + 25e0: 40 e0 ldi r20, 0x00 ; 0 + 25e2: 5f e4 ldi r21, 0x4F ; 79 + 25e4: 0e 94 56 14 call 0x28ac ; 0x28ac <__subsf3> + 25e8: 0e 94 18 17 call 0x2e30 ; 0x2e30 <__fixsfsi> + 25ec: 9b 01 movw r18, r22 + 25ee: ac 01 movw r20, r24 + 25f0: 20 50 subi r18, 0x00 ; 0 + 25f2: 30 40 sbci r19, 0x00 ; 0 + 25f4: 40 40 sbci r20, 0x00 ; 0 + 25f6: 50 48 sbci r21, 0x80 ; 128 + 25f8: 06 c0 rjmp .+12 ; 0x2606 <__fixunssfsi+0x4a> + 25fa: c8 01 movw r24, r16 + 25fc: b7 01 movw r22, r14 + 25fe: 0e 94 18 17 call 0x2e30 ; 0x2e30 <__fixsfsi> + 2602: 9b 01 movw r18, r22 + 2604: ac 01 movw r20, r24 + 2606: b9 01 movw r22, r18 + 2608: ca 01 movw r24, r20 + 260a: 1f 91 pop r17 + 260c: 0f 91 pop r16 + 260e: ff 90 pop r15 + 2610: ef 90 pop r14 + 2612: 08 95 ret + +00002614 <_fpadd_parts>: + 2614: a0 e0 ldi r26, 0x00 ; 0 + 2616: b0 e0 ldi r27, 0x00 ; 0 + 2618: e0 e1 ldi r30, 0x10 ; 16 + 261a: f3 e1 ldi r31, 0x13 ; 19 + 261c: 0c 94 2f 1a jmp 0x345e ; 0x345e <__prologue_saves__> + 2620: dc 01 movw r26, r24 + 2622: 2b 01 movw r4, r22 + 2624: fa 01 movw r30, r20 + 2626: 9c 91 ld r25, X + 2628: 92 30 cpi r25, 0x02 ; 2 + 262a: 08 f4 brcc .+2 ; 0x262e <_fpadd_parts+0x1a> + 262c: 39 c1 rjmp .+626 ; 0x28a0 <_fpadd_parts+0x28c> + 262e: eb 01 movw r28, r22 + 2630: 88 81 ld r24, Y + 2632: 82 30 cpi r24, 0x02 ; 2 + 2634: 08 f4 brcc .+2 ; 0x2638 <_fpadd_parts+0x24> + 2636: 33 c1 rjmp .+614 ; 0x289e <_fpadd_parts+0x28a> + 2638: 94 30 cpi r25, 0x04 ; 4 + 263a: 69 f4 brne .+26 ; 0x2656 <_fpadd_parts+0x42> + 263c: 84 30 cpi r24, 0x04 ; 4 + 263e: 09 f0 breq .+2 ; 0x2642 <_fpadd_parts+0x2e> + 2640: 2f c1 rjmp .+606 ; 0x28a0 <_fpadd_parts+0x28c> + 2642: 11 96 adiw r26, 0x01 ; 1 + 2644: 9c 91 ld r25, X + 2646: 11 97 sbiw r26, 0x01 ; 1 + 2648: 89 81 ldd r24, Y+1 ; 0x01 + 264a: 98 17 cp r25, r24 + 264c: 09 f4 brne .+2 ; 0x2650 <_fpadd_parts+0x3c> + 264e: 28 c1 rjmp .+592 ; 0x28a0 <_fpadd_parts+0x28c> + 2650: af e8 ldi r26, 0x8F ; 143 + 2652: b4 e0 ldi r27, 0x04 ; 4 + 2654: 25 c1 rjmp .+586 ; 0x28a0 <_fpadd_parts+0x28c> + 2656: 84 30 cpi r24, 0x04 ; 4 + 2658: 09 f4 brne .+2 ; 0x265c <_fpadd_parts+0x48> + 265a: 21 c1 rjmp .+578 ; 0x289e <_fpadd_parts+0x28a> + 265c: 82 30 cpi r24, 0x02 ; 2 + 265e: a9 f4 brne .+42 ; 0x268a <_fpadd_parts+0x76> + 2660: 92 30 cpi r25, 0x02 ; 2 + 2662: 09 f0 breq .+2 ; 0x2666 <_fpadd_parts+0x52> + 2664: 1d c1 rjmp .+570 ; 0x28a0 <_fpadd_parts+0x28c> + 2666: 9a 01 movw r18, r20 + 2668: ad 01 movw r20, r26 + 266a: 88 e0 ldi r24, 0x08 ; 8 + 266c: ea 01 movw r28, r20 + 266e: 09 90 ld r0, Y+ + 2670: ae 01 movw r20, r28 + 2672: e9 01 movw r28, r18 + 2674: 09 92 st Y+, r0 + 2676: 9e 01 movw r18, r28 + 2678: 81 50 subi r24, 0x01 ; 1 + 267a: c1 f7 brne .-16 ; 0x266c <_fpadd_parts+0x58> + 267c: e2 01 movw r28, r4 + 267e: 89 81 ldd r24, Y+1 ; 0x01 + 2680: 11 96 adiw r26, 0x01 ; 1 + 2682: 9c 91 ld r25, X + 2684: 89 23 and r24, r25 + 2686: 81 83 std Z+1, r24 ; 0x01 + 2688: 08 c1 rjmp .+528 ; 0x289a <_fpadd_parts+0x286> + 268a: 92 30 cpi r25, 0x02 ; 2 + 268c: 09 f4 brne .+2 ; 0x2690 <_fpadd_parts+0x7c> + 268e: 07 c1 rjmp .+526 ; 0x289e <_fpadd_parts+0x28a> + 2690: 12 96 adiw r26, 0x02 ; 2 + 2692: 2d 90 ld r2, X+ + 2694: 3c 90 ld r3, X + 2696: 13 97 sbiw r26, 0x03 ; 3 + 2698: eb 01 movw r28, r22 + 269a: 8a 81 ldd r24, Y+2 ; 0x02 + 269c: 9b 81 ldd r25, Y+3 ; 0x03 + 269e: 14 96 adiw r26, 0x04 ; 4 + 26a0: ad 90 ld r10, X+ + 26a2: bd 90 ld r11, X+ + 26a4: cd 90 ld r12, X+ + 26a6: dc 90 ld r13, X + 26a8: 17 97 sbiw r26, 0x07 ; 7 + 26aa: ec 80 ldd r14, Y+4 ; 0x04 + 26ac: fd 80 ldd r15, Y+5 ; 0x05 + 26ae: 0e 81 ldd r16, Y+6 ; 0x06 + 26b0: 1f 81 ldd r17, Y+7 ; 0x07 + 26b2: 91 01 movw r18, r2 + 26b4: 28 1b sub r18, r24 + 26b6: 39 0b sbc r19, r25 + 26b8: b9 01 movw r22, r18 + 26ba: 37 ff sbrs r19, 7 + 26bc: 04 c0 rjmp .+8 ; 0x26c6 <_fpadd_parts+0xb2> + 26be: 66 27 eor r22, r22 + 26c0: 77 27 eor r23, r23 + 26c2: 62 1b sub r22, r18 + 26c4: 73 0b sbc r23, r19 + 26c6: 60 32 cpi r22, 0x20 ; 32 + 26c8: 71 05 cpc r23, r1 + 26ca: 0c f0 brlt .+2 ; 0x26ce <_fpadd_parts+0xba> + 26cc: 61 c0 rjmp .+194 ; 0x2790 <_fpadd_parts+0x17c> + 26ce: 12 16 cp r1, r18 + 26d0: 13 06 cpc r1, r19 + 26d2: 6c f5 brge .+90 ; 0x272e <_fpadd_parts+0x11a> + 26d4: 37 01 movw r6, r14 + 26d6: 48 01 movw r8, r16 + 26d8: 06 2e mov r0, r22 + 26da: 04 c0 rjmp .+8 ; 0x26e4 <_fpadd_parts+0xd0> + 26dc: 96 94 lsr r9 + 26de: 87 94 ror r8 + 26e0: 77 94 ror r7 + 26e2: 67 94 ror r6 + 26e4: 0a 94 dec r0 + 26e6: d2 f7 brpl .-12 ; 0x26dc <_fpadd_parts+0xc8> + 26e8: 21 e0 ldi r18, 0x01 ; 1 + 26ea: 30 e0 ldi r19, 0x00 ; 0 + 26ec: 40 e0 ldi r20, 0x00 ; 0 + 26ee: 50 e0 ldi r21, 0x00 ; 0 + 26f0: 04 c0 rjmp .+8 ; 0x26fa <_fpadd_parts+0xe6> + 26f2: 22 0f add r18, r18 + 26f4: 33 1f adc r19, r19 + 26f6: 44 1f adc r20, r20 + 26f8: 55 1f adc r21, r21 + 26fa: 6a 95 dec r22 + 26fc: d2 f7 brpl .-12 ; 0x26f2 <_fpadd_parts+0xde> + 26fe: 21 50 subi r18, 0x01 ; 1 + 2700: 30 40 sbci r19, 0x00 ; 0 + 2702: 40 40 sbci r20, 0x00 ; 0 + 2704: 50 40 sbci r21, 0x00 ; 0 + 2706: 2e 21 and r18, r14 + 2708: 3f 21 and r19, r15 + 270a: 40 23 and r20, r16 + 270c: 51 23 and r21, r17 + 270e: 21 15 cp r18, r1 + 2710: 31 05 cpc r19, r1 + 2712: 41 05 cpc r20, r1 + 2714: 51 05 cpc r21, r1 + 2716: 21 f0 breq .+8 ; 0x2720 <_fpadd_parts+0x10c> + 2718: 21 e0 ldi r18, 0x01 ; 1 + 271a: 30 e0 ldi r19, 0x00 ; 0 + 271c: 40 e0 ldi r20, 0x00 ; 0 + 271e: 50 e0 ldi r21, 0x00 ; 0 + 2720: 79 01 movw r14, r18 + 2722: 8a 01 movw r16, r20 + 2724: e6 28 or r14, r6 + 2726: f7 28 or r15, r7 + 2728: 08 29 or r16, r8 + 272a: 19 29 or r17, r9 + 272c: 3c c0 rjmp .+120 ; 0x27a6 <_fpadd_parts+0x192> + 272e: 23 2b or r18, r19 + 2730: d1 f1 breq .+116 ; 0x27a6 <_fpadd_parts+0x192> + 2732: 26 0e add r2, r22 + 2734: 37 1e adc r3, r23 + 2736: 35 01 movw r6, r10 + 2738: 46 01 movw r8, r12 + 273a: 06 2e mov r0, r22 + 273c: 04 c0 rjmp .+8 ; 0x2746 <_fpadd_parts+0x132> + 273e: 96 94 lsr r9 + 2740: 87 94 ror r8 + 2742: 77 94 ror r7 + 2744: 67 94 ror r6 + 2746: 0a 94 dec r0 + 2748: d2 f7 brpl .-12 ; 0x273e <_fpadd_parts+0x12a> + 274a: 21 e0 ldi r18, 0x01 ; 1 + 274c: 30 e0 ldi r19, 0x00 ; 0 + 274e: 40 e0 ldi r20, 0x00 ; 0 + 2750: 50 e0 ldi r21, 0x00 ; 0 + 2752: 04 c0 rjmp .+8 ; 0x275c <_fpadd_parts+0x148> + 2754: 22 0f add r18, r18 + 2756: 33 1f adc r19, r19 + 2758: 44 1f adc r20, r20 + 275a: 55 1f adc r21, r21 + 275c: 6a 95 dec r22 + 275e: d2 f7 brpl .-12 ; 0x2754 <_fpadd_parts+0x140> + 2760: 21 50 subi r18, 0x01 ; 1 + 2762: 30 40 sbci r19, 0x00 ; 0 + 2764: 40 40 sbci r20, 0x00 ; 0 + 2766: 50 40 sbci r21, 0x00 ; 0 + 2768: 2a 21 and r18, r10 + 276a: 3b 21 and r19, r11 + 276c: 4c 21 and r20, r12 + 276e: 5d 21 and r21, r13 + 2770: 21 15 cp r18, r1 + 2772: 31 05 cpc r19, r1 + 2774: 41 05 cpc r20, r1 + 2776: 51 05 cpc r21, r1 + 2778: 21 f0 breq .+8 ; 0x2782 <_fpadd_parts+0x16e> + 277a: 21 e0 ldi r18, 0x01 ; 1 + 277c: 30 e0 ldi r19, 0x00 ; 0 + 277e: 40 e0 ldi r20, 0x00 ; 0 + 2780: 50 e0 ldi r21, 0x00 ; 0 + 2782: 59 01 movw r10, r18 + 2784: 6a 01 movw r12, r20 + 2786: a6 28 or r10, r6 + 2788: b7 28 or r11, r7 + 278a: c8 28 or r12, r8 + 278c: d9 28 or r13, r9 + 278e: 0b c0 rjmp .+22 ; 0x27a6 <_fpadd_parts+0x192> + 2790: 82 15 cp r24, r2 + 2792: 93 05 cpc r25, r3 + 2794: 2c f0 brlt .+10 ; 0x27a0 <_fpadd_parts+0x18c> + 2796: 1c 01 movw r2, r24 + 2798: aa 24 eor r10, r10 + 279a: bb 24 eor r11, r11 + 279c: 65 01 movw r12, r10 + 279e: 03 c0 rjmp .+6 ; 0x27a6 <_fpadd_parts+0x192> + 27a0: ee 24 eor r14, r14 + 27a2: ff 24 eor r15, r15 + 27a4: 87 01 movw r16, r14 + 27a6: 11 96 adiw r26, 0x01 ; 1 + 27a8: 9c 91 ld r25, X + 27aa: d2 01 movw r26, r4 + 27ac: 11 96 adiw r26, 0x01 ; 1 + 27ae: 8c 91 ld r24, X + 27b0: 98 17 cp r25, r24 + 27b2: 09 f4 brne .+2 ; 0x27b6 <_fpadd_parts+0x1a2> + 27b4: 45 c0 rjmp .+138 ; 0x2840 <_fpadd_parts+0x22c> + 27b6: 99 23 and r25, r25 + 27b8: 39 f0 breq .+14 ; 0x27c8 <_fpadd_parts+0x1b4> + 27ba: a8 01 movw r20, r16 + 27bc: 97 01 movw r18, r14 + 27be: 2a 19 sub r18, r10 + 27c0: 3b 09 sbc r19, r11 + 27c2: 4c 09 sbc r20, r12 + 27c4: 5d 09 sbc r21, r13 + 27c6: 06 c0 rjmp .+12 ; 0x27d4 <_fpadd_parts+0x1c0> + 27c8: a6 01 movw r20, r12 + 27ca: 95 01 movw r18, r10 + 27cc: 2e 19 sub r18, r14 + 27ce: 3f 09 sbc r19, r15 + 27d0: 40 0b sbc r20, r16 + 27d2: 51 0b sbc r21, r17 + 27d4: 57 fd sbrc r21, 7 + 27d6: 08 c0 rjmp .+16 ; 0x27e8 <_fpadd_parts+0x1d4> + 27d8: 11 82 std Z+1, r1 ; 0x01 + 27da: 33 82 std Z+3, r3 ; 0x03 + 27dc: 22 82 std Z+2, r2 ; 0x02 + 27de: 24 83 std Z+4, r18 ; 0x04 + 27e0: 35 83 std Z+5, r19 ; 0x05 + 27e2: 46 83 std Z+6, r20 ; 0x06 + 27e4: 57 83 std Z+7, r21 ; 0x07 + 27e6: 1d c0 rjmp .+58 ; 0x2822 <_fpadd_parts+0x20e> + 27e8: 81 e0 ldi r24, 0x01 ; 1 + 27ea: 81 83 std Z+1, r24 ; 0x01 + 27ec: 33 82 std Z+3, r3 ; 0x03 + 27ee: 22 82 std Z+2, r2 ; 0x02 + 27f0: 88 27 eor r24, r24 + 27f2: 99 27 eor r25, r25 + 27f4: dc 01 movw r26, r24 + 27f6: 82 1b sub r24, r18 + 27f8: 93 0b sbc r25, r19 + 27fa: a4 0b sbc r26, r20 + 27fc: b5 0b sbc r27, r21 + 27fe: 84 83 std Z+4, r24 ; 0x04 + 2800: 95 83 std Z+5, r25 ; 0x05 + 2802: a6 83 std Z+6, r26 ; 0x06 + 2804: b7 83 std Z+7, r27 ; 0x07 + 2806: 0d c0 rjmp .+26 ; 0x2822 <_fpadd_parts+0x20e> + 2808: 22 0f add r18, r18 + 280a: 33 1f adc r19, r19 + 280c: 44 1f adc r20, r20 + 280e: 55 1f adc r21, r21 + 2810: 24 83 std Z+4, r18 ; 0x04 + 2812: 35 83 std Z+5, r19 ; 0x05 + 2814: 46 83 std Z+6, r20 ; 0x06 + 2816: 57 83 std Z+7, r21 ; 0x07 + 2818: 82 81 ldd r24, Z+2 ; 0x02 + 281a: 93 81 ldd r25, Z+3 ; 0x03 + 281c: 01 97 sbiw r24, 0x01 ; 1 + 281e: 93 83 std Z+3, r25 ; 0x03 + 2820: 82 83 std Z+2, r24 ; 0x02 + 2822: 24 81 ldd r18, Z+4 ; 0x04 + 2824: 35 81 ldd r19, Z+5 ; 0x05 + 2826: 46 81 ldd r20, Z+6 ; 0x06 + 2828: 57 81 ldd r21, Z+7 ; 0x07 + 282a: da 01 movw r26, r20 + 282c: c9 01 movw r24, r18 + 282e: 01 97 sbiw r24, 0x01 ; 1 + 2830: a1 09 sbc r26, r1 + 2832: b1 09 sbc r27, r1 + 2834: 8f 5f subi r24, 0xFF ; 255 + 2836: 9f 4f sbci r25, 0xFF ; 255 + 2838: af 4f sbci r26, 0xFF ; 255 + 283a: bf 43 sbci r27, 0x3F ; 63 + 283c: 28 f3 brcs .-54 ; 0x2808 <_fpadd_parts+0x1f4> + 283e: 0b c0 rjmp .+22 ; 0x2856 <_fpadd_parts+0x242> + 2840: 91 83 std Z+1, r25 ; 0x01 + 2842: 33 82 std Z+3, r3 ; 0x03 + 2844: 22 82 std Z+2, r2 ; 0x02 + 2846: ea 0c add r14, r10 + 2848: fb 1c adc r15, r11 + 284a: 0c 1d adc r16, r12 + 284c: 1d 1d adc r17, r13 + 284e: e4 82 std Z+4, r14 ; 0x04 + 2850: f5 82 std Z+5, r15 ; 0x05 + 2852: 06 83 std Z+6, r16 ; 0x06 + 2854: 17 83 std Z+7, r17 ; 0x07 + 2856: 83 e0 ldi r24, 0x03 ; 3 + 2858: 80 83 st Z, r24 + 285a: 24 81 ldd r18, Z+4 ; 0x04 + 285c: 35 81 ldd r19, Z+5 ; 0x05 + 285e: 46 81 ldd r20, Z+6 ; 0x06 + 2860: 57 81 ldd r21, Z+7 ; 0x07 + 2862: 57 ff sbrs r21, 7 + 2864: 1a c0 rjmp .+52 ; 0x289a <_fpadd_parts+0x286> + 2866: c9 01 movw r24, r18 + 2868: aa 27 eor r26, r26 + 286a: 97 fd sbrc r25, 7 + 286c: a0 95 com r26 + 286e: ba 2f mov r27, r26 + 2870: 81 70 andi r24, 0x01 ; 1 + 2872: 90 70 andi r25, 0x00 ; 0 + 2874: a0 70 andi r26, 0x00 ; 0 + 2876: b0 70 andi r27, 0x00 ; 0 + 2878: 56 95 lsr r21 + 287a: 47 95 ror r20 + 287c: 37 95 ror r19 + 287e: 27 95 ror r18 + 2880: 82 2b or r24, r18 + 2882: 93 2b or r25, r19 + 2884: a4 2b or r26, r20 + 2886: b5 2b or r27, r21 + 2888: 84 83 std Z+4, r24 ; 0x04 + 288a: 95 83 std Z+5, r25 ; 0x05 + 288c: a6 83 std Z+6, r26 ; 0x06 + 288e: b7 83 std Z+7, r27 ; 0x07 + 2890: 82 81 ldd r24, Z+2 ; 0x02 + 2892: 93 81 ldd r25, Z+3 ; 0x03 + 2894: 01 96 adiw r24, 0x01 ; 1 + 2896: 93 83 std Z+3, r25 ; 0x03 + 2898: 82 83 std Z+2, r24 ; 0x02 + 289a: df 01 movw r26, r30 + 289c: 01 c0 rjmp .+2 ; 0x28a0 <_fpadd_parts+0x28c> + 289e: d2 01 movw r26, r4 + 28a0: cd 01 movw r24, r26 + 28a2: cd b7 in r28, 0x3d ; 61 + 28a4: de b7 in r29, 0x3e ; 62 + 28a6: e2 e1 ldi r30, 0x12 ; 18 + 28a8: 0c 94 4b 1a jmp 0x3496 ; 0x3496 <__epilogue_restores__> + +000028ac <__subsf3>: + 28ac: a0 e2 ldi r26, 0x20 ; 32 + 28ae: b0 e0 ldi r27, 0x00 ; 0 + 28b0: ec e5 ldi r30, 0x5C ; 92 + 28b2: f4 e1 ldi r31, 0x14 ; 20 + 28b4: 0c 94 3b 1a jmp 0x3476 ; 0x3476 <__prologue_saves__+0x18> + 28b8: 69 83 std Y+1, r22 ; 0x01 + 28ba: 7a 83 std Y+2, r23 ; 0x02 + 28bc: 8b 83 std Y+3, r24 ; 0x03 + 28be: 9c 83 std Y+4, r25 ; 0x04 + 28c0: 2d 83 std Y+5, r18 ; 0x05 + 28c2: 3e 83 std Y+6, r19 ; 0x06 + 28c4: 4f 83 std Y+7, r20 ; 0x07 + 28c6: 58 87 std Y+8, r21 ; 0x08 + 28c8: e9 e0 ldi r30, 0x09 ; 9 + 28ca: ee 2e mov r14, r30 + 28cc: f1 2c mov r15, r1 + 28ce: ec 0e add r14, r28 + 28d0: fd 1e adc r15, r29 + 28d2: ce 01 movw r24, r28 + 28d4: 01 96 adiw r24, 0x01 ; 1 + 28d6: b7 01 movw r22, r14 + 28d8: 0e 94 09 19 call 0x3212 ; 0x3212 <__unpack_f> + 28dc: 8e 01 movw r16, r28 + 28de: 0f 5e subi r16, 0xEF ; 239 + 28e0: 1f 4f sbci r17, 0xFF ; 255 + 28e2: ce 01 movw r24, r28 + 28e4: 05 96 adiw r24, 0x05 ; 5 + 28e6: b8 01 movw r22, r16 + 28e8: 0e 94 09 19 call 0x3212 ; 0x3212 <__unpack_f> + 28ec: 8a 89 ldd r24, Y+18 ; 0x12 + 28ee: 91 e0 ldi r25, 0x01 ; 1 + 28f0: 89 27 eor r24, r25 + 28f2: 8a 8b std Y+18, r24 ; 0x12 + 28f4: c7 01 movw r24, r14 + 28f6: b8 01 movw r22, r16 + 28f8: ae 01 movw r20, r28 + 28fa: 47 5e subi r20, 0xE7 ; 231 + 28fc: 5f 4f sbci r21, 0xFF ; 255 + 28fe: 0e 94 0a 13 call 0x2614 ; 0x2614 <_fpadd_parts> + 2902: 0e 94 34 18 call 0x3068 ; 0x3068 <__pack_f> + 2906: a0 96 adiw r28, 0x20 ; 32 + 2908: e6 e0 ldi r30, 0x06 ; 6 + 290a: 0c 94 57 1a jmp 0x34ae ; 0x34ae <__epilogue_restores__+0x18> + +0000290e <__addsf3>: + 290e: a0 e2 ldi r26, 0x20 ; 32 + 2910: b0 e0 ldi r27, 0x00 ; 0 + 2912: ed e8 ldi r30, 0x8D ; 141 + 2914: f4 e1 ldi r31, 0x14 ; 20 + 2916: 0c 94 3b 1a jmp 0x3476 ; 0x3476 <__prologue_saves__+0x18> + 291a: 69 83 std Y+1, r22 ; 0x01 + 291c: 7a 83 std Y+2, r23 ; 0x02 + 291e: 8b 83 std Y+3, r24 ; 0x03 + 2920: 9c 83 std Y+4, r25 ; 0x04 + 2922: 2d 83 std Y+5, r18 ; 0x05 + 2924: 3e 83 std Y+6, r19 ; 0x06 + 2926: 4f 83 std Y+7, r20 ; 0x07 + 2928: 58 87 std Y+8, r21 ; 0x08 + 292a: f9 e0 ldi r31, 0x09 ; 9 + 292c: ef 2e mov r14, r31 + 292e: f1 2c mov r15, r1 + 2930: ec 0e add r14, r28 + 2932: fd 1e adc r15, r29 + 2934: ce 01 movw r24, r28 + 2936: 01 96 adiw r24, 0x01 ; 1 + 2938: b7 01 movw r22, r14 + 293a: 0e 94 09 19 call 0x3212 ; 0x3212 <__unpack_f> + 293e: 8e 01 movw r16, r28 + 2940: 0f 5e subi r16, 0xEF ; 239 + 2942: 1f 4f sbci r17, 0xFF ; 255 + 2944: ce 01 movw r24, r28 + 2946: 05 96 adiw r24, 0x05 ; 5 + 2948: b8 01 movw r22, r16 + 294a: 0e 94 09 19 call 0x3212 ; 0x3212 <__unpack_f> + 294e: c7 01 movw r24, r14 + 2950: b8 01 movw r22, r16 + 2952: ae 01 movw r20, r28 + 2954: 47 5e subi r20, 0xE7 ; 231 + 2956: 5f 4f sbci r21, 0xFF ; 255 + 2958: 0e 94 0a 13 call 0x2614 ; 0x2614 <_fpadd_parts> + 295c: 0e 94 34 18 call 0x3068 ; 0x3068 <__pack_f> + 2960: a0 96 adiw r28, 0x20 ; 32 + 2962: e6 e0 ldi r30, 0x06 ; 6 + 2964: 0c 94 57 1a jmp 0x34ae ; 0x34ae <__epilogue_restores__+0x18> + +00002968 <__mulsf3>: + 2968: a0 e2 ldi r26, 0x20 ; 32 + 296a: b0 e0 ldi r27, 0x00 ; 0 + 296c: ea eb ldi r30, 0xBA ; 186 + 296e: f4 e1 ldi r31, 0x14 ; 20 + 2970: 0c 94 2f 1a jmp 0x345e ; 0x345e <__prologue_saves__> + 2974: 69 83 std Y+1, r22 ; 0x01 + 2976: 7a 83 std Y+2, r23 ; 0x02 + 2978: 8b 83 std Y+3, r24 ; 0x03 + 297a: 9c 83 std Y+4, r25 ; 0x04 + 297c: 2d 83 std Y+5, r18 ; 0x05 + 297e: 3e 83 std Y+6, r19 ; 0x06 + 2980: 4f 83 std Y+7, r20 ; 0x07 + 2982: 58 87 std Y+8, r21 ; 0x08 + 2984: ce 01 movw r24, r28 + 2986: 01 96 adiw r24, 0x01 ; 1 + 2988: be 01 movw r22, r28 + 298a: 67 5f subi r22, 0xF7 ; 247 + 298c: 7f 4f sbci r23, 0xFF ; 255 + 298e: 0e 94 09 19 call 0x3212 ; 0x3212 <__unpack_f> + 2992: ce 01 movw r24, r28 + 2994: 05 96 adiw r24, 0x05 ; 5 + 2996: be 01 movw r22, r28 + 2998: 6f 5e subi r22, 0xEF ; 239 + 299a: 7f 4f sbci r23, 0xFF ; 255 + 299c: 0e 94 09 19 call 0x3212 ; 0x3212 <__unpack_f> + 29a0: 99 85 ldd r25, Y+9 ; 0x09 + 29a2: 92 30 cpi r25, 0x02 ; 2 + 29a4: 88 f0 brcs .+34 ; 0x29c8 <__mulsf3+0x60> + 29a6: 89 89 ldd r24, Y+17 ; 0x11 + 29a8: 82 30 cpi r24, 0x02 ; 2 + 29aa: c8 f0 brcs .+50 ; 0x29de <__mulsf3+0x76> + 29ac: 94 30 cpi r25, 0x04 ; 4 + 29ae: 19 f4 brne .+6 ; 0x29b6 <__mulsf3+0x4e> + 29b0: 82 30 cpi r24, 0x02 ; 2 + 29b2: 51 f4 brne .+20 ; 0x29c8 <__mulsf3+0x60> + 29b4: 04 c0 rjmp .+8 ; 0x29be <__mulsf3+0x56> + 29b6: 84 30 cpi r24, 0x04 ; 4 + 29b8: 29 f4 brne .+10 ; 0x29c4 <__mulsf3+0x5c> + 29ba: 92 30 cpi r25, 0x02 ; 2 + 29bc: 81 f4 brne .+32 ; 0x29de <__mulsf3+0x76> + 29be: 8f e8 ldi r24, 0x8F ; 143 + 29c0: 94 e0 ldi r25, 0x04 ; 4 + 29c2: c6 c0 rjmp .+396 ; 0x2b50 <__mulsf3+0x1e8> + 29c4: 92 30 cpi r25, 0x02 ; 2 + 29c6: 49 f4 brne .+18 ; 0x29da <__mulsf3+0x72> + 29c8: 20 e0 ldi r18, 0x00 ; 0 + 29ca: 9a 85 ldd r25, Y+10 ; 0x0a + 29cc: 8a 89 ldd r24, Y+18 ; 0x12 + 29ce: 98 13 cpse r25, r24 + 29d0: 21 e0 ldi r18, 0x01 ; 1 + 29d2: 2a 87 std Y+10, r18 ; 0x0a + 29d4: ce 01 movw r24, r28 + 29d6: 09 96 adiw r24, 0x09 ; 9 + 29d8: bb c0 rjmp .+374 ; 0x2b50 <__mulsf3+0x1e8> + 29da: 82 30 cpi r24, 0x02 ; 2 + 29dc: 49 f4 brne .+18 ; 0x29f0 <__mulsf3+0x88> + 29de: 20 e0 ldi r18, 0x00 ; 0 + 29e0: 9a 85 ldd r25, Y+10 ; 0x0a + 29e2: 8a 89 ldd r24, Y+18 ; 0x12 + 29e4: 98 13 cpse r25, r24 + 29e6: 21 e0 ldi r18, 0x01 ; 1 + 29e8: 2a 8b std Y+18, r18 ; 0x12 + 29ea: ce 01 movw r24, r28 + 29ec: 41 96 adiw r24, 0x11 ; 17 + 29ee: b0 c0 rjmp .+352 ; 0x2b50 <__mulsf3+0x1e8> + 29f0: 2d 84 ldd r2, Y+13 ; 0x0d + 29f2: 3e 84 ldd r3, Y+14 ; 0x0e + 29f4: 4f 84 ldd r4, Y+15 ; 0x0f + 29f6: 58 88 ldd r5, Y+16 ; 0x10 + 29f8: 6d 88 ldd r6, Y+21 ; 0x15 + 29fa: 7e 88 ldd r7, Y+22 ; 0x16 + 29fc: 8f 88 ldd r8, Y+23 ; 0x17 + 29fe: 98 8c ldd r9, Y+24 ; 0x18 + 2a00: ee 24 eor r14, r14 + 2a02: ff 24 eor r15, r15 + 2a04: 87 01 movw r16, r14 + 2a06: aa 24 eor r10, r10 + 2a08: bb 24 eor r11, r11 + 2a0a: 65 01 movw r12, r10 + 2a0c: 40 e0 ldi r20, 0x00 ; 0 + 2a0e: 50 e0 ldi r21, 0x00 ; 0 + 2a10: 60 e0 ldi r22, 0x00 ; 0 + 2a12: 70 e0 ldi r23, 0x00 ; 0 + 2a14: e0 e0 ldi r30, 0x00 ; 0 + 2a16: f0 e0 ldi r31, 0x00 ; 0 + 2a18: c1 01 movw r24, r2 + 2a1a: 81 70 andi r24, 0x01 ; 1 + 2a1c: 90 70 andi r25, 0x00 ; 0 + 2a1e: 89 2b or r24, r25 + 2a20: e9 f0 breq .+58 ; 0x2a5c <__mulsf3+0xf4> + 2a22: e6 0c add r14, r6 + 2a24: f7 1c adc r15, r7 + 2a26: 08 1d adc r16, r8 + 2a28: 19 1d adc r17, r9 + 2a2a: 9a 01 movw r18, r20 + 2a2c: ab 01 movw r20, r22 + 2a2e: 2a 0d add r18, r10 + 2a30: 3b 1d adc r19, r11 + 2a32: 4c 1d adc r20, r12 + 2a34: 5d 1d adc r21, r13 + 2a36: 80 e0 ldi r24, 0x00 ; 0 + 2a38: 90 e0 ldi r25, 0x00 ; 0 + 2a3a: a0 e0 ldi r26, 0x00 ; 0 + 2a3c: b0 e0 ldi r27, 0x00 ; 0 + 2a3e: e6 14 cp r14, r6 + 2a40: f7 04 cpc r15, r7 + 2a42: 08 05 cpc r16, r8 + 2a44: 19 05 cpc r17, r9 + 2a46: 20 f4 brcc .+8 ; 0x2a50 <__mulsf3+0xe8> + 2a48: 81 e0 ldi r24, 0x01 ; 1 + 2a4a: 90 e0 ldi r25, 0x00 ; 0 + 2a4c: a0 e0 ldi r26, 0x00 ; 0 + 2a4e: b0 e0 ldi r27, 0x00 ; 0 + 2a50: ba 01 movw r22, r20 + 2a52: a9 01 movw r20, r18 + 2a54: 48 0f add r20, r24 + 2a56: 59 1f adc r21, r25 + 2a58: 6a 1f adc r22, r26 + 2a5a: 7b 1f adc r23, r27 + 2a5c: aa 0c add r10, r10 + 2a5e: bb 1c adc r11, r11 + 2a60: cc 1c adc r12, r12 + 2a62: dd 1c adc r13, r13 + 2a64: 97 fe sbrs r9, 7 + 2a66: 08 c0 rjmp .+16 ; 0x2a78 <__mulsf3+0x110> + 2a68: 81 e0 ldi r24, 0x01 ; 1 + 2a6a: 90 e0 ldi r25, 0x00 ; 0 + 2a6c: a0 e0 ldi r26, 0x00 ; 0 + 2a6e: b0 e0 ldi r27, 0x00 ; 0 + 2a70: a8 2a or r10, r24 + 2a72: b9 2a or r11, r25 + 2a74: ca 2a or r12, r26 + 2a76: db 2a or r13, r27 + 2a78: 31 96 adiw r30, 0x01 ; 1 + 2a7a: e0 32 cpi r30, 0x20 ; 32 + 2a7c: f1 05 cpc r31, r1 + 2a7e: 49 f0 breq .+18 ; 0x2a92 <__mulsf3+0x12a> + 2a80: 66 0c add r6, r6 + 2a82: 77 1c adc r7, r7 + 2a84: 88 1c adc r8, r8 + 2a86: 99 1c adc r9, r9 + 2a88: 56 94 lsr r5 + 2a8a: 47 94 ror r4 + 2a8c: 37 94 ror r3 + 2a8e: 27 94 ror r2 + 2a90: c3 cf rjmp .-122 ; 0x2a18 <__mulsf3+0xb0> + 2a92: fa 85 ldd r31, Y+10 ; 0x0a + 2a94: ea 89 ldd r30, Y+18 ; 0x12 + 2a96: 2b 89 ldd r18, Y+19 ; 0x13 + 2a98: 3c 89 ldd r19, Y+20 ; 0x14 + 2a9a: 8b 85 ldd r24, Y+11 ; 0x0b + 2a9c: 9c 85 ldd r25, Y+12 ; 0x0c + 2a9e: 28 0f add r18, r24 + 2aa0: 39 1f adc r19, r25 + 2aa2: 2e 5f subi r18, 0xFE ; 254 + 2aa4: 3f 4f sbci r19, 0xFF ; 255 + 2aa6: 17 c0 rjmp .+46 ; 0x2ad6 <__mulsf3+0x16e> + 2aa8: ca 01 movw r24, r20 + 2aaa: 81 70 andi r24, 0x01 ; 1 + 2aac: 90 70 andi r25, 0x00 ; 0 + 2aae: 89 2b or r24, r25 + 2ab0: 61 f0 breq .+24 ; 0x2aca <__mulsf3+0x162> + 2ab2: 16 95 lsr r17 + 2ab4: 07 95 ror r16 + 2ab6: f7 94 ror r15 + 2ab8: e7 94 ror r14 + 2aba: 80 e0 ldi r24, 0x00 ; 0 + 2abc: 90 e0 ldi r25, 0x00 ; 0 + 2abe: a0 e0 ldi r26, 0x00 ; 0 + 2ac0: b0 e8 ldi r27, 0x80 ; 128 + 2ac2: e8 2a or r14, r24 + 2ac4: f9 2a or r15, r25 + 2ac6: 0a 2b or r16, r26 + 2ac8: 1b 2b or r17, r27 + 2aca: 76 95 lsr r23 + 2acc: 67 95 ror r22 + 2ace: 57 95 ror r21 + 2ad0: 47 95 ror r20 + 2ad2: 2f 5f subi r18, 0xFF ; 255 + 2ad4: 3f 4f sbci r19, 0xFF ; 255 + 2ad6: 77 fd sbrc r23, 7 + 2ad8: e7 cf rjmp .-50 ; 0x2aa8 <__mulsf3+0x140> + 2ada: 0c c0 rjmp .+24 ; 0x2af4 <__mulsf3+0x18c> + 2adc: 44 0f add r20, r20 + 2ade: 55 1f adc r21, r21 + 2ae0: 66 1f adc r22, r22 + 2ae2: 77 1f adc r23, r23 + 2ae4: 17 fd sbrc r17, 7 + 2ae6: 41 60 ori r20, 0x01 ; 1 + 2ae8: ee 0c add r14, r14 + 2aea: ff 1c adc r15, r15 + 2aec: 00 1f adc r16, r16 + 2aee: 11 1f adc r17, r17 + 2af0: 21 50 subi r18, 0x01 ; 1 + 2af2: 30 40 sbci r19, 0x00 ; 0 + 2af4: 40 30 cpi r20, 0x00 ; 0 + 2af6: 90 e0 ldi r25, 0x00 ; 0 + 2af8: 59 07 cpc r21, r25 + 2afa: 90 e0 ldi r25, 0x00 ; 0 + 2afc: 69 07 cpc r22, r25 + 2afe: 90 e4 ldi r25, 0x40 ; 64 + 2b00: 79 07 cpc r23, r25 + 2b02: 60 f3 brcs .-40 ; 0x2adc <__mulsf3+0x174> + 2b04: 2b 8f std Y+27, r18 ; 0x1b + 2b06: 3c 8f std Y+28, r19 ; 0x1c + 2b08: db 01 movw r26, r22 + 2b0a: ca 01 movw r24, r20 + 2b0c: 8f 77 andi r24, 0x7F ; 127 + 2b0e: 90 70 andi r25, 0x00 ; 0 + 2b10: a0 70 andi r26, 0x00 ; 0 + 2b12: b0 70 andi r27, 0x00 ; 0 + 2b14: 80 34 cpi r24, 0x40 ; 64 + 2b16: 91 05 cpc r25, r1 + 2b18: a1 05 cpc r26, r1 + 2b1a: b1 05 cpc r27, r1 + 2b1c: 61 f4 brne .+24 ; 0x2b36 <__mulsf3+0x1ce> + 2b1e: 47 fd sbrc r20, 7 + 2b20: 0a c0 rjmp .+20 ; 0x2b36 <__mulsf3+0x1ce> + 2b22: e1 14 cp r14, r1 + 2b24: f1 04 cpc r15, r1 + 2b26: 01 05 cpc r16, r1 + 2b28: 11 05 cpc r17, r1 + 2b2a: 29 f0 breq .+10 ; 0x2b36 <__mulsf3+0x1ce> + 2b2c: 40 5c subi r20, 0xC0 ; 192 + 2b2e: 5f 4f sbci r21, 0xFF ; 255 + 2b30: 6f 4f sbci r22, 0xFF ; 255 + 2b32: 7f 4f sbci r23, 0xFF ; 255 + 2b34: 40 78 andi r20, 0x80 ; 128 + 2b36: 1a 8e std Y+26, r1 ; 0x1a + 2b38: fe 17 cp r31, r30 + 2b3a: 11 f0 breq .+4 ; 0x2b40 <__mulsf3+0x1d8> + 2b3c: 81 e0 ldi r24, 0x01 ; 1 + 2b3e: 8a 8f std Y+26, r24 ; 0x1a + 2b40: 4d 8f std Y+29, r20 ; 0x1d + 2b42: 5e 8f std Y+30, r21 ; 0x1e + 2b44: 6f 8f std Y+31, r22 ; 0x1f + 2b46: 78 a3 std Y+32, r23 ; 0x20 + 2b48: 83 e0 ldi r24, 0x03 ; 3 + 2b4a: 89 8f std Y+25, r24 ; 0x19 + 2b4c: ce 01 movw r24, r28 + 2b4e: 49 96 adiw r24, 0x19 ; 25 + 2b50: 0e 94 34 18 call 0x3068 ; 0x3068 <__pack_f> + 2b54: a0 96 adiw r28, 0x20 ; 32 + 2b56: e2 e1 ldi r30, 0x12 ; 18 + 2b58: 0c 94 4b 1a jmp 0x3496 ; 0x3496 <__epilogue_restores__> + +00002b5c <__divsf3>: + 2b5c: a8 e1 ldi r26, 0x18 ; 24 + 2b5e: b0 e0 ldi r27, 0x00 ; 0 + 2b60: e4 eb ldi r30, 0xB4 ; 180 + 2b62: f5 e1 ldi r31, 0x15 ; 21 + 2b64: 0c 94 37 1a jmp 0x346e ; 0x346e <__prologue_saves__+0x10> + 2b68: 69 83 std Y+1, r22 ; 0x01 + 2b6a: 7a 83 std Y+2, r23 ; 0x02 + 2b6c: 8b 83 std Y+3, r24 ; 0x03 + 2b6e: 9c 83 std Y+4, r25 ; 0x04 + 2b70: 2d 83 std Y+5, r18 ; 0x05 + 2b72: 3e 83 std Y+6, r19 ; 0x06 + 2b74: 4f 83 std Y+7, r20 ; 0x07 + 2b76: 58 87 std Y+8, r21 ; 0x08 + 2b78: b9 e0 ldi r27, 0x09 ; 9 + 2b7a: eb 2e mov r14, r27 + 2b7c: f1 2c mov r15, r1 + 2b7e: ec 0e add r14, r28 + 2b80: fd 1e adc r15, r29 + 2b82: ce 01 movw r24, r28 + 2b84: 01 96 adiw r24, 0x01 ; 1 + 2b86: b7 01 movw r22, r14 + 2b88: 0e 94 09 19 call 0x3212 ; 0x3212 <__unpack_f> + 2b8c: 8e 01 movw r16, r28 + 2b8e: 0f 5e subi r16, 0xEF ; 239 + 2b90: 1f 4f sbci r17, 0xFF ; 255 + 2b92: ce 01 movw r24, r28 + 2b94: 05 96 adiw r24, 0x05 ; 5 + 2b96: b8 01 movw r22, r16 + 2b98: 0e 94 09 19 call 0x3212 ; 0x3212 <__unpack_f> + 2b9c: 29 85 ldd r18, Y+9 ; 0x09 + 2b9e: 22 30 cpi r18, 0x02 ; 2 + 2ba0: 08 f4 brcc .+2 ; 0x2ba4 <__divsf3+0x48> + 2ba2: 7e c0 rjmp .+252 ; 0x2ca0 <__divsf3+0x144> + 2ba4: 39 89 ldd r19, Y+17 ; 0x11 + 2ba6: 32 30 cpi r19, 0x02 ; 2 + 2ba8: 10 f4 brcc .+4 ; 0x2bae <__divsf3+0x52> + 2baa: b8 01 movw r22, r16 + 2bac: 7c c0 rjmp .+248 ; 0x2ca6 <__divsf3+0x14a> + 2bae: 8a 85 ldd r24, Y+10 ; 0x0a + 2bb0: 9a 89 ldd r25, Y+18 ; 0x12 + 2bb2: 89 27 eor r24, r25 + 2bb4: 8a 87 std Y+10, r24 ; 0x0a + 2bb6: 24 30 cpi r18, 0x04 ; 4 + 2bb8: 11 f0 breq .+4 ; 0x2bbe <__divsf3+0x62> + 2bba: 22 30 cpi r18, 0x02 ; 2 + 2bbc: 31 f4 brne .+12 ; 0x2bca <__divsf3+0x6e> + 2bbe: 23 17 cp r18, r19 + 2bc0: 09 f0 breq .+2 ; 0x2bc4 <__divsf3+0x68> + 2bc2: 6e c0 rjmp .+220 ; 0x2ca0 <__divsf3+0x144> + 2bc4: 6f e8 ldi r22, 0x8F ; 143 + 2bc6: 74 e0 ldi r23, 0x04 ; 4 + 2bc8: 6e c0 rjmp .+220 ; 0x2ca6 <__divsf3+0x14a> + 2bca: 34 30 cpi r19, 0x04 ; 4 + 2bcc: 39 f4 brne .+14 ; 0x2bdc <__divsf3+0x80> + 2bce: 1d 86 std Y+13, r1 ; 0x0d + 2bd0: 1e 86 std Y+14, r1 ; 0x0e + 2bd2: 1f 86 std Y+15, r1 ; 0x0f + 2bd4: 18 8a std Y+16, r1 ; 0x10 + 2bd6: 1c 86 std Y+12, r1 ; 0x0c + 2bd8: 1b 86 std Y+11, r1 ; 0x0b + 2bda: 04 c0 rjmp .+8 ; 0x2be4 <__divsf3+0x88> + 2bdc: 32 30 cpi r19, 0x02 ; 2 + 2bde: 21 f4 brne .+8 ; 0x2be8 <__divsf3+0x8c> + 2be0: 84 e0 ldi r24, 0x04 ; 4 + 2be2: 89 87 std Y+9, r24 ; 0x09 + 2be4: b7 01 movw r22, r14 + 2be6: 5f c0 rjmp .+190 ; 0x2ca6 <__divsf3+0x14a> + 2be8: 2b 85 ldd r18, Y+11 ; 0x0b + 2bea: 3c 85 ldd r19, Y+12 ; 0x0c + 2bec: 8b 89 ldd r24, Y+19 ; 0x13 + 2bee: 9c 89 ldd r25, Y+20 ; 0x14 + 2bf0: 28 1b sub r18, r24 + 2bf2: 39 0b sbc r19, r25 + 2bf4: 3c 87 std Y+12, r19 ; 0x0c + 2bf6: 2b 87 std Y+11, r18 ; 0x0b + 2bf8: ed 84 ldd r14, Y+13 ; 0x0d + 2bfa: fe 84 ldd r15, Y+14 ; 0x0e + 2bfc: 0f 85 ldd r16, Y+15 ; 0x0f + 2bfe: 18 89 ldd r17, Y+16 ; 0x10 + 2c00: ad 88 ldd r10, Y+21 ; 0x15 + 2c02: be 88 ldd r11, Y+22 ; 0x16 + 2c04: cf 88 ldd r12, Y+23 ; 0x17 + 2c06: d8 8c ldd r13, Y+24 ; 0x18 + 2c08: ea 14 cp r14, r10 + 2c0a: fb 04 cpc r15, r11 + 2c0c: 0c 05 cpc r16, r12 + 2c0e: 1d 05 cpc r17, r13 + 2c10: 40 f4 brcc .+16 ; 0x2c22 <__divsf3+0xc6> + 2c12: ee 0c add r14, r14 + 2c14: ff 1c adc r15, r15 + 2c16: 00 1f adc r16, r16 + 2c18: 11 1f adc r17, r17 + 2c1a: 21 50 subi r18, 0x01 ; 1 + 2c1c: 30 40 sbci r19, 0x00 ; 0 + 2c1e: 3c 87 std Y+12, r19 ; 0x0c + 2c20: 2b 87 std Y+11, r18 ; 0x0b + 2c22: 20 e0 ldi r18, 0x00 ; 0 + 2c24: 30 e0 ldi r19, 0x00 ; 0 + 2c26: 40 e0 ldi r20, 0x00 ; 0 + 2c28: 50 e0 ldi r21, 0x00 ; 0 + 2c2a: 80 e0 ldi r24, 0x00 ; 0 + 2c2c: 90 e0 ldi r25, 0x00 ; 0 + 2c2e: a0 e0 ldi r26, 0x00 ; 0 + 2c30: b0 e4 ldi r27, 0x40 ; 64 + 2c32: 60 e0 ldi r22, 0x00 ; 0 + 2c34: 70 e0 ldi r23, 0x00 ; 0 + 2c36: ea 14 cp r14, r10 + 2c38: fb 04 cpc r15, r11 + 2c3a: 0c 05 cpc r16, r12 + 2c3c: 1d 05 cpc r17, r13 + 2c3e: 40 f0 brcs .+16 ; 0x2c50 <__divsf3+0xf4> + 2c40: 28 2b or r18, r24 + 2c42: 39 2b or r19, r25 + 2c44: 4a 2b or r20, r26 + 2c46: 5b 2b or r21, r27 + 2c48: ea 18 sub r14, r10 + 2c4a: fb 08 sbc r15, r11 + 2c4c: 0c 09 sbc r16, r12 + 2c4e: 1d 09 sbc r17, r13 + 2c50: b6 95 lsr r27 + 2c52: a7 95 ror r26 + 2c54: 97 95 ror r25 + 2c56: 87 95 ror r24 + 2c58: ee 0c add r14, r14 + 2c5a: ff 1c adc r15, r15 + 2c5c: 00 1f adc r16, r16 + 2c5e: 11 1f adc r17, r17 + 2c60: 6f 5f subi r22, 0xFF ; 255 + 2c62: 7f 4f sbci r23, 0xFF ; 255 + 2c64: 6f 31 cpi r22, 0x1F ; 31 + 2c66: 71 05 cpc r23, r1 + 2c68: 31 f7 brne .-52 ; 0x2c36 <__divsf3+0xda> + 2c6a: da 01 movw r26, r20 + 2c6c: c9 01 movw r24, r18 + 2c6e: 8f 77 andi r24, 0x7F ; 127 + 2c70: 90 70 andi r25, 0x00 ; 0 + 2c72: a0 70 andi r26, 0x00 ; 0 + 2c74: b0 70 andi r27, 0x00 ; 0 + 2c76: 80 34 cpi r24, 0x40 ; 64 + 2c78: 91 05 cpc r25, r1 + 2c7a: a1 05 cpc r26, r1 + 2c7c: b1 05 cpc r27, r1 + 2c7e: 61 f4 brne .+24 ; 0x2c98 <__divsf3+0x13c> + 2c80: 27 fd sbrc r18, 7 + 2c82: 0a c0 rjmp .+20 ; 0x2c98 <__divsf3+0x13c> + 2c84: e1 14 cp r14, r1 + 2c86: f1 04 cpc r15, r1 + 2c88: 01 05 cpc r16, r1 + 2c8a: 11 05 cpc r17, r1 + 2c8c: 29 f0 breq .+10 ; 0x2c98 <__divsf3+0x13c> + 2c8e: 20 5c subi r18, 0xC0 ; 192 + 2c90: 3f 4f sbci r19, 0xFF ; 255 + 2c92: 4f 4f sbci r20, 0xFF ; 255 + 2c94: 5f 4f sbci r21, 0xFF ; 255 + 2c96: 20 78 andi r18, 0x80 ; 128 + 2c98: 2d 87 std Y+13, r18 ; 0x0d + 2c9a: 3e 87 std Y+14, r19 ; 0x0e + 2c9c: 4f 87 std Y+15, r20 ; 0x0f + 2c9e: 58 8b std Y+16, r21 ; 0x10 + 2ca0: be 01 movw r22, r28 + 2ca2: 67 5f subi r22, 0xF7 ; 247 + 2ca4: 7f 4f sbci r23, 0xFF ; 255 + 2ca6: cb 01 movw r24, r22 + 2ca8: 0e 94 34 18 call 0x3068 ; 0x3068 <__pack_f> + 2cac: 68 96 adiw r28, 0x18 ; 24 + 2cae: ea e0 ldi r30, 0x0A ; 10 + 2cb0: 0c 94 53 1a jmp 0x34a6 ; 0x34a6 <__epilogue_restores__+0x10> + +00002cb4 <__gesf2>: + 2cb4: a8 e1 ldi r26, 0x18 ; 24 + 2cb6: b0 e0 ldi r27, 0x00 ; 0 + 2cb8: e0 e6 ldi r30, 0x60 ; 96 + 2cba: f6 e1 ldi r31, 0x16 ; 22 + 2cbc: 0c 94 3b 1a jmp 0x3476 ; 0x3476 <__prologue_saves__+0x18> + 2cc0: 69 83 std Y+1, r22 ; 0x01 + 2cc2: 7a 83 std Y+2, r23 ; 0x02 + 2cc4: 8b 83 std Y+3, r24 ; 0x03 + 2cc6: 9c 83 std Y+4, r25 ; 0x04 + 2cc8: 2d 83 std Y+5, r18 ; 0x05 + 2cca: 3e 83 std Y+6, r19 ; 0x06 + 2ccc: 4f 83 std Y+7, r20 ; 0x07 + 2cce: 58 87 std Y+8, r21 ; 0x08 + 2cd0: 89 e0 ldi r24, 0x09 ; 9 + 2cd2: e8 2e mov r14, r24 + 2cd4: f1 2c mov r15, r1 + 2cd6: ec 0e add r14, r28 + 2cd8: fd 1e adc r15, r29 + 2cda: ce 01 movw r24, r28 + 2cdc: 01 96 adiw r24, 0x01 ; 1 + 2cde: b7 01 movw r22, r14 + 2ce0: 0e 94 09 19 call 0x3212 ; 0x3212 <__unpack_f> + 2ce4: 8e 01 movw r16, r28 + 2ce6: 0f 5e subi r16, 0xEF ; 239 + 2ce8: 1f 4f sbci r17, 0xFF ; 255 + 2cea: ce 01 movw r24, r28 + 2cec: 05 96 adiw r24, 0x05 ; 5 + 2cee: b8 01 movw r22, r16 + 2cf0: 0e 94 09 19 call 0x3212 ; 0x3212 <__unpack_f> + 2cf4: 89 85 ldd r24, Y+9 ; 0x09 + 2cf6: 82 30 cpi r24, 0x02 ; 2 + 2cf8: 40 f0 brcs .+16 ; 0x2d0a <__gesf2+0x56> + 2cfa: 89 89 ldd r24, Y+17 ; 0x11 + 2cfc: 82 30 cpi r24, 0x02 ; 2 + 2cfe: 28 f0 brcs .+10 ; 0x2d0a <__gesf2+0x56> + 2d00: c7 01 movw r24, r14 + 2d02: b8 01 movw r22, r16 + 2d04: 0e 94 81 19 call 0x3302 ; 0x3302 <__fpcmp_parts_f> + 2d08: 01 c0 rjmp .+2 ; 0x2d0c <__gesf2+0x58> + 2d0a: 8f ef ldi r24, 0xFF ; 255 + 2d0c: 68 96 adiw r28, 0x18 ; 24 + 2d0e: e6 e0 ldi r30, 0x06 ; 6 + 2d10: 0c 94 57 1a jmp 0x34ae ; 0x34ae <__epilogue_restores__+0x18> + +00002d14 <__ltsf2>: + 2d14: a8 e1 ldi r26, 0x18 ; 24 + 2d16: b0 e0 ldi r27, 0x00 ; 0 + 2d18: e0 e9 ldi r30, 0x90 ; 144 + 2d1a: f6 e1 ldi r31, 0x16 ; 22 + 2d1c: 0c 94 3b 1a jmp 0x3476 ; 0x3476 <__prologue_saves__+0x18> + 2d20: 69 83 std Y+1, r22 ; 0x01 + 2d22: 7a 83 std Y+2, r23 ; 0x02 + 2d24: 8b 83 std Y+3, r24 ; 0x03 + 2d26: 9c 83 std Y+4, r25 ; 0x04 + 2d28: 2d 83 std Y+5, r18 ; 0x05 + 2d2a: 3e 83 std Y+6, r19 ; 0x06 + 2d2c: 4f 83 std Y+7, r20 ; 0x07 + 2d2e: 58 87 std Y+8, r21 ; 0x08 + 2d30: 89 e0 ldi r24, 0x09 ; 9 + 2d32: e8 2e mov r14, r24 + 2d34: f1 2c mov r15, r1 + 2d36: ec 0e add r14, r28 + 2d38: fd 1e adc r15, r29 + 2d3a: ce 01 movw r24, r28 + 2d3c: 01 96 adiw r24, 0x01 ; 1 + 2d3e: b7 01 movw r22, r14 + 2d40: 0e 94 09 19 call 0x3212 ; 0x3212 <__unpack_f> + 2d44: 8e 01 movw r16, r28 + 2d46: 0f 5e subi r16, 0xEF ; 239 + 2d48: 1f 4f sbci r17, 0xFF ; 255 + 2d4a: ce 01 movw r24, r28 + 2d4c: 05 96 adiw r24, 0x05 ; 5 + 2d4e: b8 01 movw r22, r16 + 2d50: 0e 94 09 19 call 0x3212 ; 0x3212 <__unpack_f> + 2d54: 89 85 ldd r24, Y+9 ; 0x09 + 2d56: 82 30 cpi r24, 0x02 ; 2 + 2d58: 40 f0 brcs .+16 ; 0x2d6a <__ltsf2+0x56> + 2d5a: 89 89 ldd r24, Y+17 ; 0x11 + 2d5c: 82 30 cpi r24, 0x02 ; 2 + 2d5e: 28 f0 brcs .+10 ; 0x2d6a <__ltsf2+0x56> + 2d60: c7 01 movw r24, r14 + 2d62: b8 01 movw r22, r16 + 2d64: 0e 94 81 19 call 0x3302 ; 0x3302 <__fpcmp_parts_f> + 2d68: 01 c0 rjmp .+2 ; 0x2d6c <__ltsf2+0x58> + 2d6a: 81 e0 ldi r24, 0x01 ; 1 + 2d6c: 68 96 adiw r28, 0x18 ; 24 + 2d6e: e6 e0 ldi r30, 0x06 ; 6 + 2d70: 0c 94 57 1a jmp 0x34ae ; 0x34ae <__epilogue_restores__+0x18> + +00002d74 <__floatsisf>: + 2d74: a8 e0 ldi r26, 0x08 ; 8 + 2d76: b0 e0 ldi r27, 0x00 ; 0 + 2d78: e0 ec ldi r30, 0xC0 ; 192 + 2d7a: f6 e1 ldi r31, 0x16 ; 22 + 2d7c: 0c 94 38 1a jmp 0x3470 ; 0x3470 <__prologue_saves__+0x12> + 2d80: 9b 01 movw r18, r22 + 2d82: ac 01 movw r20, r24 + 2d84: 83 e0 ldi r24, 0x03 ; 3 + 2d86: 89 83 std Y+1, r24 ; 0x01 + 2d88: da 01 movw r26, r20 + 2d8a: c9 01 movw r24, r18 + 2d8c: 88 27 eor r24, r24 + 2d8e: b7 fd sbrc r27, 7 + 2d90: 83 95 inc r24 + 2d92: 99 27 eor r25, r25 + 2d94: aa 27 eor r26, r26 + 2d96: bb 27 eor r27, r27 + 2d98: b8 2e mov r11, r24 + 2d9a: 21 15 cp r18, r1 + 2d9c: 31 05 cpc r19, r1 + 2d9e: 41 05 cpc r20, r1 + 2da0: 51 05 cpc r21, r1 + 2da2: 19 f4 brne .+6 ; 0x2daa <__floatsisf+0x36> + 2da4: 82 e0 ldi r24, 0x02 ; 2 + 2da6: 89 83 std Y+1, r24 ; 0x01 + 2da8: 3a c0 rjmp .+116 ; 0x2e1e <__floatsisf+0xaa> + 2daa: 88 23 and r24, r24 + 2dac: a9 f0 breq .+42 ; 0x2dd8 <__floatsisf+0x64> + 2dae: 20 30 cpi r18, 0x00 ; 0 + 2db0: 80 e0 ldi r24, 0x00 ; 0 + 2db2: 38 07 cpc r19, r24 + 2db4: 80 e0 ldi r24, 0x00 ; 0 + 2db6: 48 07 cpc r20, r24 + 2db8: 80 e8 ldi r24, 0x80 ; 128 + 2dba: 58 07 cpc r21, r24 + 2dbc: 29 f4 brne .+10 ; 0x2dc8 <__floatsisf+0x54> + 2dbe: 60 e0 ldi r22, 0x00 ; 0 + 2dc0: 70 e0 ldi r23, 0x00 ; 0 + 2dc2: 80 e0 ldi r24, 0x00 ; 0 + 2dc4: 9f ec ldi r25, 0xCF ; 207 + 2dc6: 30 c0 rjmp .+96 ; 0x2e28 <__floatsisf+0xb4> + 2dc8: ee 24 eor r14, r14 + 2dca: ff 24 eor r15, r15 + 2dcc: 87 01 movw r16, r14 + 2dce: e2 1a sub r14, r18 + 2dd0: f3 0a sbc r15, r19 + 2dd2: 04 0b sbc r16, r20 + 2dd4: 15 0b sbc r17, r21 + 2dd6: 02 c0 rjmp .+4 ; 0x2ddc <__floatsisf+0x68> + 2dd8: 79 01 movw r14, r18 + 2dda: 8a 01 movw r16, r20 + 2ddc: 8e e1 ldi r24, 0x1E ; 30 + 2dde: c8 2e mov r12, r24 + 2de0: d1 2c mov r13, r1 + 2de2: dc 82 std Y+4, r13 ; 0x04 + 2de4: cb 82 std Y+3, r12 ; 0x03 + 2de6: ed 82 std Y+5, r14 ; 0x05 + 2de8: fe 82 std Y+6, r15 ; 0x06 + 2dea: 0f 83 std Y+7, r16 ; 0x07 + 2dec: 18 87 std Y+8, r17 ; 0x08 + 2dee: c8 01 movw r24, r16 + 2df0: b7 01 movw r22, r14 + 2df2: 0e 94 e5 17 call 0x2fca ; 0x2fca <__clzsi2> + 2df6: 01 97 sbiw r24, 0x01 ; 1 + 2df8: 18 16 cp r1, r24 + 2dfa: 19 06 cpc r1, r25 + 2dfc: 84 f4 brge .+32 ; 0x2e1e <__floatsisf+0xaa> + 2dfe: 08 2e mov r0, r24 + 2e00: 04 c0 rjmp .+8 ; 0x2e0a <__floatsisf+0x96> + 2e02: ee 0c add r14, r14 + 2e04: ff 1c adc r15, r15 + 2e06: 00 1f adc r16, r16 + 2e08: 11 1f adc r17, r17 + 2e0a: 0a 94 dec r0 + 2e0c: d2 f7 brpl .-12 ; 0x2e02 <__floatsisf+0x8e> + 2e0e: ed 82 std Y+5, r14 ; 0x05 + 2e10: fe 82 std Y+6, r15 ; 0x06 + 2e12: 0f 83 std Y+7, r16 ; 0x07 + 2e14: 18 87 std Y+8, r17 ; 0x08 + 2e16: c8 1a sub r12, r24 + 2e18: d9 0a sbc r13, r25 + 2e1a: dc 82 std Y+4, r13 ; 0x04 + 2e1c: cb 82 std Y+3, r12 ; 0x03 + 2e1e: ba 82 std Y+2, r11 ; 0x02 + 2e20: ce 01 movw r24, r28 + 2e22: 01 96 adiw r24, 0x01 ; 1 + 2e24: 0e 94 34 18 call 0x3068 ; 0x3068 <__pack_f> + 2e28: 28 96 adiw r28, 0x08 ; 8 + 2e2a: e9 e0 ldi r30, 0x09 ; 9 + 2e2c: 0c 94 54 1a jmp 0x34a8 ; 0x34a8 <__epilogue_restores__+0x12> + +00002e30 <__fixsfsi>: + 2e30: ac e0 ldi r26, 0x0C ; 12 + 2e32: b0 e0 ldi r27, 0x00 ; 0 + 2e34: ee e1 ldi r30, 0x1E ; 30 + 2e36: f7 e1 ldi r31, 0x17 ; 23 + 2e38: 0c 94 3f 1a jmp 0x347e ; 0x347e <__prologue_saves__+0x20> + 2e3c: 69 83 std Y+1, r22 ; 0x01 + 2e3e: 7a 83 std Y+2, r23 ; 0x02 + 2e40: 8b 83 std Y+3, r24 ; 0x03 + 2e42: 9c 83 std Y+4, r25 ; 0x04 + 2e44: ce 01 movw r24, r28 + 2e46: 01 96 adiw r24, 0x01 ; 1 + 2e48: be 01 movw r22, r28 + 2e4a: 6b 5f subi r22, 0xFB ; 251 + 2e4c: 7f 4f sbci r23, 0xFF ; 255 + 2e4e: 0e 94 09 19 call 0x3212 ; 0x3212 <__unpack_f> + 2e52: 8d 81 ldd r24, Y+5 ; 0x05 + 2e54: 82 30 cpi r24, 0x02 ; 2 + 2e56: 61 f1 breq .+88 ; 0x2eb0 <__fixsfsi+0x80> + 2e58: 82 30 cpi r24, 0x02 ; 2 + 2e5a: 50 f1 brcs .+84 ; 0x2eb0 <__fixsfsi+0x80> + 2e5c: 84 30 cpi r24, 0x04 ; 4 + 2e5e: 21 f4 brne .+8 ; 0x2e68 <__fixsfsi+0x38> + 2e60: 8e 81 ldd r24, Y+6 ; 0x06 + 2e62: 88 23 and r24, r24 + 2e64: 51 f1 breq .+84 ; 0x2eba <__fixsfsi+0x8a> + 2e66: 2e c0 rjmp .+92 ; 0x2ec4 <__fixsfsi+0x94> + 2e68: 2f 81 ldd r18, Y+7 ; 0x07 + 2e6a: 38 85 ldd r19, Y+8 ; 0x08 + 2e6c: 37 fd sbrc r19, 7 + 2e6e: 20 c0 rjmp .+64 ; 0x2eb0 <__fixsfsi+0x80> + 2e70: 6e 81 ldd r22, Y+6 ; 0x06 + 2e72: 2f 31 cpi r18, 0x1F ; 31 + 2e74: 31 05 cpc r19, r1 + 2e76: 1c f0 brlt .+6 ; 0x2e7e <__fixsfsi+0x4e> + 2e78: 66 23 and r22, r22 + 2e7a: f9 f0 breq .+62 ; 0x2eba <__fixsfsi+0x8a> + 2e7c: 23 c0 rjmp .+70 ; 0x2ec4 <__fixsfsi+0x94> + 2e7e: 8e e1 ldi r24, 0x1E ; 30 + 2e80: 90 e0 ldi r25, 0x00 ; 0 + 2e82: 82 1b sub r24, r18 + 2e84: 93 0b sbc r25, r19 + 2e86: 29 85 ldd r18, Y+9 ; 0x09 + 2e88: 3a 85 ldd r19, Y+10 ; 0x0a + 2e8a: 4b 85 ldd r20, Y+11 ; 0x0b + 2e8c: 5c 85 ldd r21, Y+12 ; 0x0c + 2e8e: 04 c0 rjmp .+8 ; 0x2e98 <__fixsfsi+0x68> + 2e90: 56 95 lsr r21 + 2e92: 47 95 ror r20 + 2e94: 37 95 ror r19 + 2e96: 27 95 ror r18 + 2e98: 8a 95 dec r24 + 2e9a: d2 f7 brpl .-12 ; 0x2e90 <__fixsfsi+0x60> + 2e9c: 66 23 and r22, r22 + 2e9e: b1 f0 breq .+44 ; 0x2ecc <__fixsfsi+0x9c> + 2ea0: 50 95 com r21 + 2ea2: 40 95 com r20 + 2ea4: 30 95 com r19 + 2ea6: 21 95 neg r18 + 2ea8: 3f 4f sbci r19, 0xFF ; 255 + 2eaa: 4f 4f sbci r20, 0xFF ; 255 + 2eac: 5f 4f sbci r21, 0xFF ; 255 + 2eae: 0e c0 rjmp .+28 ; 0x2ecc <__fixsfsi+0x9c> + 2eb0: 20 e0 ldi r18, 0x00 ; 0 + 2eb2: 30 e0 ldi r19, 0x00 ; 0 + 2eb4: 40 e0 ldi r20, 0x00 ; 0 + 2eb6: 50 e0 ldi r21, 0x00 ; 0 + 2eb8: 09 c0 rjmp .+18 ; 0x2ecc <__fixsfsi+0x9c> + 2eba: 2f ef ldi r18, 0xFF ; 255 + 2ebc: 3f ef ldi r19, 0xFF ; 255 + 2ebe: 4f ef ldi r20, 0xFF ; 255 + 2ec0: 5f e7 ldi r21, 0x7F ; 127 + 2ec2: 04 c0 rjmp .+8 ; 0x2ecc <__fixsfsi+0x9c> + 2ec4: 20 e0 ldi r18, 0x00 ; 0 + 2ec6: 30 e0 ldi r19, 0x00 ; 0 + 2ec8: 40 e0 ldi r20, 0x00 ; 0 + 2eca: 50 e8 ldi r21, 0x80 ; 128 + 2ecc: b9 01 movw r22, r18 + 2ece: ca 01 movw r24, r20 + 2ed0: 2c 96 adiw r28, 0x0c ; 12 + 2ed2: e2 e0 ldi r30, 0x02 ; 2 + 2ed4: 0c 94 5b 1a jmp 0x34b6 ; 0x34b6 <__epilogue_restores__+0x20> + +00002ed8 <__floatunsisf>: + 2ed8: a8 e0 ldi r26, 0x08 ; 8 + 2eda: b0 e0 ldi r27, 0x00 ; 0 + 2edc: e2 e7 ldi r30, 0x72 ; 114 + 2ede: f7 e1 ldi r31, 0x17 ; 23 + 2ee0: 0c 94 37 1a jmp 0x346e ; 0x346e <__prologue_saves__+0x10> + 2ee4: 7b 01 movw r14, r22 + 2ee6: 8c 01 movw r16, r24 + 2ee8: 61 15 cp r22, r1 + 2eea: 71 05 cpc r23, r1 + 2eec: 81 05 cpc r24, r1 + 2eee: 91 05 cpc r25, r1 + 2ef0: 19 f4 brne .+6 ; 0x2ef8 <__floatunsisf+0x20> + 2ef2: 82 e0 ldi r24, 0x02 ; 2 + 2ef4: 89 83 std Y+1, r24 ; 0x01 + 2ef6: 60 c0 rjmp .+192 ; 0x2fb8 <__floatunsisf+0xe0> + 2ef8: 83 e0 ldi r24, 0x03 ; 3 + 2efa: 89 83 std Y+1, r24 ; 0x01 + 2efc: 8e e1 ldi r24, 0x1E ; 30 + 2efe: c8 2e mov r12, r24 + 2f00: d1 2c mov r13, r1 + 2f02: dc 82 std Y+4, r13 ; 0x04 + 2f04: cb 82 std Y+3, r12 ; 0x03 + 2f06: ed 82 std Y+5, r14 ; 0x05 + 2f08: fe 82 std Y+6, r15 ; 0x06 + 2f0a: 0f 83 std Y+7, r16 ; 0x07 + 2f0c: 18 87 std Y+8, r17 ; 0x08 + 2f0e: c8 01 movw r24, r16 + 2f10: b7 01 movw r22, r14 + 2f12: 0e 94 e5 17 call 0x2fca ; 0x2fca <__clzsi2> + 2f16: fc 01 movw r30, r24 + 2f18: 31 97 sbiw r30, 0x01 ; 1 + 2f1a: f7 ff sbrs r31, 7 + 2f1c: 3b c0 rjmp .+118 ; 0x2f94 <__floatunsisf+0xbc> + 2f1e: 22 27 eor r18, r18 + 2f20: 33 27 eor r19, r19 + 2f22: 2e 1b sub r18, r30 + 2f24: 3f 0b sbc r19, r31 + 2f26: 57 01 movw r10, r14 + 2f28: 68 01 movw r12, r16 + 2f2a: 02 2e mov r0, r18 + 2f2c: 04 c0 rjmp .+8 ; 0x2f36 <__floatunsisf+0x5e> + 2f2e: d6 94 lsr r13 + 2f30: c7 94 ror r12 + 2f32: b7 94 ror r11 + 2f34: a7 94 ror r10 + 2f36: 0a 94 dec r0 + 2f38: d2 f7 brpl .-12 ; 0x2f2e <__floatunsisf+0x56> + 2f3a: 40 e0 ldi r20, 0x00 ; 0 + 2f3c: 50 e0 ldi r21, 0x00 ; 0 + 2f3e: 60 e0 ldi r22, 0x00 ; 0 + 2f40: 70 e0 ldi r23, 0x00 ; 0 + 2f42: 81 e0 ldi r24, 0x01 ; 1 + 2f44: 90 e0 ldi r25, 0x00 ; 0 + 2f46: a0 e0 ldi r26, 0x00 ; 0 + 2f48: b0 e0 ldi r27, 0x00 ; 0 + 2f4a: 04 c0 rjmp .+8 ; 0x2f54 <__floatunsisf+0x7c> + 2f4c: 88 0f add r24, r24 + 2f4e: 99 1f adc r25, r25 + 2f50: aa 1f adc r26, r26 + 2f52: bb 1f adc r27, r27 + 2f54: 2a 95 dec r18 + 2f56: d2 f7 brpl .-12 ; 0x2f4c <__floatunsisf+0x74> + 2f58: 01 97 sbiw r24, 0x01 ; 1 + 2f5a: a1 09 sbc r26, r1 + 2f5c: b1 09 sbc r27, r1 + 2f5e: 8e 21 and r24, r14 + 2f60: 9f 21 and r25, r15 + 2f62: a0 23 and r26, r16 + 2f64: b1 23 and r27, r17 + 2f66: 00 97 sbiw r24, 0x00 ; 0 + 2f68: a1 05 cpc r26, r1 + 2f6a: b1 05 cpc r27, r1 + 2f6c: 21 f0 breq .+8 ; 0x2f76 <__floatunsisf+0x9e> + 2f6e: 41 e0 ldi r20, 0x01 ; 1 + 2f70: 50 e0 ldi r21, 0x00 ; 0 + 2f72: 60 e0 ldi r22, 0x00 ; 0 + 2f74: 70 e0 ldi r23, 0x00 ; 0 + 2f76: 4a 29 or r20, r10 + 2f78: 5b 29 or r21, r11 + 2f7a: 6c 29 or r22, r12 + 2f7c: 7d 29 or r23, r13 + 2f7e: 4d 83 std Y+5, r20 ; 0x05 + 2f80: 5e 83 std Y+6, r21 ; 0x06 + 2f82: 6f 83 std Y+7, r22 ; 0x07 + 2f84: 78 87 std Y+8, r23 ; 0x08 + 2f86: 8e e1 ldi r24, 0x1E ; 30 + 2f88: 90 e0 ldi r25, 0x00 ; 0 + 2f8a: 8e 1b sub r24, r30 + 2f8c: 9f 0b sbc r25, r31 + 2f8e: 9c 83 std Y+4, r25 ; 0x04 + 2f90: 8b 83 std Y+3, r24 ; 0x03 + 2f92: 12 c0 rjmp .+36 ; 0x2fb8 <__floatunsisf+0xe0> + 2f94: 30 97 sbiw r30, 0x00 ; 0 + 2f96: 81 f0 breq .+32 ; 0x2fb8 <__floatunsisf+0xe0> + 2f98: 0e 2e mov r0, r30 + 2f9a: 04 c0 rjmp .+8 ; 0x2fa4 <__floatunsisf+0xcc> + 2f9c: ee 0c add r14, r14 + 2f9e: ff 1c adc r15, r15 + 2fa0: 00 1f adc r16, r16 + 2fa2: 11 1f adc r17, r17 + 2fa4: 0a 94 dec r0 + 2fa6: d2 f7 brpl .-12 ; 0x2f9c <__floatunsisf+0xc4> + 2fa8: ed 82 std Y+5, r14 ; 0x05 + 2faa: fe 82 std Y+6, r15 ; 0x06 + 2fac: 0f 83 std Y+7, r16 ; 0x07 + 2fae: 18 87 std Y+8, r17 ; 0x08 + 2fb0: ce 1a sub r12, r30 + 2fb2: df 0a sbc r13, r31 + 2fb4: dc 82 std Y+4, r13 ; 0x04 + 2fb6: cb 82 std Y+3, r12 ; 0x03 + 2fb8: 1a 82 std Y+2, r1 ; 0x02 + 2fba: ce 01 movw r24, r28 + 2fbc: 01 96 adiw r24, 0x01 ; 1 + 2fbe: 0e 94 34 18 call 0x3068 ; 0x3068 <__pack_f> + 2fc2: 28 96 adiw r28, 0x08 ; 8 + 2fc4: ea e0 ldi r30, 0x0A ; 10 + 2fc6: 0c 94 53 1a jmp 0x34a6 ; 0x34a6 <__epilogue_restores__+0x10> + +00002fca <__clzsi2>: + 2fca: ef 92 push r14 + 2fcc: ff 92 push r15 + 2fce: 0f 93 push r16 + 2fd0: 1f 93 push r17 + 2fd2: 7b 01 movw r14, r22 + 2fd4: 8c 01 movw r16, r24 + 2fd6: 80 e0 ldi r24, 0x00 ; 0 + 2fd8: e8 16 cp r14, r24 + 2fda: 80 e0 ldi r24, 0x00 ; 0 + 2fdc: f8 06 cpc r15, r24 + 2fde: 81 e0 ldi r24, 0x01 ; 1 + 2fe0: 08 07 cpc r16, r24 + 2fe2: 80 e0 ldi r24, 0x00 ; 0 + 2fe4: 18 07 cpc r17, r24 + 2fe6: 88 f4 brcc .+34 ; 0x300a <__clzsi2+0x40> + 2fe8: 8f ef ldi r24, 0xFF ; 255 + 2fea: e8 16 cp r14, r24 + 2fec: f1 04 cpc r15, r1 + 2fee: 01 05 cpc r16, r1 + 2ff0: 11 05 cpc r17, r1 + 2ff2: 31 f0 breq .+12 ; 0x3000 <__clzsi2+0x36> + 2ff4: 28 f0 brcs .+10 ; 0x3000 <__clzsi2+0x36> + 2ff6: 88 e0 ldi r24, 0x08 ; 8 + 2ff8: 90 e0 ldi r25, 0x00 ; 0 + 2ffa: a0 e0 ldi r26, 0x00 ; 0 + 2ffc: b0 e0 ldi r27, 0x00 ; 0 + 2ffe: 17 c0 rjmp .+46 ; 0x302e <__clzsi2+0x64> + 3000: 80 e0 ldi r24, 0x00 ; 0 + 3002: 90 e0 ldi r25, 0x00 ; 0 + 3004: a0 e0 ldi r26, 0x00 ; 0 + 3006: b0 e0 ldi r27, 0x00 ; 0 + 3008: 12 c0 rjmp .+36 ; 0x302e <__clzsi2+0x64> + 300a: 80 e0 ldi r24, 0x00 ; 0 + 300c: e8 16 cp r14, r24 + 300e: 80 e0 ldi r24, 0x00 ; 0 + 3010: f8 06 cpc r15, r24 + 3012: 80 e0 ldi r24, 0x00 ; 0 + 3014: 08 07 cpc r16, r24 + 3016: 81 e0 ldi r24, 0x01 ; 1 + 3018: 18 07 cpc r17, r24 + 301a: 28 f0 brcs .+10 ; 0x3026 <__clzsi2+0x5c> + 301c: 88 e1 ldi r24, 0x18 ; 24 + 301e: 90 e0 ldi r25, 0x00 ; 0 + 3020: a0 e0 ldi r26, 0x00 ; 0 + 3022: b0 e0 ldi r27, 0x00 ; 0 + 3024: 04 c0 rjmp .+8 ; 0x302e <__clzsi2+0x64> + 3026: 80 e1 ldi r24, 0x10 ; 16 + 3028: 90 e0 ldi r25, 0x00 ; 0 + 302a: a0 e0 ldi r26, 0x00 ; 0 + 302c: b0 e0 ldi r27, 0x00 ; 0 + 302e: 20 e2 ldi r18, 0x20 ; 32 + 3030: 30 e0 ldi r19, 0x00 ; 0 + 3032: 40 e0 ldi r20, 0x00 ; 0 + 3034: 50 e0 ldi r21, 0x00 ; 0 + 3036: 28 1b sub r18, r24 + 3038: 39 0b sbc r19, r25 + 303a: 4a 0b sbc r20, r26 + 303c: 5b 0b sbc r21, r27 + 303e: 04 c0 rjmp .+8 ; 0x3048 <__clzsi2+0x7e> + 3040: 16 95 lsr r17 + 3042: 07 95 ror r16 + 3044: f7 94 ror r15 + 3046: e7 94 ror r14 + 3048: 8a 95 dec r24 + 304a: d2 f7 brpl .-12 ; 0x3040 <__clzsi2+0x76> + 304c: f7 01 movw r30, r14 + 304e: e9 56 subi r30, 0x69 ; 105 + 3050: fb 4f sbci r31, 0xFB ; 251 + 3052: 80 81 ld r24, Z + 3054: 28 1b sub r18, r24 + 3056: 31 09 sbc r19, r1 + 3058: 41 09 sbc r20, r1 + 305a: 51 09 sbc r21, r1 + 305c: c9 01 movw r24, r18 + 305e: 1f 91 pop r17 + 3060: 0f 91 pop r16 + 3062: ff 90 pop r15 + 3064: ef 90 pop r14 + 3066: 08 95 ret + +00003068 <__pack_f>: + 3068: df 92 push r13 + 306a: ef 92 push r14 + 306c: ff 92 push r15 + 306e: 0f 93 push r16 + 3070: 1f 93 push r17 + 3072: fc 01 movw r30, r24 + 3074: e4 80 ldd r14, Z+4 ; 0x04 + 3076: f5 80 ldd r15, Z+5 ; 0x05 + 3078: 06 81 ldd r16, Z+6 ; 0x06 + 307a: 17 81 ldd r17, Z+7 ; 0x07 + 307c: d1 80 ldd r13, Z+1 ; 0x01 + 307e: 80 81 ld r24, Z + 3080: 82 30 cpi r24, 0x02 ; 2 + 3082: 48 f4 brcc .+18 ; 0x3096 <__pack_f+0x2e> + 3084: 80 e0 ldi r24, 0x00 ; 0 + 3086: 90 e0 ldi r25, 0x00 ; 0 + 3088: a0 e1 ldi r26, 0x10 ; 16 + 308a: b0 e0 ldi r27, 0x00 ; 0 + 308c: e8 2a or r14, r24 + 308e: f9 2a or r15, r25 + 3090: 0a 2b or r16, r26 + 3092: 1b 2b or r17, r27 + 3094: a5 c0 rjmp .+330 ; 0x31e0 <__pack_f+0x178> + 3096: 84 30 cpi r24, 0x04 ; 4 + 3098: 09 f4 brne .+2 ; 0x309c <__pack_f+0x34> + 309a: 9f c0 rjmp .+318 ; 0x31da <__pack_f+0x172> + 309c: 82 30 cpi r24, 0x02 ; 2 + 309e: 21 f4 brne .+8 ; 0x30a8 <__pack_f+0x40> + 30a0: ee 24 eor r14, r14 + 30a2: ff 24 eor r15, r15 + 30a4: 87 01 movw r16, r14 + 30a6: 05 c0 rjmp .+10 ; 0x30b2 <__pack_f+0x4a> + 30a8: e1 14 cp r14, r1 + 30aa: f1 04 cpc r15, r1 + 30ac: 01 05 cpc r16, r1 + 30ae: 11 05 cpc r17, r1 + 30b0: 19 f4 brne .+6 ; 0x30b8 <__pack_f+0x50> + 30b2: e0 e0 ldi r30, 0x00 ; 0 + 30b4: f0 e0 ldi r31, 0x00 ; 0 + 30b6: 96 c0 rjmp .+300 ; 0x31e4 <__pack_f+0x17c> + 30b8: 62 81 ldd r22, Z+2 ; 0x02 + 30ba: 73 81 ldd r23, Z+3 ; 0x03 + 30bc: 9f ef ldi r25, 0xFF ; 255 + 30be: 62 38 cpi r22, 0x82 ; 130 + 30c0: 79 07 cpc r23, r25 + 30c2: 0c f0 brlt .+2 ; 0x30c6 <__pack_f+0x5e> + 30c4: 5b c0 rjmp .+182 ; 0x317c <__pack_f+0x114> + 30c6: 22 e8 ldi r18, 0x82 ; 130 + 30c8: 3f ef ldi r19, 0xFF ; 255 + 30ca: 26 1b sub r18, r22 + 30cc: 37 0b sbc r19, r23 + 30ce: 2a 31 cpi r18, 0x1A ; 26 + 30d0: 31 05 cpc r19, r1 + 30d2: 2c f0 brlt .+10 ; 0x30de <__pack_f+0x76> + 30d4: 20 e0 ldi r18, 0x00 ; 0 + 30d6: 30 e0 ldi r19, 0x00 ; 0 + 30d8: 40 e0 ldi r20, 0x00 ; 0 + 30da: 50 e0 ldi r21, 0x00 ; 0 + 30dc: 2a c0 rjmp .+84 ; 0x3132 <__pack_f+0xca> + 30de: b8 01 movw r22, r16 + 30e0: a7 01 movw r20, r14 + 30e2: 02 2e mov r0, r18 + 30e4: 04 c0 rjmp .+8 ; 0x30ee <__pack_f+0x86> + 30e6: 76 95 lsr r23 + 30e8: 67 95 ror r22 + 30ea: 57 95 ror r21 + 30ec: 47 95 ror r20 + 30ee: 0a 94 dec r0 + 30f0: d2 f7 brpl .-12 ; 0x30e6 <__pack_f+0x7e> + 30f2: 81 e0 ldi r24, 0x01 ; 1 + 30f4: 90 e0 ldi r25, 0x00 ; 0 + 30f6: a0 e0 ldi r26, 0x00 ; 0 + 30f8: b0 e0 ldi r27, 0x00 ; 0 + 30fa: 04 c0 rjmp .+8 ; 0x3104 <__pack_f+0x9c> + 30fc: 88 0f add r24, r24 + 30fe: 99 1f adc r25, r25 + 3100: aa 1f adc r26, r26 + 3102: bb 1f adc r27, r27 + 3104: 2a 95 dec r18 + 3106: d2 f7 brpl .-12 ; 0x30fc <__pack_f+0x94> + 3108: 01 97 sbiw r24, 0x01 ; 1 + 310a: a1 09 sbc r26, r1 + 310c: b1 09 sbc r27, r1 + 310e: 8e 21 and r24, r14 + 3110: 9f 21 and r25, r15 + 3112: a0 23 and r26, r16 + 3114: b1 23 and r27, r17 + 3116: 00 97 sbiw r24, 0x00 ; 0 + 3118: a1 05 cpc r26, r1 + 311a: b1 05 cpc r27, r1 + 311c: 21 f0 breq .+8 ; 0x3126 <__pack_f+0xbe> + 311e: 81 e0 ldi r24, 0x01 ; 1 + 3120: 90 e0 ldi r25, 0x00 ; 0 + 3122: a0 e0 ldi r26, 0x00 ; 0 + 3124: b0 e0 ldi r27, 0x00 ; 0 + 3126: 9a 01 movw r18, r20 + 3128: ab 01 movw r20, r22 + 312a: 28 2b or r18, r24 + 312c: 39 2b or r19, r25 + 312e: 4a 2b or r20, r26 + 3130: 5b 2b or r21, r27 + 3132: da 01 movw r26, r20 + 3134: c9 01 movw r24, r18 + 3136: 8f 77 andi r24, 0x7F ; 127 + 3138: 90 70 andi r25, 0x00 ; 0 + 313a: a0 70 andi r26, 0x00 ; 0 + 313c: b0 70 andi r27, 0x00 ; 0 + 313e: 80 34 cpi r24, 0x40 ; 64 + 3140: 91 05 cpc r25, r1 + 3142: a1 05 cpc r26, r1 + 3144: b1 05 cpc r27, r1 + 3146: 39 f4 brne .+14 ; 0x3156 <__pack_f+0xee> + 3148: 27 ff sbrs r18, 7 + 314a: 09 c0 rjmp .+18 ; 0x315e <__pack_f+0xf6> + 314c: 20 5c subi r18, 0xC0 ; 192 + 314e: 3f 4f sbci r19, 0xFF ; 255 + 3150: 4f 4f sbci r20, 0xFF ; 255 + 3152: 5f 4f sbci r21, 0xFF ; 255 + 3154: 04 c0 rjmp .+8 ; 0x315e <__pack_f+0xf6> + 3156: 21 5c subi r18, 0xC1 ; 193 + 3158: 3f 4f sbci r19, 0xFF ; 255 + 315a: 4f 4f sbci r20, 0xFF ; 255 + 315c: 5f 4f sbci r21, 0xFF ; 255 + 315e: e0 e0 ldi r30, 0x00 ; 0 + 3160: f0 e0 ldi r31, 0x00 ; 0 + 3162: 20 30 cpi r18, 0x00 ; 0 + 3164: a0 e0 ldi r26, 0x00 ; 0 + 3166: 3a 07 cpc r19, r26 + 3168: a0 e0 ldi r26, 0x00 ; 0 + 316a: 4a 07 cpc r20, r26 + 316c: a0 e4 ldi r26, 0x40 ; 64 + 316e: 5a 07 cpc r21, r26 + 3170: 10 f0 brcs .+4 ; 0x3176 <__pack_f+0x10e> + 3172: e1 e0 ldi r30, 0x01 ; 1 + 3174: f0 e0 ldi r31, 0x00 ; 0 + 3176: 79 01 movw r14, r18 + 3178: 8a 01 movw r16, r20 + 317a: 27 c0 rjmp .+78 ; 0x31ca <__pack_f+0x162> + 317c: 60 38 cpi r22, 0x80 ; 128 + 317e: 71 05 cpc r23, r1 + 3180: 64 f5 brge .+88 ; 0x31da <__pack_f+0x172> + 3182: fb 01 movw r30, r22 + 3184: e1 58 subi r30, 0x81 ; 129 + 3186: ff 4f sbci r31, 0xFF ; 255 + 3188: d8 01 movw r26, r16 + 318a: c7 01 movw r24, r14 + 318c: 8f 77 andi r24, 0x7F ; 127 + 318e: 90 70 andi r25, 0x00 ; 0 + 3190: a0 70 andi r26, 0x00 ; 0 + 3192: b0 70 andi r27, 0x00 ; 0 + 3194: 80 34 cpi r24, 0x40 ; 64 + 3196: 91 05 cpc r25, r1 + 3198: a1 05 cpc r26, r1 + 319a: b1 05 cpc r27, r1 + 319c: 39 f4 brne .+14 ; 0x31ac <__pack_f+0x144> + 319e: e7 fe sbrs r14, 7 + 31a0: 0d c0 rjmp .+26 ; 0x31bc <__pack_f+0x154> + 31a2: 80 e4 ldi r24, 0x40 ; 64 + 31a4: 90 e0 ldi r25, 0x00 ; 0 + 31a6: a0 e0 ldi r26, 0x00 ; 0 + 31a8: b0 e0 ldi r27, 0x00 ; 0 + 31aa: 04 c0 rjmp .+8 ; 0x31b4 <__pack_f+0x14c> + 31ac: 8f e3 ldi r24, 0x3F ; 63 + 31ae: 90 e0 ldi r25, 0x00 ; 0 + 31b0: a0 e0 ldi r26, 0x00 ; 0 + 31b2: b0 e0 ldi r27, 0x00 ; 0 + 31b4: e8 0e add r14, r24 + 31b6: f9 1e adc r15, r25 + 31b8: 0a 1f adc r16, r26 + 31ba: 1b 1f adc r17, r27 + 31bc: 17 ff sbrs r17, 7 + 31be: 05 c0 rjmp .+10 ; 0x31ca <__pack_f+0x162> + 31c0: 16 95 lsr r17 + 31c2: 07 95 ror r16 + 31c4: f7 94 ror r15 + 31c6: e7 94 ror r14 + 31c8: 31 96 adiw r30, 0x01 ; 1 + 31ca: 87 e0 ldi r24, 0x07 ; 7 + 31cc: 16 95 lsr r17 + 31ce: 07 95 ror r16 + 31d0: f7 94 ror r15 + 31d2: e7 94 ror r14 + 31d4: 8a 95 dec r24 + 31d6: d1 f7 brne .-12 ; 0x31cc <__pack_f+0x164> + 31d8: 05 c0 rjmp .+10 ; 0x31e4 <__pack_f+0x17c> + 31da: ee 24 eor r14, r14 + 31dc: ff 24 eor r15, r15 + 31de: 87 01 movw r16, r14 + 31e0: ef ef ldi r30, 0xFF ; 255 + 31e2: f0 e0 ldi r31, 0x00 ; 0 + 31e4: 6e 2f mov r22, r30 + 31e6: 67 95 ror r22 + 31e8: 66 27 eor r22, r22 + 31ea: 67 95 ror r22 + 31ec: 90 2f mov r25, r16 + 31ee: 9f 77 andi r25, 0x7F ; 127 + 31f0: d7 94 ror r13 + 31f2: dd 24 eor r13, r13 + 31f4: d7 94 ror r13 + 31f6: 8e 2f mov r24, r30 + 31f8: 86 95 lsr r24 + 31fa: 49 2f mov r20, r25 + 31fc: 46 2b or r20, r22 + 31fe: 58 2f mov r21, r24 + 3200: 5d 29 or r21, r13 + 3202: b7 01 movw r22, r14 + 3204: ca 01 movw r24, r20 + 3206: 1f 91 pop r17 + 3208: 0f 91 pop r16 + 320a: ff 90 pop r15 + 320c: ef 90 pop r14 + 320e: df 90 pop r13 + 3210: 08 95 ret + +00003212 <__unpack_f>: + 3212: fc 01 movw r30, r24 + 3214: db 01 movw r26, r22 + 3216: 40 81 ld r20, Z + 3218: 51 81 ldd r21, Z+1 ; 0x01 + 321a: 22 81 ldd r18, Z+2 ; 0x02 + 321c: 62 2f mov r22, r18 + 321e: 6f 77 andi r22, 0x7F ; 127 + 3220: 70 e0 ldi r23, 0x00 ; 0 + 3222: 22 1f adc r18, r18 + 3224: 22 27 eor r18, r18 + 3226: 22 1f adc r18, r18 + 3228: 93 81 ldd r25, Z+3 ; 0x03 + 322a: 89 2f mov r24, r25 + 322c: 88 0f add r24, r24 + 322e: 82 2b or r24, r18 + 3230: 28 2f mov r18, r24 + 3232: 30 e0 ldi r19, 0x00 ; 0 + 3234: 99 1f adc r25, r25 + 3236: 99 27 eor r25, r25 + 3238: 99 1f adc r25, r25 + 323a: 11 96 adiw r26, 0x01 ; 1 + 323c: 9c 93 st X, r25 + 323e: 11 97 sbiw r26, 0x01 ; 1 + 3240: 21 15 cp r18, r1 + 3242: 31 05 cpc r19, r1 + 3244: a9 f5 brne .+106 ; 0x32b0 <__unpack_f+0x9e> + 3246: 41 15 cp r20, r1 + 3248: 51 05 cpc r21, r1 + 324a: 61 05 cpc r22, r1 + 324c: 71 05 cpc r23, r1 + 324e: 11 f4 brne .+4 ; 0x3254 <__unpack_f+0x42> + 3250: 82 e0 ldi r24, 0x02 ; 2 + 3252: 37 c0 rjmp .+110 ; 0x32c2 <__unpack_f+0xb0> + 3254: 82 e8 ldi r24, 0x82 ; 130 + 3256: 9f ef ldi r25, 0xFF ; 255 + 3258: 13 96 adiw r26, 0x03 ; 3 + 325a: 9c 93 st X, r25 + 325c: 8e 93 st -X, r24 + 325e: 12 97 sbiw r26, 0x02 ; 2 + 3260: 9a 01 movw r18, r20 + 3262: ab 01 movw r20, r22 + 3264: 67 e0 ldi r22, 0x07 ; 7 + 3266: 22 0f add r18, r18 + 3268: 33 1f adc r19, r19 + 326a: 44 1f adc r20, r20 + 326c: 55 1f adc r21, r21 + 326e: 6a 95 dec r22 + 3270: d1 f7 brne .-12 ; 0x3266 <__unpack_f+0x54> + 3272: 83 e0 ldi r24, 0x03 ; 3 + 3274: 8c 93 st X, r24 + 3276: 0d c0 rjmp .+26 ; 0x3292 <__unpack_f+0x80> + 3278: 22 0f add r18, r18 + 327a: 33 1f adc r19, r19 + 327c: 44 1f adc r20, r20 + 327e: 55 1f adc r21, r21 + 3280: 12 96 adiw r26, 0x02 ; 2 + 3282: 8d 91 ld r24, X+ + 3284: 9c 91 ld r25, X + 3286: 13 97 sbiw r26, 0x03 ; 3 + 3288: 01 97 sbiw r24, 0x01 ; 1 + 328a: 13 96 adiw r26, 0x03 ; 3 + 328c: 9c 93 st X, r25 + 328e: 8e 93 st -X, r24 + 3290: 12 97 sbiw r26, 0x02 ; 2 + 3292: 20 30 cpi r18, 0x00 ; 0 + 3294: 80 e0 ldi r24, 0x00 ; 0 + 3296: 38 07 cpc r19, r24 + 3298: 80 e0 ldi r24, 0x00 ; 0 + 329a: 48 07 cpc r20, r24 + 329c: 80 e4 ldi r24, 0x40 ; 64 + 329e: 58 07 cpc r21, r24 + 32a0: 58 f3 brcs .-42 ; 0x3278 <__unpack_f+0x66> + 32a2: 14 96 adiw r26, 0x04 ; 4 + 32a4: 2d 93 st X+, r18 + 32a6: 3d 93 st X+, r19 + 32a8: 4d 93 st X+, r20 + 32aa: 5c 93 st X, r21 + 32ac: 17 97 sbiw r26, 0x07 ; 7 + 32ae: 08 95 ret + 32b0: 2f 3f cpi r18, 0xFF ; 255 + 32b2: 31 05 cpc r19, r1 + 32b4: 79 f4 brne .+30 ; 0x32d4 <__unpack_f+0xc2> + 32b6: 41 15 cp r20, r1 + 32b8: 51 05 cpc r21, r1 + 32ba: 61 05 cpc r22, r1 + 32bc: 71 05 cpc r23, r1 + 32be: 19 f4 brne .+6 ; 0x32c6 <__unpack_f+0xb4> + 32c0: 84 e0 ldi r24, 0x04 ; 4 + 32c2: 8c 93 st X, r24 + 32c4: 08 95 ret + 32c6: 64 ff sbrs r22, 4 + 32c8: 03 c0 rjmp .+6 ; 0x32d0 <__unpack_f+0xbe> + 32ca: 81 e0 ldi r24, 0x01 ; 1 + 32cc: 8c 93 st X, r24 + 32ce: 12 c0 rjmp .+36 ; 0x32f4 <__unpack_f+0xe2> + 32d0: 1c 92 st X, r1 + 32d2: 10 c0 rjmp .+32 ; 0x32f4 <__unpack_f+0xe2> + 32d4: 2f 57 subi r18, 0x7F ; 127 + 32d6: 30 40 sbci r19, 0x00 ; 0 + 32d8: 13 96 adiw r26, 0x03 ; 3 + 32da: 3c 93 st X, r19 + 32dc: 2e 93 st -X, r18 + 32de: 12 97 sbiw r26, 0x02 ; 2 + 32e0: 83 e0 ldi r24, 0x03 ; 3 + 32e2: 8c 93 st X, r24 + 32e4: 87 e0 ldi r24, 0x07 ; 7 + 32e6: 44 0f add r20, r20 + 32e8: 55 1f adc r21, r21 + 32ea: 66 1f adc r22, r22 + 32ec: 77 1f adc r23, r23 + 32ee: 8a 95 dec r24 + 32f0: d1 f7 brne .-12 ; 0x32e6 <__unpack_f+0xd4> + 32f2: 70 64 ori r23, 0x40 ; 64 + 32f4: 14 96 adiw r26, 0x04 ; 4 + 32f6: 4d 93 st X+, r20 + 32f8: 5d 93 st X+, r21 + 32fa: 6d 93 st X+, r22 + 32fc: 7c 93 st X, r23 + 32fe: 17 97 sbiw r26, 0x07 ; 7 + 3300: 08 95 ret + +00003302 <__fpcmp_parts_f>: + 3302: 1f 93 push r17 + 3304: dc 01 movw r26, r24 + 3306: fb 01 movw r30, r22 + 3308: 9c 91 ld r25, X + 330a: 92 30 cpi r25, 0x02 ; 2 + 330c: 08 f4 brcc .+2 ; 0x3310 <__fpcmp_parts_f+0xe> + 330e: 47 c0 rjmp .+142 ; 0x339e <__fpcmp_parts_f+0x9c> + 3310: 80 81 ld r24, Z + 3312: 82 30 cpi r24, 0x02 ; 2 + 3314: 08 f4 brcc .+2 ; 0x3318 <__fpcmp_parts_f+0x16> + 3316: 43 c0 rjmp .+134 ; 0x339e <__fpcmp_parts_f+0x9c> + 3318: 94 30 cpi r25, 0x04 ; 4 + 331a: 51 f4 brne .+20 ; 0x3330 <__fpcmp_parts_f+0x2e> + 331c: 11 96 adiw r26, 0x01 ; 1 + 331e: 1c 91 ld r17, X + 3320: 84 30 cpi r24, 0x04 ; 4 + 3322: 99 f5 brne .+102 ; 0x338a <__fpcmp_parts_f+0x88> + 3324: 81 81 ldd r24, Z+1 ; 0x01 + 3326: 68 2f mov r22, r24 + 3328: 70 e0 ldi r23, 0x00 ; 0 + 332a: 61 1b sub r22, r17 + 332c: 71 09 sbc r23, r1 + 332e: 3f c0 rjmp .+126 ; 0x33ae <__fpcmp_parts_f+0xac> + 3330: 84 30 cpi r24, 0x04 ; 4 + 3332: 21 f0 breq .+8 ; 0x333c <__fpcmp_parts_f+0x3a> + 3334: 92 30 cpi r25, 0x02 ; 2 + 3336: 31 f4 brne .+12 ; 0x3344 <__fpcmp_parts_f+0x42> + 3338: 82 30 cpi r24, 0x02 ; 2 + 333a: b9 f1 breq .+110 ; 0x33aa <__fpcmp_parts_f+0xa8> + 333c: 81 81 ldd r24, Z+1 ; 0x01 + 333e: 88 23 and r24, r24 + 3340: 89 f1 breq .+98 ; 0x33a4 <__fpcmp_parts_f+0xa2> + 3342: 2d c0 rjmp .+90 ; 0x339e <__fpcmp_parts_f+0x9c> + 3344: 11 96 adiw r26, 0x01 ; 1 + 3346: 1c 91 ld r17, X + 3348: 11 97 sbiw r26, 0x01 ; 1 + 334a: 82 30 cpi r24, 0x02 ; 2 + 334c: f1 f0 breq .+60 ; 0x338a <__fpcmp_parts_f+0x88> + 334e: 81 81 ldd r24, Z+1 ; 0x01 + 3350: 18 17 cp r17, r24 + 3352: d9 f4 brne .+54 ; 0x338a <__fpcmp_parts_f+0x88> + 3354: 12 96 adiw r26, 0x02 ; 2 + 3356: 2d 91 ld r18, X+ + 3358: 3c 91 ld r19, X + 335a: 13 97 sbiw r26, 0x03 ; 3 + 335c: 82 81 ldd r24, Z+2 ; 0x02 + 335e: 93 81 ldd r25, Z+3 ; 0x03 + 3360: 82 17 cp r24, r18 + 3362: 93 07 cpc r25, r19 + 3364: 94 f0 brlt .+36 ; 0x338a <__fpcmp_parts_f+0x88> + 3366: 28 17 cp r18, r24 + 3368: 39 07 cpc r19, r25 + 336a: bc f0 brlt .+46 ; 0x339a <__fpcmp_parts_f+0x98> + 336c: 14 96 adiw r26, 0x04 ; 4 + 336e: 8d 91 ld r24, X+ + 3370: 9d 91 ld r25, X+ + 3372: 0d 90 ld r0, X+ + 3374: bc 91 ld r27, X + 3376: a0 2d mov r26, r0 + 3378: 24 81 ldd r18, Z+4 ; 0x04 + 337a: 35 81 ldd r19, Z+5 ; 0x05 + 337c: 46 81 ldd r20, Z+6 ; 0x06 + 337e: 57 81 ldd r21, Z+7 ; 0x07 + 3380: 28 17 cp r18, r24 + 3382: 39 07 cpc r19, r25 + 3384: 4a 07 cpc r20, r26 + 3386: 5b 07 cpc r21, r27 + 3388: 18 f4 brcc .+6 ; 0x3390 <__fpcmp_parts_f+0x8e> + 338a: 11 23 and r17, r17 + 338c: 41 f0 breq .+16 ; 0x339e <__fpcmp_parts_f+0x9c> + 338e: 0a c0 rjmp .+20 ; 0x33a4 <__fpcmp_parts_f+0xa2> + 3390: 82 17 cp r24, r18 + 3392: 93 07 cpc r25, r19 + 3394: a4 07 cpc r26, r20 + 3396: b5 07 cpc r27, r21 + 3398: 40 f4 brcc .+16 ; 0x33aa <__fpcmp_parts_f+0xa8> + 339a: 11 23 and r17, r17 + 339c: 19 f0 breq .+6 ; 0x33a4 <__fpcmp_parts_f+0xa2> + 339e: 61 e0 ldi r22, 0x01 ; 1 + 33a0: 70 e0 ldi r23, 0x00 ; 0 + 33a2: 05 c0 rjmp .+10 ; 0x33ae <__fpcmp_parts_f+0xac> + 33a4: 6f ef ldi r22, 0xFF ; 255 + 33a6: 7f ef ldi r23, 0xFF ; 255 + 33a8: 02 c0 rjmp .+4 ; 0x33ae <__fpcmp_parts_f+0xac> + 33aa: 60 e0 ldi r22, 0x00 ; 0 + 33ac: 70 e0 ldi r23, 0x00 ; 0 + 33ae: cb 01 movw r24, r22 + 33b0: 1f 91 pop r17 + 33b2: 08 95 ret + +000033b4 <__udivmodqi4>: + 33b4: 99 1b sub r25, r25 + 33b6: 79 e0 ldi r23, 0x09 ; 9 + 33b8: 04 c0 rjmp .+8 ; 0x33c2 <__udivmodqi4_ep> + +000033ba <__udivmodqi4_loop>: + 33ba: 99 1f adc r25, r25 + 33bc: 96 17 cp r25, r22 + 33be: 08 f0 brcs .+2 ; 0x33c2 <__udivmodqi4_ep> + 33c0: 96 1b sub r25, r22 + +000033c2 <__udivmodqi4_ep>: + 33c2: 88 1f adc r24, r24 + 33c4: 7a 95 dec r23 + 33c6: c9 f7 brne .-14 ; 0x33ba <__udivmodqi4_loop> + 33c8: 80 95 com r24 + 33ca: 08 95 ret + +000033cc <__udivmodhi4>: + 33cc: aa 1b sub r26, r26 + 33ce: bb 1b sub r27, r27 + 33d0: 51 e1 ldi r21, 0x11 ; 17 + 33d2: 07 c0 rjmp .+14 ; 0x33e2 <__udivmodhi4_ep> + +000033d4 <__udivmodhi4_loop>: + 33d4: aa 1f adc r26, r26 + 33d6: bb 1f adc r27, r27 + 33d8: a6 17 cp r26, r22 + 33da: b7 07 cpc r27, r23 + 33dc: 10 f0 brcs .+4 ; 0x33e2 <__udivmodhi4_ep> + 33de: a6 1b sub r26, r22 + 33e0: b7 0b sbc r27, r23 + +000033e2 <__udivmodhi4_ep>: + 33e2: 88 1f adc r24, r24 + 33e4: 99 1f adc r25, r25 + 33e6: 5a 95 dec r21 + 33e8: a9 f7 brne .-22 ; 0x33d4 <__udivmodhi4_loop> + 33ea: 80 95 com r24 + 33ec: 90 95 com r25 + 33ee: bc 01 movw r22, r24 + 33f0: cd 01 movw r24, r26 + 33f2: 08 95 ret + +000033f4 <__divmodhi4>: + 33f4: 97 fb bst r25, 7 + 33f6: 09 2e mov r0, r25 + 33f8: 07 26 eor r0, r23 + 33fa: 0a d0 rcall .+20 ; 0x3410 <__divmodhi4_neg1> + 33fc: 77 fd sbrc r23, 7 + 33fe: 04 d0 rcall .+8 ; 0x3408 <__divmodhi4_neg2> + 3400: e5 df rcall .-54 ; 0x33cc <__udivmodhi4> + 3402: 06 d0 rcall .+12 ; 0x3410 <__divmodhi4_neg1> + 3404: 00 20 and r0, r0 + 3406: 1a f4 brpl .+6 ; 0x340e <__divmodhi4_exit> + +00003408 <__divmodhi4_neg2>: + 3408: 70 95 com r23 + 340a: 61 95 neg r22 + 340c: 7f 4f sbci r23, 0xFF ; 255 + +0000340e <__divmodhi4_exit>: + 340e: 08 95 ret + +00003410 <__divmodhi4_neg1>: + 3410: f6 f7 brtc .-4 ; 0x340e <__divmodhi4_exit> + 3412: 90 95 com r25 + 3414: 81 95 neg r24 + 3416: 9f 4f sbci r25, 0xFF ; 255 + 3418: 08 95 ret + +0000341a <__udivmodsi4>: + 341a: a1 e2 ldi r26, 0x21 ; 33 + 341c: 1a 2e mov r1, r26 + 341e: aa 1b sub r26, r26 + 3420: bb 1b sub r27, r27 + 3422: fd 01 movw r30, r26 + 3424: 0d c0 rjmp .+26 ; 0x3440 <__udivmodsi4_ep> + +00003426 <__udivmodsi4_loop>: + 3426: aa 1f adc r26, r26 + 3428: bb 1f adc r27, r27 + 342a: ee 1f adc r30, r30 + 342c: ff 1f adc r31, r31 + 342e: a2 17 cp r26, r18 + 3430: b3 07 cpc r27, r19 + 3432: e4 07 cpc r30, r20 + 3434: f5 07 cpc r31, r21 + 3436: 20 f0 brcs .+8 ; 0x3440 <__udivmodsi4_ep> + 3438: a2 1b sub r26, r18 + 343a: b3 0b sbc r27, r19 + 343c: e4 0b sbc r30, r20 + 343e: f5 0b sbc r31, r21 + +00003440 <__udivmodsi4_ep>: + 3440: 66 1f adc r22, r22 + 3442: 77 1f adc r23, r23 + 3444: 88 1f adc r24, r24 + 3446: 99 1f adc r25, r25 + 3448: 1a 94 dec r1 + 344a: 69 f7 brne .-38 ; 0x3426 <__udivmodsi4_loop> + 344c: 60 95 com r22 + 344e: 70 95 com r23 + 3450: 80 95 com r24 + 3452: 90 95 com r25 + 3454: 9b 01 movw r18, r22 + 3456: ac 01 movw r20, r24 + 3458: bd 01 movw r22, r26 + 345a: cf 01 movw r24, r30 + 345c: 08 95 ret + +0000345e <__prologue_saves__>: + 345e: 2f 92 push r2 + 3460: 3f 92 push r3 + 3462: 4f 92 push r4 + 3464: 5f 92 push r5 + 3466: 6f 92 push r6 + 3468: 7f 92 push r7 + 346a: 8f 92 push r8 + 346c: 9f 92 push r9 + 346e: af 92 push r10 + 3470: bf 92 push r11 + 3472: cf 92 push r12 + 3474: df 92 push r13 + 3476: ef 92 push r14 + 3478: ff 92 push r15 + 347a: 0f 93 push r16 + 347c: 1f 93 push r17 + 347e: cf 93 push r28 + 3480: df 93 push r29 + 3482: cd b7 in r28, 0x3d ; 61 + 3484: de b7 in r29, 0x3e ; 62 + 3486: ca 1b sub r28, r26 + 3488: db 0b sbc r29, r27 + 348a: 0f b6 in r0, 0x3f ; 63 + 348c: f8 94 cli + 348e: de bf out 0x3e, r29 ; 62 + 3490: 0f be out 0x3f, r0 ; 63 + 3492: cd bf out 0x3d, r28 ; 61 + 3494: 09 94 ijmp + +00003496 <__epilogue_restores__>: + 3496: 2a 88 ldd r2, Y+18 ; 0x12 + 3498: 39 88 ldd r3, Y+17 ; 0x11 + 349a: 48 88 ldd r4, Y+16 ; 0x10 + 349c: 5f 84 ldd r5, Y+15 ; 0x0f + 349e: 6e 84 ldd r6, Y+14 ; 0x0e + 34a0: 7d 84 ldd r7, Y+13 ; 0x0d + 34a2: 8c 84 ldd r8, Y+12 ; 0x0c + 34a4: 9b 84 ldd r9, Y+11 ; 0x0b + 34a6: aa 84 ldd r10, Y+10 ; 0x0a + 34a8: b9 84 ldd r11, Y+9 ; 0x09 + 34aa: c8 84 ldd r12, Y+8 ; 0x08 + 34ac: df 80 ldd r13, Y+7 ; 0x07 + 34ae: ee 80 ldd r14, Y+6 ; 0x06 + 34b0: fd 80 ldd r15, Y+5 ; 0x05 + 34b2: 0c 81 ldd r16, Y+4 ; 0x04 + 34b4: 1b 81 ldd r17, Y+3 ; 0x03 + 34b6: aa 81 ldd r26, Y+2 ; 0x02 + 34b8: b9 81 ldd r27, Y+1 ; 0x01 + 34ba: ce 0f add r28, r30 + 34bc: d1 1d adc r29, r1 + 34be: 0f b6 in r0, 0x3f ; 63 + 34c0: f8 94 cli + 34c2: de bf out 0x3e, r29 ; 62 + 34c4: 0f be out 0x3f, r0 ; 63 + 34c6: cd bf out 0x3d, r28 ; 61 + 34c8: ed 01 movw r28, r26 + 34ca: 08 95 ret + +000034cc <_exit>: + 34cc: f8 94 cli + +000034ce <__stop_program>: + 34ce: ff cf rjmp .-2 ; 0x34ce <__stop_program> Index: /firmware/FSC/test_projects/test_ethernet/default/test_ethernet.map =================================================================== --- /firmware/FSC/test_projects/test_ethernet/default/test_ethernet.map (revision 10668) +++ /firmware/FSC/test_projects/test_ethernet/default/test_ethernet.map (revision 10668) @@ -0,0 +1,979 @@ +Archive member included because of file (symbol) + +c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_udivmodqi4.o) + output.o (__udivmodqi4) +c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_udivmodhi4.o) + num_conversion.o (__udivmodhi4) +c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_divmodhi4.o) + application.o (__divmodhi4) +c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_udivmodsi4.o) + num_conversion.o (__udivmodsi4) +c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_exit.o) + c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/../../../../avr/lib/avr5/crtm32.o (exit) +c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_copy_data.o) + w5100_spi_interface.o (__do_copy_data) +c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_clear_bss.o) + w5100_spi_interface.o (__do_clear_bss) +c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_fixunssfsi.o) + num_conversion.o (__fixunssfsi) +c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_addsub_sf.o) + interpol.o (__subsf3) +c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_mul_sf.o) + interpol.o (__mulsf3) +c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_div_sf.o) + interpol.o (__divsf3) +c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_ge_sf.o) + c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_fixunssfsi.o) (__gesf2) +c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_lt_sf.o) + num_conversion.o (__ltsf2) +c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_si_to_sf.o) + num_conversion.o (__floatsisf) +c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_sf_to_si.o) + c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_fixunssfsi.o) (__fixsfsi) +c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_thenan_sf.o) + c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_addsub_sf.o) (__thenan_sf) +c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_usi_to_sf.o) + interpol.o (__floatunsisf) +c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_prologue.o) + c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_addsub_sf.o) (__prologue_saves__) +c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_epilogue.o) + c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_addsub_sf.o) (__epilogue_restores__) +c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_clzsi2.o) + c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_si_to_sf.o) (__clzsi2) +c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_pack_sf.o) + c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_addsub_sf.o) (__pack_f) +c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_unpack_sf.o) + c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_addsub_sf.o) (__unpack_f) +c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_fpcmp_parts_sf.o) + c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_ge_sf.o) (__fpcmp_parts_f) +c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_clz.o) + c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_clzsi2.o) (__clz_tab) + +Allocating common symbols +Common symbol size file + +usart_received_chars + 0x1 usart.o +spi_ss_active_high 0x1 spi_master.o +verbose 0x1 FSC_test.o +adc_channels_ready 0xb FSC_test.o +spi_cpol 0x1 spi_master.o +spi_write_buffer 0x10 spi_master.o +app_reset_source 0x1 application.o +nc_buffer 0x10 num_conversion.o +heartbeat_enable 0x1 FSC_test.o +spi_cpha 0x1 spi_master.o +nc_format_buffer 0x10 num_conversion.o +eth_read_buffer 0x10 w5100_spi_interface.o +spi_clock_index 0x1 spi_master.o +spi_dord 0x1 spi_master.o +adc_enables 0xb FSC_test.o +usart_last_char 0x1 FSC_test.o +ad7719_values 0x100 FSC_test.o +usart_rx_buffer 0x20 usart.o +spi_read_buffer 0x10 spi_master.o +ad7719_enables 0x8 FSC_test.o +usart_tx_buffer 0x5 FSC_test.o +eth_write_buffer 0x10 w5100_spi_interface.o +adc_values 0x54 FSC_test.o +ad7719_channels_ready + 0x8 FSC_test.o + +Memory Configuration + +Name Origin Length Attributes +text 0x00000000 0x00020000 xr +data 0x00800060 0x0000ffa0 rw !x +eeprom 0x00810000 0x00010000 rw !x +fuse 0x00820000 0x00000400 rw !x +lock 0x00830000 0x00000400 rw !x +signature 0x00840000 0x00000400 rw !x +*default* 0x00000000 0xffffffff + +Linker script and memory map + +LOAD c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/../../../../avr/lib/avr5/crtm32.o +LOAD w5100_spi_interface.o +LOAD ad7719_adc.o +LOAD application.o +LOAD atmega_adc.o +LOAD interpol.o +LOAD muxer_fsc.o +LOAD output.o +LOAD parser.o +LOAD spi_master.o +LOAD usart.o +LOAD num_conversion.o +LOAD FSC_test.o +LOAD c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a +LOAD c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/../../../../avr/lib/avr5\libc.a +LOAD c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a + +.hash + *(.hash) + +.dynsym + *(.dynsym) + +.dynstr + *(.dynstr) + +.gnu.version + *(.gnu.version) + +.gnu.version_d + *(.gnu.version_d) + +.gnu.version_r + *(.gnu.version_r) + +.rel.init + *(.rel.init) + +.rela.init + *(.rela.init) + +.rel.text + *(.rel.text) + *(.rel.text.*) + *(.rel.gnu.linkonce.t*) + +.rela.text + *(.rela.text) + *(.rela.text.*) + *(.rela.gnu.linkonce.t*) + +.rel.fini + *(.rel.fini) + +.rela.fini + *(.rela.fini) + +.rel.rodata + *(.rel.rodata) + *(.rel.rodata.*) + *(.rel.gnu.linkonce.r*) + +.rela.rodata + *(.rela.rodata) + *(.rela.rodata.*) + *(.rela.gnu.linkonce.r*) + +.rel.data + *(.rel.data) + *(.rel.data.*) + *(.rel.gnu.linkonce.d*) + +.rela.data + *(.rela.data) + *(.rela.data.*) + *(.rela.gnu.linkonce.d*) + +.rel.ctors + *(.rel.ctors) + +.rela.ctors + *(.rela.ctors) + +.rel.dtors + *(.rel.dtors) + +.rela.dtors + *(.rela.dtors) + +.rel.got + *(.rel.got) + +.rela.got + *(.rela.got) + +.rel.bss + *(.rel.bss) + +.rela.bss + *(.rela.bss) + +.rel.plt + *(.rel.plt) + +.rela.plt + *(.rela.plt) + +.text 0x00000000 0x34d0 + *(.vectors) + .vectors 0x00000000 0x54 c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/../../../../avr/lib/avr5/crtm32.o + 0x00000000 __vectors + 0x00000000 __vector_default + *(.vectors) + *(.progmem.gcc*) + *(.progmem*) + 0x00000054 . = ALIGN (0x2) + 0x00000054 __trampolines_start = . + *(.trampolines) + .trampolines 0x00000054 0x0 linker stubs + *(.trampolines*) + 0x00000054 __trampolines_end = . + *(.jumptables) + *(.jumptables*) + *(.lowtext) + *(.lowtext*) + 0x00000054 __ctors_start = . + *(.ctors) + 0x00000054 __ctors_end = . + 0x00000054 __dtors_start = . + *(.dtors) + 0x00000054 __dtors_end = . + SORT(*)(.ctors) + SORT(*)(.dtors) + *(.init0) + .init0 0x00000054 0x0 c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/../../../../avr/lib/avr5/crtm32.o + 0x00000054 __init + *(.init0) + *(.init1) + *(.init1) + *(.init2) + .init2 0x00000054 0xc c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/../../../../avr/lib/avr5/crtm32.o + *(.init2) + *(.init3) + *(.init3) + *(.init4) + .init4 0x00000060 0x16 c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_copy_data.o) + 0x00000060 __do_copy_data + .init4 0x00000076 0x10 c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_clear_bss.o) + 0x00000076 __do_clear_bss + *(.init4) + *(.init5) + *(.init5) + *(.init6) + *(.init6) + *(.init7) + *(.init7) + *(.init8) + *(.init8) + *(.init9) + .init9 0x00000086 0x8 c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/../../../../avr/lib/avr5/crtm32.o + *(.init9) + *(.text) + .text 0x0000008e 0x4 c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/../../../../avr/lib/avr5/crtm32.o + 0x0000008e __vector_1 + 0x0000008e __vector_12 + 0x0000008e __bad_interrupt + 0x0000008e __vector_6 + 0x0000008e __vector_3 + 0x0000008e __vector_11 + 0x0000008e __vector_17 + 0x0000008e __vector_19 + 0x0000008e __vector_7 + 0x0000008e __vector_5 + 0x0000008e __vector_9 + 0x0000008e __vector_2 + 0x0000008e __vector_15 + 0x0000008e __vector_8 + 0x0000008e __vector_14 + 0x0000008e __vector_10 + 0x0000008e __vector_16 + 0x0000008e __vector_18 + 0x0000008e __vector_20 + .text 0x00000092 0x556 w5100_spi_interface.o + 0x000000d6 get_S0_RX_RSR + 0x00000166 w5100_sock_status + 0x000000b2 get_S0_RX_RD + 0x00000092 w5100_read + 0x000001aa set_S0_RX_RD + 0x00000170 w5100_is_established + 0x00000142 get_S0_TX_FSR + 0x000000fa get_S0_TX_WR + 0x0000038e w5100_set_TX + 0x0000011e get_S0_TX_RD + 0x0000018e w5100_write + 0x00000492 w5100_init + 0x000001c6 w5100_get_RX + 0x00000372 set_S0_TX_WR + .text 0x000005e8 0x1a6 ad7719_adc.o + 0x000005e8 read_adc + 0x0000065a stopconv + 0x00000694 ad7719_init + 0x00000670 startconv + .text 0x0000078e 0x250 application.o + 0x00000848 increase_ad7719 + 0x000007e8 increase_adc + 0x000008e4 set_adc_enable_register + 0x000007d4 app_set_watchdog_prescaler + 0x00000886 check_if_measured_all + 0x0000078e app_init + 0x000008ee set_ad7719_enable_register + .text 0x000009de 0x22 atmega_adc.o + 0x000009de atmega_adc_init + .text 0x00000a00 0x388 interpol.o + 0x00000a06 getresistance + 0x00000a00 getadc + 0x00000d2c readandsendpress + 0x00000a34 gettemp + .text 0x00000d88 0x8e muxer_fsc.o + 0x00000de8 Set_T_Muxer + 0x00000d88 Set_V_Muxer + .text 0x00000e16 0x36e output.o + 0x00000e16 adc_output + 0x00000ea8 print_adc_nicely + 0x0000104e print_status + 0x00000f64 print_ad7719_nicely + 0x00001044 adc_output_all + 0x00000ef8 ad7719_output + .text 0x00001184 0x130 parser.o + 0x000011ba parse_ascii + 0x00001184 parse_non_human_readable_input + 0x00001186 incoming_byte_parser + .text 0x000012b4 0x2c4 spi_master.o + 0x0000132c spi_init + 0x0000138a spi_transfer + 0x0000137c spi_transfer_byte + 0x00001352 spi_set_dord + 0x000014d4 spi_transfer_string + 0x00001360 spi_set_cpol + 0x000012b4 spi_setup + 0x0000136e spi_set_cpha + 0x00001342 spi_set_clock_index + .text 0x00001578 0x1a0 usart.o + 0x000016f0 usart_write_U08_bin + 0x000015f8 usart_writeln_str + 0x000016d2 usart_write_U16_hex + 0x000016c8 usart_write_U32 + 0x000016aa usart_write_float + 0x00001592 usart_write_char + 0x000016be usart_write_S32 + 0x000015d4 usart_writeln_flash_str + 0x000016fa usart_write_U08_hex + 0x0000160e __vector_13 + 0x0000159a usart_write_crlf + 0x00001704 usart_write_S08 + 0x000016b4 usart_write_U32_hex + 0x00001578 usart_init + 0x000016dc usart_write_S16 + 0x000015ac usart_write_str + 0x0000170e usart_write_U08 + 0x000016e6 usart_write_U16 + 0x000015c0 usart_write_flash_str + .text 0x00001718 0xa4e num_conversion.o + 0x00001896 nc_float_to_str + 0x00001744 nc_U08_to_bin + 0x00001fbc nc_U16_to_str + 0x00001cbe nc_U32_to_str + 0x000020f0 nc_U08_to_str + 0x00001854 nc_format + 0x000017c8 nc_U32_to_hex + 0x00002074 nc_S08_to_str + 0x00001a84 nc_S32_to_str + 0x00001718 nc_U08_to_hex + 0x00001ef6 nc_S16_to_str + 0x0000177c nc_U16_to_hex + .text 0x00002166 0x456 FSC_test.o + 0x000021b0 main + 0x00002166 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c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_addsub_sf.o) + .debug_loc 0x00001d71 0x104 c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_mul_sf.o) + .debug_loc 0x00001e75 0xc0 c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_div_sf.o) + .debug_loc 0x00001f35 0x3c c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_ge_sf.o) + .debug_loc 0x00001f71 0x3c c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_lt_sf.o) + .debug_loc 0x00001fad 0xac c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_si_to_sf.o) + .debug_loc 0x00002059 0x7e c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_sf_to_si.o) + .debug_loc 0x000020d7 0x4c c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_usi_to_sf.o) + .debug_loc 0x00002123 0x94 c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_clzsi2.o) + .debug_loc 0x000021b7 0x13e c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_pack_sf.o) + .debug_loc 0x000022f5 0xac c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_unpack_sf.o) + .debug_loc 0x000023a1 0x50 c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_fpcmp_parts_sf.o) + +.debug_macinfo + *(.debug_macinfo) +OUTPUT(test_ethernet.elf elf32-avr) +LOAD linker stubs + +.debug_ranges 0x00000000 0x1d0 + .debug_ranges 0x00000000 0x48 usart.o + .debug_ranges 0x00000048 0x138 FSC_test.o + .debug_ranges 0x00000180 0x50 c:/winavr-20100110/bin/../lib/gcc/avr/4.3.3/avr5\libgcc.a(_mul_sf.o) Index: /firmware/FSC/test_projects/test_ethernet/test_ethernet.aps =================================================================== --- /firmware/FSC/test_projects/test_ethernet/test_ethernet.aps (revision 10668) +++ /firmware/FSC/test_projects/test_ethernet/test_ethernet.aps (revision 10668) @@ -0,0 +1,1 @@ +test_ethernet11-May-2011 09:47:3311-May-2011 13:10:54241011-May-2011 09:47:3344, 18, 0, 670AVR GCCdefault\test_ethernet.elfC:\fact.isdc.unige.ch_svn_firmware\FSC\test_projects\test_ethernet\AVR SimulatorATmega32.xmlfalseR00R01R02R03R04R05R06R07R08R09R10R11R12R13R14R15R16R17R18R19R20R21R22R23R24R25R26R27R28R29R30R31Auto000C:\fact.isdc.unige.ch_svn_firmware\FSC\src\w5100_spi_interface.cC:\fact.isdc.unige.ch_svn_firmware\FSC\src\ad7719_adc.cC:\fact.isdc.unige.ch_svn_firmware\FSC\src\application.cC:\fact.isdc.unige.ch_svn_firmware\FSC\src\atmega_adc.cC:\fact.isdc.unige.ch_svn_firmware\FSC\src\interpol.cC:\fact.isdc.unige.ch_svn_firmware\FSC\src\muxer_fsc.cC:\fact.isdc.unige.ch_svn_firmware\FSC\src\output.cC:\fact.isdc.unige.ch_svn_firmware\FSC\src\parser.cC:\fact.isdc.unige.ch_svn_firmware\FSC\src\spi_master.cC:\fact.isdc.unige.ch_svn_firmware\FSC\src\usart.cC:\fact.isdc.unige.ch_svn_firmware\FSC\src\num_conversion.cC:\fact.isdc.unige.ch_svn_firmware\FSC\src\FSC_test.cC:\fact.isdc.unige.ch_svn_firmware\FSC\src\typedefs.hC:\fact.isdc.unige.ch_svn_firmware\FSC\src\w5100_spi_interface.hC:\fact.isdc.unige.ch_svn_firmware\FSC\src\ad7719_adc.hC:\fact.isdc.unige.ch_svn_firmware\FSC\src\application.hC:\fact.isdc.unige.ch_svn_firmware\FSC\src\atmega_adc.hC:\fact.isdc.unige.ch_svn_firmware\FSC\src\interpol.hC:\fact.isdc.unige.ch_svn_firmware\FSC\src\macros.hC:\fact.isdc.unige.ch_svn_firmware\FSC\src\muxer_fsc.hC:\fact.isdc.unige.ch_svn_firmware\FSC\src\output.hC:\fact.isdc.unige.ch_svn_firmware\FSC\src\parser.hC:\fact.isdc.unige.ch_svn_firmware\FSC\src\spi_master.hC:\fact.isdc.unige.ch_svn_firmware\FSC\src\usart.hC:\fact.isdc.unige.ch_svn_firmware\FSC\src\num_conversion.hdefault\test_ethernet.lssdefault\test_ethernet.mapdefaultNOatmega32111test_ethernet.elfdefault\1-Wall -gdwarf-2 -std=gnu99 -DF_CPU=8000000UL -Os -funsigned-char -funsigned-bitfields -fpack-struct -fshort-enumsdefault1C:\WinAVR-20100110\bin\avr-gcc.exeC:\WinAVR-20100110\utils\bin\make.exeC:\fact.isdc.unige.ch_svn_firmware\FSC\src\typedefs.hC:\fact.isdc.unige.ch_svn_firmware\FSC\src\w5100_spi_interface.hC:\fact.isdc.unige.ch_svn_firmware\FSC\src\ad7719_adc.hC:\fact.isdc.unige.ch_svn_firmware\FSC\src\application.hC:\fact.isdc.unige.ch_svn_firmware\FSC\src\atmega_adc.hC:\fact.isdc.unige.ch_svn_firmware\FSC\src\interpol.hC:\fact.isdc.unige.ch_svn_firmware\FSC\src\macros.hC:\fact.isdc.unige.ch_svn_firmware\FSC\src\muxer_fsc.hC:\fact.isdc.unige.ch_svn_firmware\FSC\src\output.hC:\fact.isdc.unige.ch_svn_firmware\FSC\src\parser.hC:\fact.isdc.unige.ch_svn_firmware\FSC\src\spi_master.hC:\fact.isdc.unige.ch_svn_firmware\FSC\src\usart.hC:\fact.isdc.unige.ch_svn_firmware\FSC\src\num_conversion.hC:\fact.isdc.unige.ch_svn_firmware\FSC\src\FSC_test_electrical_connection.cC:\fact.isdc.unige.ch_svn_firmware\FSC\src\w5100_spi_interface.cC:\fact.isdc.unige.ch_svn_firmware\FSC\src\ad7719_adc.cC:\fact.isdc.unige.ch_svn_firmware\FSC\src\application.cC:\fact.isdc.unige.ch_svn_firmware\FSC\src\atmega_adc.cC:\fact.isdc.unige.ch_svn_firmware\FSC\src\interpol.cC:\fact.isdc.unige.ch_svn_firmware\FSC\src\muxer_fsc.cC:\fact.isdc.unige.ch_svn_firmware\FSC\src\output.cC:\fact.isdc.unige.ch_svn_firmware\FSC\src\parser.cC:\fact.isdc.unige.ch_svn_firmware\FSC\src\spi_master.cC:\fact.isdc.unige.ch_svn_firmware\FSC\src\usart.cC:\fact.isdc.unige.ch_svn_firmware\FSC\src\num_conversion.c Index: /firmware/FSC/test_projects/test_ethernet/test_ethernet.aws =================================================================== --- /firmware/FSC/test_projects/test_ethernet/test_ethernet.aws (revision 10668) +++ /firmware/FSC/test_projects/test_ethernet/test_ethernet.aws (revision 10668) @@ -0,0 +1,1 @@ +