Changeset 10729


Ignore:
Timestamp:
May 17, 2011, 6:29:09 PM (9 years ago)
Author:
neise
Message:
 
Location:
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib
Files:
18 edited

Legend:

Unmodified
Added
Removed
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd

    r10502 r10729  
    161161signal internal_roi_max : roi_max_type;
    162162
     163signal config_start_sr : std_logic_vector(1 downto 0) := "00";
     164
     165signal adc_data_sig : adc_data_array_type;
     166signal adc_otr_sig : std_logic_vector(3 downto 0) ;
     167type adc_data_16bit_t is array (3 downto 0) of sdt_logic_vector(15 downto 0);
     168signal data_16bit : adc_data_16bit_t;
     169
    163170begin
    164171drs_readout_started <= sig_drs_readout_started;
     
    166173begin
    167174        if rising_edge (clk) then
    168 
    169                 if (config_start = '1') then
     175        -- synch
     176        config_start_sr <= config_start_sr(0) & config_start;
     177
     178                if (config_start_sr(1) = '1') then
    170179                        config_start_sig <= '1';
    171180                        config_done <= '0';
     
    393402                                state_generate <= WRITE_ADC_DATA;
    394403                        end if;
     404
     405--              when CATCH_ADC_DATA =>
     406--                      adc_data_sig <= adc_data_array;
     407--                      adc_otr_sig <= adc_otr;
     408--                      state_generate <= PREPARE_ADC_DATA_01;
     409--                     
     410--              when PREPARE_ADC_DATA_01 =>
     411--                      for i in 3 downto 0 loop
     412--                              if (adc_otr_sig(i)='1') then
     413--                                      if (adc_data_sig(i)(11)='1') then
     414--                                              data_16bit(i) = X"8000" --this is decimal -1
     415--                                      else -- adc_data_sig(i)(11)='0'
     416--                                              data_16bit(i) = X"1001" --this is decimal +4097
     417--                                      end if;
     418--                              else -- no over/underflow
     419--                                      data_16bit(i) =
     420--                      end loop;
     421                       
     422               
     423                       
    395424                when WRITE_ADC_DATA =>
    396425                        if (data_cntr < roi_max_int (channel_id)) then
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd

    r10567 r10729  
    33-- Created:
    44--          by - daqct3.UNKNOWN (IHP110)
    5 --          at - 15:22:10 04.05.2011
     5--          at - 17:58:44 17.05.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
     
    7676-- Created:
    7777--          by - daqct3.UNKNOWN (IHP110)
    78 --          at - 15:22:11 04.05.2011
     78--          at - 17:58:44 17.05.2011
    7979--
    8080-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
     
    105105   SIGNAL counter_result        : std_logic_vector(11 DOWNTO 0) := (others => '0');
    106106   SIGNAL crate_id              : std_logic_vector(1 DOWNTO 0);
     107   SIGNAL debug_data_ram_empty  : std_logic;
     108   SIGNAL debug_data_valid      : std_logic;
    107109   SIGNAL led                   : std_logic_vector(7 DOWNTO 0)  := (OTHERS => '0');
     110   SIGNAL w5300_state           : std_logic_vector(7 DOWNTO 0);                        -- state is encoded here ... useful for debugging.
    108111
    109112
     
    144147      counter_result        : OUT    std_logic_vector (11 DOWNTO 0);
    145148      dac_cs                : OUT    std_logic ;
     149      debug_data_ram_empty  : OUT    std_logic ;
     150      debug_data_valid      : OUT    std_logic ;
    146151      denable               : OUT    std_logic                     := '0';           -- default domino wave off
    147152      drs_channel_id        : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
     
    154159      sensor_cs             : OUT    std_logic_vector (3 DOWNTO 0);
    155160      trigger_veto          : OUT    std_logic                     := '1';
     161      w5300_state           : OUT    std_logic_vector (7 DOWNTO 0);                  -- state is encoded here ... useful for debugging.
    156162      wiz_addr              : OUT    std_logic_vector (9 DOWNTO 0);
    157163      wiz_cs                : OUT    std_logic                     := '1';
     
    195201   
    196202   --D_T <= (others => '0');
     203   D_T <= w5300_state;
     204   D_T2(0) <= debug_data_valid;
     205   D_T2(1) <= debug_data_ram_empty;
    197206   --D_T2 <= ( others => '0' );
    198    D_T2(1) <= '0';
     207   
    199208   -- A0_T(7 downto 0) <= (others => '0');
    200209   --A1_T(7 downto 0) <= (others => '0');
    201210   
    202211   A1_T <= counter_result ( 7 downto 0);
    203    D_T(3 downto 0) <=  counter_result ( 11 downto 8);
    204    D_T(4) <= alarm_refclk_too_low;
    205    D_T(5) <= alarm_refclk_too_high;
    206    D_T(6) <= '0';
    207    D_T(7) <= '0';
     212   --D_T(3 downto 0) <=  counter_result ( 11 downto 8);
     213   --D_T(4) <= alarm_refclk_too_low;
     214   --D_T(5) <= alarm_refclk_too_high;
     215   --D_T(6) <= '0';
     216   --D_T(7) <= '0';
    208217   
    209218   -- led output is driven by w5300 modul
     
    216225   RS485_C_DO <= '0';
    217226   -- MAX3485 receiver out pit is fed out... should be HIGH-Z
    218    D_T2(0) <= RS485_C_DI;
     227   
    219228   
    220229   -- EEPROM is not used on FAD. CS is always high.
     
    258267         counter_result        => counter_result,
    259268         dac_cs                => DAC_CS,
     269         debug_data_ram_empty  => debug_data_ram_empty,
     270         debug_data_valid      => debug_data_valid,
    260271         denable               => DENABLE,
    261272         drs_channel_id        => D_A,
     
    268279         sensor_cs             => TCS,
    269280         trigger_veto          => TRG_V,
     281         w5300_state           => w5300_state,
    270282         wiz_addr              => W_A,
    271283         wiz_cs                => W_CS,
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd

    r10567 r10729  
    5757        --constant SUBVERSION_NUMBER : std_logic_vector (15 downto 0) := conv_std_logic_vector(str_to_int(SUBVERSION_STRING),16);
    5858        constant PACKAGE_VERSION : std_logic_vector(7 downto 0) := X"01";
    59         constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"04";
     59        constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"07";
    6060        constant PACKAGE_HEADER_LENGTH : integer := 36;
    6161        constant PACKAGE_HEADER_ZEROS : integer := 0; 
     
    8989  constant W5300_MTYPER : std_logic_vector (9 downto 0) := W5300_BASE_ADR + X"30";
    9090       
    91         constant W5300_S0_MR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"0";
    92         constant W5300_S0_CR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2";
    93         constant W5300_S0_IMR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"4";
    94         constant W5300_S0_IR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"6";
    95         constant W5300_S0_SSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"8";
    96         constant W5300_S0_PORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"A";
    97         constant W5300_S0_DPORTR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"12";
    98         constant W5300_S0_DIPR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"14";
    99         constant W5300_S0_TX_WRSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"20";
    100         constant W5300_S0_TX_FSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"24";
    101   constant W5300_S0_RX_RSR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"28";
    102         constant W5300_S0_TX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2E";
    103   constant W5300_S0_RX_FIFOR : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"30";
     91        constant W5300_S0_MR            : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"0";
     92        constant W5300_S0_CR            : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2";
     93        constant W5300_S0_IMR           : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"4";
     94        constant W5300_S0_IR            : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"6";
     95        constant W5300_S0_SSR           : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"8";
     96        constant W5300_S0_PORTR         : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"A";
     97        constant W5300_S0_DPORTR        : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"12";
     98        constant W5300_S0_DIPR          : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"14";
     99        constant W5300_S0_PORTOR        : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"1A";  -- HIGH byte is S0_KPALVTR register
     100        constant W5300_S0_TX_WRSR       : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"20";
     101        constant W5300_S0_TX_FSR        : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"24";
     102  constant W5300_S0_RX_RSR              : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"28";
     103        constant W5300_S0_TX_FIFOR      : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"2E";
     104  constant W5300_S0_RX_FIFOR    : std_logic_vector (9 downto 0) := W5300_BASE_ADR + "1000000000" + X"30";
    104105-- End W5300 registers 
    105106
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd

    r10567 r10729  
    33-- Created:
    44--          by - daqct3.UNKNOWN (IHP110)
    5 --          at - 15:22:09 04.05.2011
     5--          at - 17:58:42 17.05.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
     
    4848      counter_result        : OUT    std_logic_vector (11 DOWNTO 0);
    4949      dac_cs                : OUT    std_logic;
     50      debug_data_ram_empty  : OUT    std_logic;
     51      debug_data_valid      : OUT    std_logic;
    5052      denable               : OUT    std_logic                     := '0';              -- default domino wave off
    5153      drs_channel_id        : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
     
    5860      sensor_cs             : OUT    std_logic_vector (3 DOWNTO 0);
    5961      trigger_veto          : OUT    std_logic                     := '1';
     62      w5300_state           : OUT    std_logic_vector (7 DOWNTO 0);                     -- state is encoded here ... useful for debugging.
    6063      wiz_addr              : OUT    std_logic_vector (9 DOWNTO 0);
    6164      wiz_cs                : OUT    std_logic                     := '1';
     
    7679-- Created:
    7780--          by - daqct3.UNKNOWN (IHP110)
    78 --          at - 15:22:10 04.05.2011
     81--          at - 17:58:43 17.05.2011
    7982--
    8083-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
     
    484487   );
    485488   PORT (
     489      state                         : OUT    std_logic_vector (7 DOWNTO 0);                                  -- state is encoded here ... useful for debugging.
     490      debug_data_ram_empty          : OUT    std_logic ;
     491      debug_data_valid              : OUT    std_logic ;
    486492      clk                           : IN     std_logic ;
    487493      wiz_reset                     : OUT    std_logic                      := '1';
     
    886892      )
    887893      PORT MAP (
     894         state                         => w5300_state,
     895         debug_data_ram_empty          => debug_data_ram_empty,
     896         debug_data_valid              => debug_data_valid,
    888897         clk                           => CLK_50_internal,
    889898         wiz_reset                     => wiz_reset,
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd

    r10225 r10729  
    102102signal temp_roi : integer range 0 to 1024 := 0;
    103103
     104-- SYNCH IN INPUT SIGNALS -----------------------------------------
     105
     106        signal config_start_sr          : std_logic_vector(1 downto 0) := "00";
     107        signal ram_write_ready_sr       : std_logic_vector(1 downto 0) := "00";
     108        signal wiz_busy_sr                      : std_logic_vector(1 downto 0) := "00";
     109        signal wiz_ack_sr                       : std_logic_vector(1 downto 0) := "00";
     110                -- no shift register, but local copy.
     111        signal roi_array_local : roi_array_type;
     112
    104113BEGIN
    105114
     
    110119  begin
    111120    if rising_edge (clk) then
     121        -- here: the synchin in of asynchronous input signals takes place.
     122        config_start_sr         <= config_start_sr(0) & config_start;
     123        ram_write_ready_sr      <= ram_write_ready_sr(0) & ram_write_ready;
     124        wiz_busy_sr                     <= wiz_busy_sr(0) & wiz_busy;
     125        wiz_ack_sr                      <= wiz_ack_sr(0) & wiz_ack;
     126
     127        roi_array_local         <= roi_array;
     128       
    112129      case state_mm is
    113130   
    114131        when MM_CONFIG =>
    115           if (config_start = '1') then
     132                        -- this if clause was doubled ... already in MAIN state config_start = '1' was checked...
     133                        -- this is imho not needed and can cause trouble... DN 17.05.11
     134          --if (config_start_sr = "11") then
    116135            config_ready <= '0';
    117136            roi_max_array <= (others => 0);
     
    122141            ram_write_ea <= '0';
    123142            state_mm <= MAX_ROI;
    124           end if;
     143          --end if;
    125144       
    126145        -- calculate max ROIs and channel sizes
     
    129148          state_mm <= MAX_ROI1;
    130149        when MAX_ROI1 =>
    131           temp_roi <= roi_array (roi_index);
     150          temp_roi <= roi_array_local (roi_index);
    132151          state_mm <= MAX_ROI2;
    133152        when MAX_ROI2 =>
     
    222241        when MM_MAIN =>
    223242          state_mm <= MM_MAIN1;
    224           if (config_start = '1') then
     243          if (config_start_sr = "11") then
    225244            --config_ready <= '0';
    226245            if (events_in_ram = 0) then
     
    231250        when MM_MAIN1 =>
    232251          state_mm <= MM_MAIN2;
    233           if ((ram_write_ready = '1') and (event_ready_flag = '0')) then
     252          if ((ram_write_ready_sr = "11") and (event_ready_flag = '0')) then
    234253            ram_write_ea <= '0';
    235254            -- --
     
    248267        when MM_MAIN2 =>
    249268          state_mm <= MM_MAIN3;
    250           if ((event_ready_flag = '1') and (ram_write_ready = '0')) then
     269          if ((event_ready_flag = '1') and (ram_write_ready_sr = "00")) then
    251270            if (events_in_ram < max_events_ram) then
    252271              ram_write_ea <= '1';             
     
    261280        when MM_MAIN3 =>
    262281          state_mm <= MM_MAIN4;
    263           if ((wiz_ack = '1') and (wiz_ack_flag = '0')) then
     282          if ((wiz_ack_sr = "11") and (wiz_ack_flag = '0')) then
    264283            wiz_ack_flag <= '1';
    265284            wiz_write_ea <= '0';
     
    279298        when MM_MAIN4 =>
    280299          state_mm <= MM_MAIN;
    281           if ((events_in_ram > 0) and (wiz_busy = '0')) then
     300          if ((events_in_ram > 0) and (wiz_busy_sr = "00")) then
    282301            if (package_index < number_of_packages) then             
    283302              wiz_ram_start_addr <= conv_std_logic_vector(write_start_addr, RAM_ADDR_WIDTH_16B);
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_controller_beha.vhd

    r9912 r10729  
    3939  signal data_reg      : std_logic_vector (15 downto 0) := (others => '0');
    4040 
     41  signal dac_start_sr           : std_logic_vector (1 downto 0) := "00";
     42  signal sensor_start_sr        : std_logic_vector (1 downto 0) := "00";
     43 
    4144BEGIN
    4245 
     
    4447  begin
    4548    if falling_edge(clk) then
     49                dac_start_sr    <= dac_start_sr(0)              & dac_start;
     50                sensor_start_sr <= sensor_start_sr(0)   & sensor_start;
     51               
     52       
    4653      dac_cs <= '1';
    4754      sensor_cs <= (others => '1');
     
    5158      case spi_state is
    5259        when SPI_IDLE =>
    53           if (dac_start = '1') then
     60          if (dac_start_sr(1) = '1') then
    5461            dac_ready <= '0';
    5562            spi_state <= SPI_LOAD_COMMAND;
    56           elsif (sensor_start = '1') then
     63          elsif (sensor_start_sr(1) = '1') then
    5764            sensor_valid <= '0';
    5865            spi_state <= SPI_LOAD_COMMAND;
     
    6168        when SPI_LOAD_COMMAND =>
    6269          spi_cycle_cnt <= 0;
    63             if (sensor_start = '1') then
     70            if (sensor_start_sr(1) = '1') then
    6471              shift_reg <= X"C1" & X"0000";   -- command: Temperature register read
    6572              spi_state <= SPI_GET_TEMP;
    66             elsif (dac_start = '1') then
     73            elsif (dac_start_sr(1) = '1') then
    6774              shift_reg <= "0011" & '0' & dac_id & data;
    6875              spi_state <= SPI_LOAD_DAC;
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_distributor_beha.vhd

    r10225 r10729  
    5858  signal sclk_enable_override_sig : std_logic := '0';
    5959 
     60  -- synching signals
     61  signal config_start_sr                : std_logic_vector (1 downto 0) := "00";
     62 
    6063BEGIN
    6164  sclk_enable_override <= sclk_enable_override_sig;
     
    6669   
    6770    if rising_edge(clk) then
     71                -- synch in
     72                config_start_sr <= config_start_sr(0) & config_start;
     73               
    6874      data <= (others => 'Z');
    6975      case spi_distr_state is
     
    8086          data <= (others => 'Z');
    8187         -- start DAC configuration
    82           if (config_start = '1' AND int_sensor_valid = '1') then
     88          if (config_start_sr(1) = '1' AND int_sensor_valid = '1') then
    8389            config_ready <= '0';
    8490                        sclk_enable_override_sig <= '1';
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_interface_struct.vhd

    r10225 r10729  
    33-- Created:
    44--          by - daqct3.UNKNOWN (IHP110)
    5 --          at - 16:52:21 02.03.2011
     5--          at - 10:39:55 17.05.2011
    66--
    77-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
     
    3939-- Created:
    4040--          by - daqct3.UNKNOWN (IHP110)
    41 --          at - 16:52:21 02.03.2011
     41--          at - 10:39:56 17.05.2011
    4242--
    4343-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd

    r10565 r10729  
    1212  );
    1313   PORT(
     14      state          : OUT    std_logic_vector (7 DOWNTO 0);  -- state is encoded here ... useful for debugging.
     15          debug_data_ram_empty : OUT    std_logic;
     16          debug_data_valid : OUT    std_logic;
     17     
    1418      clk            : IN     std_logic;
    1519      wiz_reset      : OUT    std_logic                     := '1';
     
    3438      c_trigger_enable: out std_logic := '0';
    3539      c_trigger_mult: out std_logic_vector (15 DOWNTO 0) := conv_std_logic_vector(0 ,16); --subject to changes
     40     
     41     
    3642
    3743          -- FAD configuration signals:
     
    94100END w5300_modul ;
    95101
    96 architecture Behavioral of w5300_modul is
     102architecture Behavioral of w5300_modul is 
    97103
    98104type state_init_type is (
    99105        INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA,
    100106        INIT, LOCATE, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY,
    101         SI, SI1, SI2, SI3, SI4, SI5, SI6,       ESTABLISH, EST1,
     107        SI, SI1, SI1b, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1,
    102108       
    103         CONFIG,
    104         WAIT_FOR_OLLI,
    105         WAIT_FOR_DATA_RAM_EMPTY,
     109        --CONFIG, WAIT_FOR_OLLI, WAIT_FOR_DATA_RAM_EMPTY,
    106110        CONFIG_MEMORY_MANAGER, WAIT_FOR_CONFIG_MEMORY_MANAGER,
    107111        CONFIG_DATA_GENERATOR, WAIT_FOR_CONFIG_DATA_GENERATOR,
     
    185189signal local_fifo_channels : std_logic_vector (3 downto 0);
    186190
    187 signal data_ram_empty_sr : std_logic_vector (3 downto 0) := "0000";
    188 
    189191signal config_addr : integer range 0 to 44;
    190192type config_data_type is array (0 to 46) of std_logic_vector(15 downto 0);
     
    219221
    220222        -- signals for synching in asynchronous input signals
    221         ------------------------------------------------------------------------------
    222         signal w5300_interrupt_sr : std_logic_vector(1 downto 0) := "11";
    223          --?? not sure if this init value is good
    224          -- but should be no problem, because interrupt_ignore is not true during the first 2 clock cycles.
    225          -- I hope!
    226         signal data_valid_sr : std_logic_vector(1 downto 0) := "00";
    227         ------------------------------------------------------------------------------
    228 
     223                ------------------------------------------------------------------------------
     224                signal w5300_interrupt_sr : std_logic_vector(1 downto 0) := "11";
     225                 --?? not sure if this init value is good
     226                 -- but should be no problem, because interrupt_ignore is not true during the first 2 clock cycles.
     227                 -- I hope!
     228                signal data_valid_sr : std_logic_vector(1 downto 0) := "00";
     229                ------------------------------------------------------------------------------
     230                -- synch in CONFIG inputs
     231                signal memory_manager_config_valid_i_sr         : std_logic_vector(1 downto 0) := "00";
     232                signal spi_interface_config_valid_i_sr          : std_logic_vector(1 downto 0) := "00";
     233                signal data_generator_config_valid_i_sr         : std_logic_vector(1 downto 0) := "00";
     234                signal data_ram_empty_sr                                        : std_logic_vector(1 downto 0) := (OTHERS => '0');
     235
     236
     237               
    229238
    230239-- only for debugging
     
    243252signal mod7_result : std_logic_vector(2 downto 0);
    244253
     254signal state_sig : std_logic_vector(7 downto 0) := X"FF";
    245255
    246256
     
    279289 
    280290-- output config settings as DAC and ROI arrays.
    281 
     291state <= state_sig;
     292debug_data_ram_empty <= data_ram_empty_sr(1);
     293debug_data_valid <= data_valid_sr(1);
    282294
    283295roi_mapping : for i in 0 to 35 generate
     
    296308        begin
    297309                if rising_edge (clk) then
    298                 -- synch asynchronous input in:
    299                 data_ram_empty_sr <= data_ram_empty_sr(2 downto 0) & data_ram_empty;
    300                 w5300_interrupt_sr <= w5300_interrupt_sr(1) & int;
    301                 data_valid_sr <= data_valid_sr(1) & data_valid;
     310                -- synch asynchronous inputs in:
     311                memory_manager_config_valid_i_sr        <= memory_manager_config_valid_i_sr(0)  & memory_manager_config_valid_i;
     312                spi_interface_config_valid_i_sr         <= spi_interface_config_valid_i_sr(0)   & spi_interface_config_valid_i;
     313                data_generator_config_valid_i_sr        <=      data_generator_config_valid_i_sr(0)     & data_generator_config_valid_i;
     314                data_ram_empty_sr                                       <= data_ram_empty_sr(0)                 & data_ram_empty;                               
     315               
     316                w5300_interrupt_sr <= w5300_interrupt_sr(0) & int;
     317                data_valid_sr <= data_valid_sr(0) & data_valid;
    302318               
    303319                        -- interrupt is handled synchronously
     
    393409                                        -- reset W5300
    394410                                        when RESET =>
     411                                          state_sig <= X"01";
    395412                                                socket_send_mode <= '0';
    396413                                                busy <= '1';
     
    418435                                        -- Init
    419436                                        when INIT =>
     437                                          state_sig <= X"02";
    420438                                                -- status of MAC jumpers is synched in
    421439                                                -- and Board- and CrateID are synched in
     
    429447                                                next_state <= LOCATE;
    430448                               
    431                                         when LOCATE =>                                   
     449                                        when LOCATE =>
     450                                           state_sig <= X"03";                                   
    432451                                                state_init <= IM;
    433452
     
    481500                                        -- Interrupt Mask
    482501                                        when IM =>
     502                                          state_sig <= X"04";
    483503                                                par_addr <= W5300_IMR;
    484504                                                par_data <= X"00FF"; -- S0-S7 Interrupts
     
    604624                                        -- Socket Init
    605625                                        when SI =>
     626                                          state_sig <= X"05";
    606627                                                par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC;
    607628                                                par_data <= X"0101"; -- ALIGN, TCP
     
    613634                                                par_data <= X"000A"; -- TIMEOUT, DISCON
    614635                                                state_init <= WRITE_REG;
    615                                                 next_state <= SI2;
     636                                                next_state <= SI1b;
     637                                        when SI1b =>
     638                                                par_addr <= W5300_S0_PORTOR + socket_cnt * W5300_S_INC;
     639                                                par_data <= X"0606"; -- send automatic KEEP ALIVE every 30s.
     640                                                state_init <= WRITE_REG;
     641                                                next_state <= SI2;                                             
    616642                                        when SI2 =>
    617643                                                par_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC;
     
    668694                                                end case;
    669695                                               
    670                                         when CONFIG =>   -- Triggers are disabled here!
    671                                                 trigger_enable_storage_sig <= trigger_enable_sig;                               -- store last value of this signal.
    672                                                 trigger_enable_sig <= '0';                                                                              --no triggers must occur, while configurating.
    673                                                 state_init <= WAIT_FOR_OLLI;                                                                    -- now wait until the last event was send down..
    674                                        
    675                                         when WAIT_FOR_OLLI =>                                                                                   -- This single wait state is not needed, I guess.
    676                                                 state_init <= WAIT_FOR_DATA_RAM_EMPTY;                                          -- should be removed asap, but not now. 28.04.11 DN
    677                                        
    678                                                
    679                                         when WAIT_FOR_DATA_RAM_EMPTY =>
    680                                                 if (data_ram_empty_sr(3) = '1') then
    681                                                         state_init <= CONFIG_MEMORY_MANAGER;
    682                                                 end if;
     696--                                      when CONFIG =>   -- Triggers are disabled here!
     697--                                        state_sig <= X"06";
     698--                                              trigger_enable_storage_sig <= trigger_enable_sig;                               -- store last value of this signal.
     699--                                              trigger_enable_sig <= '0';                                                                              --no triggers must occur, while configurating.
     700--                                              state_init <= WAIT_FOR_OLLI;                                                                    -- now wait until the last event was send down..
     701--                                     
     702--                                      when WAIT_FOR_OLLI =>                                                                                   -- This single wait state is not needed, I guess.
     703--                                        state_sig <= X"16";
     704--                                              state_init <= WAIT_FOR_DATA_RAM_EMPTY;                                          -- should be removed asap, but not now. 28.04.11 DN
     705--                                     
     706--                                             
     707--                                      when WAIT_FOR_DATA_RAM_EMPTY =>
     708--                                        state_sig <= X"17";
     709--                                              if (data_ram_empty_sr(1) = '1') then
     710--                                                      state_init <= CONFIG_MEMORY_MANAGER;
     711--                                              end if;
    683712                                       
    684713                                        when CONFIG_MEMORY_MANAGER =>
     714                                          state_sig <= X"18";
    685715                                                memory_manager_config_start_o <= '1';
    686                                                 if (memory_manager_config_valid_i = '0') then
     716                                                if (memory_manager_config_valid_i_sr = "00") then
    687717                                                        state_init <= WAIT_FOR_CONFIG_MEMORY_MANAGER;
    688718                                                end if;
    689719                                       
    690720                                        when WAIT_FOR_CONFIG_MEMORY_MANAGER =>
     721                                          state_sig <= X"19";
    691722                                                memory_manager_config_start_o <= '0';
    692                                                 if (memory_manager_config_valid_i = '1') then
     723                                                if (memory_manager_config_valid_i_sr = "11") then
    693724                                                        state_init <= CONFIG_DATA_GENERATOR;
    694725                                                end if;
    695726                                       
    696727                                        when CONFIG_DATA_GENERATOR =>
     728                                          state_sig <= X"1A";
    697729                                                data_generator_config_start_o <= '1';
    698                                                 if (data_generator_config_valid_i = '0') then
     730                                                if (data_generator_config_valid_i_sr = "00") then
    699731                                                        state_init <= WAIT_FOR_CONFIG_DATA_GENERATOR;
    700732                                                end if;
    701733                                        when WAIT_FOR_CONFIG_DATA_GENERATOR =>
     734                                          state_sig <= X"1B";
    702735                                                data_generator_config_start_o <= '0';
    703                                                 if (data_generator_config_valid_i = '1') then
     736                                                if (data_generator_config_valid_i_sr ="11") then
    704737                                                        trigger_enable_sig <= trigger_enable_storage_sig; --restore value of this signal to the value it had before CONFIG
    705738                                                        state_init <= MAIN;
     
    708741                                               
    709742                                                when CONFIG_DAC_ONLY =>
     743                                                  state_sig <= X"1C";
    710744                                                        spi_interface_config_start_o <= '1';
    711                                                         if (spi_interface_config_valid_i ='0') then
     745                                                        if (spi_interface_config_valid_i_sr ="00") then
    712746                                                                state_init <= WAIT_FOR_CONFIG_DAC_ONLY;
    713747                                                        end if;
    714748                                               
    715749                                                when WAIT_FOR_CONFIG_DAC_ONLY =>
     750                                                  state_sig <= X"1D";
    716751                                                        spi_interface_config_start_o <= '0';
    717                                                         if (spi_interface_config_valid_i ='1') then
     752                                                        if (spi_interface_config_valid_i_sr ="11") then
    718753                                                                state_init <= MAIN;
    719754                                                        end if;
     
    724759         
    725760                                        when MAIN =>
     761                                        state_sig <= X"20";
     762                                        socks_waiting <= '0';
     763                                        socks_connected <= '1';
     764                                        ps_do_phase_shift <= '0';
     765                                        ps_reset <= '0';
     766                                        data_valid_ack <= '0';
    726767                                       
    727768                                               
    728                                                 if (update_of_rois = '1') then                         
    729                                                         update_of_rois <= '0';
    730                                                         state_init <= CONFIG;
     769                                                if (update_of_rois = '1') then
     770                                                        trigger_enable_storage_sig <= trigger_enable_sig;
     771                                                        trigger_enable_sig <= '0';
     772
     773                                                        if (data_ram_empty_sr(1) = '1') then
     774                                                                update_of_rois <= '0';
     775                                                                state_init <= CONFIG_MEMORY_MANAGER;
     776                                                        else
     777                                                                state_init <= MAIN2;
     778                                                        end if;
    731779                                                elsif (update_of_lessimportant = '1') then                             
    732780                                                        update_of_lessimportant <= '0';
    733781                                                        state_init <= CONFIG_DAC_ONLY;
    734782                                                elsif ( update_of_rois='0' and update_of_lessimportant='0' ) then
    735                                                         socks_waiting <= '0';
    736                                                         socks_connected <= '1';
    737                                                         ps_do_phase_shift <= '0';
    738                                                         ps_reset <= '0';
    739                                                         data_valid_ack <= '0';
    740783                                                        state_init <= MAIN1;
    741784                                                        --data_valid_int <= data_valid;
     
    743786                       
    744787                                        when MAIN1 =>
     788                                          state_sig <= X"21";
    745789                                                if (chk_recv_cntr = 1000) then
    746790                                                        chk_recv_cntr <= 0;
     
    753797                                                end if;
    754798                                        when MAIN2 =>
     799                                          state_sig <= X"22";
    755800                                                busy <= '0';
    756801                                                --if (data_valid = '1') then
    757                                                 if (data_valid_sr = "01" or data_valid_sr = "11") then
     802                                                if (data_valid_sr(1) = '1') then
    758803                                                        --data_valid_int <= '0';
    759804                                                        busy <= '1';
     
    769814                                                        state_init <= MAIN3;
    770815                                                else
    771                                                         state_init <= MAIN1;
     816                                                        state_init <= MAIN;  -- MAIN1
    772817                                                end if;
    773818                                        when MAIN3 =>
     819                                          state_sig <= X"23";
    774820                                                -- needed for the check: if there is enough space in W5300 FIFO
    775821                                                write_length_bytes <= local_write_length (15 downto 0) & '0'; -- shift left (*2)
     
    786832                                                case state_read_data is
    787833                                                when RD_1 =>
     834                                                  state_sig <= X"30";
    788835                                                        par_addr <= W5300_S0_RX_RSR;
    789836                                                        state_init <= READ_REG;
     
    791838                                                        state_read_data <= RD_2;
    792839                                                when RD_2 =>
     840                                                  state_sig <= X"31";
    793841                                                        socket_rx_received (16) <= data_read(0);
    794842                                                        par_addr <= W5300_S0_RX_RSR + X"2";
     
    797845                                                        state_read_data <= RD_3;
    798846                                                when RD_3 =>
     847                                                  state_sig <= X"32";
    799848                                                        socket_rx_received (15 downto 0) <= data_read;
    800849                                                        state_read_data <= RD_4;
    801850                                                when RD_4 =>
     851                                                  state_sig <= X"33";
    802852                                                        if (socket_rx_received (16 downto 0) > ('0' & X"000")) then
    803853                                                                rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2
     
    808858                                                        end if;
    809859                                                when RD_5 =>
     860                                                  state_sig <= X"34";
    810861                                                        s_trigger <= '0';
    811862                                                        ps_do_phase_shift <= '0';
     
    823874                                                       
    824875                                                when RD_6 =>
     876                                                  state_sig <= X"35";
    825877                                                        -- The next 16bit word is assumed to contain a 'command' so it is
    826878                                                        -- beeing parsed in this state
     
    905957                               
    906958                                                when WAIT_FOR_TRIGGER_ID_RESET_1 =>
     959                                                  state_sig <= X"36";
    907960                                                        state_read_data <= WAIT_FOR_TRIGGER_ID_RESET_2;
    908961                                                when WAIT_FOR_TRIGGER_ID_RESET_2 =>
     962                                                  state_sig <= X"37";
    909963                                                        state_read_data <= RD_5;
    910964                        -- these states are beeing processed, if the 'command' was a 'write command'
    911965                        --      so it is assumed, that some data in config RAM changed, and we need full (re)config
    912966                        when READ_COMMAND_DATA_SECTION =>
     967                          state_sig <= X"38";
    913968                                if (rx_packets_cnt > 0) then
    914969                                        rx_packets_cnt <= rx_packets_cnt - '1';
     
    922977                       
    923978                        when PUT_COMMAND_DATA_SECTION =>
     979                          state_sig <= X"39";
    924980                                config_setting(config_addr) <= data_read;
    925981                                if (config_addr < 36) then
     
    934990
    935991                        when RD_END =>
     992                          state_sig <= X"3A";
    936993                                par_addr <= W5300_S0_CR;
    937994                par_data <= X"0040"; -- RECV
    938995                state_init <= WRITE_REG;
    939996                                next_state <= MAIN;
    940 
    941 
     997                               
     998      when others =>
     999        state_sig <= X"3F";
     1000     
    9421001            end case; -- state_data_read
    9431002               
     
    9481007                                                       
    9491008                                                  when WR_START =>
     1009                                                    state_sig <= X"40";
    9501010                                                    if (local_write_header_flag = '1') then
    9511011                                                      ram_addr <= local_ram_start_addr + 6; -- Address of HIGH word of Event ID
     
    9561016                                                     
    9571017                                                  when WR_GET_EVT_ID_WAIT1 =>
     1018                                                    state_sig <= X"41";
    9581019                                                    state_write <= WR_GET_EVT_ID1;
    9591020                                                  when WR_GET_EVT_ID1 =>
     1021                                                    state_sig <= X"42";
    9601022                                                                event_number(31 downto 16) <= ram_data;
    9611023                                                                ram_addr <= local_ram_start_addr + 9; -- Address of LOW word of Event ID
     
    9641026                                                                state_write <= WR_GET_EVT_ID2;
    9651027                                                  when WR_GET_EVT_ID2 =>
     1028                                                    state_sig <= X"43";
    9661029                                                                event_number(15 downto 0) <= ram_data;
    9671030                                                                mod7_start <= '1';
     
    9731036                                                               
    9741037                                                        when WR_MOD7_STARTED =>
     1038                                                          state_sig <= X"44";
    9751039                                                                if (mod7_started = '1') then
    9761040                                                                        mod7_start <= '0';
     
    9791043
    9801044                                                        when WR_WAIT_FOR_MOD7 =>
     1045                                                          state_sig <= X"45";
    9811046                                                                if (mod7_valid = '1') then
    9821047                                                                        if (socket_send_mode = '1') then -- send via all sockets
     
    9941059                                                        -- Check FIFO Size
    9951060                                                        when WR_CHECK_FOR_FIFO_SPACE_01 =>
     1061                                                          state_sig <= X"46";
    9961062                                                                par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC;
    9971063                                                                state_init <= READ_REG;
     
    9991065                                                                state_write <= WR_CHECK_FOR_FIFO_SPACE_02;
    10001066                                                        when WR_CHECK_FOR_FIFO_SPACE_02 =>
     1067                                                          state_sig <= X"47";
    10011068                                                                socket_tx_free (16) <= data_read(0);
    10021069                                                                par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2";
     
    10051072                                                                state_write <= WR_CHECK_FOR_FIFO_SPACE_03;
    10061073                                                        when WR_CHECK_FOR_FIFO_SPACE_03 =>
     1074                                                          state_sig <= X"48";
    10071075                                                                socket_tx_free (15 downto 0) <= data_read;
    10081076                                                                state_write <= WR_CHECK_FOR_FIFO_SPACE_04;
    10091077                                                        when WR_CHECK_FOR_FIFO_SPACE_04 =>
     1078                                                          state_sig <= X"49";
    10101079--                                                              if (socket_tx_free (16 downto 0) < write_length_bytes) then
    10111080                                                                if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then
     
    10231092                                                        -- Write Header
    10241093                                                        when WR_FIFO =>
     1094                                                          state_sig <= X"4A";
    10251095                                                                ram_addr <= local_ram_start_addr + local_ram_addr;
    10261096                                                                state_write <= WR_FIFO1;
    10271097                                                        when WR_FIFO1 =>
     1098                                                          state_sig <= X"4B";
    10281099                                                                data_cnt <= data_cnt + 1;
    10291100                                                                if (data_cnt < PACKAGE_HEADER_LENGTH) then --???
     
    10481119                                                        ---- Start...
    10491120                                                        when WR_ADC =>
     1121                                                          state_sig <= X"4C";
    10501122                                                                adc_data_addr <= local_ram_start_addr + local_ram_addr;
    10511123                                                                drs_cnt <= 0;
     
    10581130                                                        ---- Write Channel
    10591131                                                        when WR_ADC1 =>
     1132                                                          state_sig <= X"4D";
    10601133                                                                -- read ROI and set end of Channel-Data
    10611134                                                                if (data_cnt = POSITION_OF_ROI_IN_CHANNEL_HEADER) then
     
    11061179              -- Write End Package Flag
    11071180              when WR_ENDFLAG =>
     1181                state_sig <= X"4E";
    11081182                ram_addr <= adc_data_addr + ((conv_integer(roi_max) + CHANNEL_HEADER_SIZE) * 4);
    11091183                state_write <= WR_ENDFLAG1;
     
    11551229                                                                state_init <= next_state_tmp;
    11561230                                                                state_write <= WR_START;
     1231                                                                state_sig <= X"4F";
    11571232                                                end case;
    11581233                                                -- End WRITE_DATA
    11591234                                               
    11601235                                        when READ_REG =>
     1236                                          state_sig <= X"50";
    11611237                                                case count is
    11621238                                                        when "000" =>
     
    11861262                                       
    11871263                                        when WRITE_REG =>
     1264                                          state_sig <= X"60";
    11881265                                                case count is
    11891266                                                        when "000" =>
     
    12081285                                                                count <= "000";
    12091286                                                        when others =>
     1287                                                          state_sig <= X"E0";
    12101288                                                                null;
    12111289                                                end case;
    12121290                                       
    12131291                                        when others =>
     1292                                          state_sig <= X"F0";
    12141293                                                null;
    12151294                                end case;
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_board_struct.xrf

    r10566 r10729  
    208208DESIGN @f@a@d_@board
    209209VIEW struct.bd
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    211 DESIGN @f@a@d_@board
    212 VIEW struct.bd
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    214 DESIGN @f@a@d_@board
    215 VIEW struct.bd
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     211DESIGN @f@a@d_@board
     212VIEW struct.bd
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     214DESIGN @f@a@d_@board
     215VIEW struct.bd
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     217DESIGN @f@a@d_@board
     218VIEW struct.bd
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     220DESIGN @f@a@d_@board
     221VIEW struct.bd
     222NO_GRAPHIC 110
     223DESIGN @f@a@d_@board
     224VIEW struct.bd
     225NO_GRAPHIC 111
    217226LIBRARY FACT_FAD_lib
    218227DESIGN @f@a@d_main
    219228VIEW struct
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    221 DESIGN @f@a@d_main
    222 VIEW symbol.sb
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    364 GRAPHIC 1042,0 161 0
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     231VIEW symbol.sb
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     233DESIGN @f@a@d_main
     234VIEW symbol.sb
     235GRAPHIC 1755,0 118 0
     236DESIGN @f@a@d_main
     237VIEW symbol.sb
     238GRAPHIC 5328,0 119 0
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     332DESIGN @f@a@d_main
     333VIEW symbol.sb
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     335DESIGN @f@a@d_main
     336VIEW symbol.sb
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     339VIEW symbol.sb
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     342VIEW symbol.sb
     343GRAPHIC 163,0 154 0
     344DESIGN @f@a@d_main
     345VIEW symbol.sb
     346GRAPHIC 4067,0 155 0
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     348VIEW symbol.sb
     349GRAPHIC 4916,0 156 0
     350DESIGN @f@a@d_main
     351VIEW symbol.sb
     352GRAPHIC 3631,0 157 0
     353DESIGN @f@a@d_main
     354VIEW symbol.sb
     355GRAPHIC 3646,0 158 0
     356DESIGN @f@a@d_main
     357VIEW symbol.sb
     358GRAPHIC 7539,0 159 0
     359DESIGN @f@a@d_main
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     361GRAPHIC 7850,0 160 0
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     363VIEW symbol.sb
     364GRAPHIC 1037,0 161 0
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     372VIEW symbol.sb
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     375VIEW symbol.sb
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     377DESIGN @f@a@d_main
     378VIEW symbol.sb
     379GRAPHIC 3636,0 166 0
     380DESIGN @f@a@d_main
     381VIEW symbol.sb
     382GRAPHIC 1042,0 167 0
    365383LIBRARY FACT_FAD_lib
    366384DESIGN @f@a@d_@board
    367385VIEW struct.bd
    368 NO_GRAPHIC 164
    369 DESIGN @f@a@d_@board
    370 VIEW struct.bd
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    376388VIEW struct.bd
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    384 DESIGN @f@a@d_@board
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    386 NO_GRAPHIC 183
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    403 VIEW struct.bd
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    406 VIEW struct.bd
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    409 VIEW struct.bd
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    412 VIEW struct.bd
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  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/.xrf/fad_main_struct.xrf

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     292DESIGN @f@a@d_main
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     298DESIGN @f@a@d_main
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     301DESIGN @f@a@d_main
     302VIEW struct.bd
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     304DESIGN @f@a@d_main
     305VIEW struct.bd
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     307DESIGN @f@a@d_main
     308VIEW struct.bd
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     310DESIGN @f@a@d_main
     311VIEW struct.bd
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     313DESIGN @f@a@d_main
     314VIEW struct.bd
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     316DESIGN @f@a@d_main
     317VIEW struct.bd
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     319DESIGN @f@a@d_main
     320VIEW struct.bd
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     322DESIGN @f@a@d_main
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     325DESIGN @f@a@d_main
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     328DESIGN @f@a@d_main
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     331DESIGN @f@a@d_main
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     334DESIGN @f@a@d_main
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     358DESIGN @f@a@d_main
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     362VIEW struct.bd
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     373DESIGN @f@a@d_main
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     376DESIGN @f@a@d_main
     377VIEW struct.bd
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     379DESIGN @f@a@d_main
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     385DESIGN @f@a@d_main
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     391DESIGN @f@a@d_main
     392VIEW struct.bd
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     395VIEW struct.bd
     396GRAPHIC 21043,0 185 0
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     398VIEW struct.bd
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     400DESIGN @f@a@d_main
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     403DESIGN @f@a@d_main
     404VIEW struct.bd
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     412DESIGN @f@a@d_main
     413VIEW struct.bd
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     415DESIGN @f@a@d_main
     416VIEW struct.bd
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     418DESIGN @f@a@d_main
     419VIEW struct.bd
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     421DESIGN @f@a@d_main
     422VIEW struct.bd
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     424DESIGN @f@a@d_main
     425VIEW struct.bd
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     428VIEW struct.bd
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     430DESIGN @f@a@d_main
     431VIEW struct.bd
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     433DESIGN @f@a@d_main
     434VIEW struct.bd
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     436DESIGN @f@a@d_main
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     439DESIGN @f@a@d_main
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     442DESIGN @f@a@d_main
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     446VIEW struct.bd
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     448DESIGN @f@a@d_main
     449VIEW struct.bd
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     451DESIGN @f@a@d_main
     452VIEW struct.bd
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     455VIEW struct.bd
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     460DESIGN @f@a@d_main
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     466DESIGN @f@a@d_main
     467VIEW struct.bd
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     469DESIGN @f@a@d_main
     470VIEW struct.bd
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    463472LIBRARY FACT_FAD_lib
    464473DESIGN @f@a@d_rs485_receiver
    465474VIEW beha
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    467 DESIGN @f@a@d_main
    468 VIEW struct.bd
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    470 DESIGN @f@a@d_main
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    473 DESIGN @f@a@d_main
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    476 DESIGN @f@a@d_main
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    479 DESIGN @f@a@d_main
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    482 DESIGN @f@a@d_main
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    485 DESIGN @f@a@d_main
    486 VIEW struct.bd
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     475GRAPHIC 24570,0 217 0
     476DESIGN @f@a@d_main
     477VIEW struct.bd
     478GRAPHIC 24577,0 218 1
     479DESIGN @f@a@d_main
     480VIEW struct.bd
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     482DESIGN @f@a@d_main
     483VIEW struct.bd
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     485DESIGN @f@a@d_main
     486VIEW struct.bd
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     488DESIGN @f@a@d_main
     489VIEW struct.bd
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     491DESIGN @f@a@d_main
     492VIEW struct.bd
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     494DESIGN @f@a@d_main
     495VIEW struct.bd
     496GRAPHIC 9175,0 253 0
    488497DESIGN clock_generator_var_ps
    489498VIEW symbol.sb
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     499GRAPHIC 168,0 255 0
    491500DESIGN clock_generator_var_ps
    492501VIEW symbol.sb
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     502GRAPHIC 848,0 256 0
    494503DESIGN clock_generator_var_ps
    495504VIEW symbol.sb
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     505GRAPHIC 703,0 257 0
    497506DESIGN clock_generator_var_ps
    498507VIEW symbol.sb
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     508GRAPHIC 698,0 258 0
    500509DESIGN clock_generator_var_ps
    501510VIEW symbol.sb
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     511GRAPHIC 126,0 259 0
    503512DESIGN clock_generator_var_ps
    504513VIEW symbol.sb
    505 GRAPHIC 643,0 257 0
     514GRAPHIC 643,0 260 0
    506515DESIGN clock_generator_var_ps
    507516VIEW symbol.sb
    508 GRAPHIC 121,0 258 0
     517GRAPHIC 121,0 261 0
    509518DESIGN clock_generator_var_ps
    510519VIEW symbol.sb
    511 GRAPHIC 1141,0 259 0
     520GRAPHIC 1141,0 262 0
    512521DESIGN clock_generator_var_ps
    513522VIEW symbol.sb
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     523GRAPHIC 947,0 263 0
    515524DESIGN clock_generator_var_ps
    516525VIEW symbol.sb
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    518 DESIGN @f@a@d_main
    519 VIEW struct.bd
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    521 DESIGN @f@a@d_main
    522 VIEW struct.bd
    523 GRAPHIC 13124,0 265 1
    524 DESIGN @f@a@d_main
    525 VIEW struct.bd
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    527 DESIGN @f@a@d_main
    528 VIEW struct.bd
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     526GRAPHIC 1146,0 264 0
     527DESIGN @f@a@d_main
     528VIEW struct.bd
     529GRAPHIC 13117,0 267 0
     530DESIGN @f@a@d_main
     531VIEW struct.bd
     532GRAPHIC 13124,0 268 1
     533DESIGN @f@a@d_main
     534VIEW struct.bd
     535NO_GRAPHIC 277
     536DESIGN @f@a@d_main
     537VIEW struct.bd
     538GRAPHIC 8277,0 279 0
    530539DESIGN data@r@a@m_64b_16b_width14_5
    531540VIEW data@r@a@m_64b_16b_width14_5_a
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     541GRAPHIC 48,0 281 0
    533542DESIGN data@r@a@m_64b_16b_width14_5
    534543VIEW data@r@a@m_64b_16b_width14_5_a
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     544GRAPHIC 53,0 282 0
    536545DESIGN data@r@a@m_64b_16b_width14_5
    537546VIEW data@r@a@m_64b_16b_width14_5_a
    538 GRAPHIC 58,0 280 0
     547GRAPHIC 58,0 283 0
    539548DESIGN data@r@a@m_64b_16b_width14_5
    540549VIEW data@r@a@m_64b_16b_width14_5_a
    541 GRAPHIC 63,0 281 0
     550GRAPHIC 63,0 284 0
    542551DESIGN data@r@a@m_64b_16b_width14_5
    543552VIEW data@r@a@m_64b_16b_width14_5_a
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     553GRAPHIC 68,0 285 0
    545554DESIGN data@r@a@m_64b_16b_width14_5
    546555VIEW data@r@a@m_64b_16b_width14_5_a
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     556GRAPHIC 73,0 286 0
    548557DESIGN data@r@a@m_64b_16b_width14_5
    549558VIEW data@r@a@m_64b_16b_width14_5_a
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    551 DESIGN @f@a@d_main
    552 VIEW struct.bd
    553 GRAPHIC 1399,0 287 0
    554 DESIGN data_generator
    555 VIEW symbol.sb
    556 GRAPHIC 14,0 288 1
    557 DESIGN data_generator
    558 VIEW @behavioral
    559 GRAPHIC 48,0 292 0
    560 DESIGN data_generator
    561 VIEW @behavioral
    562 GRAPHIC 53,0 293 0
    563 DESIGN data_generator
    564 VIEW @behavioral
    565 GRAPHIC 58,0 294 0
    566 DESIGN data_generator
    567 VIEW @behavioral
    568 GRAPHIC 1932,0 295 0
    569 DESIGN data_generator
    570 VIEW @behavioral
    571 GRAPHIC 78,0 296 0
    572 DESIGN data_generator
    573 VIEW @behavioral
    574 GRAPHIC 402,0 297 0
    575 DESIGN data_generator
    576 VIEW @behavioral
    577 GRAPHIC 407,0 298 0
    578 DESIGN data_generator
    579 VIEW @behavioral
    580 GRAPHIC 1479,0 299 0
    581 DESIGN data_generator
    582 VIEW @behavioral
    583 GRAPHIC 473,0 300 0
    584 DESIGN data_generator
    585 VIEW @behavioral
    586 GRAPHIC 412,0 301 0
    587 DESIGN data_generator
    588 VIEW @behavioral
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    590 DESIGN data_generator
    591 VIEW @behavioral
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    593 DESIGN data_generator
    594 VIEW @behavioral
    595 GRAPHIC 1240,0 304 0
    596 DESIGN data_generator
    597 VIEW @behavioral
    598 GRAPHIC 2051,0 305 0
    599 DESIGN data_generator
    600 VIEW @behavioral
    601 GRAPHIC 2046,0 306 0
    602 DESIGN data_generator
    603 VIEW @behavioral
    604 GRAPHIC 526,0 307 0
    605 DESIGN data_generator
    606 VIEW @behavioral
    607 GRAPHIC 1615,0 309 0
    608 DESIGN data_generator
    609 VIEW @behavioral
    610 GRAPHIC 2100,0 310 0
    611 DESIGN data_generator
    612 VIEW @behavioral
    613 GRAPHIC 2095,0 311 0
    614 DESIGN data_generator
    615 VIEW @behavioral
    616 GRAPHIC 1725,0 312 0
    617 DESIGN data_generator
    618 VIEW @behavioral
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    620 DESIGN data_generator
    621 VIEW @behavioral
    622 GRAPHIC 2202,0 317 0
    623 DESIGN data_generator
    624 VIEW @behavioral
    625 GRAPHIC 1647,0 318 0
    626 DESIGN data_generator
    627 VIEW @behavioral
    628 GRAPHIC 1679,0 320 0
    629 DESIGN data_generator
    630 VIEW @behavioral
    631 GRAPHIC 1684,0 321 0
    632 DESIGN data_generator
    633 VIEW @behavioral
    634 GRAPHIC 1689,0 322 0
    635 DESIGN data_generator
    636 VIEW @behavioral
    637 GRAPHIC 88,0 323 0
    638 DESIGN data_generator
    639 VIEW @behavioral
    640 GRAPHIC 285,0 325 0
    641 DESIGN data_generator
    642 VIEW @behavioral
    643 GRAPHIC 1764,0 326 0
    644 DESIGN data_generator
    645 VIEW @behavioral
    646 GRAPHIC 2085,0 327 0
    647 DESIGN data_generator
    648 VIEW @behavioral
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    650 DESIGN data_generator
    651 VIEW @behavioral
    652 GRAPHIC 2138,0 329 0
    653 DESIGN data_generator
    654 VIEW @behavioral
    655 GRAPHIC 1769,0 330 0
    656 DESIGN data_generator
    657 VIEW @behavioral
    658 GRAPHIC 1810,0 331 0
    659 DESIGN data_generator
    660 VIEW @behavioral
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    662 DESIGN data_generator
    663 VIEW @behavioral
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    665 DESIGN data_generator
    666 VIEW @behavioral
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    668 DESIGN data_generator
    669 VIEW @behavioral
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    671 DESIGN data_generator
    672 VIEW @behavioral
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    674 DESIGN data_generator
    675 VIEW @behavioral
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    677 DESIGN data_generator
    678 VIEW @behavioral
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    680 DESIGN data_generator
    681 VIEW @behavioral
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    683 DESIGN data_generator
    684 VIEW @behavioral
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    686 DESIGN data_generator
    687 VIEW @behavioral
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    689 DESIGN data_generator
    690 VIEW @behavioral
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    692 DESIGN data_generator
    693 VIEW @behavioral
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    695 DESIGN data_generator
    696 VIEW @behavioral
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    698 DESIGN data_generator
    699 VIEW @behavioral
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    701 DESIGN data_generator
    702 VIEW @behavioral
    703 GRAPHIC 1459,0 349 0
    704 DESIGN data_generator
    705 VIEW @behavioral
    706 GRAPHIC 1474,0 350 0
    707 DESIGN data_generator
    708 VIEW @behavioral
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    710 DESIGN data_generator
    711 VIEW @behavioral
    712 GRAPHIC 811,0 352 0
    713 DESIGN data_generator
    714 VIEW @behavioral
    715 GRAPHIC 1519,0 353 0
    716 DESIGN data_generator
    717 VIEW @behavioral
    718 GRAPHIC 2170,0 354 0
    719 DESIGN @f@a@d_main
    720 VIEW struct.bd
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     559GRAPHIC 78,0 287 0
     560DESIGN @f@a@d_main
     561VIEW struct.bd
     562GRAPHIC 1399,0 290 0
     563DESIGN data_generator
     564VIEW symbol.sb
     565GRAPHIC 14,0 291 1
     566DESIGN data_generator
     567VIEW @behavioral
     568GRAPHIC 48,0 295 0
     569DESIGN data_generator
     570VIEW @behavioral
     571GRAPHIC 53,0 296 0
     572DESIGN data_generator
     573VIEW @behavioral
     574GRAPHIC 58,0 297 0
     575DESIGN data_generator
     576VIEW @behavioral
     577GRAPHIC 1932,0 298 0
     578DESIGN data_generator
     579VIEW @behavioral
     580GRAPHIC 78,0 299 0
     581DESIGN data_generator
     582VIEW @behavioral
     583GRAPHIC 402,0 300 0
     584DESIGN data_generator
     585VIEW @behavioral
     586GRAPHIC 407,0 301 0
     587DESIGN data_generator
     588VIEW @behavioral
     589GRAPHIC 1479,0 302 0
     590DESIGN data_generator
     591VIEW @behavioral
     592GRAPHIC 473,0 303 0
     593DESIGN data_generator
     594VIEW @behavioral
     595GRAPHIC 412,0 304 0
     596DESIGN data_generator
     597VIEW @behavioral
     598GRAPHIC 1085,0 305 0
     599DESIGN data_generator
     600VIEW @behavioral
     601GRAPHIC 1090,0 306 0
     602DESIGN data_generator
     603VIEW @behavioral
     604GRAPHIC 1240,0 307 0
     605DESIGN data_generator
     606VIEW @behavioral
     607GRAPHIC 2051,0 308 0
     608DESIGN data_generator
     609VIEW @behavioral
     610GRAPHIC 2046,0 309 0
     611DESIGN data_generator
     612VIEW @behavioral
     613GRAPHIC 526,0 310 0
     614DESIGN data_generator
     615VIEW @behavioral
     616GRAPHIC 1615,0 312 0
     617DESIGN data_generator
     618VIEW @behavioral
     619GRAPHIC 2100,0 313 0
     620DESIGN data_generator
     621VIEW @behavioral
     622GRAPHIC 2095,0 314 0
     623DESIGN data_generator
     624VIEW @behavioral
     625GRAPHIC 1725,0 315 0
     626DESIGN data_generator
     627VIEW @behavioral
     628GRAPHIC 1730,0 319 0
     629DESIGN data_generator
     630VIEW @behavioral
     631GRAPHIC 2202,0 320 0
     632DESIGN data_generator
     633VIEW @behavioral
     634GRAPHIC 1647,0 321 0
     635DESIGN data_generator
     636VIEW @behavioral
     637GRAPHIC 1679,0 323 0
     638DESIGN data_generator
     639VIEW @behavioral
     640GRAPHIC 1684,0 324 0
     641DESIGN data_generator
     642VIEW @behavioral
     643GRAPHIC 1689,0 325 0
     644DESIGN data_generator
     645VIEW @behavioral
     646GRAPHIC 88,0 326 0
     647DESIGN data_generator
     648VIEW @behavioral
     649GRAPHIC 285,0 328 0
     650DESIGN data_generator
     651VIEW @behavioral
     652GRAPHIC 1764,0 329 0
     653DESIGN data_generator
     654VIEW @behavioral
     655GRAPHIC 2085,0 330 0
     656DESIGN data_generator
     657VIEW @behavioral
     658GRAPHIC 2090,0 331 0
     659DESIGN data_generator
     660VIEW @behavioral
     661GRAPHIC 2138,0 332 0
     662DESIGN data_generator
     663VIEW @behavioral
     664GRAPHIC 1769,0 333 0
     665DESIGN data_generator
     666VIEW @behavioral
     667GRAPHIC 1810,0 334 0
     668DESIGN data_generator
     669VIEW @behavioral
     670GRAPHIC 2234,0 336 0
     671DESIGN data_generator
     672VIEW @behavioral
     673GRAPHIC 1842,0 338 0
     674DESIGN data_generator
     675VIEW @behavioral
     676GRAPHIC 2305,0 339 0
     677DESIGN data_generator
     678VIEW @behavioral
     679GRAPHIC 898,0 340 0
     680DESIGN data_generator
     681VIEW @behavioral
     682GRAPHIC 1922,0 341 0
     683DESIGN data_generator
     684VIEW @behavioral
     685GRAPHIC 1395,0 342 0
     686DESIGN data_generator
     687VIEW @behavioral
     688GRAPHIC 1427,0 343 0
     689DESIGN data_generator
     690VIEW @behavioral
     691GRAPHIC 676,0 344 0
     692DESIGN data_generator
     693VIEW @behavioral
     694GRAPHIC 1551,0 345 0
     695DESIGN data_generator
     696VIEW @behavioral
     697GRAPHIC 1583,0 347 0
     698DESIGN data_generator
     699VIEW @behavioral
     700GRAPHIC 681,0 348 0
     701DESIGN data_generator
     702VIEW @behavioral
     703GRAPHIC 1942,0 349 0
     704DESIGN data_generator
     705VIEW @behavioral
     706GRAPHIC 1464,0 350 0
     707DESIGN data_generator
     708VIEW @behavioral
     709GRAPHIC 1469,0 351 0
     710DESIGN data_generator
     711VIEW @behavioral
     712GRAPHIC 1459,0 352 0
     713DESIGN data_generator
     714VIEW @behavioral
     715GRAPHIC 1474,0 353 0
     716DESIGN data_generator
     717VIEW @behavioral
     718GRAPHIC 806,0 354 0
     719DESIGN data_generator
     720VIEW @behavioral
     721GRAPHIC 811,0 355 0
     722DESIGN data_generator
     723VIEW @behavioral
     724GRAPHIC 1519,0 356 0
     725DESIGN data_generator
     726VIEW @behavioral
     727GRAPHIC 2170,0 357 0
     728DESIGN @f@a@d_main
     729VIEW struct.bd
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     1463GRAPHIC 11405,0 772 0
     1464DESIGN @f@a@d_main
     1465VIEW struct.bd
     1466GRAPHIC 24078,0 773 0
     1467DESIGN @f@a@d_main
     1468VIEW struct.bd
     1469GRAPHIC 16404,0 775 0
     1470DESIGN @f@a@d_main
     1471VIEW struct.bd
     1472GRAPHIC 16556,0 777 0
     1473DESIGN @f@a@d_main
     1474VIEW struct.bd
     1475GRAPHIC 16547,0 778 0
     1476DESIGN @f@a@d_main
     1477VIEW struct.bd
     1478GRAPHIC 16564,0 779 0
     1479DESIGN @f@a@d_main
     1480VIEW struct.bd
     1481GRAPHIC 4903,0 781 0
     1482DESIGN @f@a@d_main
     1483VIEW struct.bd
     1484GRAPHIC 18081,0 783 0
     1485DESIGN @f@a@d_main
     1486VIEW struct.bd
     1487GRAPHIC 4401,0 784 0
     1488DESIGN @f@a@d_main
     1489VIEW struct.bd
     1490GRAPHIC 4419,0 785 0
     1491DESIGN @f@a@d_main
     1492VIEW struct.bd
     1493GRAPHIC 4671,0 786 0
     1494DESIGN @f@a@d_main
     1495VIEW struct.bd
     1496GRAPHIC 4679,0 787 0
     1497DESIGN @f@a@d_main
     1498VIEW struct.bd
     1499GRAPHIC 4687,0 788 0
     1500DESIGN @f@a@d_main
     1501VIEW struct.bd
     1502GRAPHIC 4695,0 789 0
     1503DESIGN @f@a@d_main
     1504VIEW struct.bd
     1505GRAPHIC 4407,0 790 0
     1506DESIGN @f@a@d_main
     1507VIEW struct.bd
     1508GRAPHIC 4743,0 791 0
     1509DESIGN @f@a@d_main
     1510VIEW struct.bd
     1511GRAPHIC 10298,0 792 0
     1512DESIGN @f@a@d_main
     1513VIEW struct.bd
     1514GRAPHIC 10310,0 793 0
     1515DESIGN @f@a@d_main
     1516VIEW struct.bd
     1517GRAPHIC 10304,0 794 0
     1518DESIGN @f@a@d_main
     1519VIEW struct.bd
     1520GRAPHIC 10316,0 795 0
     1521DESIGN @f@a@d_main
     1522VIEW struct.bd
     1523GRAPHIC 10322,0 796 0
     1524DESIGN @f@a@d_main
     1525VIEW struct.bd
     1526GRAPHIC 4948,0 797 0
     1527DESIGN @f@a@d_main
     1528VIEW struct.bd
     1529GRAPHIC 10010,0 798 0
     1530DESIGN @f@a@d_main
     1531VIEW struct.bd
     1532GRAPHIC 11209,0 800 0
     1533DESIGN @f@a@d_main
     1534VIEW struct.bd
     1535GRAPHIC 11216,0 801 1
     1536DESIGN @f@a@d_main
     1537VIEW struct.bd
     1538GRAPHIC 10699,0 806 0
     1539DESIGN @f@a@d_main
     1540VIEW struct.bd
     1541GRAPHIC 10723,0 807 0
     1542DESIGN @f@a@d_main
     1543VIEW struct.bd
     1544GRAPHIC 10737,0 808 0
     1545DESIGN @f@a@d_main
     1546VIEW struct.bd
     1547GRAPHIC 10751,0 809 0
     1548DESIGN @f@a@d_main
     1549VIEW struct.bd
     1550GRAPHIC 10707,0 811 0
     1551DESIGN @f@a@d_main
     1552VIEW struct.bd
     1553GRAPHIC 22360,0 812 0
     1554DESIGN @f@a@d_main
     1555VIEW struct.bd
     1556GRAPHIC 22352,0 813 0
     1557DESIGN @f@a@d_main
     1558VIEW struct.bd
     1559GRAPHIC 10685,0 814 0
     1560DESIGN @f@a@d_main
     1561VIEW struct.bd
     1562GRAPHIC 10691,0 815 0
     1563DESIGN @f@a@d_main
     1564VIEW struct.bd
     1565GRAPHIC 2311,0 817 0
     1566DESIGN @f@a@d_main
     1567VIEW struct.bd
     1568GRAPHIC 2318,0 818 1
     1569DESIGN @f@a@d_main
     1570VIEW struct.bd
     1571GRAPHIC 15379,0 823 0
     1572DESIGN @f@a@d_main
     1573VIEW struct.bd
     1574GRAPHIC 21067,0 824 0
     1575DESIGN @f@a@d_main
     1576VIEW struct.bd
     1577GRAPHIC 2582,0 825 0
     1578DESIGN @f@a@d_main
     1579VIEW struct.bd
     1580GRAPHIC 10467,0 826 0
     1581DESIGN @f@a@d_main
     1582VIEW struct.bd
     1583GRAPHIC 20945,0 827 0
     1584DESIGN @f@a@d_main
     1585VIEW struct.bd
     1586GRAPHIC 2576,0 828 0
     1587DESIGN @f@a@d_main
     1588VIEW struct.bd
     1589GRAPHIC 21083,0 829 0
     1590DESIGN @f@a@d_main
     1591VIEW struct.bd
     1592GRAPHIC 2600,0 830 0
     1593DESIGN @f@a@d_main
     1594VIEW struct.bd
     1595GRAPHIC 2642,0 831 0
     1596DESIGN @f@a@d_main
     1597VIEW struct.bd
     1598GRAPHIC 2488,0 832 0
     1599DESIGN @f@a@d_main
     1600VIEW struct.bd
     1601GRAPHIC 2482,0 833 0
     1602DESIGN @f@a@d_main
     1603VIEW struct.bd
     1604GRAPHIC 2494,0 834 0
     1605DESIGN @f@a@d_main
     1606VIEW struct.bd
     1607GRAPHIC 2476,0 835 0
     1608DESIGN @f@a@d_main
     1609VIEW struct.bd
     1610GRAPHIC 2506,0 836 0
     1611DESIGN @f@a@d_main
     1612VIEW struct.bd
     1613GRAPHIC 2500,0 837 0
     1614DESIGN @f@a@d_main
     1615VIEW struct.bd
     1616GRAPHIC 2470,0 838 0
     1617DESIGN @f@a@d_main
     1618VIEW struct.bd
     1619GRAPHIC 8416,0 839 0
     1620DESIGN @f@a@d_main
     1621VIEW struct.bd
     1622GRAPHIC 2299,0 840 0
     1623DESIGN @f@a@d_main
     1624VIEW struct.bd
     1625GRAPHIC 18459,0 841 0
     1626DESIGN @f@a@d_main
     1627VIEW struct.bd
     1628GRAPHIC 5793,0 843 0
     1629DESIGN @f@a@d_main
     1630VIEW struct.bd
     1631GRAPHIC 5805,0 845 0
     1632DESIGN @f@a@d_main
     1633VIEW struct.bd
     1634GRAPHIC 21049,0 846 0
     1635DESIGN @f@a@d_main
     1636VIEW struct.bd
     1637GRAPHIC 20931,0 847 0
     1638DESIGN @f@a@d_main
     1639VIEW struct.bd
     1640GRAPHIC 21559,0 848 0
     1641DESIGN @f@a@d_main
     1642VIEW struct.bd
     1643GRAPHIC 21061,0 849 0
     1644DESIGN @f@a@d_main
     1645VIEW struct.bd
     1646GRAPHIC 20153,0 850 0
     1647DESIGN @f@a@d_main
     1648VIEW struct.bd
     1649GRAPHIC 5829,0 851 0
     1650DESIGN @f@a@d_main
     1651VIEW struct.bd
     1652GRAPHIC 6160,0 852 0
     1653DESIGN @f@a@d_main
     1654VIEW struct.bd
     1655GRAPHIC 5813,0 853 0
     1656DESIGN @f@a@d_main
     1657VIEW struct.bd
     1658GRAPHIC 5480,0 854 0
     1659DESIGN @f@a@d_main
     1660VIEW struct.bd
     1661GRAPHIC 5837,0 855 0
     1662DESIGN @f@a@d_main
     1663VIEW struct.bd
     1664GRAPHIC 5474,0 856 0
     1665DESIGN @f@a@d_main
     1666VIEW struct.bd
     1667GRAPHIC 5821,0 857 0
     1668DESIGN @f@a@d_main
     1669VIEW struct.bd
     1670GRAPHIC 16865,0 859 0
     1671DESIGN @f@a@d_main
     1672VIEW struct.bd
     1673GRAPHIC 16872,0 860 1
     1674DESIGN @f@a@d_main
     1675VIEW struct.bd
     1676GRAPHIC 16877,0 865 0
     1677DESIGN @f@a@d_main
     1678VIEW struct.bd
     1679GRAPHIC 16945,0 866 0
     1680DESIGN @f@a@d_main
     1681VIEW struct.bd
     1682GRAPHIC 16885,0 867 0
     1683DESIGN @f@a@d_main
     1684VIEW struct.bd
     1685GRAPHIC 16939,0 869 0
     1686DESIGN @f@a@d_main
     1687VIEW struct.bd
     1688GRAPHIC 16914,0 870 0
     1689DESIGN @f@a@d_main
     1690VIEW struct.bd
     1691GRAPHIC 1768,0 872 0
     1692DESIGN @f@a@d_main
     1693VIEW struct.bd
     1694GRAPHIC 15750,0 874 0
     1695DESIGN @f@a@d_main
     1696VIEW struct.bd
     1697GRAPHIC 15498,0 875 0
     1698DESIGN @f@a@d_main
     1699VIEW struct.bd
     1700GRAPHIC 25035,0 876 0
     1701DESIGN @f@a@d_main
     1702VIEW struct.bd
     1703GRAPHIC 6276,0 877 0
     1704DESIGN @f@a@d_main
     1705VIEW struct.bd
     1706GRAPHIC 12625,0 879 0
     1707DESIGN @f@a@d_main
     1708VIEW struct.bd
     1709GRAPHIC 12687,0 881 0
     1710DESIGN @f@a@d_main
     1711VIEW struct.bd
     1712GRAPHIC 12643,0 882 0
     1713DESIGN @f@a@d_main
     1714VIEW struct.bd
     1715GRAPHIC 15494,0 883 0
     1716DESIGN @f@a@d_main
     1717VIEW struct.bd
     1718GRAPHIC 6540,0 884 0
     1719DESIGN @f@a@d_main
     1720VIEW struct.bd
     1721GRAPHIC 12649,0 885 0
     1722DESIGN @f@a@d_main
     1723VIEW struct.bd
     1724GRAPHIC 12655,0 886 0
     1725DESIGN @f@a@d_main
     1726VIEW struct.bd
     1727GRAPHIC 1606,0 888 0
     1728DESIGN @f@a@d_main
     1729VIEW struct.bd
     1730GRAPHIC 1613,0 889 1
     1731DESIGN @f@a@d_main
     1732VIEW struct.bd
     1733GRAPHIC 25298,0 893 0
     1734DESIGN @f@a@d_main
     1735VIEW struct.bd
     1736GRAPHIC 25543,0 894 0
     1737DESIGN @f@a@d_main
     1738VIEW struct.bd
     1739GRAPHIC 25557,0 895 0
     1740DESIGN @f@a@d_main
     1741VIEW struct.bd
     1742GRAPHIC 4240,0 896 0
     1743DESIGN @f@a@d_main
     1744VIEW struct.bd
     1745GRAPHIC 376,0 897 0
     1746DESIGN @f@a@d_main
     1747VIEW struct.bd
     1748GRAPHIC 384,0 898 0
     1749DESIGN @f@a@d_main
     1750VIEW struct.bd
     1751GRAPHIC 392,0 899 0
     1752DESIGN @f@a@d_main
     1753VIEW struct.bd
     1754GRAPHIC 400,0 900 0
     1755DESIGN @f@a@d_main
     1756VIEW struct.bd
     1757GRAPHIC 408,0 901 0
     1758DESIGN @f@a@d_main
     1759VIEW struct.bd
     1760GRAPHIC 5222,0 902 0
     1761DESIGN @f@a@d_main
     1762VIEW struct.bd
     1763GRAPHIC 424,0 903 0
     1764DESIGN @f@a@d_main
     1765VIEW struct.bd
     1766GRAPHIC 432,0 904 0
     1767DESIGN @f@a@d_main
     1768VIEW struct.bd
     1769GRAPHIC 2482,0 905 0
     1770DESIGN @f@a@d_main
     1771VIEW struct.bd
     1772GRAPHIC 2488,0 906 0
     1773DESIGN @f@a@d_main
     1774VIEW struct.bd
     1775GRAPHIC 370,0 907 0
     1776DESIGN @f@a@d_main
     1777VIEW struct.bd
     1778GRAPHIC 364,0 908 0
     1779DESIGN @f@a@d_main
     1780VIEW struct.bd
     1781GRAPHIC 2476,0 909 0
     1782DESIGN @f@a@d_main
     1783VIEW struct.bd
     1784GRAPHIC 8416,0 910 0
     1785DESIGN @f@a@d_main
     1786VIEW struct.bd
     1787GRAPHIC 2470,0 911 0
     1788DESIGN @f@a@d_main
     1789VIEW struct.bd
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     1791DESIGN @f@a@d_main
     1792VIEW struct.bd
     1793GRAPHIC 2500,0 913 0
     1794DESIGN @f@a@d_main
     1795VIEW struct.bd
     1796GRAPHIC 2494,0 914 0
     1797DESIGN @f@a@d_main
     1798VIEW struct.bd
     1799GRAPHIC 10266,0 915 0
     1800DESIGN @f@a@d_main
     1801VIEW struct.bd
     1802GRAPHIC 13159,0 916 0
     1803DESIGN @f@a@d_main
     1804VIEW struct.bd
     1805GRAPHIC 17393,0 917 0
     1806DESIGN @f@a@d_main
     1807VIEW struct.bd
     1808GRAPHIC 20987,0 918 0
     1809DESIGN @f@a@d_main
     1810VIEW struct.bd
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     1812DESIGN @f@a@d_main
     1813VIEW struct.bd
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     1815DESIGN @f@a@d_main
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     1818DESIGN @f@a@d_main
     1819VIEW struct.bd
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     1821DESIGN @f@a@d_main
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     1824DESIGN @f@a@d_main
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     1827DESIGN @f@a@d_main
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     1830DESIGN @f@a@d_main
     1831VIEW struct.bd
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     1833DESIGN @f@a@d_main
     1834VIEW struct.bd
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     1836DESIGN @f@a@d_main
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     1839DESIGN @f@a@d_main
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     1842DESIGN @f@a@d_main
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     1845DESIGN @f@a@d_main
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     1848DESIGN @f@a@d_main
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     1851DESIGN @f@a@d_main
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     1854DESIGN @f@a@d_main
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     1857DESIGN @f@a@d_main
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     1860DESIGN @f@a@d_main
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     1863DESIGN @f@a@d_main
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     1866DESIGN @f@a@d_main
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     1869DESIGN @f@a@d_main
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     1872DESIGN @f@a@d_main
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     1875DESIGN @f@a@d_main
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     1887DESIGN @f@a@d_main
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     1897VIEW struct.bd
     1898NO_GRAPHIC 952
  • firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hds/@f@a@d_@board/struct.bd

    r10566 r10729  
    115115(vvPair
    116116variable "date"
    117 value "26.04.2011"
     117value "17.05.2011"
    118118)
    119119(vvPair
     
    127127(vvPair
    128128variable "dd"
    129 value "26"
     129value "17"
    130130)
    131131(vvPair
     
    187187(vvPair
    188188variable "mm"
    189 value "04"
     189value "05"
    190190)
    191191(vvPair
     
    195195(vvPair
    196196variable "month"
    197 value "Apr"
     197value "Mai"
    198198)
    199199(vvPair
    200200variable "month_long"
    201 value "April"
     201value "Mai"
    202202)
    203203(vvPair
     
    263263(vvPair
    264264variable "time"
    265 value "17:09:12"
     265value "17:57:36"
    266266)
    267267(vvPair
     
    315315bg "0,0,32768"
    316316)
    317 xt "99200,4000,110100,5000"
     317xt "99200,4000,109900,5000"
    318318st "
    319319by %user on %dd %month %year
     
    33273327va (VaSet
    33283328)
    3329 xt "154200,66200,178100,94200"
     3329xt "154200,66200,178100,97200"
    33303330st "
    33313331-- testpins D_T2 are used as MAX3485 outputs.
    33323332
    33333333--D_T <= (others => '0');
     3334D_T <= w5300_state;
     3335D_T2(0) <= debug_data_valid;
     3336D_T2(1) <= debug_data_ram_empty;
    33343337--D_T2 <= ( others => '0' );
    3335 D_T2(1) <= '0';
     3338
    33363339-- A0_T(7 downto 0) <= (others => '0');
    33373340--A1_T(7 downto 0) <= (others => '0');
    33383341
    33393342A1_T <= counter_result ( 7 downto 0);
    3340 D_T(3 downto 0) <=  counter_result ( 11 downto 8);
    3341 D_T(4) <= alarm_refclk_too_low;
    3342 D_T(5) <= alarm_refclk_too_high;
    3343 D_T(6) <= '0';
    3344 D_T(7) <= '0';
     3343--D_T(3 downto 0) <=  counter_result ( 11 downto 8);
     3344--D_T(4) <= alarm_refclk_too_low;
     3345--D_T(5) <= alarm_refclk_too_high;
     3346--D_T(6) <= '0';
     3347--D_T(7) <= '0';
    33453348
    33463349-- led output is driven by w5300 modul
     
    33533356RS485_C_DO <= '0';
    33543357-- MAX3485 receiver out pit is fed out... should be HIGH-Z
    3355 D_T2(0) <= RS485_C_DI;
     3358
    33563359
    33573360-- EEPROM is not used on FAD. CS is always high.
     
    40794082font "Courier New,8,0"
    40804083)
    4081 xt "39000,53600,80500,54400"
     4084xt "39000,55200,80500,56000"
    40824085st "SIGNAL led                   : std_logic_vector(7 DOWNTO 0)  := (OTHERS => '0')
    40834086"
     
    45184521n "wiz_reset"
    45194522t "std_logic"
    4520 o 44
     4523o 47
    45214524suid 2,0
    45224525i "'1'"
     
    45574560b "(7 DOWNTO 0)"
    45584561posAdd 0
    4559 o 35
     4562o 37
    45604563suid 7,0
    45614564i "(OTHERS => '0')"
     
    47374740t "std_logic_vector"
    47384741b "(9 DOWNTO 0)"
    4739 o 41
     4742o 44
    47404743suid 26,0
    47414744)
     
    47744777t "std_logic_vector"
    47754778b "(15 DOWNTO 0)"
    4776 o 47
     4779o 50
    47774780suid 27,0
    47784781)
     
    48104813n "wiz_cs"
    48114814t "std_logic"
    4812 o 42
     4815o 45
    48134816suid 28,0
    48144817i "'1'"
     
    48474850n "wiz_wr"
    48484851t "std_logic"
    4849 o 45
     4852o 48
    48504853suid 29,0
    48514854i "'1'"
     
    48844887n "wiz_rd"
    48854888t "std_logic"
    4886 o 43
     4889o 46
    48874890suid 30,0
    48884891i "'1'"
     
    51325135t "std_logic_vector"
    51335136b "(3 downto 0)"
    5134 o 32
     5137o 34
    51355138suid 48,0
    51365139i "(others => '0')"
     
    51685171n "drs_dwrite"
    51695172t "std_logic"
    5170 o 33
     5173o 35
    51715174suid 49,0
    51725175i "'1'"
     
    54135416n "sclk"
    54145417t "std_logic"
    5415 o 38
     5418o 40
    54165419suid 62,0
    54175420)
     
    54515454preAdd 0
    54525455posAdd 0
    5453 o 46
     5456o 49
    54545457suid 63,0
    54555458)
     
    55245527t "std_logic_vector"
    55255528b "(3 DOWNTO 0)"
    5526 o 39
     5529o 41
    55275530suid 65,0
    55285531)
     
    55605563n "mosi"
    55615564t "std_logic"
    5562 o 36
     5565o 38
    55635566suid 66,0
    55645567i "'0'"
     
    55995602eolc "-- default domino wave off"
    56005603posAdd 0
    5601 o 31
     5604o 33
    56025605suid 67,0
    56035606i "'0'"
     
    56735676n "green"
    56745677t "std_logic"
    5675 o 34
     5678o 36
    56765679suid 86,0
    56775680)
     
    57455748n "red"
    57465749t "std_logic"
    5747 o 37
     5750o 39
    57485751suid 88,0
    57495752)
     
    60336036n "trigger_veto"
    60346037t "std_logic"
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     6038o 42
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    60376040i "'1'"
     
    61826185)
    61836186)
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     6195fg "0,65535,0"
     6196)
     6197xt "80000,105625,80750,106375"
     6198)
     6199tg (CPTG
     6200uid 17844,0
     6201ps "CptPortTextPlaceStrategy"
     6202stg "RightVerticalLayoutStrategy"
     6203f (Text
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     6205va (VaSet
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     6207xt "70600,105500,79000,106500"
     6208st "w5300_state : (7:0)"
     6209ju 2
     6210blo "79000,106300"
     6211)
     6212)
     6213thePort (LogicalPort
     6214m 1
     6215decl (Decl
     6216n "w5300_state"
     6217t "std_logic_vector"
     6218b "(7 DOWNTO 0)"
     6219eolc "-- state is encoded here ... useful for debugging."
     6220posAdd 0
     6221o 43
     6222suid 103,0
     6223)
     6224)
     6225)
     6226*192 (CptPort
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     6228ps "OnEdgeStrategy"
     6229shape (Triangle
     6230uid 18059,0
     6231ro 90
     6232va (VaSet
     6233vasetType 1
     6234fg "0,65535,0"
     6235)
     6236xt "80000,106625,80750,107375"
     6237)
     6238tg (CPTG
     6239uid 18060,0
     6240ps "CptPortTextPlaceStrategy"
     6241stg "RightVerticalLayoutStrategy"
     6242f (Text
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     6244va (VaSet
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     6246xt "68600,106500,79000,107500"
     6247st "debug_data_ram_empty"
     6248ju 2
     6249blo "79000,107300"
     6250)
     6251)
     6252thePort (LogicalPort
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     6254decl (Decl
     6255n "debug_data_ram_empty"
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     6257o 31
     6258suid 104,0
     6259)
     6260)
     6261)
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     6264ps "OnEdgeStrategy"
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     6267ro 90
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     6270fg "0,65535,0"
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     6272xt "80000,107625,80750,108375"
     6273)
     6274tg (CPTG
     6275uid 18064,0
     6276ps "CptPortTextPlaceStrategy"
     6277stg "RightVerticalLayoutStrategy"
     6278f (Text
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     6280va (VaSet
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     6282xt "71500,107500,79000,108500"
     6283st "debug_data_valid"
     6284ju 2
     6285blo "79000,108300"
     6286)
     6287)
     6288thePort (LogicalPort
     6289m 1
     6290decl (Decl
     6291n "debug_data_valid"
     6292t "std_logic"
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     6294suid 105,0
     6295)
     6296)
     6297)
    61846298]
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    61916305lineWidth 2
    61926306)
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     6307xt "52000,66000,80000,153000"
    61946308)
    61956309oxt "15000,-8000,43000,70000"
     
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    62206334)
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    62656379iconMaskName "BlockDiagram.msk"
     
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    62726386)
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     6387*197 (Net
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    62756389lang 2
     
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    63556469)
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     6470*200 (Net
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     6472decl (Decl
     6473n "w5300_state"
     6474t "std_logic_vector"
     6475b "(7 DOWNTO 0)"
     6476eolc "-- state is encoded here ... useful for debugging."
     6477posAdd 0
     6478o 63
     6479suid 233,0
     6480)
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     6487st "SIGNAL w5300_state           : std_logic_vector(7 DOWNTO 0) -- state is encoded here ... useful for debugging.
     6488"
     6489)
     6490)
     6491*201 (Net
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     6493decl (Decl
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     6495t "std_logic"
     6496o 64
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     6498)
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     6500uid 18067,0
     6501va (VaSet
     6502font "Courier New,8,0"
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     6504xt "39000,53600,61000,54400"
     6505st "SIGNAL debug_data_ram_empty  : std_logic
     6506"
     6507)
     6508)
     6509*202 (Net
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     6511decl (Decl
     6512n "debug_data_valid"
     6513t "std_logic"
     6514o 65
     6515suid 235,0
     6516)
     6517declText (MLText
     6518uid 18075,0
     6519va (VaSet
     6520font "Courier New,8,0"
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     6522xt "39000,54400,61000,55200"
     6523st "SIGNAL debug_data_valid      : std_logic
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