Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd
===================================================================
--- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd	(revision 10737)
+++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_beha.vhd	(revision 10738)
@@ -97,5 +97,7 @@
 signal write_start_addr : integer range 0 to (RAM_SIZE_16B - 1);
 signal event_ready_flag : std_logic := '0';
-signal wiz_ack_flag, wiz_write_ea_flag: std_logic := '0';
+signal wiz_ack_flag : std_logic := '0';
+-- never used DN18.05.11
+--signal wiz_write_ea_flag: std_logic := '0';
 
 signal roi_index : integer range 0 to 45 := 0;
@@ -236,5 +238,6 @@
           event_ready_flag <= '0';
           wiz_ack_flag <= '0';
-          wiz_write_ea_flag <= '0';
+          -- never used --> commented out: DN18.05.11
+		  --wiz_write_ea_flag <= '0';
           state_mm <= MM_MAIN;
           
Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_distributor_beha.vhd
===================================================================
--- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_distributor_beha.vhd	(revision 10737)
+++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_distributor_beha.vhd	(revision 10738)
@@ -26,19 +26,19 @@
 
   PORT(
-    clk               : IN 			std_logic; -- 50MHz
-    config_start      : IN 			std_logic;
-    config_ready		: OUT   std_logic := '1'; 
-    sensor_valid      : OUT 		std_logic := '0';
-    dac_array         : IN 			dac_array_type;
-	current_dac_array : OUT			dac_array_type := ( others => 0);
-    sensor_array      : OUT 		sensor_array_type; 
-    dac_config_start  : OUT   std_logic := '0';
-    dac_config_ready  : IN    std_logic;
-    sclk_enable_override : OUT std_logic := '0';
-    sensor_read_start : OUT   std_logic := '0';
-    sensor_read_valid : IN    std_logic;
-    dac_id            : OUT   std_logic_vector(2 downto 0) := (others => '0');
-    sensor_id         : OUT   std_logic_vector(1 downto 0) := (others => '0');
-    data              : INOUT std_logic_vector(15 downto 0) := (others => 'Z')
+    clk						: IN 			std_logic; -- 50MHz
+    config_start			: IN 			std_logic;
+    config_ready			: OUT			std_logic := '1'; 
+    sensor_valid			: OUT 			std_logic := '0';
+    dac_array				: IN 			dac_array_type;
+	current_dac_array		: OUT			dac_array_type := ( others => 0);
+    sensor_array			: OUT 			sensor_array_type; 
+    dac_config_start		: OUT			std_logic := '0';
+    dac_config_ready		: IN			std_logic;
+    sclk_enable_override	: OUT			std_logic := '0';
+    sensor_read_start		: OUT			std_logic := '0';
+    sensor_read_valid 		: IN			std_logic;
+    dac_id					: OUT			std_logic_vector(2 downto 0) := (others => '0');
+    sensor_id				: OUT			std_logic_vector(1 downto 0) := (others => '0');
+    data					: INOUT			std_logic_vector(15 downto 0) := (others => 'Z')
   );
 END ENTITY spi_distributor;
Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd
===================================================================
--- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd	(revision 10737)
+++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd	(revision 10738)
@@ -768,17 +768,21 @@
 						
 						if (update_of_rois = '1') then
-							trigger_enable_storage_sig <= trigger_enable_sig;
+							if (trigger_enable_sig = '1') then 
+								trigger_enable_storage_sig <= trigger_enable_sig;
+							end if;
 							trigger_enable_sig <= '0';
 
-							if (data_ram_empty_sr(1) = '1') then
-								update_of_rois <= '0';
-								state_init <= CONFIG_MEMORY_MANAGER;
-							else 
-								state_init <= MAIN2;
-							end if;
+							update_of_rois <= '0';
+							state_init <= CONFIG_MEMORY_MANAGER;
+--							if (data_ram_empty_sr(1) = '1') then
+--								update_of_rois <= '0';
+--								state_init <= CONFIG_MEMORY_MANAGER;
+--							else 
+--								state_init <= MAIN2;
+--							end if;
 						elsif (update_of_lessimportant = '1') then				
 							update_of_lessimportant <= '0';
 							state_init <= CONFIG_DAC_ONLY;
-						elsif ( update_of_rois='0' and update_of_lessimportant='0' ) then
+						else -- update_of_rois='0' and update_of_lessimportant='0' 
 							state_init <= MAIN1;
 							--data_valid_int <= data_valid;
