Index: firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd
===================================================================
--- firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd	(revision 10639)
+++ firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd	(revision 10740)
@@ -45,5 +45,4 @@
     clk   : IN  STD_LOGIC;               -- 50 MHz system clock
 
-   
     -- Clock conditioner LMK03000
     -------------------------------------------------------------------------------
@@ -55,5 +54,4 @@
     LD_Clk_Cond   : in STD_LOGIC;   -- clock conditioner lock detect                  
 
-   
     -- Time Marker
     -------------------------------------------------------------------------------
@@ -65,5 +63,4 @@
                                  --     operation / physics run
 
-   
     -- FPGA intern clock conditioner configuration data
     -------------------------------------------------------------------------------
@@ -77,5 +74,4 @@
     cc_R15            : in std_logic_vector (31 downto 0) := (others => '0');
 
-   
     -- FPGA intern control signals
     -------------------------------------------------------------------------------
@@ -97,5 +93,5 @@
                                        -- 0 = time marker from FPGA for normal
                                        --     operation / physics run
-   
+    
   );
 end Clock_cond_interface;
@@ -103,10 +99,9 @@
 
 architecture Behavioral of Clock_cond_interface is
-  
- 
+   
   component microwire_interface IS
     PORT(
       clk               : IN     std_logic;
-      clk_uwire         : OUT    std_logic;  --- IN or OUT ?         
+      clk_uwire         : OUT    std_logic;
       data_uwire        : OUT    std_logic;       
       le_uwire          : OUT    std_logic;
@@ -118,11 +113,8 @@
   end component;
 
-  
-  signal clk_50M_sig : STD_LOGIC;       -- system clock
-  --signal start_config_sig : STD_LOGIC;  
-
+  signal clk_50M_sig   : STD_LOGIC;  -- system clock (50MHz)
+  signal clk_uwire_sig : STD_LOGIC;  -- 2 MHz
+  
   signal config_ready_sig : STD_LOGIC;
-  signal clk_uwire_sig : STD_LOGIC;
-
   signal config_started_sig : STD_LOGIC;
  
@@ -151,4 +143,5 @@
   signal tim_sel_state : TIM_SEL_STATE_TYPE := IDLE;
 
+  signal load_detect_sr : std_logic_vector (1 downto 0) := "00";
 
 begin
@@ -162,29 +155,26 @@
         clk_cond_array      => clk_cond_array_sig,  
         config_start        => start_config,
-        
-   --   config_start        => start_config_sig,  
-   --	config_start        <= start_config_sig,
-        
         config_ready        => config_ready_sig,
         config_started      => config_started_sig
     );
 
- 
-        
+  sync_ld_proc : process (clk_uwire_sig)
+  begin
+    if rising_edge(clk_uwire_sig) then
+      load_detect_sr <= load_detect_sr(0) & LD_Clk_Cond;
+    end if;
+  end process sync_ld_proc;
+  
   --config_done <= config_ready_sig;  -- indicates that the configuration 
                                     -- has been loaded 
 
-
-  
-  config_done <= (config_ready_sig AND LD_Clk_Cond);  -- indicates that the configuration 
+  --config_done <= (config_ready_sig AND LD_Clk_Cond);  -- indicates that the configuration 
                                                       -- has been loaded and
-                                                      -- the PLL is locked again
-
-
- 
-  --TIM_Sel <= timemarker_select;                                   
-
+                                                      -- the PLL has locked
+  
+  config_done <= config_ready_sig and (load_detect_sr(1) and load_detect_sr(0));
+  
   TIM_Sel <= timemarker_select_sig; 
-
+  
   tim_sel_proc : process (clk_uwire_sig)
   begin
@@ -205,11 +195,8 @@
   end process tim_sel_proc;
      
-           
   CLK_Clk_Cond <= clk_uwire_sig;
 
   clk_50M_sig <= clk;
   
-  -- start_config_sig <= start_config;
-  --  start_config <= start_config_sig;      
   config_started <= config_started_sig;