Ignore:
Timestamp:
May 18, 2011, 1:59:12 PM (9 years ago)
Author:
weitzel
Message:
several bugfixes for FTM firmware
File:
1 edited

Legend:

Unmodified
Added
Removed
  • firmware/FTM/FTM_central_control.vhd

    r10639 r10740  
    7777    stop_run_ack         : OUT std_logic := '0';
    7878    current_cc_state     : OUT std_logic_vector (15 DOWNTO 0) := X"FFFF";
     79    cc_state_test        : OUT std_logic_vector ( 7 downto 0) := X"FF";
    7980    start_run_param      : IN  std_logic_vector (15 DOWNTO 0);
    8081    start_run_num_events : IN  std_logic_vector (31 DOWNTO 0);
     
    8788architecture Behavioral of FTM_central_control is
    8889
    89   signal reset_scaler_sig    : std_logic := '0';
    90   signal reset_period_sig    : std_logic := '0';
    91   signal scaler_counts_sig   : integer := 0;
    92   signal scaler_period_sig   : integer range 0 to 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER) := 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
    93   signal period_finished_sig : std_logic := '0';
    94   signal wait_cnt_sig        : integer range 0 to 10 := 0;
    95   signal new_period_sr_sig   : std_logic_vector(1 downto 0) := (others => '0');
    96   signal new_period_sig      : std_logic := '0';
    97   signal new_period_ack_sig  : std_logic := '0';
    98   signal prescaling_FTU01_sig : std_logic_vector(7 downto 0) := "00100111";
     90  signal reset_scaler_sig      : std_logic := '0';
     91  signal reset_period_sig      : std_logic := '0';
     92  signal scaler_counts_sig     : integer := 0;
     93  signal scaler_period_sig     : integer range 0 to 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER) := 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER);
     94  signal period_finished_sig   : std_logic := '0';
     95  signal wait_cnt_sig          : integer range 0 to 10 := 0;
     96  signal new_period_sr_sig     : std_logic_vector(1 downto 0) := (others => '0');
     97  signal new_period_sig        : std_logic := '0';
     98  signal new_period_ack_sig    : std_logic := '0';
     99  signal prescaling_FTU01_sig  : std_logic_vector(7 downto 0) := "00100111";
    99100 
    100101  type state_central_proc_type is (CP_INIT, CP_INIT_DNA,
     
    114115begin
    115116
    116   central_proc : process (clk, prescaling_FTU01)
     117  --central_proc : process (clk, prescaling_FTU01)
     118  central_proc : process (clk)
    117119  begin
    118120    if rising_edge (clk) then
     
    120122
    121123        when CP_INIT =>  -- wait for DCMs to lock
     124          current_cc_state <= X"FFFF";
     125          --cc_state_test <= X"00";
     126          cc_state_test <= X"19";
    122127          if (clk_ready = '1') then
    123128            state_central_proc <= CP_INIT_DNA;
    124129          end if;
    125130
    126         when CP_INIT_DNA =>  -- get FPGA DNA
     131        when CP_INIT_DNA =>  -- get FPGA DNA
     132          current_cc_state <= X"FFFF";
     133          cc_state_test <= X"01";
    127134          if (dna_ready = '1') then
    128135            state_central_proc <= CP_CONFIG;
     
    134141         
    135142        when CP_CONFIG_START =>
     143          current_cc_state <= FTM_STATE_CFG;
     144          cc_state_test <= X"02";
    136145          if (config_started_ack = '1') then
    137146            config_started <= '0';
     
    140149
    141150        when CP_CONFIG =>
     151          current_cc_state <= FTM_STATE_CFG;
     152          cc_state_test <= X"03";
    142153          config_start_eth <= '1';
    143154          if (config_started_eth = '1') then
     
    147158
    148159        when CP_CONFIG_01 =>
     160          current_cc_state <= FTM_STATE_CFG;
     161          cc_state_test <= X"04";
    149162          if (config_ready_eth = '1') then
    150163            state_central_proc <= CP_CONFIG_CC;
     
    154167
    155168        when CP_CONFIG_CC =>
     169          current_cc_state <= FTM_STATE_CFG;
     170          cc_state_test <= X"05";
    156171          config_start_cc <= '1';
    157172          if (config_started_cc = '1') then
     
    161176
    162177        when CP_CONFIG_CC_01 =>
     178          current_cc_state <= FTM_STATE_CFG;
     179          cc_state_test <= X"06";
    163180          if (config_ready_cc = '1') then
    164181            state_central_proc <= CP_CONFIG_FTU;
     
    166183         
    167184        when CP_CONFIG_FTU =>
     185          current_cc_state <= FTM_STATE_CFG;
     186          cc_state_test <= X"07";
    168187          config_start_ftu <= '1';
    169188          if (config_started_ftu = '1') then
     
    173192
    174193        when CP_CONFIG_FTU_01 =>
     194          current_cc_state <= FTM_STATE_CFG;
     195          cc_state_test <= X"08";
    175196          if (config_ready_ftu = '1') then
    176197            state_central_proc <= CP_CONFIG_SCALER;
     
    178199         
    179200        when CP_CONFIG_SCALER =>
     201          current_cc_state <= FTM_STATE_CFG;
     202          cc_state_test <= X"09";
    180203          prescaling_FTU01_sig <= prescaling_FTU01;
    181204          --reset_period_sig <= '1';
     
    183206
    184207        when CP_CONFIG_SCALER_01 =>
     208          current_cc_state <= FTM_STATE_CFG;
     209          cc_state_test <= X"0A";
    185210          --reset_period_sig <= '0';
    186211          if wait_cnt_sig < 5 then
     
    195220
    196221        when CP_CONFIG_TRIGGER =>
     222          current_cc_state <= FTM_STATE_CFG;
     223          cc_state_test <= X"0B";
    197224          --config trigger_manager block
    198225          config_trigger <= '1';
     
    200227
    201228        when CP_CONFIG_TRIGGER_01 =>
     229          current_cc_state <= FTM_STATE_CFG;
     230          cc_state_test <= X"0C";
    202231          config_trigger <= '0';
    203232          if (config_trigger_done = '1') then
     
    207236        when CP_IDLE =>
    208237          current_cc_state <= FTM_STATE_IDLE;
     238          cc_state_test <= X"0D";
    209239          stop_run_ack <= '1';
    210240          start_run_ack <= '0';
     
    238268        when CP_RUNNING =>
    239269          current_cc_state <= FTM_STATE_RUN;
     270          cc_state_test <= X"0E";
    240271          if (start_run = '0') then
    241272            start_run_ack <= '0';
     
    246277        when CP_RUNNING_01 =>
    247278          current_cc_state <= FTM_STATE_RUN;
     279          cc_state_test <= X"0F";
    248280          start_run_ack <= '1';
    249281          trigger_start <= '1';
     
    277309
    278310        when CP_RUNNING_02 =>
     311          current_cc_state <= FTM_STATE_RUN;
     312          cc_state_test <= X"10";
    279313          if (stop_run = '0') then
    280314            stop_run_ack <= '0';
     
    283317         
    284318        when CP_CONFIG_ACK =>
     319          current_cc_state <= FTM_STATE_CFG;
     320          cc_state_test <= X"11";
    285321          if (config_started_ack = '1') then
    286322            config_started <= '0';
     
    289325         
    290326        when CP_PING =>
     327          cc_state_test <= X"12";
    291328          if (ping_ftu_ready_ftu = '1') then
    292329            if (ping_ftu_start = '0') then
     
    299336
    300337        when CP_START_RATES =>
     338          cc_state_test <= X"13";
    301339          new_period_ack_sig <= '0';
    302340          dd_block_start_ftu <= '1';
     
    309347         
    310348        when CP_READ_RATES =>
     349          cc_state_test <= X"14";
    311350          new_period_ack_sig <= '0';
    312351          if (rates_started_ftu = '1') then
     
    316355
    317356        when CP_READ_RATES_01 =>
     357          cc_state_test <= X"15";
    318358          if (rates_ready_ftu = '1') then
    319359            dd_block_ready_ftu <= '1';
     
    326366         
    327367        when CP_SEND_START =>
     368          cc_state_test <= X"16";
    328369          dd_send <= '1';
    329370          if (dd_send_ack = '1') then
     
    333374         
    334375        when CP_SEND_END =>
     376          cc_state_test <= X"17";
    335377          if (dd_send_ready = '1') then
    336378            --state_central_proc <= CP_IDLE;
     
    338380          end if;
    339381
     382        when others =>
     383          cc_state_test <= X"18";
     384         
    340385      end case;
    341386    end if;
Note: See TracChangeset for help on using the changeset viewer.