Index: /firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd =================================================================== --- /firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd (revision 10739) +++ /firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd (revision 10740) @@ -45,5 +45,4 @@ clk : IN STD_LOGIC; -- 50 MHz system clock - -- Clock conditioner LMK03000 ------------------------------------------------------------------------------- @@ -55,5 +54,4 @@ LD_Clk_Cond : in STD_LOGIC; -- clock conditioner lock detect - -- Time Marker ------------------------------------------------------------------------------- @@ -65,5 +63,4 @@ -- operation / physics run - -- FPGA intern clock conditioner configuration data ------------------------------------------------------------------------------- @@ -77,5 +74,4 @@ cc_R15 : in std_logic_vector (31 downto 0) := (others => '0'); - -- FPGA intern control signals ------------------------------------------------------------------------------- @@ -97,5 +93,5 @@ -- 0 = time marker from FPGA for normal -- operation / physics run - + ); end Clock_cond_interface; @@ -103,10 +99,9 @@ architecture Behavioral of Clock_cond_interface is - - + component microwire_interface IS PORT( clk : IN std_logic; - clk_uwire : OUT std_logic; --- IN or OUT ? + clk_uwire : OUT std_logic; data_uwire : OUT std_logic; le_uwire : OUT std_logic; @@ -118,11 +113,8 @@ end component; - - signal clk_50M_sig : STD_LOGIC; -- system clock - --signal start_config_sig : STD_LOGIC; - + signal clk_50M_sig : STD_LOGIC; -- system clock (50MHz) + signal clk_uwire_sig : STD_LOGIC; -- 2 MHz + signal config_ready_sig : STD_LOGIC; - signal clk_uwire_sig : STD_LOGIC; - signal config_started_sig : STD_LOGIC; @@ -151,4 +143,5 @@ signal tim_sel_state : TIM_SEL_STATE_TYPE := IDLE; + signal load_detect_sr : std_logic_vector (1 downto 0) := "00"; begin @@ -162,29 +155,26 @@ clk_cond_array => clk_cond_array_sig, config_start => start_config, - - -- config_start => start_config_sig, - -- config_start <= start_config_sig, - config_ready => config_ready_sig, config_started => config_started_sig ); - - + sync_ld_proc : process (clk_uwire_sig) + begin + if rising_edge(clk_uwire_sig) then + load_detect_sr <= load_detect_sr(0) & LD_Clk_Cond; + end if; + end process sync_ld_proc; + --config_done <= config_ready_sig; -- indicates that the configuration -- has been loaded - - - config_done <= (config_ready_sig AND LD_Clk_Cond); -- indicates that the configuration + --config_done <= (config_ready_sig AND LD_Clk_Cond); -- indicates that the configuration -- has been loaded and - -- the PLL is locked again - - - - --TIM_Sel <= timemarker_select; - + -- the PLL has locked + + config_done <= config_ready_sig and (load_detect_sr(1) and load_detect_sr(0)); + TIM_Sel <= timemarker_select_sig; - + tim_sel_proc : process (clk_uwire_sig) begin @@ -205,11 +195,8 @@ end process tim_sel_proc; - CLK_Clk_Cond <= clk_uwire_sig; clk_50M_sig <= clk; - -- start_config_sig <= start_config; - -- start_config <= start_config_sig; config_started <= config_started_sig; Index: /firmware/FTM/FTM_central_control.vhd =================================================================== --- /firmware/FTM/FTM_central_control.vhd (revision 10739) +++ /firmware/FTM/FTM_central_control.vhd (revision 10740) @@ -77,4 +77,5 @@ stop_run_ack : OUT std_logic := '0'; current_cc_state : OUT std_logic_vector (15 DOWNTO 0) := X"FFFF"; + cc_state_test : OUT std_logic_vector ( 7 downto 0) := X"FF"; start_run_param : IN std_logic_vector (15 DOWNTO 0); start_run_num_events : IN std_logic_vector (31 DOWNTO 0); @@ -87,14 +88,14 @@ architecture Behavioral of FTM_central_control is - signal reset_scaler_sig : std_logic := '0'; - signal reset_period_sig : std_logic := '0'; - signal scaler_counts_sig : integer := 0; - signal scaler_period_sig : integer range 0 to 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER) := 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER); - signal period_finished_sig : std_logic := '0'; - signal wait_cnt_sig : integer range 0 to 10 := 0; - signal new_period_sr_sig : std_logic_vector(1 downto 0) := (others => '0'); - signal new_period_sig : std_logic := '0'; - signal new_period_ack_sig : std_logic := '0'; - signal prescaling_FTU01_sig : std_logic_vector(7 downto 0) := "00100111"; + signal reset_scaler_sig : std_logic := '0'; + signal reset_period_sig : std_logic := '0'; + signal scaler_counts_sig : integer := 0; + signal scaler_period_sig : integer range 0 to 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER) := 128 * (LOW_FREQUENCY / SCALER_FREQ_DIVIDER); + signal period_finished_sig : std_logic := '0'; + signal wait_cnt_sig : integer range 0 to 10 := 0; + signal new_period_sr_sig : std_logic_vector(1 downto 0) := (others => '0'); + signal new_period_sig : std_logic := '0'; + signal new_period_ack_sig : std_logic := '0'; + signal prescaling_FTU01_sig : std_logic_vector(7 downto 0) := "00100111"; type state_central_proc_type is (CP_INIT, CP_INIT_DNA, @@ -114,5 +115,6 @@ begin - central_proc : process (clk, prescaling_FTU01) + --central_proc : process (clk, prescaling_FTU01) + central_proc : process (clk) begin if rising_edge (clk) then @@ -120,9 +122,14 @@ when CP_INIT => -- wait for DCMs to lock + current_cc_state <= X"FFFF"; + --cc_state_test <= X"00"; + cc_state_test <= X"19"; if (clk_ready = '1') then state_central_proc <= CP_INIT_DNA; end if; - when CP_INIT_DNA => -- get FPGA DNA + when CP_INIT_DNA => -- get FPGA DNA + current_cc_state <= X"FFFF"; + cc_state_test <= X"01"; if (dna_ready = '1') then state_central_proc <= CP_CONFIG; @@ -134,4 +141,6 @@ when CP_CONFIG_START => + current_cc_state <= FTM_STATE_CFG; + cc_state_test <= X"02"; if (config_started_ack = '1') then config_started <= '0'; @@ -140,4 +149,6 @@ when CP_CONFIG => + current_cc_state <= FTM_STATE_CFG; + cc_state_test <= X"03"; config_start_eth <= '1'; if (config_started_eth = '1') then @@ -147,4 +158,6 @@ when CP_CONFIG_01 => + current_cc_state <= FTM_STATE_CFG; + cc_state_test <= X"04"; if (config_ready_eth = '1') then state_central_proc <= CP_CONFIG_CC; @@ -154,4 +167,6 @@ when CP_CONFIG_CC => + current_cc_state <= FTM_STATE_CFG; + cc_state_test <= X"05"; config_start_cc <= '1'; if (config_started_cc = '1') then @@ -161,4 +176,6 @@ when CP_CONFIG_CC_01 => + current_cc_state <= FTM_STATE_CFG; + cc_state_test <= X"06"; if (config_ready_cc = '1') then state_central_proc <= CP_CONFIG_FTU; @@ -166,4 +183,6 @@ when CP_CONFIG_FTU => + current_cc_state <= FTM_STATE_CFG; + cc_state_test <= X"07"; config_start_ftu <= '1'; if (config_started_ftu = '1') then @@ -173,4 +192,6 @@ when CP_CONFIG_FTU_01 => + current_cc_state <= FTM_STATE_CFG; + cc_state_test <= X"08"; if (config_ready_ftu = '1') then state_central_proc <= CP_CONFIG_SCALER; @@ -178,4 +199,6 @@ when CP_CONFIG_SCALER => + current_cc_state <= FTM_STATE_CFG; + cc_state_test <= X"09"; prescaling_FTU01_sig <= prescaling_FTU01; --reset_period_sig <= '1'; @@ -183,4 +206,6 @@ when CP_CONFIG_SCALER_01 => + current_cc_state <= FTM_STATE_CFG; + cc_state_test <= X"0A"; --reset_period_sig <= '0'; if wait_cnt_sig < 5 then @@ -195,4 +220,6 @@ when CP_CONFIG_TRIGGER => + current_cc_state <= FTM_STATE_CFG; + cc_state_test <= X"0B"; --config trigger_manager block config_trigger <= '1'; @@ -200,4 +227,6 @@ when CP_CONFIG_TRIGGER_01 => + current_cc_state <= FTM_STATE_CFG; + cc_state_test <= X"0C"; config_trigger <= '0'; if (config_trigger_done = '1') then @@ -207,4 +236,5 @@ when CP_IDLE => current_cc_state <= FTM_STATE_IDLE; + cc_state_test <= X"0D"; stop_run_ack <= '1'; start_run_ack <= '0'; @@ -238,4 +268,5 @@ when CP_RUNNING => current_cc_state <= FTM_STATE_RUN; + cc_state_test <= X"0E"; if (start_run = '0') then start_run_ack <= '0'; @@ -246,4 +277,5 @@ when CP_RUNNING_01 => current_cc_state <= FTM_STATE_RUN; + cc_state_test <= X"0F"; start_run_ack <= '1'; trigger_start <= '1'; @@ -277,4 +309,6 @@ when CP_RUNNING_02 => + current_cc_state <= FTM_STATE_RUN; + cc_state_test <= X"10"; if (stop_run = '0') then stop_run_ack <= '0'; @@ -283,4 +317,6 @@ when CP_CONFIG_ACK => + current_cc_state <= FTM_STATE_CFG; + cc_state_test <= X"11"; if (config_started_ack = '1') then config_started <= '0'; @@ -289,4 +325,5 @@ when CP_PING => + cc_state_test <= X"12"; if (ping_ftu_ready_ftu = '1') then if (ping_ftu_start = '0') then @@ -299,4 +336,5 @@ when CP_START_RATES => + cc_state_test <= X"13"; new_period_ack_sig <= '0'; dd_block_start_ftu <= '1'; @@ -309,4 +347,5 @@ when CP_READ_RATES => + cc_state_test <= X"14"; new_period_ack_sig <= '0'; if (rates_started_ftu = '1') then @@ -316,4 +355,5 @@ when CP_READ_RATES_01 => + cc_state_test <= X"15"; if (rates_ready_ftu = '1') then dd_block_ready_ftu <= '1'; @@ -326,4 +366,5 @@ when CP_SEND_START => + cc_state_test <= X"16"; dd_send <= '1'; if (dd_send_ack = '1') then @@ -333,4 +374,5 @@ when CP_SEND_END => + cc_state_test <= X"17"; if (dd_send_ready = '1') then --state_central_proc <= CP_IDLE; @@ -338,4 +380,7 @@ end if; + when others => + cc_state_test <= X"18"; + end case; end if; Index: /firmware/FTM/FTM_top.vhd =================================================================== --- /firmware/FTM/FTM_top.vhd (revision 10739) +++ /firmware/FTM/FTM_top.vhd (revision 10740) @@ -177,8 +177,8 @@ -- on IO-Bank 3 ------------------------------------------------------------------------------- - -- Crate_Res0 : out STD_LOGIC; - -- Crate_Res1 : out STD_LOGIC; - -- Crate_Res2 : out STD_LOGIC; - -- Crate_Res3 : out STD_LOGIC; + Crate_Res0 : out STD_LOGIC; + Crate_Res1 : out STD_LOGIC; + Crate_Res2 : out STD_LOGIC; + Crate_Res3 : out STD_LOGIC; @@ -220,5 +220,5 @@ TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker TIM_Run_n : out STD_LOGIC; -- TIM_Run- IO-Bank 2 - TIM_Sel : out STD_LOGIC -- Time Marker selector on IO-Bank 2 + TIM_Sel : out STD_LOGIC; -- Time Marker selector on IO-Bank 2 -- CLD_FPGA : in STD_LOGIC; -- DRS-Clock feedback into FPGA @@ -253,5 +253,5 @@ -- Testpoints ------------------------------------------------------------------------------- - -- TP : inout STD_LOGIC_VECTOR(32 downto 0); + TP : inout STD_LOGIC_VECTOR(32 downto 0) -- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only @@ -395,4 +395,5 @@ signal stop_run_ack_sig : std_logic; signal current_cc_state_sig : std_logic_vector (15 DOWNTO 0); + signal cc_state_test_sig : std_logic_vector ( 7 downto 0); signal start_run_param_sig : std_logic_vector (15 DOWNTO 0); signal start_run_num_events_sig : std_logic_vector (31 DOWNTO 0); @@ -560,4 +561,5 @@ stop_run_ack : OUT std_logic; current_cc_state : OUT std_logic_vector (15 DOWNTO 0); + cc_state_test : OUT std_logic_vector ( 7 downto 0); start_run_param : IN std_logic_vector (15 DOWNTO 0); start_run_num_events : IN std_logic_vector (31 DOWNTO 0); @@ -942,4 +944,5 @@ stop_run_ack => stop_run_ack_sig, current_cc_state => current_cc_state_sig, + cc_state_test => cc_state_test_sig, start_run_param => start_run_param_sig, start_run_num_events => start_run_num_events_sig, @@ -1149,4 +1152,13 @@ LED_ye <= led_sig(5 downto 4); LED_gn <= led_sig(7 downto 6); + + TP(32 downto 8) <= (others => '0'); + --TP(8) <= clk_50M_sig; + TP( 7 downto 0) <= cc_state_test_sig; + + Crate_Res0 <= '1'; + Crate_Res1 <= '1'; + Crate_Res2 <= '1'; + Crate_Res3 <= '1'; end Behavioral; Index: /firmware/FTM/FTM_top_tb.vhd =================================================================== --- /firmware/FTM/FTM_top_tb.vhd (revision 10739) +++ /firmware/FTM/FTM_top_tb.vhd (revision 10740) @@ -175,8 +175,8 @@ -- Crate-Resets ------------------------------------------------------------------------------- - -- Crate_Res0 : out STD_LOGIC; - -- Crate_Res1 : out STD_LOGIC; - -- Crate_Res2 : out STD_LOGIC; - -- Crate_Res3 : out STD_LOGIC; + Crate_Res0 : out STD_LOGIC; + Crate_Res1 : out STD_LOGIC; + Crate_Res2 : out STD_LOGIC; + Crate_Res3 : out STD_LOGIC; @@ -215,5 +215,5 @@ TIM_Run_p : out STD_LOGIC; -- TIM_Run+ Time Marker - TIM_Run_n : out STD_LOGIC -- TIM_Run- + TIM_Run_n : out STD_LOGIC; -- TIM_Run- -- TIM_Sel : out STD_LOGIC; -- Time Marker selector @@ -248,5 +248,5 @@ -- Testpoints ------------------------------------------------------------------------------- - -- TP : inout STD_LOGIC_VECTOR(32 downto 0); + TP : inout STD_LOGIC_VECTOR(32 downto 0) -- TP_in : in STD_LOGIC_VECTOR(34 downto 33); -- input only @@ -290,4 +290,5 @@ signal W_T_sig : STD_LOGIC_VECTOR(3 downto 0) := (others => '0'); signal SIO_sig : STD_LOGIC := '0'; + signal TP_sig : STD_LOGIC_VECTOR(32 downto 0) := (others => '0'); --Outputs @@ -405,8 +406,8 @@ Bus2_RxD_3 => Bus2_RxD_3_sig, Bus2_TxD_3 => Bus2_TxD_3_sig, --- Crate_Res0 => Crate_Res0_sig, --- Crate_Res1 => Crate_Res1_sig, --- Crate_Res2 => Crate_Res2_sig, --- Crate_Res3 => Crate_Res3_sig, + Crate_Res0 => Crate_Res0_sig, + Crate_Res1 => Crate_Res1_sig, + Crate_Res2 => Crate_Res2_sig, + Crate_Res3 => Crate_Res3_sig, Busy0 => Busy0_sig, Busy1 => Busy1_sig, @@ -418,5 +419,5 @@ TRG_n => TRG_n_sig, TIM_Run_p => TIM_Run_p_sig, - TIM_Run_n => TIM_Run_n_sig + TIM_Run_n => TIM_Run_n_sig, -- TIM_Sel => TIM_Sel_sig, -- Cal_0_p => Cal_0_p_sig, @@ -435,5 +436,6 @@ -- Cal_6_n => Cal_6_n_sig, -- Cal_7_p => Cal_7_p_sig, --- Cal_7_n => Cal_7_n_sig +-- Cal_7_n => Cal_7_n_sig, + TP => TP_sig ); Index: /firmware/FTM/ethernet/w5300_modul.vhd =================================================================== --- /firmware/FTM/ethernet/w5300_modul.vhd (revision 10739) +++ /firmware/FTM/ethernet/w5300_modul.vhd (revision 10740) @@ -18,5 +18,4 @@ -- ---------------------------------------------------------------------------------- - LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; @@ -118,10 +117,10 @@ INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1, TIMEOUT, RETRY, SI, SI0, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, SEND_FTU_ERROR, - READ_DATA, WRITE_TO_SD_ADDR, READ_FTU_ERROR, READ_FROM_SD_ADDR, READ_FROM_DD_ADDR, READ_FROM_FL_ADDR, READ_FROM_HEADER_MODUL); + READ_DATA, WRITE_TO_SD_ADDR, READ_FTU_ERROR, READ_DD_BLOCK, READ_FROM_SD_ADDR, READ_FROM_DD_ADDR, READ_FROM_FL_ADDR, READ_FROM_HEADER_MODUL); type state_write_type is (WR_START, WR_LENGTH, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08, WR_WRITE_START_DEL, WR_GET_HEADER, WR_GET_HEADER_WAIT, WR_SD_ADDR, WR_FIFO_DATA, WR_FIFO_DATA_01, WR_FIFO_HEADER, WR_FIFO_HEADER_01, WR_WRITE_END_DEL); type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04); type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06); - type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_CMD, RD_CMD_PARSE, RD_PING, RD_WRITE_SD_ADDR, RD_READ_SD_ADDR, RD_READ_SD_BLOCK, RD_READ_DD_BLOCK, RD_WRITE_SD_BLOCK, RD_X_EVNTS,RD_END); + type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_CMD, RD_CMD_PARSE, RD_PING, RD_WRITE_SD_ADDR, RD_READ_SD_ADDR, RD_READ_SD_BLOCK, RD_WRITE_SD_BLOCK, RD_X_EVNTS,RD_END); type state_write_sd_type is (WRITE_SD_START, WRITE_SD_WAIT, WRITE_SD_END); type state_read_sd_type is (READ_SD_START, READ_SD_WAIT, READ_SD_END); @@ -131,4 +130,5 @@ type state_read_dd_block_type is (READ_DD_BLOCK_START, READ_DD_BLOCK_WRITE_GENERAL, READ_DD_BLOCK_WRITE, READ_DD_BLOCK_END, READ_DD_BLOCK_INTERN); type state_send_ftu_error_type is (SFE_START, SFE_END); + type state_rd_x_evnts_type is (RD_X_01, RD_X_02, RD_X_03); signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120"; @@ -153,5 +153,5 @@ signal state_read_dd_block : state_read_dd_block_type := READ_DD_BLOCK_START; signal state_send_ftu_error : state_send_ftu_error_type := SFE_START; - + signal state_rd_x_evnts : state_rd_x_evnts_type := RD_X_01; signal interrupt_ignore : std_logic := '1'; @@ -460,5 +460,5 @@ when SI => par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC; - par_data <= X"0101"; -- ALIGN, TCP + par_data <= X"0101"; -- 0x0101: ALIGN, TCP state_init <= WRITE_REG; next_state <= SI0; @@ -554,16 +554,15 @@ new_config <= '1'; config_started_ack <= '0'; + state_init <= MAIN; + + -- main "loop" + when MAIN => if (config_started = '1') then new_config <= '0'; config_started_ack <= '1'; - state_init <= MAIN; end if; - - -- main "loop" - when MAIN => chk_recv_cntr <= chk_recv_cntr + 1; if (chk_recv_cntr = 1000) then chk_recv_cntr <= 0; - state_read_data <= RD_1; state_init <= READ_DATA; busy <= '1'; @@ -575,6 +574,5 @@ state_read_dd_block <= READ_DD_BLOCK_END; end if; - state_read_data <= RD_READ_DD_BLOCK; - state_init <= READ_DATA; + state_init <= READ_DD_BLOCK; elsif ((ftu_error_send = '1') and (wait_for_data_flag = '0')) then ftu_error_send_ack <= '1'; @@ -587,4 +585,53 @@ + -- read dynamic data block and write it to ethernet + when READ_DD_BLOCK => + case state_read_dd_block is + when READ_DD_BLOCK_START => + dd_block_start <= '1'; + dd_block_ready <= '0'; + if (dd_block_start_ack = '1') then + dd_block_start <= '0'; + state_read_dd_block <= READ_DD_BLOCK_WRITE_GENERAL; + end if; + -- write on-time counter and tempertures to dd-block + when READ_DD_BLOCK_WRITE_GENERAL => + dd_write_general <= '1'; + if (dd_write_general_started = '1') then + dd_write_general <= '0'; + state_read_dd_block <= READ_DD_BLOCK_WRITE; + end if; + -- write dd-block to ethernet when on-time counter and temperatures are ready + when READ_DD_BLOCK_WRITE => + if (dd_write_general_ready = '1') then + data_package_type <= FTM_PACKAGE_TYPE_DD; + data_package_length <= DD_BLOCK_SIZE + 1; -- +1 := package end + read_addr_state <= READ_FROM_DD_ADDR; + local_sd_addr <= X"000"; -- start at address 0x000 + local_write_length <= "00000" & DD_BLOCK_SIZE; + state_read_dd_block <= READ_DD_BLOCK_END; + next_state <= READ_DD_BLOCK; + state_init <= WRITE_DATA; + end if; + when READ_DD_BLOCK_END => + dd_block_ready <= '1'; + if (internal_cmd = '1') then + state_read_dd_block <= READ_DD_BLOCK_INTERN; + else + next_state_read_data <= RD_CMD; + state_read_dd_block <= READ_DD_BLOCK_START; + state_init <= READ_DATA; + state_read_data <= RD_5; + end if; + when READ_DD_BLOCK_INTERN => + if (dd_send = '0') then + dd_send_ready <= '1'; + dd_send_ack <= '0'; + internal_cmd <= '0'; + state_read_dd_block <= READ_DD_BLOCK_START; + state_init <= MAIN; + end if; + end case; -- state_read_dd_block + -- send FTU error message when SEND_FTU_ERROR => @@ -632,4 +679,5 @@ else busy <= '0'; + state_read_data <= RD_1; state_init <= MAIN; end if; @@ -646,4 +694,5 @@ when RD_END => + state_read_data <= RD_1; if (new_config_flag = '1') then new_config_flag <= '0'; @@ -652,12 +701,7 @@ next_state <= MAIN; end if; - if (internal_cmd = '0') then - par_addr <= W5300_S0_CR; - par_data <= X"0040"; -- RECV - state_init <= WRITE_REG; - else - internal_cmd <= '0'; - state_init <= MAIN; - end if; + par_addr <= W5300_S0_CR; + par_data <= X"0040"; -- RECV + state_init <= WRITE_REG; @@ -701,4 +745,6 @@ start_run <= '0'; state_read_data <= RD_5; + else + state_init <= MAIN; end if; -- start run an take X events @@ -716,4 +762,6 @@ stop_run <= '0'; state_read_data <= RD_5; + else + state_init <= MAIN; end if; @@ -724,4 +772,6 @@ crate_reset <= '0'; state_read_data <= RD_5; + else + state_init <= MAIN; end if; @@ -754,5 +804,6 @@ -- read dynamic data block when PAR_READ_DD => - state_read_data <= RD_READ_DD_BLOCK; + state_init <= READ_DD_BLOCK; + state_read_data <= RD_5; when others => state_read_data <= RD_5; @@ -788,8 +839,12 @@ ping_ftu_start <= '0'; state_ping <= PING_WAIT; + else + state_init <= MAIN; end if; when PING_WAIT => if (ping_ftu_ready = '1') then state_ping <= PING_WRITE_LIST; + else + state_init <= MAIN; end if; when PING_WRITE_LIST => @@ -803,53 +858,4 @@ next_state <= READ_DATA; state_init <= WRITE_DATA; - end case; - - -- read dynamic data block and write it to ethernet - when RD_READ_DD_BLOCK => - case state_read_dd_block is - when READ_DD_BLOCK_START => - dd_block_start <= '1'; - dd_block_ready <= '0'; - if (dd_block_start_ack = '1') then - dd_block_start <= '0'; - state_read_dd_block <= READ_DD_BLOCK_WRITE_GENERAL; - end if; - -- write on-time counter and tempertures to dd-block - when READ_DD_BLOCK_WRITE_GENERAL => - dd_write_general <= '1'; - if (dd_write_general_started = '1') then - dd_write_general <= '0'; - state_read_dd_block <= READ_DD_BLOCK_WRITE; - end if; - -- write dd-block to ethernet when on-time counter and temperatures are ready - when READ_DD_BLOCK_WRITE => - if (dd_write_general_ready = '1') then - data_package_type <= FTM_PACKAGE_TYPE_DD; - data_package_length <= DD_BLOCK_SIZE + 1; -- +1 := package end - read_addr_state <= READ_FROM_DD_ADDR; - local_sd_addr <= X"000"; -- start at address 0x000 - local_write_length <= "00000" & DD_BLOCK_SIZE; - state_read_dd_block <= READ_DD_BLOCK_END; - next_state <= READ_DATA; - state_init <= WRITE_DATA; - end if; - when READ_DD_BLOCK_END => - dd_block_ready <= '1'; - next_state_read_data <= RD_CMD; - -- - if (internal_cmd = '1') then - state_read_dd_block <= READ_DD_BLOCK_INTERN; - else - state_read_dd_block <= READ_DD_BLOCK_START; - state_read_data <= RD_5; - end if; - when READ_DD_BLOCK_INTERN => - if (dd_send = '0') then - dd_send_ready <= '1'; - dd_send_ack <= '0'; - state_read_dd_block <= READ_DD_BLOCK_START; - state_read_data <= RD_5; - end if; - end case; @@ -913,19 +919,26 @@ -- read X events when RD_X_EVNTS => - if (next_packet_data_cnt = 0) then - start_run_num_events (31 downto 16) <= data_read; - else - start_run_num_events (15 downto 0) <= data_read; - start_run_param <= cmd_array (2); - start_run <= '1'; - if (start_run_ack = '1') then - start_run <= '0'; - next_packet_data_cnt <= 0; + case state_rd_x_evnts is + when RD_X_01 => + start_run_num_events (31 downto 16) <= data_read; + state_read_data <= RD_5; + state_rd_x_evnts <= RD_X_02; + when RD_X_02 => + start_run_num_events (15 downto 0) <= data_read; + start_run_param <= cmd_array (2); + start_run <= '1'; wait_for_data_flag <= '0'; - next_state_read_data <= RD_CMD; - state_read_data <= RD_5; - end if; - end if; - + state_rd_x_evnts <= RD_X_03; + when RD_X_03 => + if (start_run_ack = '1') then + start_run <= '0'; + state_rd_x_evnts <= RD_X_01; + next_state_read_data <= RD_CMD; + state_read_data <= RD_5; + else + state_init <= MAIN; + end if; + end case; + end case; -- state_read_data Index: /firmware/FTM/ftm_board.ucf =================================================================== --- /firmware/FTM/ftm_board.ucf (revision 10739) +++ /firmware/FTM/ftm_board.ucf (revision 10740) @@ -251,8 +251,8 @@ # on IO-Bank 3 ####################################################### -# NET Crate_Res0 LOC = M1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -# NET Crate_Res1 LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -# NET Crate_Res2 LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # -# NET Crate_Res3 LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Crate_Res0 LOC = M1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Crate_Res1 LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Crate_Res2 LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # +NET Crate_Res3 LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # @@ -330,63 +330,63 @@ # Connector T7 # IO-Bank 0 -# NET TP<0> LOC = B14 | IOSTANDARD=LVCMOS33; # -# NET TP<1> LOC = A14 | IOSTANDARD=LVCMOS33; # -# NET TP<2> LOC = C13 | IOSTANDARD=LVCMOS33; # -# NET TP<3> LOC = B13 | IOSTANDARD=LVCMOS33; # +NET TP<0> LOC = B14 | IOSTANDARD=LVCMOS33; # +NET TP<1> LOC = A14 | IOSTANDARD=LVCMOS33; # +NET TP<2> LOC = C13 | IOSTANDARD=LVCMOS33; # +NET TP<3> LOC = B13 | IOSTANDARD=LVCMOS33; # # Connector T10 # IO-Bank 0 -# NET TP<4> LOC = D13 | IOSTANDARD=LVCMOS33; # -# NET TP<5> LOC = C12 | IOSTANDARD=LVCMOS33; # -# NET TP<6> LOC = B12 | IOSTANDARD=LVCMOS33; # -# NET TP<7> LOC = A12 | IOSTANDARD=LVCMOS33; # +NET TP<4> LOC = D13 | IOSTANDARD=LVCMOS33; # +NET TP<5> LOC = C12 | IOSTANDARD=LVCMOS33; # +NET TP<6> LOC = B12 | IOSTANDARD=LVCMOS33; # +NET TP<7> LOC = A12 | IOSTANDARD=LVCMOS33; # # on Connector T12 # IO-Bank 0 -# NET TP<8> LOC = D11 | IOSTANDARD=LVCMOS33; # -# NET TP<9> LOC = C11 | IOSTANDARD=LVCMOS33; # +NET TP<8> LOC = D11 | IOSTANDARD=LVCMOS33; # +NET TP<9> LOC = C11 | IOSTANDARD=LVCMOS33; # # on Connector T14 # IO-Bank 0 -# NET TP<10> LOC = D10 | IOSTANDARD=LVCMOS33; # -# NET TP<11> LOC = C10 | IOSTANDARD=LVCMOS33; # -# NET TP<12> LOC = A10 | IOSTANDARD=LVCMOS33; # -# NET TP<13> LOC = B10 | IOSTANDARD=LVCMOS33; # +NET TP<10> LOC = D10 | IOSTANDARD=LVCMOS33; # +NET TP<11> LOC = C10 | IOSTANDARD=LVCMOS33; # +NET TP<12> LOC = A10 | IOSTANDARD=LVCMOS33; # +NET TP<13> LOC = B10 | IOSTANDARD=LVCMOS33; # # on Connector T16 # IO-Bank 0 -# NET TP<14> LOC = A9 | IOSTANDARD=LVCMOS33; # -# NET TP<15> LOC = B9 | IOSTANDARD=LVCMOS33; # -# NET TP<16> LOC = A8 | IOSTANDARD=LVCMOS33; # -# NET TP<17> LOC = B8 | IOSTANDARD=LVCMOS33; # +NET TP<14> LOC = A9 | IOSTANDARD=LVCMOS33; # +NET TP<15> LOC = B9 | IOSTANDARD=LVCMOS33; # +NET TP<16> LOC = A8 | IOSTANDARD=LVCMOS33; # +NET TP<17> LOC = B8 | IOSTANDARD=LVCMOS33; # # on Connector T8 # IO-Bank 0 -# NET TP<18> LOC = C8 | IOSTANDARD=LVCMOS33; # -# NET TP<19> LOC = D8 | IOSTANDARD=LVCMOS33; # -# NET TP<20> LOC = C6 | IOSTANDARD=LVCMOS33; # -# NET TP<21> LOC = B6 | IOSTANDARD=LVCMOS33; # +NET TP<18> LOC = C8 | IOSTANDARD=LVCMOS33; # +NET TP<19> LOC = D8 | IOSTANDARD=LVCMOS33; # +NET TP<20> LOC = C6 | IOSTANDARD=LVCMOS33; # +NET TP<21> LOC = B6 | IOSTANDARD=LVCMOS33; # # on Connector T9 # IO-Bank 0 -# NET TP<22> LOC = C7 | IOSTANDARD=LVCMOS33; # -# NET TP<23> LOC = B7 | IOSTANDARD=LVCMOS33; # +NET TP<22> LOC = C7 | IOSTANDARD=LVCMOS33; # +NET TP<23> LOC = B7 | IOSTANDARD=LVCMOS33; # # on Connector T11 # IO-Bank 3 -# NET TP<24> LOC = Y1 | IOSTANDARD=LVCMOS33; # -# NET TP<25> LOC = AA3 | IOSTANDARD=LVCMOS33; # -# NET TP<26> LOC = AA2 | IOSTANDARD=LVCMOS33; # -# NET TP<27> LOC = AC1 | IOSTANDARD=LVCMOS33; # +NET TP<24> LOC = Y1 | IOSTANDARD=LVCMOS33; # +NET TP<25> LOC = AA3 | IOSTANDARD=LVCMOS33; # +NET TP<26> LOC = AA2 | IOSTANDARD=LVCMOS33; # +NET TP<27> LOC = AC1 | IOSTANDARD=LVCMOS33; # # on Connector T13 # IO-Bank 3 -# NET TP<28> LOC = AB1 | IOSTANDARD=LVCMOS33; # -# NET TP<29> LOC = AC3 | IOSTANDARD=LVCMOS33; # -# NET TP<30> LOC = AC2 | IOSTANDARD=LVCMOS33; # -# NET TP<31> LOC = AD2 | IOSTANDARD=LVCMOS33; # +NET TP<28> LOC = AB1 | IOSTANDARD=LVCMOS33; # +NET TP<29> LOC = AC3 | IOSTANDARD=LVCMOS33; # +NET TP<30> LOC = AC2 | IOSTANDARD=LVCMOS33; # +NET TP<31> LOC = AD2 | IOSTANDARD=LVCMOS33; # # on Connector T15 -# NET TP<32> LOC = AD1 | IOSTANDARD=LVCMOS33; # IO-Bank 3 +NET TP<32> LOC = AD1 | IOSTANDARD=LVCMOS33; # IO-Bank 3 # NET TP_in<33> LOC = AE2 | IOSTANDARD=LVCMOS33; # input only # NET TP_in<34> LOC = AE1 | IOSTANDARD=LVCMOS33; # input only Index: /firmware/FTM/ftm_definitions.vhd =================================================================== --- /firmware/FTM/ftm_definitions.vhd (revision 10739) +++ /firmware/FTM/ftm_definitions.vhd (revision 10740) @@ -331,8 +331,8 @@ --X"0010", -- SD_ADDR_general_settings -- general settings X"0000", -- SD_ADDR_led -- on-board status LEDs - X"03FF", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency + X"03E8", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency --X"0001", -- SD_ADDR_lp_pt_freq -- light pulser and pedestal trigger frequency + X"0000", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers --X"0001", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers - X"0001", -- SD_ADDR_lp_pt_ratio... -- ratio between LP1, LP2 and pedestal triggers X"0004", -- SD_ADDR_lp1_amplitude -- light pulser 1 amplitude X"0005", -- SD_ADDR_lp2_amplitude -- light pulser 2 amplitude @@ -344,5 +344,4 @@ X"0000", -- SD_ADDR_timemarker_delay -- timemarker delay X"0017", -- SD_ADDR_dead_time -- dead time, 8ns + 4x23ns = 100ns - --X"0000", -- SD_ADDR_dead_time -- dead time, 8ns + 4x25ns = 108ns X"0003", -- SD_ADDR_cc_R0_HI -- clock conditioner R0 bits 31...16 X"8000", -- SD_ADDR_cc_R0_LO -- clock conditioner R0 bits 15...0 Index: /firmware/FTM/ftu_control/FTM_ftu_control.vhd =================================================================== --- /firmware/FTM/ftu_control/FTM_ftu_control.vhd (revision 10739) +++ /firmware/FTM/ftu_control/FTM_ftu_control.vhd (revision 10740) @@ -219,5 +219,5 @@ signal frame_cnt : integer range 0 to (FTU_RS485_BLOCK_WIDTH / 8) := 0; signal FTU_list_reg_cnt : integer range 0 to NO_OF_FTU_LIST_REG := 0; - signal FTU_list_header_cnt : integer range 0 to FTU_LIST_RAM_OFFSET := 0; + signal FTU_list_header_cnt : integer range 0 to (FTU_LIST_RAM_OFFSET + 1):= 0; signal DD_RAM_reg_cnt : integer range 0 to NO_OF_DD_RAM_REG := 0; @@ -442,8 +442,9 @@ reset_crc_from_FSM_sig <= '0'; enable_crc_from_FSM_sig <= '0'; - new_config_done <= '0'; - ping_all_done <= '0'; - read_rates_done <= '0'; + --new_config_done <= '0'; + --ping_all_done <= '0'; + --read_rates_done <= '0'; if (new_config = '1') then + new_config_done <= '0';-- new_config_started <= '1'; ping_all_started <= '0'; @@ -451,4 +452,5 @@ FTM_ftu_rs485_control_State <= ACTIVE_LIST; elsif (new_config = '0' and ping_all = '1') then + ping_all_done <= '0';-- new_config_started <= '0'; ping_all_started <= '1'; @@ -457,4 +459,5 @@ FTM_ftu_rs485_control_State <= PING; elsif (new_config = '0' and ping_all = '0' and read_rates = '1') then + read_rates_done <= '0';-- new_config_started <= '0'; ping_all_started <= '0'; @@ -836,5 +839,5 @@ when PING_END => -- add final ping statistics to FTU-list if (FTU_list_header_cnt < FTU_LIST_RAM_OFFSET) then - FTU_list_header_cnt <= FTU_list_header_cnt + 1; + --FTU_list_header_cnt <= FTU_list_header_cnt + 1; FTM_ftu_rs485_control_State <= PING_END_1; else @@ -854,11 +857,18 @@ if (FTUlist_RAM_busy = '0') then write_FTUlist_RAM <= '1'; - addr_FTUlist_RAM <= conv_std_logic_vector((FTU_list_header_cnt - 1), FTU_LIST_RAM_ADDR_WIDTH); - if ((FTU_list_header_cnt - 1) = 0) then + --addr_FTUlist_RAM <= conv_std_logic_vector((FTU_list_header_cnt - 1), FTU_LIST_RAM_ADDR_WIDTH); + addr_FTUlist_RAM <= conv_std_logic_vector((FTU_list_header_cnt), FTU_LIST_RAM_ADDR_WIDTH); + --if ((FTU_list_header_cnt - 1) = 0) then + if ((FTU_list_header_cnt) = 0) then data_FTUlist_RAM <= conv_std_logic_vector(no_of_FTU_answer_sig, 16); - elsif ((FTU_list_header_cnt - 1) < 5) then - data_FTUlist_RAM <= conv_std_logic_vector(FTU_answer_array_sig(FTU_list_header_cnt - 2), 16); - elsif ((FTU_list_header_cnt - 1) < 9) then - data_FTUlist_RAM <= active_FTU_array_sig(FTU_list_header_cnt - 6); + --elsif ((FTU_list_header_cnt - 1) < 5) then + elsif ((FTU_list_header_cnt) < 5) then + --data_FTUlist_RAM <= conv_std_logic_vector(FTU_answer_array_sig(FTU_list_header_cnt - 2), 16); + data_FTUlist_RAM <= conv_std_logic_vector(FTU_answer_array_sig(FTU_list_header_cnt - 1), 16); + --elsif ((FTU_list_header_cnt - 1) < 9) then + elsif ((FTU_list_header_cnt) < 9) then + --data_FTUlist_RAM <= active_FTU_array_sig(FTU_list_header_cnt - 6); + --data_FTUlist_RAM <= conv_std_logic_vector(FTU_list_header_cnt - 6, 16); + data_FTUlist_RAM <= active_FTU_array_sig(FTU_list_header_cnt - 5); end if; FTM_ftu_rs485_control_State <= PING_END_2; @@ -873,4 +883,5 @@ when PING_END_3 => if (FTUlist_RAM_ready = '1') then + FTU_list_header_cnt <= FTU_list_header_cnt + 1; FTM_ftu_rs485_control_State <= PING_END; end if;