Index: /firmware/FTM/FTM_central_control.vhd =================================================================== --- /firmware/FTM/FTM_central_control.vhd (revision 10759) +++ /firmware/FTM/FTM_central_control.vhd (revision 10760) @@ -82,5 +82,6 @@ trigger_start : out std_logic := '0'; trigger_stop : out std_logic := '1'; - enable_ID_sending : out std_logic := '0' + enable_ID_sending : out std_logic := '0'; + reset_timer : out std_logic := '0' ); end FTM_central_control; @@ -99,5 +100,5 @@ signal prescaling_FTU01_sig : std_logic_vector(7 downto 0) := "00100111"; - type state_central_proc_type is (CP_INIT, CP_INIT_DNA, + type state_central_proc_type is (CP_INIT, CP_INIT_DNA, CP_INIT_TIMER, CP_RUNNING, CP_RUNNING_01, CP_RUNNING_02, CP_CONFIG_ACK, CP_CONFIG_START, CP_CONFIG, CP_CONFIG_01, @@ -124,5 +125,5 @@ current_cc_state <= X"FFFF"; --cc_state_test <= X"00"; - cc_state_test <= X"19"; + cc_state_test <= X"01"; if (clk_ready = '1') then state_central_proc <= CP_INIT_DNA; @@ -133,10 +134,17 @@ cc_state_test <= X"01"; if (dna_ready = '1') then - state_central_proc <= CP_CONFIG; + state_central_proc <= CP_INIT_TIMER; dna_start <= '0'; + reset_timer <= '1'; -- reset timer after power-up else dna_start <= '1'; state_central_proc <= CP_INIT_DNA; end if; + + when CP_INIT_TIMER => + current_cc_state <= X"FFFF"; + cc_state_test <= X"01"; + reset_timer <= '0'; -- finish reset timer after power-up + state_central_proc <= CP_CONFIG; when CP_CONFIG_START => @@ -236,4 +244,5 @@ when CP_IDLE => current_cc_state <= FTM_STATE_IDLE; + reset_timer <= '0'; cc_state_test <= X"0D"; stop_run_ack <= '1'; @@ -262,4 +271,5 @@ start_run_ack <= '1'; if (start_run_param = PAR_START_RUN) then + reset_timer <= '1'; state_central_proc <= CP_RUNNING; end if; @@ -267,4 +277,5 @@ when CP_RUNNING => + reset_timer <= '0'; current_cc_state <= FTM_STATE_RUN; cc_state_test <= X"0E"; @@ -313,4 +324,5 @@ if (stop_run = '0') then stop_run_ack <= '0'; + reset_timer <= '1'; state_central_proc <= CP_IDLE; end if; @@ -393,5 +405,5 @@ period_finished_sig <= '0'; elsif rising_edge(clk_scaler) then - if (scaler_counts_sig < scaler_period_sig) then + if (scaler_counts_sig < (scaler_period_sig - 1)) then scaler_counts_sig <= scaler_counts_sig + 1; period_finished_sig <= '0'; Index: /firmware/FTM/FTM_top.vhd =================================================================== --- /firmware/FTM/FTM_top.vhd (revision 10759) +++ /firmware/FTM/FTM_top.vhd (revision 10760) @@ -364,4 +364,6 @@ signal trigger_ID_sig : std_logic_vector(55 downto 0); -- initialized in trigger manager signal trigger_ID_read_sig : std_logic; -- initialized in FTM_fad_broadcast + + signal trigger_active_sig : std_logic; -- initialized in trigger manager signal reset_sig : STD_LOGIC := '0'; -- initialize to 0 on power-up @@ -403,4 +405,5 @@ signal enable_ID_sending_sig : std_logic; + signal reset_timer_sig : std_logic; -- initialized in FTM_central_control -- component FTM_clk_gen @@ -566,5 +569,6 @@ trigger_start : out std_logic; trigger_stop : out std_logic; - enable_ID_sending : out std_logic + enable_ID_sending : out std_logic; + reset_timer : out std_logic ); end component; @@ -750,14 +754,27 @@ end component; - component counter_dummy IS - PORT( - clk : IN std_logic; - get_counter : IN std_logic; - get_counter_started : OUT std_logic := '0'; - get_counter_ready : OUT std_logic := '0'; - counter : OUT std_logic_vector (47 DOWNTO 0) := (others => '0') +-- component counter_dummy IS +-- PORT( +-- clk : IN std_logic; +-- get_counter : IN std_logic; +-- get_counter_started : OUT std_logic := '0'; +-- get_counter_ready : OUT std_logic := '0'; +-- counter : OUT std_logic_vector (47 DOWNTO 0) := (others => '0') +-- ); +-- end component; + + component Timing_counter is + port( + clk : in STD_LOGIC; -- 50 MHz system clock + enable : in STD_LOGIC; -- enable counter + reset : in Std_LOGIC; -- reset counter + read_counter : in STD_LOGIC; -- read counter + reading_started : out STD_LOGIC; + reading_valid : out STD_LOGIC; -- counter reading at output ready + counter_reading : out std_logic_vector (TC_WIDTH - 1 downto 0) ); end component; - + + begin @@ -867,5 +884,5 @@ trig_cnt_copy => trigger_counter_sig, --counter reading trig_cnt_copy_valid => trigger_counter_valid_sig, --trigger counter reading is valid - trigger_active => open, --phys triggers are enabled/active + trigger_active => trigger_active_sig, --phys triggers are enabled/active config_done => config_trigger_done_sig, LP1_pulse => open, --send start signal to light pulser 1 @@ -949,5 +966,6 @@ trigger_start => trigger_start_sig, trigger_stop => trigger_stop_sig, - enable_ID_sending => enable_ID_sending_sig + enable_ID_sending => enable_ID_sending_sig, + reset_timer => reset_timer_sig ); @@ -1131,20 +1149,42 @@ ); - Inst_counter_dummy_ts : counter_dummy +-- Inst_counter_dummy_ts : counter_dummy +-- port map( +-- clk => clk_50M_sig, +-- get_counter => get_ts_counter_sig, +-- get_counter_started => get_ts_counter_started_sig, +-- get_counter_ready => get_ts_counter_ready_sig, +-- counter => timestamp_counter_sig +-- ); + +-- Inst_counter_dummy_ot : counter_dummy +-- port map( +-- clk => clk_50M_sig, +-- get_counter => get_ot_counter_sig, +-- get_counter_started => get_ot_counter_started_sig, +-- get_counter_ready => get_ot_counter_ready_sig, +-- counter => on_time_counter_sig +-- ); + + Inst_Timing_counter_ts : Timing_counter port map( clk => clk_50M_sig, - get_counter => get_ts_counter_sig, - get_counter_started => get_ts_counter_started_sig, - get_counter_ready => get_ts_counter_ready_sig, - counter => timestamp_counter_sig - ); - - Inst_counter_dummy_ot : counter_dummy + enable => '1', + reset => reset_timer_sig, + read_counter => get_ts_counter_sig, + reading_started => get_ts_counter_started_sig, + reading_valid => get_ts_counter_ready_sig, + counter_reading => timestamp_counter_sig + ); + + Inst_Timing_counter_ot : Timing_counter port map( clk => clk_50M_sig, - get_counter => get_ot_counter_sig, - get_counter_started => get_ot_counter_started_sig, - get_counter_ready => get_ot_counter_ready_sig, - counter => on_time_counter_sig + enable => trigger_active_sig, + reset => reset_timer_sig, + read_counter => get_ot_counter_sig, + reading_started => get_ot_counter_started_sig, + reading_valid => get_ot_counter_ready_sig, + counter_reading => on_time_counter_sig ); Index: /firmware/FTM/Timing_counters/Timing_counter.vhd =================================================================== --- /firmware/FTM/Timing_counters/Timing_counter.vhd (revision 10759) +++ /firmware/FTM/Timing_counters/Timing_counter.vhd (revision 10760) @@ -70,7 +70,7 @@ signal read_counter_state : type_read_counter_state := IDLE; -signal counting : std_logic_vector (TC_WIDTH - 1 downto 0); -signal counter_reading_sig : std_logic_vector (TC_WIDTH - 1 downto 0); -signal precounting : std_logic_vector (PRECOUNT_WIDTH - 1 downto 0); +signal counting : std_logic_vector (TC_WIDTH - 1 downto 0) := (others => '0'); +signal counter_reading_sig : std_logic_vector (TC_WIDTH - 1 downto 0) := (others => '0'); +signal precounting : std_logic_vector (PRECOUNT_WIDTH - 1 downto 0) := (others => '0'); @@ -87,7 +87,7 @@ if enable = '1' then precounting <= precounting + 1; - if (precounting = PRECOUNT_DIVIDER) then + if (precounting = (PRECOUNT_DIVIDER - 1)) then counting <= counting + 1; - precounting <= (others => '0'); + precounting <= (others => '0'); end if; end if;