Index: /firmware/FTM/Lightpulser_interface/FM_pulse_generator.vhd =================================================================== --- /firmware/FTM/Lightpulser_interface/FM_pulse_generator.vhd (revision 10761) +++ /firmware/FTM/Lightpulser_interface/FM_pulse_generator.vhd (revision 10761) @@ -0,0 +1,73 @@ +-- ---------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- FTM Light pulser interface: FM__pulse generator for feedback +------------------------------------------------------------------------------- +-- +-- +-- Created: May 13 2011 +-- by Patrick Vogler +-- +-- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; + + +library ftm_definitions; +USE ftm_definitions.ftm_constants.all; + + +ENTITY FM_pulse_generator IS + GENERIC( + pulse_length : integer := FLD_PULSE_LENGTH -- 48ns + ); + PORT( + clk : in std_logic; + pulse_freq : in std_logic_vector (5 downto 0); + FM_out : out std_logic := '0' + ); +END FM_pulse_generator; + +ARCHITECTURE beha OF FM_pulse_generator IS + +BEGIN + + clk_div: process (clk) + variable Z : integer range - FLD_MIN_FREQ_DIV to FLD_FD_MAX_RANGE; + variable MAX : integer range 0 to FLD_FD_MAX_RANGE; + variable Y : integer range 0 to pulse_length; + variable X : integer range 0 to FLD_FD_MULT; + + begin + + -- MAX := (FLD_MIN_FREQ_DIV + FLD_FD_MULT * integer(pulse_freq)); + + if rising_edge(clk) then + if (X < FLD_FD_MULT) then + X := X+1; + else + X := 0; + if (Z < pulse_freq) then + Z := Z + 1; + else + Z := - FLD_MIN_FREQ_DIV; + Y := 0; + end if; + end if; + + + + + if (Y < pulse_length) then + Y := Y + 1; + FM_out <= '1'; + else + FM_out <= '0'; + end if; + + end if; + end process clk_div; + +END ARCHITECTURE beha; Index: /firmware/FTM/Lightpulser_interface/FM_pulse_generator_tb.vhd =================================================================== --- /firmware/FTM/Lightpulser_interface/FM_pulse_generator_tb.vhd (revision 10761) +++ /firmware/FTM/Lightpulser_interface/FM_pulse_generator_tb.vhd (revision 10761) @@ -0,0 +1,96 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15:21:36 05/16/2011 +-- Design Name: +-- Module Name: /home/pavogler/ISDC_repos/firmware/FTM/Lightpulser_interface/V2//FM_pulse_generator_tb.vhd +-- Project Name: FLD_2 +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: FM_pulse_generator +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE ieee.numeric_std.ALL; + +ENTITY FM_pulse_generator_tb IS +END FM_pulse_generator_tb; + +ARCHITECTURE behavior OF FM_pulse_generator_tb IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT FM_pulse_generator + PORT( + clk : IN std_logic; + pulse_freq : IN std_logic_vector(5 downto 0); + FM_out : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal clk : std_logic := '0'; + signal pulse_freq : std_logic_vector(5 downto 0) := (others => '0'); + + --Outputs + signal FM_out : std_logic; + + -- Clock period definitions + constant clk_period : time := 4 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: FM_pulse_generator PORT MAP ( + clk => clk, + pulse_freq => pulse_freq, + FM_out => FM_out + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100 ms. + -- wait for 100 ms; + wait for clk_period*10; + + -- insert stimulus here + + pulse_freq <= "000000"; + wait for clk_period*15000; + pulse_freq <= "001000"; + wait for clk_period*15000; + pulse_freq <= "111111"; + + wait; + end process; + +END; Index: /firmware/FTM/Lightpulser_interface/Lightpulser_interface.vhd =================================================================== --- /firmware/FTM/Lightpulser_interface/Lightpulser_interface.vhd (revision 10761) +++ /firmware/FTM/Lightpulser_interface/Lightpulser_interface.vhd (revision 10761) @@ -0,0 +1,289 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: Patrick Vogler +-- +-- Create Date: 24 February 2010 +-- Design Name: +-- Module Name: FTM Lightpulser interface +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Interface to the lightpulsers LP1 (in the mirror dish) +-- and LP2 (inside the shutter) +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- +-- modifications: May 13 2011 +-- +-- Version 2 +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +library ftm_definitions; +USE ftm_definitions.ftm_array_types.all; +USE ftm_definitions.ftm_constants.all; + + + +entity Lightpulser_interface is + port( + +-- Clock +------------------------------------------------------------------------------- + clk_50 : IN STD_LOGIC; -- 50 MHz system clock + clk_250 : IN STD_LOGIC; -- 250 MHz system clock + +-- Lightpulser +-- RJ-45 connectors J13 or J12 on the FTM board +-- LVDS calibration outputs +-- on IO-Bank 0 +------------------------------------------------------------------------------- +-- connector J13 => Light Pulser 1 in the mirror dish + Cal_0_p : out STD_LOGIC := '0'; -- Feedback / pulse width modulation + Cal_0_n : out STD_LOGIC := '1'; + Cal_1_p : out STD_LOGIC := '0'; -- Pulse + Cal_1_n : out STD_LOGIC := '1'; + Cal_2_p : out STD_LOGIC := '0'; -- Gate_1_4_7 + Cal_2_n : out STD_LOGIC := '1'; + Cal_3_p : out STD_LOGIC := '0'; -- Gate_3_5_8 + Cal_3_n : out STD_LOGIC := '1'; + +-- connector J12 => Light Pulser 2 in the shutter + Cal_4_p : out STD_LOGIC := '0'; -- Feedback / pulse width modulation + Cal_4_n : out STD_LOGIC := '1'; + Cal_5_p : out STD_LOGIC := '0'; -- Pulse + Cal_5_n : out STD_LOGIC := '1'; + Cal_6_p : out STD_LOGIC := '0'; -- Gate_1_4_7 + Cal_6_n : out STD_LOGIC := '1'; + Cal_7_p : out STD_LOGIC := '0'; -- Gate_3_5_8 + Cal_7_n : out STD_LOGIC := '1'; + + +-- FPGA intern signals: Lightpulser brightness +------------------------------------------------------------------------------- + + LP1_ampl : in std_logic_vector (15 downto 0); + LP2_ampl : in std_logic_vector (15 downto 0); + + LP1_delay : in std_logic_vector (15 downto 0); + LP2_delay : in std_logic_vector (15 downto 0); + + + LP1_pulse : in std_logic; -- trigger lightpulse in the mirror dish + LP2_pulse : in std_logic; -- trigger lightpulse in the shutter + + + start_config : in std_logic; -- handshaking + config_started : out std_logic := '0'; + config_done : out std_logic := '0' + + ); +end Lightpulser_interface; + + +architecture Behavioral of Lightpulser_interface is + + + +component FM_pulse_generator is + port( + clk : in std_logic; -- 250 MHz + pulse_freq : in std_logic_vector (5 downto 0); + FM_out : out std_logic := '0' + ); +end component; + + + component single_LP is + port( + clk_250 : in STD_LOGIC; + LP_Pulse_out : out STD_LOGIC; + LP_pulse_in : in std_logic; + LP_delay : in std_logic_vector (15 downto 0) + ); +end component; + + + + + -- LP1: mirror dish + signal Cal_0_1 : STD_LOGIC := '0'; +-- signal Cal_1_1 : STD_LOGIC; + + -- LP2: shutter + signal Cal_0_2 : STD_LOGIC := '0'; +-- signal Cal_1_2 : STD_LOGIC; + + -- PWM for amplitude stabilization + signal PWM_sig_1 : std_logic := '0'; -- LP1: mirror dish + signal PWM_sig_2 : std_logic := '0'; -- LP2: shutter + + -- control data latch + signal LP1_ampl_sig : std_logic_vector (15 downto 0) := (others => '0'); + signal LP2_ampl_sig : std_logic_vector (15 downto 0) := (others => '0'); + signal LP1_delay_sig : std_logic_vector (15 downto 0) := (others => '0'); + signal LP2_delay_sig : std_logic_vector (15 downto 0) := (others => '0'); + + type type_latch_state is (IDLE, COPY, CONFIGURED); + signal latch_state : type_latch_state := IDLE; + + + + + +begin + + +-- input latch +input_latch : process (clk_50, start_config) + begin + if rising_edge(clk_50) then + case latch_state is + + when IDLE => + if start_config = '1' then + config_done <= '0'; + config_started <= '1'; + latch_state <= COPY; + end if; + + when COPY => + LP1_ampl_sig <= LP1_ampl; + LP2_ampl_sig <= LP2_ampl; + LP1_delay_sig <= LP1_delay; + LP2_delay_sig <= LP2_delay; + latch_state <= CONFIGURED; + + when CONFIGURED => + config_started <= '0'; + config_done <= '1'; + latch_state <= IDLE; + + end case; + end if; +end process input_latch; + + + + Inst_LP1_mirror_dish:single_LP + port map ( + clk_250 => clk_250, + LP_Pulse_out => Cal_0_1, + LP_pulse_in => LP1_pulse, + LP_delay => LP1_delay_sig + ); + + + Inst_LP2_shutter:single_LP + port map ( + clk_250 => clk_250, + LP_Pulse_out => Cal_0_2, + LP_pulse_in => LP2_pulse, + LP_delay => LP2_delay_sig + ); + +Inst_LP1_FM_pulse_generator:FM_pulse_generator -- LP1: mirror dish + port map( + clk => clk_250, + pulse_freq => LP1_ampl_sig(5 downto 0), + FM_out => PWM_sig_1 + ); + + +Inst_LP2_FM_pulse_generator:FM_pulse_generator -- LP2: shutter + port map( + clk => clk_250, + pulse_freq => LP2_ampl_sig(5 downto 0), + FM_out => PWM_sig_2 + ); + + +-- Light Pulser 1 (in the mirror dish): differential output buffers + + OBUFDS_inst_Cal_0 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_0_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_0_n , -- Diff_n output (connect directly to top-level port) + I => Cal_0_1 -- Buffer input + ); + + OBUFDS_inst_Cal_1 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_1_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_1_n , -- Diff_n output (connect directly to top-level port) + I => PWM_sig_1 -- Buffer input + ); + + OBUFDS_inst_Cal_2 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_2_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_2_n , -- Diff_n output (connect directly to top-level port) + I => LP1_ampl_sig(14) -- Buffer input + ); + + OBUFDS_inst_Cal_3 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_3_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_3_n , -- Diff_n output (connect directly to top-level port) + I => LP1_ampl_sig(15) -- Buffer input + ); + + + +-- Light Pulser 2 (in the shutter): differential output buffers + + OBUFDS_inst_Cal_4 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_4_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_4_n , -- Diff_n output (connect directly to top-level port) + I => Cal_0_2 -- Buffer input + ); + + OBUFDS_inst_Cal_5 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_5_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_5_n , -- Diff_n output (connect directly to top-level port) + I => PWM_sig_2 -- Buffer input + ); + + OBUFDS_inst_Cal_6 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_6_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_6_n , -- Diff_n output (connect directly to top-level port) + I => LP2_ampl_sig(14) + ); + + OBUFDS_inst_Cal_7 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_7_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_7_n , -- Diff_n output (connect directly to top-level port) + I => LP2_ampl_sig(15) -- Buffer input + ); + + +end Behavioral; + + Index: /firmware/FTM/Lightpulser_interface/Lightpulser_interface_tb.vhd =================================================================== --- /firmware/FTM/Lightpulser_interface/Lightpulser_interface_tb.vhd (revision 10761) +++ /firmware/FTM/Lightpulser_interface/Lightpulser_interface_tb.vhd (revision 10761) @@ -0,0 +1,244 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: Patrick Vogler +-- +-- Create Date: 14:09:52 05/13/2011 +-- Design Name: +-- Module Name: /home/pavogler/ISDC_repos/firmware/FTM/Lightpulser_interface//Lightpulser_interface_tb.vhd +-- Project Name: FLD +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: Lightpulser_interface +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE ieee.numeric_std.ALL; + +ENTITY Lightpulser_interface_tb IS +END Lightpulser_interface_tb; + +ARCHITECTURE behavior OF Lightpulser_interface_tb IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT Lightpulser_interface + PORT( + clk_50 : IN std_logic; + clk_250 : IN std_logic; + Cal_0_p : OUT std_logic; + Cal_0_n : OUT std_logic; + Cal_1_p : OUT std_logic; + Cal_1_n : OUT std_logic; + Cal_2_p : OUT std_logic; + Cal_2_n : OUT std_logic; + Cal_3_p : OUT std_logic; + Cal_3_n : OUT std_logic; + Cal_4_p : OUT std_logic; + Cal_4_n : OUT std_logic; + Cal_5_p : OUT std_logic; + Cal_5_n : OUT std_logic; + Cal_6_p : OUT std_logic; + Cal_6_n : OUT std_logic; + Cal_7_p : OUT std_logic; + Cal_7_n : OUT std_logic; + LP1_ampl : IN std_logic_vector(15 downto 0); + LP2_ampl : IN std_logic_vector(15 downto 0); + LP1_delay : IN std_logic_vector(15 downto 0); + LP2_delay : IN std_logic_vector(15 downto 0); + LP1_pulse : IN std_logic; + LP2_pulse : IN std_logic; + start_config : IN std_logic; + config_started : OUT std_logic; + config_done : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal clk_50 : std_logic := '0'; + signal clk_250 : std_logic := '0'; + signal LP1_ampl : std_logic_vector(15 downto 0) := (others => '0'); + signal LP2_ampl : std_logic_vector(15 downto 0) := (others => '0'); + signal LP1_delay : std_logic_vector(15 downto 0) := (others => '0'); + signal LP2_delay : std_logic_vector(15 downto 0) := (others => '0'); + signal LP1_pulse : std_logic := '0'; + signal LP2_pulse : std_logic := '0'; + signal start_config : std_logic := '0'; + + --Outputs + signal Cal_0_p : std_logic; + signal Cal_0_n : std_logic; + signal Cal_1_p : std_logic; + signal Cal_1_n : std_logic; + signal Cal_2_p : std_logic; + signal Cal_2_n : std_logic; + signal Cal_3_p : std_logic; + signal Cal_3_n : std_logic; + signal Cal_4_p : std_logic; + signal Cal_4_n : std_logic; + signal Cal_5_p : std_logic; + signal Cal_5_n : std_logic; + signal Cal_6_p : std_logic; + signal Cal_6_n : std_logic; + signal Cal_7_p : std_logic; + signal Cal_7_n : std_logic; + signal config_started : std_logic; + signal config_done : std_logic; + + -- Clock period definitions + constant clk_50_period : time := 20 ns; + constant clk_250_period : time := 4 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: Lightpulser_interface PORT MAP ( + clk_50 => clk_50, + clk_250 => clk_250, + Cal_0_p => Cal_0_p, + Cal_0_n => Cal_0_n, + Cal_1_p => Cal_1_p, + Cal_1_n => Cal_1_n, + Cal_2_p => Cal_2_p, + Cal_2_n => Cal_2_n, + Cal_3_p => Cal_3_p, + Cal_3_n => Cal_3_n, + Cal_4_p => Cal_4_p, + Cal_4_n => Cal_4_n, + Cal_5_p => Cal_5_p, + Cal_5_n => Cal_5_n, + Cal_6_p => Cal_6_p, + Cal_6_n => Cal_6_n, + Cal_7_p => Cal_7_p, + Cal_7_n => Cal_7_n, + LP1_ampl => LP1_ampl, + LP2_ampl => LP2_ampl, + LP1_delay => LP1_delay, + LP2_delay => LP2_delay, + LP1_pulse => LP1_pulse, + LP2_pulse => LP2_pulse, + start_config => start_config, + config_started => config_started, + config_done => config_done + ); + + -- Clock process definitions + clk_50_process :process + begin + clk_50 <= '0'; + wait for clk_50_period/2; + clk_50 <= '1'; + wait for clk_50_period/2; + end process; + + clk_250_process :process + begin + clk_250 <= '0'; + wait for clk_250_period/2; + clk_250 <= '1'; + wait for clk_250_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100 ms. + -- wait for 100 ms; + + wait for clk_50_period*10; + + -- insert stimulus here + + -- init input signals + start_config <= '0'; + LP1_pulse <= '0'; + LP2_pulse <= '0'; + + + + -- latch settings + LP1_ampl <= "1000000000000111"; + LP2_ampl <= "0100000000010000"; + + LP1_delay <= "0000000000010000"; + LP2_delay <= "0000000000000001"; + + wait for clk_50_period*5; + start_config <= '1'; + wait for clk_50_period*1; + start_config <= '0'; + + + wait for clk_50_period*5; + + + -- trigger lightpulses + + -- LP1: mirror dish + LP1_pulse <= '1'; + wait for clk_50_period*5; + LP1_pulse <= '0'; + + -- LP2: shutter + LP2_pulse <= '1'; + wait for clk_50_period*5; + LP2_pulse <= '0'; + + + + + + -- next cyclus + wait for clk_50_period*10; + + + -- latch settings + LP1_ampl <= "1100000000000111"; + LP2_ampl <= "0000000000010000"; + + LP1_delay <= "0000000001010000"; + LP2_delay <= "0000000000000101"; + + wait for clk_50_period*5; + start_config <= '1'; + wait for clk_50_period*1; + start_config <= '0'; + + + wait for clk_50_period*5; + + -- trigger lightpulses + + -- LP1: mirror dish + LP1_pulse <= '1'; + wait for clk_50_period*2; + LP1_pulse <= '0'; + + -- LP2: shutter + LP2_pulse <= '1'; + wait for clk_50_period*2; + LP2_pulse <= '0'; + + + + wait; + end process; + +END; Index: /firmware/FTM/Lightpulser_interface/delayed_pulse.vhd =================================================================== --- /firmware/FTM/Lightpulser_interface/delayed_pulse.vhd (revision 10761) +++ /firmware/FTM/Lightpulser_interface/delayed_pulse.vhd (revision 10761) @@ -0,0 +1,208 @@ +--======================================================================================= +-- TITLE : Pulse generation with programmable delay +-- DESCRIPTION : Generate pulse from an input with a programmable delay and width +-- FILE : time_counter.vhd +-- COMPANY : Micro-Cameras & Space Exploration SA +--======================================================================================= +-- CREATION +-- DATE AUTHOR PROJECT REVISION +-- 02/03/2011 JGi FTM 110302a +--======================================================================================= +-- MODIFICATION HISTORY +-- DATE AUTHOR PROJECT REVISION COMMENTS +-- 02/03/2011 JGi FTM 110302a Description +--======================================================================================= +-- Library Definition +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library unisim; + use unisim.vcomponents.all; + +-- Entity Definition +entity delayed_pulse is + generic( pulse_width : integer range 0 to 15 := 10); + port( --clock + clk_250MHz : in std_logic; + --control + delay : in std_logic_vector(9 downto 0); + --I/O + input : in std_logic; + output : out std_logic); +end delayed_pulse; + +-- Architecture Definition +architecture RTL of delayed_pulse is + + type t_reg is record + -- Internal register declaration + delayed_input : std_logic; + enable : std_logic_vector(3 downto 0); + delay : std_logic_vector(9 downto 0); + delay_counter : std_logic_vector(9 downto 0); + delay_value_reached : std_logic_vector(2 downto 0); + delay_0_done : std_logic_vector(1 downto 0); + delay_1_done : std_logic; + pulse_shifter : std_logic_vector(pulse_width downto 0); + -- Ouput register declaration + output : std_logic_vector(1 downto 0); + end record; + + signal i_next_reg : t_reg := (delayed_input => '0', + enable => (others => '0'), + delay => (others => '0'), + delay_counter => (others => '0'), + delay_value_reached => (others => '0'), + delay_0_done => (others => '0'), + delay_1_done => '0', + pulse_shifter => (others => '0'), + output => (others => '0')); + signal i_reg : t_reg := (delayed_input => '0', + enable => (others => '0'), + delay => (others => '0'), + delay_counter => (others => '0'), + delay_value_reached => (others => '0'), + delay_0_done => (others => '0'), + delay_1_done => '0', + pulse_shifter => (others => '0'), + output => (others => '0')); + + signal i_shifted_data : std_logic; + +begin + + -- Generate shift register depending on pulse width generic + -- defined in ftm_definitions + -- Shifter logic + gen_shifter_0: if pulse_width = 0 generate + process(clk_250MHz) + variable shifter : std_logic := '0'; + begin + if rising_edge(clk_250MHz) then + shifter := i_reg.output(0) and not(i_reg.output(1)); + end if; + i_shifted_data <= shifter; + end process; + end generate gen_shifter_0; + gen_shifter_1: if pulse_width > 0 generate + process(clk_250MHz) + variable shifter : std_logic_vector(pulse_width downto 0) := (others => '0'); + begin + if rising_edge(clk_250MHz) then + shifter := shifter(pulse_width-1 downto 0) & (i_reg.output(0) and not(i_reg.output(1))); + end if; + i_shifted_data <= shifter(pulse_width); + end process; + end generate gen_shifter_1; + + -- Combinatorial logic + process(input, delay, i_shifted_data, i_reg) + variable v_reg : t_reg := (delayed_input => '0', + enable => (others => '0'), + delay => (others => '0'), + delay_counter => (others => '0'), + delay_value_reached => (others => '0'), + delay_0_done => (others => '0'), + delay_1_done => '0', + pulse_shifter => (others => '0'), + output => (others => '0')); + begin + v_reg := i_reg; + --=================================================================================== + + --=================================================================================== + -- Delay Counter management + --=================================================================================== + -- Register delay + v_reg.delay := delay; + + -- Count delay when input (master trigger) rising edge detected + if i_reg.enable(0) = '1' then + v_reg.delay_counter(3 downto 0) := std_logic_vector(unsigned(i_reg.delay_counter(3 downto 0))+1); + if i_reg.delay_0_done(1) = '1' then + v_reg.delay_counter(7 downto 4) := std_logic_vector(unsigned(i_reg.delay_counter(7 downto 4))+1); + end if; + if i_reg.delay_1_done = '1' then + v_reg.delay_counter(9 downto 8) := std_logic_vector(unsigned(i_reg.delay_counter(9 downto 8))+1); + end if; + else + v_reg.delay_counter := (others => '0'); + end if; + + v_reg.delayed_input := input; + + -- Detect input (master trigger) rising edge to enable counting + if input = '1' and i_reg.delayed_input = '0' then + v_reg.enable := (others => '1'); + end if; + + -- Generate partial comparison between counter and setting + if i_reg.delay_counter(3 downto 0) = i_reg.delay(3 downto 0) then + v_reg.delay_value_reached(0) := i_reg.enable(1); + else + v_reg.delay_value_reached(0) := '0'; + end if; + if i_reg.delay_counter(7 downto 4) = i_reg.delay(7 downto 4) then + v_reg.delay_value_reached(1) := i_reg.enable(1); + else + v_reg.delay_value_reached(1) := '0'; + end if; + if i_reg.delay_counter(9 downto 8) = i_reg.delay(9 downto 8) then + v_reg.delay_value_reached(2) := i_reg.enable(1); + else + v_reg.delay_value_reached(2) := '0'; + end if; + + -- Generate partial counter enable + if i_reg.delay_counter(3 downto 0) = "1101" then + v_reg.delay_0_done(0) := i_reg.enable(2); + else + v_reg.delay_0_done(0) := '0'; + end if; + v_reg.delay_0_done(1) := i_reg.delay_0_done(0) and i_reg.enable(2); + + if i_reg.delay_counter(7 downto 4) = "1111" then + v_reg.delay_1_done := i_reg.delay_0_done(0) and i_reg.enable(2); + end if; + --=================================================================================== + + --=================================================================================== + -- Pulse Counter management + --=================================================================================== + -- Enable output when delay is reached, and disable it after shift register + -- has finished + if i_shifted_data = '1' then + v_reg.output(0) := '0'; + elsif i_reg.delay_value_reached = "111" and i_reg.enable(3) = '1' then + v_reg.output(0) := '1'; + v_reg.pulse_shifter(0) := '1'; + end if; + + -- Once the output falls, reset enable + if i_reg.output(1) = '1' and i_reg.output(0) = '0' then + v_reg.enable := (others => '0'); + end if; + + v_reg.output(1) := i_reg.output(0); + --=================================================================================== + + --=================================================================================== + -- Drive register input + i_next_reg <= v_reg; + + --=================================================================================== + -- Output assignation + output <= i_reg.output(0); + --=================================================================================== + end process; + + -- Sequential logic + process(clk_250MHz) + begin + if rising_edge(clk_250MHz) then + i_reg <= i_next_reg; + end if; + end process; + +end RTL;