Index: firmware/FTM/FTM_central_control.vhd =================================================================== --- firmware/FTM/FTM_central_control.vhd (revision 10761) +++ firmware/FTM/FTM_central_control.vhd (revision 10779) @@ -83,5 +83,9 @@ trigger_stop : out std_logic := '1'; enable_ID_sending : out std_logic := '0'; - reset_timer : out std_logic := '0' + reset_timer : out std_logic := '0'; + crate_res_0 : out std_logic := '1'; + crate_res_1 : out std_logic := '1'; + crate_res_2 : out std_logic := '1'; + crate_res_3 : out std_logic := '1' ); end FTM_central_control; @@ -99,4 +103,5 @@ signal new_period_ack_sig : std_logic := '0'; signal prescaling_FTU01_sig : std_logic_vector(7 downto 0) := "00100111"; + signal reset_cnt_sig : integer range 0 to RESET_TIME := 0; type state_central_proc_type is (CP_INIT, CP_INIT_DNA, CP_INIT_TIMER, @@ -108,5 +113,6 @@ CP_CONFIG_TRIGGER, CP_CONFIG_TRIGGER_01, CP_IDLE, CP_PING, CP_START_RATES, CP_READ_RATES, CP_READ_RATES_01, - CP_SEND_START, CP_SEND_END); + CP_SEND_START, CP_SEND_END, + CP_CRATE_RESET, CP_CRATE_RESET_ACK); signal state_central_proc : state_central_proc_type := CP_INIT; @@ -124,5 +130,4 @@ when CP_INIT => -- wait for DCMs to lock current_cc_state <= X"FFFF"; - --cc_state_test <= X"00"; cc_state_test <= X"01"; if (clk_ready = '1') then @@ -250,5 +255,5 @@ if (new_config = '1') then config_started <= '1'; - start_run_ack <= '1'; + start_run_ack <= '1'; --remove this line??? state_central_proc <= CP_CONFIG_START; elsif (ping_ftu_start = '1') then @@ -274,4 +279,7 @@ state_central_proc <= CP_RUNNING; end if; + elsif (crate_reset = '1') then + crate_reset_ack <= '1'; + state_central_proc <= CP_CRATE_RESET; end if; @@ -317,4 +325,7 @@ enable_Id_sending <= '0'; state_central_proc <= CP_RUNNING_02; + elsif (crate_reset = '1') then + crate_reset_ack <= '1'; + state_central_proc <= CP_CRATE_RESET_ACK; end if; @@ -329,5 +340,4 @@ when CP_CONFIG_ACK => - current_cc_state <= FTM_STATE_CFG; cc_state_test <= X"11"; if (config_started_ack = '1') then @@ -335,5 +345,5 @@ state_central_proc <= CP_RUNNING_01; end if; - + when CP_PING => cc_state_test <= X"12"; @@ -392,6 +402,20 @@ end if; + when CP_CRATE_RESET_ACK => + cc_state_test <= X"18"; + if (crate_reset = '0') then + crate_reset_ack <= '0'; + state_central_proc <= CP_RUNNING_01; + end if; + + when CP_CRATE_RESET => + cc_state_test <= X"19"; + if (crate_reset = '0') then + crate_reset_ack <= '0'; + state_central_proc <= CP_IDLE; + end if; + when others => - cc_state_test <= X"18"; + cc_state_test <= X"1A"; end case; Index: firmware/FTM/FTM_top.vhd =================================================================== --- firmware/FTM/FTM_top.vhd (revision 10761) +++ firmware/FTM/FTM_top.vhd (revision 10779) @@ -406,5 +406,10 @@ signal enable_ID_sending_sig : std_logic; signal reset_timer_sig : std_logic; -- initialized in FTM_central_control - + + signal crate_res0_sig : std_logic; -- initialized in FTM_central_control + signal crate_res1_sig : std_logic; -- initialized in FTM_central_control + signal crate_res2_sig : std_logic; -- initialized in FTM_central_control + signal crate_res3_sig : std_logic; -- initialized in FTM_central_control + -- component FTM_clk_gen -- port( @@ -570,5 +575,9 @@ trigger_stop : out std_logic; enable_ID_sending : out std_logic; - reset_timer : out std_logic + reset_timer : out std_logic; + crate_res_0 : out std_logic; + crate_res_1 : out std_logic; + crate_res_2 : out std_logic; + crate_res_3 : out std_logic ); end component; @@ -967,5 +976,9 @@ trigger_stop => trigger_stop_sig, enable_ID_sending => enable_ID_sending_sig, - reset_timer => reset_timer_sig + reset_timer => reset_timer_sig, + crate_res_0 => crate_res0_sig, + crate_res_1 => crate_res1_sig, + crate_res_2 => crate_res2_sig, + crate_res_3 => crate_res3_sig ); @@ -1034,7 +1047,5 @@ rx_d_3 => Bus2_RxD_3, tx_d_3 => Bus2_TxD_3, - --enable_ID_sending => trigger_start_sig, enable_ID_sending => enable_ID_sending_sig, - --enable_ID_sending => '1', TIM_source => general_settings_sig(0), LP_settings => "0000", @@ -1197,8 +1208,8 @@ TP( 7 downto 0) <= cc_state_test_sig; - Crate_Res0 <= '1'; - Crate_Res1 <= '1'; - Crate_Res2 <= '1'; - Crate_Res3 <= '1'; + Crate_Res0 <= crate_res0_sig; + Crate_Res1 <= crate_res1_sig; + Crate_Res2 <= crate_res2_sig; + Crate_Res3 <= crate_res3_sig; end Behavioral; Index: firmware/FTM/Timing_counters/Timing_counter.vhd =================================================================== --- firmware/FTM/Timing_counters/Timing_counter.vhd (revision 10761) +++ firmware/FTM/Timing_counters/Timing_counter.vhd (revision 10779) @@ -23,4 +23,12 @@ -- -- May 18 2011 by Patrick Vogler +-- +-- May 20, 2011, by Q. Weitzel +-- counting was wrong by one clock cycle (1 us) +-- +-- May 23, 2011, by Q. Weitzel +-- counter reset changed from async to sync reset +-- reset, enable and read_counter removed from sensitity lists +-- ---------------------------------------------------------------------------------- @@ -40,5 +48,4 @@ USE ftm_definitions.ftm_array_types.all; USE ftm_definitions.ftm_constants.all; - @@ -64,5 +71,4 @@ - architecture Behavioral of Timing_counter is @@ -78,25 +84,25 @@ -- counting ------------------------------------------------------------------------------- - count : process (clk, reset, enable) - begin - if reset = '1' then - counting <= (others => '0'); - precounting <= (others => '0'); - - elsif rising_edge(clk) then - if enable = '1' then - precounting <= precounting + 1; - if (precounting = (PRECOUNT_DIVIDER - 1)) then - counting <= counting + 1; - precounting <= (others => '0'); - end if; - end if; - end if; + count : process (clk) + begin + + if rising_edge(clk) then + if (reset = '1') then + counting <= (others => '0'); + precounting <= (others => '0'); + elsif enable = '1' then + precounting <= precounting + 1; + if (precounting = (PRECOUNT_DIVIDER - 1)) then + counting <= counting + 1; + precounting <= (others => '0'); + end if; + end if; + end if; + end process count; - -- read counter ------------------------------------------------------------------------------- - readout_counter : process (clk, read_counter) + readout_counter : process (clk) begin if rising_edge(clk) then @@ -131,4 +137,2 @@ end Behavioral; - - Index: firmware/FTM/ftm_definitions.vhd =================================================================== --- firmware/FTM/ftm_definitions.vhd (revision 10761) +++ firmware/FTM/ftm_definitions.vhd (revision 10779) @@ -234,5 +234,6 @@ -- crate reset constant CMD_CRESET : std_logic_vector := X"0020"; - + constant RESET_TIME : integer := 1000; + -- start and end of package constant FTM_PACKAGE_START : std_logic_vector := X"FB01";