Index: firmware/FTM/Lightpulser_interface/Basic_Version/FM_Pulse_generator_Basic_tb.vhd =================================================================== --- firmware/FTM/Lightpulser_interface/Basic_Version/FM_Pulse_generator_Basic_tb.vhd (revision 10855) +++ firmware/FTM/Lightpulser_interface/Basic_Version/FM_Pulse_generator_Basic_tb.vhd (revision 10855) @@ -0,0 +1,97 @@ +-------------------------------------------------------------------------------- +-- Company: IPP +-- Engineer: Patrick Vogler +-- +-- Create Date: 10:06:23 05/27/2011 +-- Design Name: +-- Module Name: /home/pavogler/ISDC_repos/firmware/FTM/Lightpulser_interface/Basic_Version//FM_Pulse_generator_Basic_tb.vhd +-- Project Name: Lightpulser_Basic +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: FM_pulse_generator_Basic +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE ieee.numeric_std.ALL; + +ENTITY FM_Pulse_generator_Basic_tb IS +END FM_Pulse_generator_Basic_tb; + +ARCHITECTURE behavior OF FM_Pulse_generator_Basic_tb IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT FM_pulse_generator_Basic + PORT( + clk : IN std_logic; + pulse_freq : IN std_logic_vector(5 downto 0); + FM_out : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal clk : std_logic := '0'; + signal pulse_freq : std_logic_vector(5 downto 0) := (others => '0'); + + --Outputs + signal FM_out : std_logic; + + -- Clock period definitions + constant clk_period : time := 20 ns; -- 50MHz Clock + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: FM_pulse_generator_Basic PORT MAP ( + clk => clk, + pulse_freq => pulse_freq, + FM_out => FM_out + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100 ms. +-- wait for 100 ms; + + wait for clk_period*10; + + -- insert stimulus here + + pulse_freq <= "000000"; + wait for clk_period*15000; + pulse_freq <= "001000"; + wait for clk_period*15000; + pulse_freq <= "111111"; + + wait; + end process; + +END; Index: firmware/FTM/Lightpulser_interface/Basic_Version/FM_pulse_generator_Basic.vhd =================================================================== --- firmware/FTM/Lightpulser_interface/Basic_Version/FM_pulse_generator_Basic.vhd (revision 10855) +++ firmware/FTM/Lightpulser_interface/Basic_Version/FM_pulse_generator_Basic.vhd (revision 10855) @@ -0,0 +1,69 @@ +-- ---------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- FTM Light pulser interface: FM__pulse generator for feedback +------------------------------------------------------------------------------- +-- +-- +-- Created: May 13 2011 +-- by Patrick Vogler +-- +-- modified: May 26 2011 +-- by Patrick Vogler +-- "Lightpulser Basic Version" + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE ieee.std_logic_unsigned.all; + + +library ftm_definitions; +USE ftm_definitions.ftm_constants.all; + + +ENTITY FM_pulse_generator_Basic IS + GENERIC( + pulse_length : integer := FLD_PULSE_LENGTH -- 48ns + ); + PORT( + clk : in std_logic; + pulse_freq : in std_logic_vector (5 downto 0); + FM_out : out std_logic := '0' + ); +END FM_pulse_generator_Basic; + +ARCHITECTURE beha OF FM_pulse_generator_Basic IS + +BEGIN + + clk_div: process (clk) + variable Z : integer range - FLD_MIN_FREQ_DIV_BASIC to FLD_FD_MAX_RANGE_BASIC; + variable Y : integer range 0 to FLD_PULSE_LENGTH_BASIC; + variable X : integer range 0 to FLD_FD_MULT_BASIC ; + + begin + + if rising_edge(clk) then + if (X < FLD_FD_MULT_BASIC) then + X := X+1; + else + X := 0; + if (Z < pulse_freq) then + Z := Z + 1; + else + Z := - FLD_MIN_FREQ_DIV; + Y := 0; + end if; + end if; + + if (Y < FLD_PULSE_LENGTH_BASIC) then + Y := Y + 1; + FM_out <= '1'; + else + FM_out <= '0'; + end if; + + end if; + end process clk_div; + +END ARCHITECTURE beha; Index: firmware/FTM/Lightpulser_interface/Basic_Version/Lightpulser_Basic_tb.vhd =================================================================== --- firmware/FTM/Lightpulser_interface/Basic_Version/Lightpulser_Basic_tb.vhd (revision 10855) +++ firmware/FTM/Lightpulser_interface/Basic_Version/Lightpulser_Basic_tb.vhd (revision 10855) @@ -0,0 +1,223 @@ +-------------------------------------------------------------------------------- +-- Company: IPP +-- Engineer: Patrick Vogler +-- +-- Create Date: 14:13:24 05/27/2011 +-- Design Name: +-- Module Name: /home/pavogler/ISDC_repos/firmware/FTM/Lightpulser_interface/Basic_Version//Lightpulser_Basic_tb.vhd +-- Project Name: Lightpulser_Basic +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: Lightpulser_interface +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE ieee.numeric_std.ALL; + +ENTITY Lightpulser_Basic_tb IS +END Lightpulser_Basic_tb; + +ARCHITECTURE behavior OF Lightpulser_Basic_tb IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT Lightpulser_interface + PORT( + clk_50 : IN std_logic; + Cal_0_p : OUT std_logic; + Cal_0_n : OUT std_logic; + Cal_1_p : OUT std_logic; + Cal_1_n : OUT std_logic; + Cal_2_p : OUT std_logic; + Cal_2_n : OUT std_logic; + Cal_3_p : OUT std_logic; + Cal_3_n : OUT std_logic; + Cal_4_p : OUT std_logic; + Cal_4_n : OUT std_logic; + Cal_5_p : OUT std_logic; + Cal_5_n : OUT std_logic; + Cal_6_p : OUT std_logic; + Cal_6_n : OUT std_logic; + Cal_7_p : OUT std_logic; + Cal_7_n : OUT std_logic; + LP1_ampl : IN std_logic_vector(15 downto 0); + LP2_ampl : IN std_logic_vector(15 downto 0); + LP1_pulse : IN std_logic; + LP2_pulse : IN std_logic; + start_config : IN std_logic; + config_started : OUT std_logic; + config_done : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal clk_50 : std_logic := '0'; + signal LP1_ampl : std_logic_vector(15 downto 0) := (others => '0'); + signal LP2_ampl : std_logic_vector(15 downto 0) := (others => '0'); + signal LP1_pulse : std_logic := '0'; + signal LP2_pulse : std_logic := '0'; + signal start_config : std_logic := '0'; + + --Outputs + signal Cal_0_p : std_logic; + signal Cal_0_n : std_logic; + signal Cal_1_p : std_logic; + signal Cal_1_n : std_logic; + signal Cal_2_p : std_logic; + signal Cal_2_n : std_logic; + signal Cal_3_p : std_logic; + signal Cal_3_n : std_logic; + signal Cal_4_p : std_logic; + signal Cal_4_n : std_logic; + signal Cal_5_p : std_logic; + signal Cal_5_n : std_logic; + signal Cal_6_p : std_logic; + signal Cal_6_n : std_logic; + signal Cal_7_p : std_logic; + signal Cal_7_n : std_logic; + signal config_started : std_logic; + signal config_done : std_logic; + + -- Clock period definitions + constant clk_50_period : time := 20 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: Lightpulser_interface PORT MAP ( + clk_50 => clk_50, + Cal_0_p => Cal_0_p, + Cal_0_n => Cal_0_n, + Cal_1_p => Cal_1_p, + Cal_1_n => Cal_1_n, + Cal_2_p => Cal_2_p, + Cal_2_n => Cal_2_n, + Cal_3_p => Cal_3_p, + Cal_3_n => Cal_3_n, + Cal_4_p => Cal_4_p, + Cal_4_n => Cal_4_n, + Cal_5_p => Cal_5_p, + Cal_5_n => Cal_5_n, + Cal_6_p => Cal_6_p, + Cal_6_n => Cal_6_n, + Cal_7_p => Cal_7_p, + Cal_7_n => Cal_7_n, + LP1_ampl => LP1_ampl, + LP2_ampl => LP2_ampl, + LP1_pulse => LP1_pulse, + LP2_pulse => LP2_pulse, + start_config => start_config, + config_started => config_started, + config_done => config_done + ); + + -- Clock process definitions + clk_50_process :process + begin + clk_50 <= '0'; + wait for clk_50_period/2; + clk_50 <= '1'; + wait for clk_50_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100 ms. + -- wait for 100 ms; + + wait for clk_50_period*10; + + -- insert stimulus here + + + + -- init input signals + start_config <= '0'; + LP1_pulse <= '0'; + LP2_pulse <= '0'; + + + + -- latch settings + LP1_ampl <= "1000000000000111"; + LP2_ampl <= "0100000000010000"; + + + wait for clk_50_period*5; + start_config <= '1'; + wait for clk_50_period*1; + start_config <= '0'; + + + wait for clk_50_period*5; + + + -- trigger lightpulses + + -- LP1: mirror dish + LP1_pulse <= '1'; + wait for clk_50_period*5; + LP1_pulse <= '0'; + + -- LP2: shutter + LP2_pulse <= '1'; + wait for clk_50_period*5; + LP2_pulse <= '0'; + + + + + + -- next cyclus + wait for clk_50_period*10; + + + -- latch settings + LP1_ampl <= "1100000000000111"; + LP2_ampl <= "0000000000010000"; + + wait for clk_50_period*5; + start_config <= '1'; + wait for clk_50_period*1; + start_config <= '0'; + + + wait for clk_50_period*5; + + -- trigger lightpulses + + -- LP1: mirror dish + LP1_pulse <= '1'; + wait for clk_50_period*2; + LP1_pulse <= '0'; + + -- LP2: shutter + LP2_pulse <= '1'; + wait for clk_50_period*2; + LP2_pulse <= '0'; + + + + wait; + end process; + +END; Index: firmware/FTM/Lightpulser_interface/Basic_Version/Lightpulser_interface_Basic.vhd =================================================================== --- firmware/FTM/Lightpulser_interface/Basic_Version/Lightpulser_interface_Basic.vhd (revision 10855) +++ firmware/FTM/Lightpulser_interface/Basic_Version/Lightpulser_interface_Basic.vhd (revision 10855) @@ -0,0 +1,290 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: Patrick Vogler +-- +-- Create Date: 24 February 2010 +-- Design Name: +-- Module Name: FTM Lightpulser interface +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: Interface to the lightpulsers LP1 (in the mirror dish) +-- and LP2 (inside the shutter) +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- +-- modifications: May 13 2011 +-- +-- Version 2 +-- +-- +-- modified: May 26 2011 +-- by Patrick Vogler +-- "Lightpulser Basic Version" +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +library ftm_definitions; +USE ftm_definitions.ftm_array_types.all; +USE ftm_definitions.ftm_constants.all; + + + +entity Lightpulser_interface is + port( + +-- Clock +------------------------------------------------------------------------------- + clk_50 : IN STD_LOGIC; -- 50 MHz system clock +-- clk_250 : IN STD_LOGIC; -- 250 MHz system clock + +-- Lightpulser +-- RJ-45 connectors J13 or J12 on the FTM board +-- LVDS calibration outputs +-- on IO-Bank 0 +------------------------------------------------------------------------------- +-- connector J13 => Light Pulser 1 in the mirror dish + Cal_0_p : out STD_LOGIC := '0'; -- Feedback / pulse width modulation + Cal_0_n : out STD_LOGIC := '1'; + Cal_1_p : out STD_LOGIC := '0'; -- Pulse + Cal_1_n : out STD_LOGIC := '1'; + Cal_2_p : out STD_LOGIC := '0'; -- Gate_1_4_7 + Cal_2_n : out STD_LOGIC := '1'; + Cal_3_p : out STD_LOGIC := '0'; -- Gate_3_5_8 + Cal_3_n : out STD_LOGIC := '1'; + +-- connector J12 => Light Pulser 2 in the shutter + Cal_4_p : out STD_LOGIC := '0'; -- Feedback / pulse width modulation + Cal_4_n : out STD_LOGIC := '1'; + Cal_5_p : out STD_LOGIC := '0'; -- Pulse + Cal_5_n : out STD_LOGIC := '1'; + Cal_6_p : out STD_LOGIC := '0'; -- Gate_1_4_7 + Cal_6_n : out STD_LOGIC := '1'; + Cal_7_p : out STD_LOGIC := '0'; -- Gate_3_5_8 + Cal_7_n : out STD_LOGIC := '1'; + + +-- FPGA intern signals: Lightpulser brightness +------------------------------------------------------------------------------- + + LP1_ampl : in std_logic_vector (15 downto 0); + LP2_ampl : in std_logic_vector (15 downto 0); + +-- LP1_delay : in std_logic_vector (15 downto 0); +-- LP2_delay : in std_logic_vector (15 downto 0); + + + LP1_pulse : in std_logic; -- trigger lightpulse in the mirror dish + LP2_pulse : in std_logic; -- trigger lightpulse in the shutter + + + start_config : in std_logic; -- handshaking + config_started : out std_logic := '0'; + config_done : out std_logic := '0' + + ); +end Lightpulser_interface; + + +architecture Behavioral of Lightpulser_interface is + + + +component FM_pulse_generator_Basic is + port( + clk : in std_logic; -- 50 MHz + pulse_freq : in std_logic_vector (5 downto 0); + FM_out : out std_logic := '0' + ); +end component; + + + component single_LP_Basic is + port( + clk_50 : in STD_LOGIC; + LP_Pulse_out : out STD_LOGIC; + LP_pulse_in : in std_logic + ); +end component; + + + + + -- LP1: mirror dish + signal Cal_0_1 : STD_LOGIC := '0'; +-- signal Cal_1_1 : STD_LOGIC; + + -- LP2: shutter + signal Cal_0_2 : STD_LOGIC := '0'; +-- signal Cal_1_2 : STD_LOGIC; + + -- PWM for amplitude stabilization + signal PWM_sig_1 : std_logic := '0'; -- LP1: mirror dish + signal PWM_sig_2 : std_logic := '0'; -- LP2: shutter + + -- control data latch + signal LP1_ampl_sig : std_logic_vector (15 downto 0) := (others => '0'); + signal LP2_ampl_sig : std_logic_vector (15 downto 0) := (others => '0'); + + + type type_latch_state is (IDLE, COPY, CONFIGURED); + signal latch_state : type_latch_state := IDLE; + + + + + +begin + + +-- input latch +input_latch : process (clk_50) + begin + if rising_edge(clk_50) then + case latch_state is + + when IDLE => + if start_config = '1' then + config_done <= '0'; + config_started <= '1'; + latch_state <= COPY; + end if; + + when COPY => + LP1_ampl_sig <= LP1_ampl; + LP2_ampl_sig <= LP2_ampl; + -- LP1_delay_sig <= LP1_delay; + -- LP2_delay_sig <= LP2_delay; + latch_state <= CONFIGURED; + + when CONFIGURED => + config_started <= '0'; + config_done <= '1'; + latch_state <= IDLE; + + end case; + end if; +end process input_latch; + + + + Inst_LP1_mirror_dish:single_LP_Basic + port map ( + clk_50 => clk_50, + LP_Pulse_out => Cal_0_1, + LP_pulse_in => LP1_pulse + ); + + + Inst_LP2_shutter:single_LP_Basic + port map ( + clk_50 => clk_50, + LP_Pulse_out => Cal_0_2, + LP_pulse_in => LP2_pulse + ); + +Inst_LP1_FM_pulse_generator:FM_pulse_generator_Basic -- LP1: mirror dish + port map( + clk => clk_50, + pulse_freq => LP1_ampl_sig(5 downto 0), + FM_out => PWM_sig_1 + ); + + +Inst_LP2_FM_pulse_generator:FM_pulse_generator_Basic -- LP2: shutter + port map( + clk => clk_50, + pulse_freq => LP2_ampl_sig(5 downto 0), + FM_out => PWM_sig_2 + ); + + +-- Light Pulser 1 (in the mirror dish): differential output buffers + + OBUFDS_inst_Cal_0 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_0_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_0_n , -- Diff_n output (connect directly to top-level port) + I => Cal_0_1 -- Buffer input + ); + + OBUFDS_inst_Cal_1 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_1_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_1_n , -- Diff_n output (connect directly to top-level port) + I => PWM_sig_1 -- Buffer input + ); + + OBUFDS_inst_Cal_2 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_2_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_2_n , -- Diff_n output (connect directly to top-level port) + I => LP1_ampl_sig(14) -- Buffer input + ); + + OBUFDS_inst_Cal_3 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_3_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_3_n , -- Diff_n output (connect directly to top-level port) + I => LP1_ampl_sig(15) -- Buffer input + ); + + + +-- Light Pulser 2 (in the shutter): differential output buffers + + OBUFDS_inst_Cal_4 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_4_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_4_n , -- Diff_n output (connect directly to top-level port) + I => Cal_0_2 -- Buffer input + ); + + OBUFDS_inst_Cal_5 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_5_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_5_n , -- Diff_n output (connect directly to top-level port) + I => PWM_sig_2 -- Buffer input + ); + + OBUFDS_inst_Cal_6 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_6_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_6_n , -- Diff_n output (connect directly to top-level port) + I => LP2_ampl_sig(14) + ); + + OBUFDS_inst_Cal_7 : OBUFDS + generic map ( + IOSTANDARD => "DEFAULT") + port map ( O => Cal_7_p , -- Diff_p output (connect directly to top-level port) + OB => Cal_7_n , -- Diff_n output (connect directly to top-level port) + I => LP2_ampl_sig(15) -- Buffer input + ); + + +end Behavioral; + + Index: firmware/FTM/Lightpulser_interface/Basic_Version/single_LP_Basci_tb.vhd =================================================================== --- firmware/FTM/Lightpulser_interface/Basic_Version/single_LP_Basci_tb.vhd (revision 10855) +++ firmware/FTM/Lightpulser_interface/Basic_Version/single_LP_Basci_tb.vhd (revision 10855) @@ -0,0 +1,118 @@ +-------------------------------------------------------------------------------- +-- Company: IPP +-- Engineer: Patrick Vogler +-- +-- Create Date: 10:45:29 05/27/2011 +-- Design Name: +-- Module Name: /home/pavogler/ISDC_repos/firmware/FTM/Lightpulser_interface/Basic_Version//single_LP_Basci_tb.vhd +-- Project Name: Lightpulser_Basic +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: single_LP_Basic +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE ieee.numeric_std.ALL; + +ENTITY single_LP_Basci_tb IS +END single_LP_Basci_tb; + +ARCHITECTURE behavior OF single_LP_Basci_tb IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT single_LP_Basic + PORT( + clk_50 : IN std_logic; + LP_Pulse_out : OUT std_logic; + LP_pulse_in : IN std_logic + ); + END COMPONENT; + + + --Inputs + signal clk_50 : std_logic := '0'; + signal LP_pulse_in : std_logic := '0'; + + --Outputs + signal LP_Pulse_out : std_logic; + + -- Clock period definitions + constant clk_50_period : time := 20 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: single_LP_Basic PORT MAP ( + clk_50 => clk_50, + LP_Pulse_out => LP_Pulse_out, + LP_pulse_in => LP_pulse_in + ); + + -- Clock process definitions + clk_50_process :process + begin + clk_50 <= '0'; + wait for clk_50_period/2; + clk_50 <= '1'; + wait for clk_50_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100 ms. + -- wait for 100 ms; + + wait for clk_50_period*10; + + -- insert stimulus here + + LP_pulse_in <= '0'; -- init input + wait for clk_50_period*10; + + LP_pulse_in <= '1'; -- short 20ns pulse + wait for clk_50_period*1; + LP_pulse_in <= '0'; + wait for clk_50_period*10; + + + + LP_pulse_in <= '1'; -- 60ns pulse + wait for clk_50_period*3; + LP_pulse_in <= '0'; + wait for clk_50_period*10; + + + + LP_pulse_in <= '1'; -- long 200ns pulse + wait for clk_50_period*10; + LP_pulse_in <= '0'; + wait for clk_50_period*10; + + + + + + + wait; + end process; + +END; Index: firmware/FTM/Lightpulser_interface/Basic_Version/single_LP_Basic.vhd =================================================================== --- firmware/FTM/Lightpulser_interface/Basic_Version/single_LP_Basic.vhd (revision 10855) +++ firmware/FTM/Lightpulser_interface/Basic_Version/single_LP_Basic.vhd (revision 10855) @@ -0,0 +1,101 @@ +---------------------------------------------------------------------------------- +-- Company: ETH Zurich, Institute for Particle Physics +-- Engineer: Patrick Vogler +-- +-- Create Date: March 2 2010 +-- Design Name: +-- Module Name: FTM Lightpulser interface: single lightpulser +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: generates the signals to control a single lightpulser +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- +-- modifications: +-- +-- +-- +-- modified: May 26 2011 +-- by Patrick Vogler +-- "Lightpulser Basic Version" +-- +-- modified: May 27 2011 +-- by Patrick Vogler +---------------------------------------------------------------------------------- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + + +library ftm_definitions; +USE ftm_definitions.ftm_array_types.all; +USE ftm_definitions.ftm_constants.all; + + + +entity single_LP_Basic is + port( + +-- Clock +------------------------------------------------------------------------------- + clk_50 : IN STD_LOGIC; -- 50 MHz system clock +-- clk_250 : IN STD_LOGIC; -- 250 MHz system clock + +-- Lightpulser +------------------------------------------------------------------------------- + LP_Pulse_out : out STD_LOGIC :='0'; -- + + +-- FPGA intern signals: Lightpulser brightness +------------------------------------------------------------------------------- + LP_pulse_in : in std_logic -- trigger lightpulse + +-- LP_delay : in std_logic_vector (15 downto 0) + ); +end single_LP_Basic; + +architecture Behavioral of single_LP_Basic is + +signal LP_in_prev : STD_LOGIC := '0'; +signal Pulse_Flag : STD_LOGIC := '0'; + +begin + +single_LP_Basic_proc: process (clk_50) + +variable Y : integer range 0 to FLD_PULSE_LENGTH_BASIC; + +begin + + if rising_edge(clk_50) then + LP_in_prev <= LP_pulse_in; + + if ((LP_pulse_in = '1') and (LP_in_prev = '0')) then + Pulse_Flag <= '1'; + end if; + + if (Pulse_Flag = '1') then + if (Y < FLD_PULSE_LENGTH_BASIC) then + Y := Y + 1; + LP_Pulse_out <= '1'; + else + Y := 0; + LP_Pulse_out <= '0'; + Pulse_Flag <= '0'; + end if; + end if; + + end if; + +end process single_LP_Basic_proc; + +end Behavioral;