Ignore:
Timestamp:
May 27, 2011, 5:28:59 PM (9 years ago)
Author:
weitzel
Message:
FTM: new light pulser interface, new timing constraint in .ucf file 
File:
1 edited

Legend:

Unmodified
Added
Removed
  • firmware/FTM/ftm_board.ucf

    r10740 r10879  
    1111########################################################
    1212
    13 
    1413#Clock
    1514#######################################################
    16 NET clk LOC = Y14 | IOSTANDARD=LVCMOS33; # FPGA-CLK from oscillator U47
    17 
     15NET clk LOC = Y14 |IOSTANDARD=LVCMOS33; # FPGA-CLK from oscillator U47
    1816
    1917# Ethernet Interface
     
    2220#######################################################
    2321# data bus
    24 NET W_D<0>  LOC  = M22 | IOSTANDARD=LVCMOS33; # 16-bit data bus to W5300       
    25 NET W_D<1>  LOC  = L22 | IOSTANDARD=LVCMOS33; #
    26 NET W_D<2>  LOC  = K23 | IOSTANDARD=LVCMOS33; #
    27 NET W_D<3>  LOC  = K25 | IOSTANDARD=LVCMOS33; #
    28 NET W_D<4>  LOC  = K26 | IOSTANDARD=LVCMOS33; #
    29 NET W_D<5>  LOC  = J22 | IOSTANDARD=LVCMOS33; #
    30 NET W_D<6>  LOC  = J23 | IOSTANDARD=LVCMOS33; #         
    31 NET W_D<7>  LOC  = G23 | IOSTANDARD=LVCMOS33; #
    32 NET W_D<8>  LOC  = G24 | IOSTANDARD=LVCMOS33; #
    33 NET W_D<9>  LOC  = F24 | IOSTANDARD=LVCMOS33; #
    34 NET W_D<10> LOC  = F25 | IOSTANDARD=LVCMOS33; #
    35 NET W_D<11> LOC  = E24 | IOSTANDARD=LVCMOS33; #
    36 NET W_D<12> LOC  = E26 | IOSTANDARD=LVCMOS33; #
    37 NET W_D<13> LOC  = D24 | IOSTANDARD=LVCMOS33; #
    38 NET W_D<14> LOC  = D26 | IOSTANDARD=LVCMOS33; #
    39 NET W_D<15> LOC  = D25 | IOSTANDARD=LVCMOS33; #
    40 
     22NET W_D<0>  LOC  = M22 |IOSTANDARD=LVCMOS33; # 16-bit data bus to W5300
     23NET W_D<1>  LOC  = L22 |IOSTANDARD=LVCMOS33; #
     24NET W_D<2>  LOC  = K23 |IOSTANDARD=LVCMOS33; #
     25NET W_D<3>  LOC  = K25 |IOSTANDARD=LVCMOS33; #
     26NET W_D<4>  LOC  = K26 |IOSTANDARD=LVCMOS33; #
     27NET W_D<5>  LOC  = J22 |IOSTANDARD=LVCMOS33; #
     28NET W_D<6>  LOC  = J23 |IOSTANDARD=LVCMOS33; # 
     29NET W_D<7>  LOC  = G23 |IOSTANDARD=LVCMOS33; #
     30NET W_D<8>  LOC  = G24 |IOSTANDARD=LVCMOS33; #
     31NET W_D<9>  LOC  = F24 |IOSTANDARD=LVCMOS33; #
     32NET W_D<10> LOC  = F25 |IOSTANDARD=LVCMOS33; #
     33NET W_D<11> LOC  = E24 |IOSTANDARD=LVCMOS33; #
     34NET W_D<12> LOC  = E26 |IOSTANDARD=LVCMOS33; #
     35NET W_D<13> LOC  = D24 |IOSTANDARD=LVCMOS33; #
     36NET W_D<14> LOC  = D26 |IOSTANDARD=LVCMOS33; #
     37NET W_D<15> LOC  = D25 |IOSTANDARD=LVCMOS33; #
    4138# W5300 address bus
    42 NET W_A<0> LOC  = U18  | IOSTANDARD=LVCMOS33; # there is no real net W_A0 because
    43 NET W_A<1> LOC  = AA25 | IOSTANDARD=LVCMOS33; # the W5300 is operated in the 16-bit mode
    44 NET W_A<2> LOC  = AA24 | IOSTANDARD=LVCMOS33; # (see W5300 datasheet)
    45 NET W_A<3> LOC  = AA23 | IOSTANDARD=LVCMOS33; # -> W_A<0> assigned to unconnected pin
    46 NET W_A<4> LOC  = Y25  | IOSTANDARD=LVCMOS33; #
    47 NET W_A<5> LOC  = Y24  | IOSTANDARD=LVCMOS33; #
    48 NET W_A<6> LOC  = Y23  | IOSTANDARD=LVCMOS33; #
    49 NET W_A<7> LOC  = W23  | IOSTANDARD=LVCMOS33; #
    50 NET W_A<8> LOC  = V25  | IOSTANDARD=LVCMOS33; #
    51 NET W_A<9> LOC  = V24  | IOSTANDARD=LVCMOS33; #
    52 
     39NET W_A<0> LOC  = U18  |IOSTANDARD=LVCMOS33; # there is no real net W_A0 because
     40NET W_A<1> LOC  = AA25 |IOSTANDARD=LVCMOS33; # the W5300 is operated in the 16-bit mode
     41NET W_A<2> LOC  = AA24 |IOSTANDARD=LVCMOS33; #  (see W5300 datasheet)
     42NET W_A<3> LOC  = AA23 |IOSTANDARD=LVCMOS33; # -> W_A<0> assigned to unconnected pin
     43NET W_A<4> LOC  = Y25  |IOSTANDARD=LVCMOS33; #
     44NET W_A<5> LOC  = Y24  |IOSTANDARD=LVCMOS33; #
     45NET W_A<6> LOC  = Y23  |IOSTANDARD=LVCMOS33; #
     46NET W_A<7> LOC  = W23  |IOSTANDARD=LVCMOS33; #
     47NET W_A<8> LOC  = V25  |IOSTANDARD=LVCMOS33; #
     48NET W_A<9> LOC  = V24  |IOSTANDARD=LVCMOS33; #
    5349# W5300 control signals
    5450# the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17
    5551# W_CS is also routed to testpoint JP7
    56 NET W_CS    LOC  = T20  | IOSTANDARD=LVCMOS33; # W5300 chip select
    57 NET W_INT   LOC  = U22  | IOSTANDARD=LVCMOS33; # interrupt
    58 NET W_RD    LOC  = R20  | IOSTANDARD=LVCMOS33; # read
    59 NET W_WR    LOC  = P22  | IOSTANDARD=LVCMOS33; # write
    60 NET W_RES   LOC  = U23  | IOSTANDARD=LVCMOS33; # reset W5300 chip
    61 
     52NET W_CS    LOC  = T20  |IOSTANDARD=LVCMOS33; # W5300 chip select
     53NET W_INT   LOC  = U22  |IOSTANDARD=LVCMOS33; # interrupt
     54NET W_RD    LOC  = R20  |IOSTANDARD=LVCMOS33; # read
     55NET W_WR    LOC  = P22  |IOSTANDARD=LVCMOS33; # write
     56NET W_RES   LOC  = U23  |IOSTANDARD=LVCMOS33; # reset W5300 chip
    6257# W5300 buffer ready indicator
    6358# NET W_BRDY<0>   LOC  = AB26  | IOSTANDARD=LVCMOS33; #
     
    6560# NET W_BRDY<2>   LOC  = AC25  | IOSTANDARD=LVCMOS33; #
    6661# NET W_BRDY<3>   LOC  = AD26  | IOSTANDARD=LVCMOS33; #
    67 
    6862# W5300 associated testpoints
    6963# NET W_T<0>   LOC  = N21  | IOSTANDARD=LVCMOS33; #
     
    7266# NET W_T<3>   LOC  = R19  | IOSTANDARD=LVCMOS33; #
    7367
    74 
    7568# SPI Interface
    7669# connection to the EEPROM U36 (AL25L016M) and the temperature
     
    7972#######################################################
    8073# NET S_CLK  LOC  = U20  | IOSTANDARD=LVCMOS33;  # SPI clock
    81 
    8274# EEPROM
    8375# NET MOSI   LOC  = AA22 | IOSTANDARD=LVCMOS33;    # master out slave in
    8476# NET MISO   LOC  = V22  | IOSTANDARD=LVCMOS33;    # master in slave out
    8577# NET EE_CS  LOC  = G22  | IOSTANDARD=LVCMOS33;    # master out slave in
    86 
    8778# temperature sensors
    8879# NET SIO       LOC  = F22  | IOSTANDARD=LVCMOS33;  # serial IO
     
    9283# NET TS_CS<3>  LOC  = C26  | IOSTANDARD=LVCMOS33;  # temperature sensors chip select3
    9384
    94 
    9585# Trigger primitives inputs
    9686# on IO-Bank 2
     
    9888# crate 0
    9989# crate A
    100 NET Trig_Prim_A<0>  LOC  = AC6  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<0>       
    101 NET Trig_Prim_A<1>  LOC  = AD6  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<1>
    102 NET Trig_Prim_A<2>  LOC  = AF3  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<2>
    103 NET Trig_Prim_A<3>  LOC  = AE4  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<3>
    104 NET Trig_Prim_A<4>  LOC  = AE6  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<4>
    105 NET Trig_Prim_A<5>  LOC  = AE7  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<5>
    106 NET Trig_Prim_A<6>  LOC  = AE8  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<6>
    107 NET Trig_Prim_A<7>  LOC  = AC8  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<7>
    108 NET Trig_Prim_A<8>  LOC  = AC11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<8>
    109 NET Trig_Prim_A<9>  LOC  = AD11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<9>
    110 
     90NET Trig_Prim_A<0>  LOC  = AC6  |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<0>
     91NET Trig_Prim_A<1>  LOC  = AD6  |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<1>
     92NET Trig_Prim_A<2>  LOC  = AF3  |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<2>
     93NET Trig_Prim_A<3>  LOC  = AE4  |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<3>
     94NET Trig_Prim_A<4>  LOC  = AE6  |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<4>
     95NET Trig_Prim_A<5>  LOC  = AE7  |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<5>
     96NET Trig_Prim_A<6>  LOC  = AE8  |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<6>
     97NET Trig_Prim_A<7>  LOC  = AC8  |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<7>
     98NET Trig_Prim_A<8>  LOC  = AC11 |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<8>
     99NET Trig_Prim_A<9>  LOC  = AD11 |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<9>
    111100# crate 1
    112101# crate B
    113 NET Trig_Prim_B<0>  LOC  = AB16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<0>       
    114 NET Trig_Prim_B<1>  LOC  = AC15 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<1>
    115 NET Trig_Prim_B<2>  LOC  = AC16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<2>
    116 NET Trig_Prim_B<3>  LOC  = AE17 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<3>
    117 NET Trig_Prim_B<4>  LOC  = AD19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<4>
    118 NET Trig_Prim_B<5>  LOC  = AE19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<5>
    119 NET Trig_Prim_B<6>  LOC  = AE20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<6>
    120 NET Trig_Prim_B<7>  LOC  = AF20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<7>
    121 NET Trig_Prim_B<8>  LOC  = AD21 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<8>
    122 NET Trig_Prim_B<9>  LOC  = AE23 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<9>
    123 
     102NET Trig_Prim_B<0>  LOC  = AB16 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<0>
     103NET Trig_Prim_B<1>  LOC  = AC15 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<1>
     104NET Trig_Prim_B<2>  LOC  = AC16 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<2>
     105NET Trig_Prim_B<3>  LOC  = AE17 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<3>
     106NET Trig_Prim_B<4>  LOC  = AD19 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<4>
     107NET Trig_Prim_B<5>  LOC  = AE19 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<5>
     108NET Trig_Prim_B<6>  LOC  = AE20 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<6>
     109NET Trig_Prim_B<7>  LOC  = AF20 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<7>
     110NET Trig_Prim_B<8>  LOC  = AD21 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<8>
     111NET Trig_Prim_B<9>  LOC  = AE23 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<9>
    124112# crate 2
    125113# crate C
    126 NET Trig_Prim_C<0>  LOC  = AF23 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<0>       
    127 NET Trig_Prim_C<1>  LOC  = AC21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<1>
    128 NET Trig_Prim_C<2>  LOC  = AE21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<2>
    129 NET Trig_Prim_C<3>  LOC  = AD20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<3>
    130 NET Trig_Prim_C<4>  LOC  = AC20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<4>
    131 NET Trig_Prim_C<5>  LOC  = AF19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<5>
    132 NET Trig_Prim_C<6>  LOC  = AC19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<6>
    133 NET Trig_Prim_C<7>  LOC  = AD17 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<7>
    134 NET Trig_Prim_C<8>  LOC  = AD14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<8>
    135 NET Trig_Prim_C<9>  LOC  = AC14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<9>
    136 
     114NET Trig_Prim_C<0>  LOC  = AF23 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<0>
     115NET Trig_Prim_C<1>  LOC  = AC21 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<1>
     116NET Trig_Prim_C<2>  LOC  = AE21 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<2>
     117NET Trig_Prim_C<3>  LOC  = AD20 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<3>
     118NET Trig_Prim_C<4>  LOC  = AC20 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<4>
     119NET Trig_Prim_C<5>  LOC  = AF19 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<5>
     120NET Trig_Prim_C<6>  LOC  = AC19 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<6>
     121NET Trig_Prim_C<7>  LOC  = AD17 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<7>
     122NET Trig_Prim_C<8>  LOC  = AD14 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<8>
     123NET Trig_Prim_C<9>  LOC  = AC14 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<9>
    137124# crate 3
    138125# crate D
    139 NET Trig_Prim_D<0>  LOC  = AB12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<0>       
    140 NET Trig_Prim_D<1>  LOC  = AC12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<1>
    141 NET Trig_Prim_D<2>  LOC  = AC9  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<2>
    142 NET Trig_Prim_D<3>  LOC  = AB9  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<3>
    143 NET Trig_Prim_D<4>  LOC  = AB7  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<4>
    144 NET Trig_Prim_D<5>  LOC  = AF8  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<5>
    145 NET Trig_Prim_D<6>  LOC  = AF4  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<6>
    146 NET Trig_Prim_D<7>  LOC  = AF5  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<7>
    147 NET Trig_Prim_D<8>  LOC  = AD7  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<8>
    148 NET Trig_Prim_D<9>  LOC  = AE3  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<9>
    149 
     126NET Trig_Prim_D<0>  LOC  = AB12 |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<0>
     127NET Trig_Prim_D<1>  LOC  = AC12 |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<1>
     128NET Trig_Prim_D<2>  LOC  = AC9  |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<2>
     129NET Trig_Prim_D<3>  LOC  = AB9  |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<3>
     130NET Trig_Prim_D<4>  LOC  = AB7  |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<4>
     131NET Trig_Prim_D<5>  LOC  = AF8  |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<5>
     132NET Trig_Prim_D<6>  LOC  = AF4  |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<6>
     133NET Trig_Prim_D<7>  LOC  = AF5  |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<7>
     134NET Trig_Prim_D<8>  LOC  = AD7  |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<8>
     135NET Trig_Prim_D<9>  LOC  = AE3  |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<9>
    150136
    151137# NIM inputs
    152138#######################################################
    153139# on IO-Bank 3
    154 NET ext_Trig<1>  LOC  = B1  | IOSTANDARD=LVCMOS33; #   
    155 NET ext_Trig<2>  LOC  = B2  | IOSTANDARD=LVCMOS33; #
    156 NET Veto         LOC  = E4  | IOSTANDARD=LVCMOS33; #
     140NET ext_Trig<1>  LOC  = B1  |IOSTANDARD=LVCMOS33; #     
     141NET ext_Trig<2>  LOC  = B2  |IOSTANDARD=LVCMOS33; #
     142NET Veto         LOC  = E4  |IOSTANDARD=LVCMOS33; #
    157143# NET NIM_In<0>    LOC  = D3  | IOSTANDARD=LVCMOS33; #
    158144# NET NIM_In<1>    LOC  = F4  | IOSTANDARD=LVCMOS33; #
    159145# NET NIM_In<2>    LOC  = E3  | IOSTANDARD=LVCMOS33; #
    160 
    161146# on IO-Bank 0
    162147# input pin with global clock buffer available
    163148# NET NIM_In3_GCLK  LOC  = K14  | IOSTANDARD=LVCMOS33;
    164149
    165 
    166150# LEDs
    167151# on IO-Banks 0 and 3
    168152#######################################################
    169153# red
    170 NET LED_red<0>  LOC  = D6  | IOSTANDARD=LVCMOS33; # IO-Bank 0   
    171 NET LED_red<1>  LOC  = A4  | IOSTANDARD=LVCMOS33; # IO-Bank 0   
    172 NET LED_red<2>  LOC  = E1  | IOSTANDARD=LVCMOS33; # IO-Bank 3   
    173 NET LED_red<3>  LOC  = J5  | IOSTANDARD=LVCMOS33; # IO-Bank 3   
    174 
     154NET LED_red<0>  LOC  = D6  |IOSTANDARD=LVCMOS33; # IO-Bank 0   
     155NET LED_red<1>  LOC  = A4  |IOSTANDARD=LVCMOS33; # IO-Bank 0   
     156NET LED_red<2>  LOC  = E1  |IOSTANDARD=LVCMOS33; # IO-Bank 3   
     157NET LED_red<3>  LOC  = J5  |IOSTANDARD=LVCMOS33; # IO-Bank 3   
    175158# yellow
    176 NET LED_ye<0>   LOC  = C5  | IOSTANDARD=LVCMOS33; # IO-Bank 0   
    177 NET LED_ye<1>   LOC  = B3  | IOSTANDARD=LVCMOS33; # IO-Bank 0
    178 
     159NET LED_ye<0>   LOC  = C5  |IOSTANDARD=LVCMOS33; # IO-Bank 0   
     160NET LED_ye<1>   LOC  = B3  |IOSTANDARD=LVCMOS33; # IO-Bank 0
    179161# green
    180 NET LED_gn<0>   LOC  = B4  | IOSTANDARD=LVCMOS33; # IO-Bank 0   
    181 NET LED_gn<1>   LOC  = A3  | IOSTANDARD=LVCMOS33; # IO-Bank 0
    182 
     162NET LED_gn<0>   LOC  = B4  |IOSTANDARD=LVCMOS33; # IO-Bank 0   
     163NET LED_gn<1>   LOC  = A3  |IOSTANDARD=LVCMOS33; # IO-Bank 0
    183164
    184165# Clock conditioner LMK03000
    185166# on IO-Bank 3
    186167#######################################################
    187 NET CLK_Clk_Cond    LOC  = G4  | IOSTANDARD=LVCMOS33; # IO-Bank 3
    188 NET LE_Clk_Cond     LOC  = F2  | IOSTANDARD=LVCMOS33; # IO-Bank 3
    189 NET LD_Clk_Cond     LOC  = J4  | IOSTANDARD=LVCMOS33; # IO-Bank 3
    190 NET DATA_Clk_Cond   LOC  = F3  | IOSTANDARD=LVCMOS33; # IO-Bank 3
    191 NET SYNC_Clk_Cond   LOC  = H2  | IOSTANDARD=LVCMOS33; # IO-Bank 3
    192 
     168NET CLK_Clk_Cond    LOC  = G4  |IOSTANDARD=LVCMOS33; # IO-Bank 3
     169NET LE_Clk_Cond     LOC  = F2  |IOSTANDARD=LVCMOS33; # IO-Bank 3
     170NET LD_Clk_Cond     LOC  = J4  |IOSTANDARD=LVCMOS33; # IO-Bank 3
     171NET DATA_Clk_Cond   LOC  = F3  |IOSTANDARD=LVCMOS33; # IO-Bank 3
     172NET SYNC_Clk_Cond   LOC  = H2  |IOSTANDARD=LVCMOS33; # IO-Bank 3
    193173
    194174# various RS-485 Interfaces
     
    196176#######################################################
    197177# Bus 1: FTU slow control
    198 NET Bus1_Tx_En   LOC  = H1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    199 NET Bus1_Rx_En   LOC  = G3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    200 
     178NET Bus1_Tx_En   LOC  = H1  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     179NET Bus1_Rx_En   LOC  = G3  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
    201180# crate 0
    202 NET Bus1_RxD_0   LOC  = K3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    203 NET Bus1_TxD_0   LOC  = L3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    204 
     181NET Bus1_RxD_0   LOC  = K3  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     182NET Bus1_TxD_0   LOC  = L3  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
    205183# crate 1
    206 NET Bus1_RxD_1   LOC  = M2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    207 NET Bus1_TxD_1   LOC  = N4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    208 
     184NET Bus1_RxD_1   LOC  = M2  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     185NET Bus1_TxD_1   LOC  = N4  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
    209186# crate 2
    210 NET Bus1_RxD_2   LOC  = P3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    211 NET Bus1_TxD_2   LOC  = P4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    212 
     187NET Bus1_RxD_2   LOC  = P3  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     188NET Bus1_TxD_2   LOC  = P4  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
    213189# crate 3
    214 NET Bus1_RxD_3   LOC  = T4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    215 NET Bus1_TxD_3   LOC  = T3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    216 
     190NET Bus1_RxD_3   LOC  = T4  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     191NET Bus1_TxD_3   LOC  = T3  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
    217192
    218193# Bus 2: Trigger-ID to FAD boards
    219 NET Bus2_Tx_En   LOC  = K2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    220 NET Bus2_Rx_En   LOC  = K4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    221 
     194NET Bus2_Tx_En   LOC  = K2  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     195NET Bus2_Rx_En   LOC  = K4  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
    222196# crate 0
    223 NET Bus2_RxD_0   LOC  = L4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    224 NET Bus2_TxD_0   LOC  = M3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    225 
     197NET Bus2_RxD_0   LOC  = L4  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     198NET Bus2_TxD_0   LOC  = M3  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
    226199# crate 1
    227 NET Bus2_RxD_1   LOC  = N2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    228 NET Bus2_TxD_1   LOC  = N1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    229 
     200NET Bus2_RxD_1   LOC  = N2  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     201NET Bus2_TxD_1   LOC  = N1  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
    230202# crate 2
    231 NET Bus2_RxD_2   LOC  = R2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    232 NET Bus2_TxD_2   LOC  = R1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    233 
     203NET Bus2_RxD_2   LOC  = R2  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     204NET Bus2_TxD_2   LOC  = R1  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
    234205# crate 3
    235 NET Bus2_RxD_3   LOC  = U4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    236 NET Bus2_TxD_3   LOC  = U2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    237 
     206NET Bus2_RxD_3   LOC  = U4  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     207NET Bus2_TxD_3   LOC  = U2  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
    238208
    239209# auxiliary access
     
    242212# NET Aux_Rx_En    LOC  = W4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # Rx- and Tx enable
    243213# NET Aux_Tx_En    LOC  = V1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary Trigger-ID
    244 
    245214# auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container)
    246215# NET TrID_Rx_D    LOC  = U6  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    247216# NET TrID_Tx_D    LOC  = T7  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    248217
    249 
    250218# Crate-Resets
    251219# on IO-Bank 3
    252220#######################################################
    253 NET Crate_Res0    LOC  = M1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    254 NET Crate_Res1    LOC  = P1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    255 NET Crate_Res2    LOC  = R3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    256 NET Crate_Res3    LOC  = V2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    257 
     221NET Crate_Res0    LOC  = M1  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     222NET Crate_Res1    LOC  = P1  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     223NET Crate_Res2    LOC  = R3  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     224NET Crate_Res3    LOC  = V2  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
    258225
    259226# Busy signals from the FAD boards
    260227# on IO-Bank 3
    261228#######################################################
    262 NET Busy0    LOC  = M4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    263 NET Busy1    LOC  = P2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    264 NET Busy2    LOC  = R4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    265 NET Busy3    LOC  = U1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
    266 
     229NET Busy0    LOC  = M4  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     230NET Busy1    LOC  = P2  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     231NET Busy2    LOC  = R4  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
     232NET Busy3    LOC  = U1  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
    267233
    268234# NIM outputs
     
    276242# NET Cal_NIM2_p   LOC  = B18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; #  Cal_NIM2+
    277243# NET Cal_NIM2_n   LOC  = A18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; #  Cal_NIM2-
    278 
    279244# auxiliarry / spare NIM outputs
    280245# NET NIM_Out0_p  LOC  = C17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; #  NIM_Out0+
     
    283248# NET NIM_Out1_n  LOC  = C16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out1-
    284249
    285 
    286250# fast control signal outputs
    287251# LVDS output at the FPGA followed by LVDS to NIM
    288252# conversion stage
    289253#######################################################
    290 # NET RES_p       LOC  = D16  | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES+ Reset
    291 # NET RES_n       LOC  = C15  | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES- IO-Bank 0
    292 
    293 NET TRG_p       LOC  = B15  | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG+ Trigger
    294 NET TRG_n       LOC  = A15  | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG- IO-Bank 0
    295 
    296 NET TIM_Run_p   LOC  = AF25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run+ Time Marker
    297 NET TIM_Run_n   LOC  = AE25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run- on IO-Bank2
    298 
    299 NET TIM_Sel     LOC  = AD22 | IOSTANDARD=LVCMOS33;  # Time Marker selector IO-Bank 2
    300 
     254NET RES_p       LOC  = D16  |IOSTANDARD=LVDS_33; # RES+ Reset
     255NET RES_n       LOC  = C15  |IOSTANDARD=LVDS_33; # RES- IO-Bank 0
     256NET TRG_p       LOC  = B15  |IOSTANDARD=LVDS_33; # TRG+ Trigger
     257NET TRG_n       LOC  = A15  |IOSTANDARD=LVDS_33; # TRG- IO-Bank 0
     258NET TIM_Run_p   LOC  = AF25 |IOSTANDARD=LVDS_33; # TIM_Run+ Time Marker
     259NET TIM_Run_n   LOC  = AE25 |IOSTANDARD=LVDS_33; # TIM_Run- on IO-Bank2
     260NET TIM_Sel     LOC  = AD22 |IOSTANDARD=LVCMOS33;  # Time Marker selector IO-Bank 2
    301261# NET CLD_FPGA    LOC  = AA14 | IOSTANDARD=LVCMOS33;  # DRS-Clock feedback into FPGA
    302 
    303262
    304263# LVDS calibration outputs
     
    306265#######################################################
    307266# to connector J13
    308 # NET Cal_0_p   LOC  = D22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0+
    309 # NET Cal_0_n   LOC  = C22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0-
    310 # NET Cal_1_p   LOC  = D23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1+
    311 # NET Cal_1_n   LOC  = C23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1-
    312 # NET Cal_2_p   LOC  = B23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2+
    313 # NET Cal_2_n   LOC  = A22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2-
    314 # NET Cal_3_p   LOC  = C21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3+
    315 # NET Cal_3_n   LOC  = B21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3-
    316 
     267NET Cal_0_p   LOC  = D22 | IOSTANDARD=LVDS_33; # Cal_0+
     268NET Cal_0_n   LOC  = C22 | IOSTANDARD=LVDS_33; # Cal_0-
     269NET Cal_1_p   LOC  = D23 | IOSTANDARD=LVDS_33; # Cal_1+
     270NET Cal_1_n   LOC  = C23 | IOSTANDARD=LVDS_33; # Cal_1-
     271NET Cal_2_p   LOC  = B23 | IOSTANDARD=LVDS_33; # Cal_2+
     272NET Cal_2_n   LOC  = A22 | IOSTANDARD=LVDS_33; # Cal_2-
     273NET Cal_3_p   LOC  = C21 | IOSTANDARD=LVDS_33; # Cal_3+
     274NET Cal_3_n   LOC  = B21 | IOSTANDARD=LVDS_33; # Cal_3-
    317275# to connector J12
    318 # NET Cal_4_p   LOC  = E21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4+   
    319 # NET Cal_4_n   LOC  = D21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4-   
    320 # NET Cal_5_p   LOC  = D20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5+   
    321 # NET Cal_5_n   LOC  = C20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5-   
    322 # NET Cal_6_p   LOC  = B20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6+   
    323 # NET Cal_6_n   LOC  = A20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6-   
    324 # NET Cal_7_p   LOC  = B19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7+   
    325 # NET Cal_7_n   LOC  = A19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7-   
    326 
     276NET Cal_4_p   LOC  = E21 | IOSTANDARD=LVDS_33; # Cal_4+   
     277NET Cal_4_n   LOC  = D21 | IOSTANDARD=LVDS_33; # Cal_4-   
     278NET Cal_5_p   LOC  = D20 | IOSTANDARD=LVDS_33; # Cal_5+   
     279NET Cal_5_n   LOC  = C20 | IOSTANDARD=LVDS_33; # Cal_5-   
     280NET Cal_6_p   LOC  = B20 | IOSTANDARD=LVDS_33; # Cal_6+   
     281NET Cal_6_n   LOC  = A20 | IOSTANDARD=LVDS_33; # Cal_6-   
     282NET Cal_7_p   LOC  = B19 | IOSTANDARD=LVDS_33; # Cal_7+   
     283NET Cal_7_n   LOC  = A19 | IOSTANDARD=LVDS_33; # Cal_7-   
    327284
    328285# Testpoints
     
    330287# Connector T7
    331288# IO-Bank 0
    332 NET TP<0> LOC  = B14 | IOSTANDARD=LVCMOS33;  #
    333 NET TP<1> LOC  = A14 | IOSTANDARD=LVCMOS33;  #
    334 NET TP<2> LOC  = C13 | IOSTANDARD=LVCMOS33;  #
    335 NET TP<3> LOC  = B13 | IOSTANDARD=LVCMOS33;  #
    336 
     289NET TP<0> LOC  = B14 |IOSTANDARD=LVCMOS33;  #
     290NET TP<1> LOC  = A14 |IOSTANDARD=LVCMOS33;  #
     291NET TP<2> LOC  = C13 |IOSTANDARD=LVCMOS33;  #
     292NET TP<3> LOC  = B13 |IOSTANDARD=LVCMOS33;  #
    337293# Connector T10
    338294# IO-Bank 0
    339 NET TP<4> LOC  = D13 | IOSTANDARD=LVCMOS33;  #
    340 NET TP<5> LOC  = C12 | IOSTANDARD=LVCMOS33;  #
    341 NET TP<6> LOC  = B12 | IOSTANDARD=LVCMOS33;  #
    342 NET TP<7> LOC  = A12 | IOSTANDARD=LVCMOS33;  #
    343 
     295NET TP<4> LOC  = D13 |IOSTANDARD=LVCMOS33;  #
     296NET TP<5> LOC  = C12 |IOSTANDARD=LVCMOS33;  #
     297NET TP<6> LOC  = B12 |IOSTANDARD=LVCMOS33;  #
     298NET TP<7> LOC  = A12 |IOSTANDARD=LVCMOS33;  #
    344299# on Connector T12
    345300# IO-Bank 0
    346 NET TP<8> LOC  = D11 | IOSTANDARD=LVCMOS33;  #
    347 NET TP<9> LOC  = C11 | IOSTANDARD=LVCMOS33;  #
    348 
     301NET TP<8> LOC  = D11 |IOSTANDARD=LVCMOS33;  #
     302NET TP<9> LOC  = C11 |IOSTANDARD=LVCMOS33;  #
    349303# on Connector T14
    350304# IO-Bank 0
    351 NET TP<10> LOC  = D10 | IOSTANDARD=LVCMOS33;  #
    352 NET TP<11> LOC  = C10 | IOSTANDARD=LVCMOS33;  #
    353 NET TP<12> LOC  = A10 | IOSTANDARD=LVCMOS33;  #
    354 NET TP<13> LOC  = B10 | IOSTANDARD=LVCMOS33;  #
    355 
     305NET TP<10> LOC  = D10 |IOSTANDARD=LVCMOS33;  #
     306NET TP<11> LOC  = C10 |IOSTANDARD=LVCMOS33;  #
     307NET TP<12> LOC  = A10 |IOSTANDARD=LVCMOS33;  #
     308NET TP<13> LOC  = B10 |IOSTANDARD=LVCMOS33;  #
    356309# on Connector T16
    357310# IO-Bank 0
    358 NET TP<14> LOC  = A9 | IOSTANDARD=LVCMOS33;  #
    359 NET TP<15> LOC  = B9 | IOSTANDARD=LVCMOS33;  #
    360 NET TP<16> LOC  = A8 | IOSTANDARD=LVCMOS33;  #
    361 NET TP<17> LOC  = B8 | IOSTANDARD=LVCMOS33;  #
    362 
     311NET TP<14> LOC  = A9 |IOSTANDARD=LVCMOS33;  #
     312NET TP<15> LOC  = B9 |IOSTANDARD=LVCMOS33;  #
     313NET TP<16> LOC  = A8 |IOSTANDARD=LVCMOS33;  #
     314NET TP<17> LOC  = B8 |IOSTANDARD=LVCMOS33;  #
    363315# on Connector T8
    364316# IO-Bank 0
    365 NET TP<18> LOC  = C8 | IOSTANDARD=LVCMOS33;  #
    366 NET TP<19> LOC  = D8 | IOSTANDARD=LVCMOS33;  #
    367 NET TP<20> LOC  = C6 | IOSTANDARD=LVCMOS33;  #
    368 NET TP<21> LOC  = B6 | IOSTANDARD=LVCMOS33;  #
    369 
     317NET TP<18> LOC  = C8 |IOSTANDARD=LVCMOS33;  #
     318NET TP<19> LOC  = D8 |IOSTANDARD=LVCMOS33;  #
     319NET TP<20> LOC  = C6 |IOSTANDARD=LVCMOS33;  #
     320NET TP<21> LOC  = B6 |IOSTANDARD=LVCMOS33;  #
    370321# on Connector T9
    371322# IO-Bank 0
    372 NET TP<22> LOC  = C7 | IOSTANDARD=LVCMOS33;  #
    373 NET TP<23> LOC  = B7 | IOSTANDARD=LVCMOS33;  #
    374 
     323NET TP<22> LOC  = C7 |IOSTANDARD=LVCMOS33;  #
     324NET TP<23> LOC  = B7 |IOSTANDARD=LVCMOS33;  #
    375325# on Connector T11
    376326# IO-Bank 3
    377 NET TP<24> LOC  = Y1  | IOSTANDARD=LVCMOS33;  #
    378 NET TP<25> LOC  = AA3 | IOSTANDARD=LVCMOS33;  #
    379 NET TP<26> LOC  = AA2 | IOSTANDARD=LVCMOS33;  #
    380 NET TP<27> LOC  = AC1 | IOSTANDARD=LVCMOS33;  #
    381 
     327NET TP<24> LOC  = Y1  |IOSTANDARD=LVCMOS33;  #
     328NET TP<25> LOC  = AA3 |IOSTANDARD=LVCMOS33;  #
     329NET TP<26> LOC  = AA2 |IOSTANDARD=LVCMOS33;  #
     330NET TP<27> LOC  = AC1 |IOSTANDARD=LVCMOS33;  #
    382331# on Connector T13
    383332# IO-Bank 3
    384 NET TP<28> LOC  = AB1 | IOSTANDARD=LVCMOS33;  #
    385 NET TP<29> LOC  = AC3 | IOSTANDARD=LVCMOS33;  #
    386 NET TP<30> LOC  = AC2 | IOSTANDARD=LVCMOS33;  #
    387 NET TP<31> LOC  = AD2 | IOSTANDARD=LVCMOS33;  #
    388 
     333NET TP<28> LOC  = AB1 |IOSTANDARD=LVCMOS33;  #
     334NET TP<29> LOC  = AC3 |IOSTANDARD=LVCMOS33;  #
     335NET TP<30> LOC  = AC2 |IOSTANDARD=LVCMOS33;  #
     336NET TP<31> LOC  = AD2 |IOSTANDARD=LVCMOS33;  #
    389337# on Connector T15
    390 NET TP<32> LOC  = AD1 | IOSTANDARD=LVCMOS33;  # IO-Bank 3
     338NET TP<32> LOC  = AD1 |IOSTANDARD=LVCMOS33;  # IO-Bank 3
    391339# NET TP_in<33> LOC  = AE2 | IOSTANDARD=LVCMOS33;  # input only
    392340# NET TP_in<34> LOC  = AE1 | IOSTANDARD=LVCMOS33;  # input only
    393 
    394341
    395342# Board ID - inputs
     
    405352# NET brd_id<6> LOC  = H24 | IOSTANDARD=LVCMOS33; #
    406353# NET brd_id<7> LOC  = Y26 | IOSTANDARD=LVCMOS33; #
     354
     355NET "clk" TNM_NET = clk;
     356TIMESPEC TS_clk = PERIOD "clk" 25 ns HIGH 50%;
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