Index: firmware/FTM/FTM_central_control.vhd
===================================================================
--- firmware/FTM/FTM_central_control.vhd	(revision 10857)
+++ firmware/FTM/FTM_central_control.vhd	(revision 10879)
@@ -65,4 +65,7 @@
     config_started_cc    : in  std_logic;
     config_ready_cc      : in  std_logic;
+    config_start_lp      : out std_logic := '0';
+    config_started_lp    : in  std_logic;
+    config_ready_lp      : in  std_logic;
     config_trigger       : out  std_logic := '0';
     config_trigger_done  : in  std_logic;
@@ -110,4 +113,5 @@
                                    CP_CONFIG_START, CP_CONFIG, CP_CONFIG_01,
                                    CP_CONFIG_CC, CP_CONFIG_CC_01,
+                                   CP_CONFIG_LP, CP_CONFIG_LP_01,
                                    CP_CONFIG_FTU, CP_CONFIG_FTU_01,
                                    CP_CONFIG_SCALER, CP_CONFIG_SCALER_01,
@@ -194,4 +198,21 @@
           cc_state_test <= X"06";
           if (config_ready_cc = '1') then
+            state_central_proc <= CP_CONFIG_LP;
+            --state_central_proc <= CP_CONFIG_FTU;
+          end if;
+
+        when CP_CONFIG_LP =>
+          current_cc_state <= FTM_STATE_CFG;
+          cc_state_test <= X"1C";
+          config_start_lp <= '1';
+          if (config_started_lp = '1') then
+            config_start_lp <= '0';
+            state_central_proc <= CP_CONFIG_LP_01;
+          end if;
+          
+        when CP_CONFIG_LP_01 =>
+          current_cc_state <= FTM_STATE_CFG;
+          cc_state_test <= X"1D";
+          if (config_ready_lp = '1') then
             state_central_proc <= CP_CONFIG_FTU;
           end if;
Index: firmware/FTM/FTM_top.vhd
===================================================================
--- firmware/FTM/FTM_top.vhd	(revision 10857)
+++ firmware/FTM/FTM_top.vhd	(revision 10879)
@@ -212,6 +212,6 @@
     -- LVDS output at the FPGA followed by LVDS to NIM conversion stage
     -------------------------------------------------------------------------------
-    -- RES_p      : out STD_LOGIC;   --  RES+   Reset
-    -- RES_n      : out STD_LOGIC;   --  RES-  IO-Bank 0
+    RES_p      : out STD_LOGIC;   -- RES+  Reset
+    RES_n      : out STD_LOGIC;   -- RES-  IO-Bank 0
 
     TRG_p      : out STD_LOGIC;   -- TRG+  Trigger
@@ -230,23 +230,23 @@
     -- to connector J13
     -- for light pulsar in the mirror dish
-    -- Cal_0_p    : out STD_LOGIC;  
-    -- Cal_0_n    : out STD_LOGIC;
-    -- Cal_1_p    : out STD_LOGIC;
-    -- Cal_1_n    : out STD_LOGIC;
-    -- Cal_2_p    : out STD_LOGIC;
-    -- Cal_2_n    : out STD_LOGIC;
-    -- Cal_3_p    : out STD_LOGIC;
-    -- Cal_3_n    : out STD_LOGIC;
+    Cal_0_p    : out STD_LOGIC;  
+    Cal_0_n    : out STD_LOGIC;
+    Cal_1_p    : out STD_LOGIC;
+    Cal_1_n    : out STD_LOGIC;
+    Cal_2_p    : out STD_LOGIC;
+    Cal_2_n    : out STD_LOGIC;
+    Cal_3_p    : out STD_LOGIC;
+    Cal_3_n    : out STD_LOGIC;
 
     -- to connector J12
     -- for light pulsar inside shutter
-    -- Cal_4_p    : out STD_LOGIC;
-    -- Cal_4_n    : out STD_LOGIC;
-    -- Cal_5_p    : out STD_LOGIC;
-    -- Cal_5_n    : out STD_LOGIC;
-    -- Cal_6_p    : out STD_LOGIC;
-    -- Cal_6_n    : out STD_LOGIC; 
-    -- Cal_7_p    : out STD_LOGIC;
-    -- Cal_7_n    : out STD_LOGIC  
+    Cal_4_p    : out STD_LOGIC;
+    Cal_4_n    : out STD_LOGIC;
+    Cal_5_p    : out STD_LOGIC;
+    Cal_5_n    : out STD_LOGIC;
+    Cal_6_p    : out STD_LOGIC;
+    Cal_6_n    : out STD_LOGIC; 
+    Cal_7_p    : out STD_LOGIC;
+    Cal_7_n    : out STD_LOGIC;  
 
 
@@ -347,8 +347,12 @@
   signal trigger_counter_valid_sig  : std_logic;
   
-  signal config_start_cc_sig   : std_logic := '0';
+  signal config_start_cc_sig   : std_logic;  -- initialized in central control
   signal config_started_cc_sig : std_logic := '0';
   signal config_ready_cc_sig   : std_logic := '0';
 
+  signal config_start_lp_sig   : std_logic;  -- initialized in central control
+  signal config_started_lp_sig : std_logic;  -- initialized in light pulser interface
+  signal config_ready_lp_sig   : std_logic;  -- initialized in light pulser interface
+  
   signal config_trigger_sig : std_logic;
   signal config_trigger_done_sig : std_logic;
@@ -412,4 +416,7 @@
   signal crate_res3_sig : std_logic;  -- initialized in FTM_central_control
 
+  signal LP1_pulse_sig : std_logic := '0';
+  signal LP2_pulse_sig : std_logic := '0';
+  
 --  component FTM_clk_gen
 --    port(
@@ -557,4 +564,7 @@
       config_started_cc    : in  std_logic;
       config_ready_cc      : in  std_logic;
+      config_start_lp      : out std_logic := '0';
+      config_started_lp    : in  std_logic;
+      config_ready_lp      : in  std_logic;
       config_trigger       : out std_logic;
       config_trigger_done  : in  std_logic;
@@ -785,4 +795,35 @@
   end component;
 
+  component Lightpulser_interface_Basic is
+    port(
+      clk_50    : IN  STD_LOGIC;
+      --clk_250   : IN  STD_LOGIC;
+      Cal_0_p   : out STD_LOGIC := '0';
+      Cal_0_n   : out STD_LOGIC := '1';
+      Cal_1_p   : out STD_LOGIC := '0';
+      Cal_1_n   : out STD_LOGIC := '1';
+      Cal_2_p   : out STD_LOGIC := '0';
+      Cal_2_n   : out STD_LOGIC := '1';
+      Cal_3_p   : out STD_LOGIC := '0';
+      Cal_3_n   : out STD_LOGIC := '1';
+      Cal_4_p    : out STD_LOGIC := '0';
+      Cal_4_n    : out STD_LOGIC := '1';
+      Cal_5_p    : out STD_LOGIC := '0';
+      Cal_5_n    : out STD_LOGIC := '1';
+      Cal_6_p    : out STD_LOGIC := '0';
+      Cal_6_n    : out STD_LOGIC := '1'; 
+      Cal_7_p    : out STD_LOGIC := '0';
+      Cal_7_n    : out STD_LOGIC := '1';  
+      LP1_ampl       : in std_logic_vector (15 downto 0);
+      LP2_ampl       : in std_logic_vector (15 downto 0);
+      --LP1_delay      : in std_logic_vector (15 downto 0);
+      --LP2_delay      : in std_logic_vector (15 downto 0);
+      LP1_pulse      : in std_logic;
+      LP2_pulse      : in std_logic;
+      start_config   : in std_logic;
+      config_started : out std_logic := '0';
+      config_done    : out std_logic := '0' 
+    );
+  end component;
   
 begin
@@ -832,20 +873,28 @@
     );
   
-   --differential output buffer for trigger signal
-   OBUFDS_LVDS_33_TRG : OBUFDS_LVDS_33
-     port map(
-       O  => TRG_p,
-       OB => TRG_n,
-       I  => trigger_signal_sig
-     );
-
-   --differential output buffer for trigger signal
-   OBUFDS_LVDS_33_TIM : OBUFDS_LVDS_33
-     port map(
-       O  => TIM_Run_p,
-       OB => TIM_Run_n,
-       I  => TIM_signal_sig
-     );
-   
+  --differential output buffer for trigger signal
+  OBUFDS_LVDS_33_TRG : OBUFDS_LVDS_33
+    port map(
+      O  => TRG_p,
+      OB => TRG_n,
+      I  => trigger_signal_sig
+    );
+
+  --differential output buffer for TIM signal
+  OBUFDS_LVDS_33_TIM : OBUFDS_LVDS_33
+    port map(
+      O  => TIM_Run_p,
+      OB => TIM_Run_n,
+      I  => TIM_signal_sig
+    );
+
+  --differential output buffer for fast reset signal
+  OBUFDS_LVDS_33_RES : OBUFDS_LVDS_33
+    port map(
+      O  => RES_p,
+      OB => RES_n,
+      I  => '0'
+    );
+  
    Inst_trigger_manager : trigger_manager
      port map(
@@ -895,6 +944,6 @@
       trigger_active      => trigger_active_sig,  --phys triggers are enabled/active
       config_done         => config_trigger_done_sig,
-      LP1_pulse           => open,  --send start signal to light pulser 1
-      LP2_pulse           => open,  --send start signal to light pulser 2
+      LP1_pulse           => LP1_pulse_sig,  --send start signal to light pulser 1
+      LP2_pulse           => LP2_pulse_sig,  --send start signal to light pulser 2
       --trigger and time marker output signals to FADs
       trigger_signal      => trigger_signal_sig,
@@ -958,4 +1007,7 @@
       config_started_cc    => config_started_cc_sig,
       config_ready_cc      => config_ready_cc_sig,
+      config_start_lp      => config_start_lp_sig,
+      config_started_lp    => config_started_lp_sig,
+      config_ready_lp      => config_ready_lp_sig,
       config_trigger       => config_trigger_sig,
       config_trigger_done  => config_trigger_done_sig,
@@ -1199,4 +1251,35 @@
       counter_reading     => on_time_counter_sig
     );
+
+  Inst_Lightpulser_interface_Basic : Lightpulser_interface_Basic
+    port map (
+      clk_50         => clk_50M_sig,
+      --clk_250        => clk_250M_sig,
+      Cal_0_p        => Cal_0_p,
+      Cal_0_n        => Cal_0_n,
+      Cal_1_p        => Cal_1_p,
+      Cal_1_n        => Cal_1_n,
+      Cal_2_p        => Cal_2_p,
+      Cal_2_n        => Cal_2_n,
+      Cal_3_p        => Cal_3_p,
+      Cal_3_n        => Cal_3_n,
+      Cal_4_p        => Cal_4_p,
+      Cal_4_n        => Cal_4_n,
+      Cal_5_p        => Cal_5_p,
+      Cal_5_n        => Cal_5_n,
+      Cal_6_p        => Cal_6_p,
+      Cal_6_n        => Cal_6_n,
+      Cal_7_p        => Cal_7_p,
+      Cal_7_n        => Cal_7_n,
+      LP1_ampl       => lp1_amplitude_sig,
+      LP2_ampl       => lp2_amplitude_sig,
+      --LP1_delay      => lp1_delay_sig,
+      --LP2_delay      => lp2_delay_sig,
+      LP1_pulse      => LP1_pulse_sig,
+      LP2_pulse      => LP2_pulse_sig,
+      start_config   => config_start_lp_sig,
+      config_started => config_started_lp_sig,
+      config_done    => config_ready_lp_sig
+    );
   
   LED_red <= led_sig(3 downto 0);
Index: firmware/FTM/FTM_top_tb.vhd
===================================================================
--- firmware/FTM/FTM_top_tb.vhd	(revision 10857)
+++ firmware/FTM/FTM_top_tb.vhd	(revision 10879)
@@ -208,6 +208,6 @@
       -- LVDS output at the FPGA followed by LVDS to NIM conversion stage
       -------------------------------------------------------------------------------
---      RES_p      : out STD_LOGIC;   --  RES+   Reset
---      RES_n      : out STD_LOGIC;   --  RES-
+      RES_p      : out STD_LOGIC;   --  RES+   Reset
+      RES_n      : out STD_LOGIC;   --  RES-
 
       TRG_p      : out STD_LOGIC;   -- TRG+  Trigger
@@ -216,5 +216,5 @@
       TIM_Run_p  : out STD_LOGIC;   -- TIM_Run+  Time Marker
       TIM_Run_n  : out STD_LOGIC;   -- TIM_Run-
---      TIM_Sel    : out STD_LOGIC;   -- Time Marker selector
+      TIM_Sel    : out STD_LOGIC;   -- Time Marker selector
                                                     
       -- CLD_FPGA   : in STD_LOGIC;    -- DRS-Clock feedback into FPGA
@@ -225,23 +225,23 @@
       -- to connector J13
       -- for light pulsar in the mirror dish
---      Cal_0_p    : out STD_LOGIC;  
---      Cal_0_n    : out STD_LOGIC;
---      Cal_1_p    : out STD_LOGIC;
---      Cal_1_n    : out STD_LOGIC;
---      Cal_2_p    : out STD_LOGIC;
---      Cal_2_n    : out STD_LOGIC;
---      Cal_3_p    : out STD_LOGIC;
---      Cal_3_n    : out STD_LOGIC;
+      Cal_0_p    : out STD_LOGIC;  
+      Cal_0_n    : out STD_LOGIC;
+      Cal_1_p    : out STD_LOGIC;
+      Cal_1_n    : out STD_LOGIC;
+      Cal_2_p    : out STD_LOGIC;
+      Cal_2_n    : out STD_LOGIC;
+      Cal_3_p    : out STD_LOGIC;
+      Cal_3_n    : out STD_LOGIC;
 
       -- to connector J12
       -- for light pulsar inside shutter
---      Cal_4_p    : out STD_LOGIC;
---      Cal_4_n    : out STD_LOGIC;
---      Cal_5_p    : out STD_LOGIC;
---      Cal_5_n    : out STD_LOGIC;
---      Cal_6_p    : out STD_LOGIC;
---      Cal_6_n    : out STD_LOGIC; 
---      Cal_7_p    : out STD_LOGIC;
---      Cal_7_n    : out STD_LOGIC  
+      Cal_4_p    : out STD_LOGIC;
+      Cal_4_n    : out STD_LOGIC;
+      Cal_5_p    : out STD_LOGIC;
+      Cal_5_n    : out STD_LOGIC;
+      Cal_6_p    : out STD_LOGIC;
+      Cal_6_n    : out STD_LOGIC; 
+      Cal_7_p    : out STD_LOGIC;
+      Cal_7_n    : out STD_LOGIC;  
 
 
@@ -414,27 +414,27 @@
       Busy2         => Busy2_sig,
       Busy3         => Busy3_sig,
---      RES_p         => RES_p_sig,
---      RES_n         => RES_n_sig,
+      RES_p         => RES_p_sig,
+      RES_n         => RES_n_sig,
       TRG_p         => TRG_p_sig,
       TRG_n         => TRG_n_sig,
       TIM_Run_p     => TIM_Run_p_sig,
       TIM_Run_n     => TIM_Run_n_sig,
---      TIM_Sel       => TIM_Sel_sig,
---      Cal_0_p       => Cal_0_p_sig,  
---      Cal_0_n       => Cal_0_n_sig,
---      Cal_1_p       => Cal_1_p_sig,
---      Cal_1_n       => Cal_1_n_sig,
---      Cal_2_p       => Cal_2_p_sig,
---      Cal_2_n       => Cal_2_n_sig,
---      Cal_3_p       => Cal_3_p_sig,
---      Cal_3_n       => Cal_3_n_sig,
---      Cal_4_p       => Cal_4_p_sig,
---      Cal_4_n       => Cal_4_n_sig,
---      Cal_5_p       => Cal_5_p_sig,
---      Cal_5_n       => Cal_5_n_sig,
---      Cal_6_p       => Cal_6_p_sig,
---      Cal_6_n       => Cal_6_n_sig, 
---      Cal_7_p       => Cal_7_p_sig,
---      Cal_7_n       => Cal_7_n_sig,
+      TIM_Sel       => TIM_Sel_sig,
+      Cal_0_p       => Cal_0_p_sig,  
+      Cal_0_n       => Cal_0_n_sig,
+      Cal_1_p       => Cal_1_p_sig,
+      Cal_1_n       => Cal_1_n_sig,
+      Cal_2_p       => Cal_2_p_sig,
+      Cal_2_n       => Cal_2_n_sig,
+      Cal_3_p       => Cal_3_p_sig,
+      Cal_3_n       => Cal_3_n_sig,
+      Cal_4_p       => Cal_4_p_sig,
+      Cal_4_n       => Cal_4_n_sig,
+      Cal_5_p       => Cal_5_p_sig,
+      Cal_5_n       => Cal_5_n_sig,
+      Cal_6_p       => Cal_6_p_sig,
+      Cal_6_n       => Cal_6_n_sig, 
+      Cal_7_p       => Cal_7_p_sig,
+      Cal_7_n       => Cal_7_n_sig,
       TP            => TP_sig
     );
Index: firmware/FTM/Lightpulser_interface/Basic_Version/FM_pulse_generator_Basic.vhd
===================================================================
--- firmware/FTM/Lightpulser_interface/Basic_Version/FM_pulse_generator_Basic.vhd	(revision 10857)
+++ firmware/FTM/Lightpulser_interface/Basic_Version/FM_pulse_generator_Basic.vhd	(revision 10879)
@@ -11,4 +11,9 @@
 --               by Patrick Vogler
 --               "Lightpulser Basic Version"
+--
+-- modified:     May 27 2011
+--               by Patrick Vogler, Quirin Weitzel
+--               -> clean up
+
 
 LIBRARY ieee;
@@ -24,5 +29,5 @@
 ENTITY FM_pulse_generator_Basic IS
    GENERIC( 
-      pulse_length : integer := FLD_PULSE_LENGTH   -- 48ns                                                               
+      pulse_length : integer := FLD_PULSE_LENGTH_BASIC   -- 60ns                                                               
          );
    PORT( 
@@ -52,10 +57,10 @@
                       Z := Z + 1;
                   else 
-                      Z := - FLD_MIN_FREQ_DIV;
+                      Z := - FLD_MIN_FREQ_DIV_BASIC;
                       Y := 0;
                   end if;		  
         end if;   
 
-      if (Y < FLD_PULSE_LENGTH_BASIC) then 
+      if (Y < pulse_length) then 
         Y := Y + 1;
         FM_out <= '1';
Index: firmware/FTM/Lightpulser_interface/Basic_Version/Lightpulser_interface_Basic.vhd
===================================================================
--- firmware/FTM/Lightpulser_interface/Basic_Version/Lightpulser_interface_Basic.vhd	(revision 10857)
+++ firmware/FTM/Lightpulser_interface/Basic_Version/Lightpulser_interface_Basic.vhd	(revision 10879)
@@ -5,5 +5,5 @@
 -- Create Date:    24 February 2010
 -- Design Name:    
--- Module Name:    FTM Lightpulser interface  
+-- Module Name:    FTM Lightpulser interface Basic 
 -- Project Name: 
 -- Target Devices: 
@@ -28,4 +28,8 @@
 --               "Lightpulser Basic Version"
 --
+-- modified:     May 27 2011
+--               by Patrick Vogler, Quirin Weitzel
+--               -> clean up
+--
 ----------------------------------------------------------------------------------
 
@@ -45,6 +49,5 @@
 
 
-
-entity Lightpulser_interface is
+entity Lightpulser_interface_Basic is
   port(
     
@@ -99,60 +102,54 @@
    
   );
-end Lightpulser_interface;
-
-
-architecture Behavioral of Lightpulser_interface is
-
+end Lightpulser_interface_Basic;
+
+
+architecture Behavioral of Lightpulser_interface_Basic is
 
 
 component FM_pulse_generator_Basic is
-   port( 
-      clk            : in  std_logic;    -- 50 MHz
-      pulse_freq     : in  std_logic_vector (5 downto 0);
-      FM_out         : out std_logic  := '0'
-         );
+  port( 
+    clk            : in  std_logic;    -- 50 MHz
+    pulse_freq     : in  std_logic_vector (5 downto 0);
+    FM_out         : out std_logic  := '0'
+  );
 end component;
 
 
-  component single_LP_Basic is
+component single_LP_Basic is
   port(  
-   clk_50         : in  STD_LOGIC;       
-   LP_Pulse_out    : out STD_LOGIC;                                                 
-   LP_pulse_in     : in std_logic  
-   );
+    clk_50         : in  STD_LOGIC;       
+    LP_Pulse_out   : out STD_LOGIC;                                                 
+    LP_pulse_in    : in  std_logic  
+  );
 end component;
 
 
-
-
-  -- LP1: mirror dish
-  signal Cal_0_1 : STD_LOGIC := '0';  
+-- LP1: mirror dish
+signal Cal_0_1 : STD_LOGIC := '0';  
 --  signal Cal_1_1 : STD_LOGIC;
 
-  -- LP2: shutter
-  signal Cal_0_2 : STD_LOGIC := '0';
+-- LP2: shutter
+signal Cal_0_2 : STD_LOGIC := '0';
 --  signal Cal_1_2 : STD_LOGIC;
 
- -- PWM for amplitude stabilization
-  signal PWM_sig_1 : std_logic := '0';  -- LP1: mirror dish
-  signal PWM_sig_2 : std_logic := '0';  -- LP2: shutter
-
-  -- control data latch
-  signal LP1_ampl_sig   :  std_logic_vector (15 downto 0) := (others => '0');
-  signal LP2_ampl_sig   :  std_logic_vector (15 downto 0) := (others => '0'); 
+-- PWM for amplitude stabilization
+signal PWM_sig_1 : std_logic := '0';  -- LP1: mirror dish
+signal PWM_sig_2 : std_logic := '0';  -- LP2: shutter
+
+-- control data latch
+signal LP1_ampl_sig   :  std_logic_vector (15 downto 0) := (others => '0');
+signal LP2_ampl_sig   :  std_logic_vector (15 downto 0) := (others => '0'); 
  
 
-  type type_latch_state is (IDLE, COPY, CONFIGURED);   
-  signal latch_state       : type_latch_state  := IDLE;   
-  
-
-
-
+type type_latch_state is (IDLE, COPY, CONFIGURED);   
+signal latch_state : type_latch_state  := IDLE;   
+  
 
 begin
   
 
--- input latch
-input_latch : process (clk_50)
+  -- input latch
+  input_latch : process (clk_50)
   begin
     if rising_edge(clk_50) then
@@ -180,111 +177,108 @@
        end case;           
     end if;  
-end process input_latch; 
+  end process input_latch; 
 	  	 
-
   
   Inst_LP1_mirror_dish:single_LP_Basic
     port map (
-        clk_50        => clk_50,    
-        LP_Pulse_out  => Cal_0_1,                                     
-        LP_pulse_in   => LP1_pulse               
-              );
-
-  
-    Inst_LP2_shutter:single_LP_Basic
+      clk_50        => clk_50,    
+      LP_Pulse_out  => Cal_0_1,                                     
+      LP_pulse_in   => LP1_pulse               
+      );
+
+  
+  Inst_LP2_shutter:single_LP_Basic
     port map (
-        clk_50        => clk_50,    
-        LP_Pulse_out  => Cal_0_2,                                     
-        LP_pulse_in   => LP2_pulse               
-          );
-
-Inst_LP1_FM_pulse_generator:FM_pulse_generator_Basic    -- LP1: mirror dish
-   port map( 
+      clk_50        => clk_50,    
+      LP_Pulse_out  => Cal_0_2,                                     
+      LP_pulse_in   => LP2_pulse               
+    );
+
+  Inst_LP1_FM_pulse_generator:FM_pulse_generator_Basic    -- LP1: mirror dish
+    port map( 
       clk            => clk_50,  
       pulse_freq     => LP1_ampl_sig(5 downto 0),
       FM_out         => PWM_sig_1   
-         );
-
-
-Inst_LP2_FM_pulse_generator:FM_pulse_generator_Basic    -- LP2: shutter
-   port map( 
+    );
+
+
+  Inst_LP2_FM_pulse_generator:FM_pulse_generator_Basic    -- LP2: shutter
+    port map( 
       clk            => clk_50,  
       pulse_freq     => LP2_ampl_sig(5 downto 0),
       FM_out         => PWM_sig_2   
-         );
-
-
--- Light Pulser 1 (in the mirror dish): differential output buffers 
+    );
+
+
+  -- Light Pulser 1 (in the mirror dish): differential output buffers 
 
   OBUFDS_inst_Cal_0 : OBUFDS
-   generic map (
-      IOSTANDARD => "DEFAULT")
-   port map  (  O  => Cal_0_p ,     -- Diff_p output (connect directly to top-level port)
-      OB =>  Cal_0_n ,   -- Diff_n output (connect directly to top-level port)
-      I  =>  Cal_0_1     -- Buffer input 
-   ); 
-
-     OBUFDS_inst_Cal_1 : OBUFDS
-   generic map (
-      IOSTANDARD => "DEFAULT")
-   port map  (  O  => Cal_1_p ,     -- Diff_p output (connect directly to top-level port)
-      OB =>  Cal_1_n ,   -- Diff_n output (connect directly to top-level port)
-      I  =>  PWM_sig_1   -- Buffer input 
-   ); 
-
-     OBUFDS_inst_Cal_2 : OBUFDS
-   generic map (
-      IOSTANDARD => "DEFAULT")
-   port map  (  O  => Cal_2_p ,     -- Diff_p output (connect directly to top-level port)
-      OB =>  Cal_2_n ,   -- Diff_n output (connect directly to top-level port)
-      I  =>  LP1_ampl_sig(14)       -- Buffer input 
-   ); 
-
-     OBUFDS_inst_Cal_3 : OBUFDS
-   generic map (
-      IOSTANDARD => "DEFAULT")
-   port map (   O  => Cal_3_p ,     -- Diff_p output (connect directly to top-level port)
-      OB =>  Cal_3_n ,   -- Diff_n output (connect directly to top-level port)
-      I  =>  LP1_ampl_sig(15)      -- Buffer input 
-   );     
+    generic map (
+      IOSTANDARD => "DEFAULT")
+    port map (  O  => Cal_0_p ,    -- Diff_p output (connect directly to top-level port)
+                OB =>  Cal_0_n ,   -- Diff_n output (connect directly to top-level port)
+                I  =>  Cal_0_1     -- Buffer input 
+                ); 
+
+  OBUFDS_inst_Cal_1 : OBUFDS
+    generic map (
+      IOSTANDARD => "DEFAULT")
+    port map  (  O  => Cal_1_p ,    -- Diff_p output (connect directly to top-level port)
+                 OB =>  Cal_1_n ,   -- Diff_n output (connect directly to top-level port)
+                 I  =>  PWM_sig_1   -- Buffer input 
+                 ); 
+
+  OBUFDS_inst_Cal_2 : OBUFDS
+    generic map (
+      IOSTANDARD => "DEFAULT")
+    port map  (  O  => Cal_2_p ,     -- Diff_p output (connect directly to top-level port)
+                 OB =>  Cal_2_n ,    -- Diff_n output (connect directly to top-level port)
+                 I  =>  LP1_ampl_sig(14)       -- Buffer input 
+                 ); 
+
+  OBUFDS_inst_Cal_3 : OBUFDS
+    generic map (
+      IOSTANDARD => "DEFAULT")
+    port map (   O  => Cal_3_p ,     -- Diff_p output (connect directly to top-level port)
+                 OB =>  Cal_3_n ,    -- Diff_n output (connect directly to top-level port)
+                 I  =>  LP1_ampl_sig(15)      -- Buffer input 
+                 );     
 
 
      
---  Light Pulser 2 (in the shutter): differential output buffers 
+  --  Light Pulser 2 (in the shutter): differential output buffers 
      
- OBUFDS_inst_Cal_4 : OBUFDS
-   generic map (
-      IOSTANDARD => "DEFAULT")
-   port map (   O  => Cal_4_p ,     -- Diff_p output (connect directly to top-level port)
-      OB =>  Cal_4_n ,   -- Diff_n output (connect directly to top-level port)
-      I  =>  Cal_0_2      -- Buffer input 
-   ); 
-
-     OBUFDS_inst_Cal_5 : OBUFDS
-   generic map (
-      IOSTANDARD => "DEFAULT")
-   port map  (  O  => Cal_5_p ,     -- Diff_p output (connect directly to top-level port)
-      OB =>  Cal_5_n ,   -- Diff_n output (connect directly to top-level port)
-      I  =>  PWM_sig_2        -- Buffer input 
-   ); 
-
-     OBUFDS_inst_Cal_6 : OBUFDS
-   generic map (
-      IOSTANDARD => "DEFAULT")
-   port map  (  O  => Cal_6_p ,     -- Diff_p output (connect directly to top-level port)
-      OB =>  Cal_6_n ,   -- Diff_n output (connect directly to top-level port)
-      I  =>  LP2_ampl_sig(14)
-    );             
-
-     OBUFDS_inst_Cal_7 : OBUFDS
-   generic map (
-      IOSTANDARD => "DEFAULT")
-   port map  (  O  => Cal_7_p ,     -- Diff_p output (connect directly to top-level port)
-      OB =>  Cal_7_n ,   -- Diff_n output (connect directly to top-level port)
-      I  =>  LP2_ampl_sig(15)   -- Buffer input 
-   );     
+  OBUFDS_inst_Cal_4 : OBUFDS
+    generic map (
+      IOSTANDARD => "DEFAULT")
+    port map (   O  => Cal_4_p ,    -- Diff_p output (connect directly to top-level port)
+                 OB =>  Cal_4_n ,   -- Diff_n output (connect directly to top-level port)
+                 I  =>  Cal_0_2     -- Buffer input 
+                 ); 
+
+  OBUFDS_inst_Cal_5 : OBUFDS
+    generic map (
+      IOSTANDARD => "DEFAULT")
+    port map  (  O  => Cal_5_p ,    -- Diff_p output (connect directly to top-level port)
+                 OB =>  Cal_5_n ,   -- Diff_n output (connect directly to top-level port)
+                 I  =>  PWM_sig_2   -- Buffer input 
+                 ); 
+
+  OBUFDS_inst_Cal_6 : OBUFDS
+    generic map (
+      IOSTANDARD => "DEFAULT")
+    port map  (  O  => Cal_6_p ,     -- Diff_p output (connect directly to top-level port)
+                 OB =>  Cal_6_n ,    -- Diff_n output (connect directly to top-level port)
+                 I  =>  LP2_ampl_sig(14)
+                 );             
+
+  OBUFDS_inst_Cal_7 : OBUFDS
+    generic map (
+      IOSTANDARD => "DEFAULT")
+    port map  (  O  => Cal_7_p ,     -- Diff_p output (connect directly to top-level port)
+                 OB =>  Cal_7_n ,    -- Diff_n output (connect directly to top-level port)
+                 I  =>  LP2_ampl_sig(15)   -- Buffer input 
+                 );     
     
 
 end Behavioral;
-
-
Index: firmware/FTM/Lightpulser_interface/Basic_Version/single_LP_Basic.vhd
===================================================================
--- firmware/FTM/Lightpulser_interface/Basic_Version/single_LP_Basic.vhd	(revision 10857)
+++ firmware/FTM/Lightpulser_interface/Basic_Version/single_LP_Basic.vhd	(revision 10879)
@@ -28,4 +28,8 @@
 -- modified:     May 27 2011
 --               by Patrick Vogler
+--
+-- modified:     May 27 2011
+--               by Patrick Vogler, Quirin Weitzel
+--               -> clean up
 ----------------------------------------------------------------------------------
 ----------------------------------------------------------------------------------
Index: firmware/FTM/ftm_board.ucf
===================================================================
--- firmware/FTM/ftm_board.ucf	(revision 10857)
+++ firmware/FTM/ftm_board.ucf	(revision 10879)
@@ -11,9 +11,7 @@
 ########################################################
 
-
 #Clock
 #######################################################
-NET clk LOC = Y14 | IOSTANDARD=LVCMOS33; # FPGA-CLK from oscillator U47
-
+NET clk LOC = Y14 |IOSTANDARD=LVCMOS33; # FPGA-CLK from oscillator U47
 
 # Ethernet Interface
@@ -22,42 +20,39 @@
 #######################################################
 # data bus
-NET W_D<0>  LOC  = M22 | IOSTANDARD=LVCMOS33; # 16-bit data bus to W5300	
-NET W_D<1>  LOC  = L22 | IOSTANDARD=LVCMOS33; # 
-NET W_D<2>  LOC  = K23 | IOSTANDARD=LVCMOS33; # 
-NET W_D<3>  LOC  = K25 | IOSTANDARD=LVCMOS33; # 
-NET W_D<4>  LOC  = K26 | IOSTANDARD=LVCMOS33; # 
-NET W_D<5>  LOC  = J22 | IOSTANDARD=LVCMOS33; # 
-NET W_D<6>  LOC  = J23 | IOSTANDARD=LVCMOS33; # 	
-NET W_D<7>  LOC  = G23 | IOSTANDARD=LVCMOS33; # 
-NET W_D<8>  LOC  = G24 | IOSTANDARD=LVCMOS33; # 
-NET W_D<9>  LOC  = F24 | IOSTANDARD=LVCMOS33; # 
-NET W_D<10> LOC  = F25 | IOSTANDARD=LVCMOS33; # 
-NET W_D<11> LOC  = E24 | IOSTANDARD=LVCMOS33; # 
-NET W_D<12> LOC  = E26 | IOSTANDARD=LVCMOS33; # 
-NET W_D<13> LOC  = D24 | IOSTANDARD=LVCMOS33; # 
-NET W_D<14> LOC  = D26 | IOSTANDARD=LVCMOS33; # 
-NET W_D<15> LOC  = D25 | IOSTANDARD=LVCMOS33; # 
-
+NET W_D<0>  LOC  = M22 |IOSTANDARD=LVCMOS33; # 16-bit data bus to W5300	
+NET W_D<1>  LOC  = L22 |IOSTANDARD=LVCMOS33; # 
+NET W_D<2>  LOC  = K23 |IOSTANDARD=LVCMOS33; # 
+NET W_D<3>  LOC  = K25 |IOSTANDARD=LVCMOS33; # 
+NET W_D<4>  LOC  = K26 |IOSTANDARD=LVCMOS33; # 
+NET W_D<5>  LOC  = J22 |IOSTANDARD=LVCMOS33; # 
+NET W_D<6>  LOC  = J23 |IOSTANDARD=LVCMOS33; # 	
+NET W_D<7>  LOC  = G23 |IOSTANDARD=LVCMOS33; # 
+NET W_D<8>  LOC  = G24 |IOSTANDARD=LVCMOS33; # 
+NET W_D<9>  LOC  = F24 |IOSTANDARD=LVCMOS33; # 
+NET W_D<10> LOC  = F25 |IOSTANDARD=LVCMOS33; # 
+NET W_D<11> LOC  = E24 |IOSTANDARD=LVCMOS33; # 
+NET W_D<12> LOC  = E26 |IOSTANDARD=LVCMOS33; # 
+NET W_D<13> LOC  = D24 |IOSTANDARD=LVCMOS33; # 
+NET W_D<14> LOC  = D26 |IOSTANDARD=LVCMOS33; # 
+NET W_D<15> LOC  = D25 |IOSTANDARD=LVCMOS33; # 
 # W5300 address bus
-NET W_A<0> LOC  = U18  | IOSTANDARD=LVCMOS33; # there is no real net W_A0 because
-NET W_A<1> LOC  = AA25 | IOSTANDARD=LVCMOS33; # the W5300 is operated in the 16-bit mode 
-NET W_A<2> LOC  = AA24 | IOSTANDARD=LVCMOS33; #	(see W5300 datasheet)
-NET W_A<3> LOC  = AA23 | IOSTANDARD=LVCMOS33; # -> W_A<0> assigned to unconnected pin
-NET W_A<4> LOC  = Y25  | IOSTANDARD=LVCMOS33; #
-NET W_A<5> LOC  = Y24  | IOSTANDARD=LVCMOS33; #
-NET W_A<6> LOC  = Y23  | IOSTANDARD=LVCMOS33; #
-NET W_A<7> LOC  = W23  | IOSTANDARD=LVCMOS33; #
-NET W_A<8> LOC  = V25  | IOSTANDARD=LVCMOS33; #
-NET W_A<9> LOC  = V24  | IOSTANDARD=LVCMOS33; #
-
+NET W_A<0> LOC  = U18  |IOSTANDARD=LVCMOS33; # there is no real net W_A0 because
+NET W_A<1> LOC  = AA25 |IOSTANDARD=LVCMOS33; # the W5300 is operated in the 16-bit mode 
+NET W_A<2> LOC  = AA24 |IOSTANDARD=LVCMOS33; #	(see W5300 datasheet)
+NET W_A<3> LOC  = AA23 |IOSTANDARD=LVCMOS33; # -> W_A<0> assigned to unconnected pin
+NET W_A<4> LOC  = Y25  |IOSTANDARD=LVCMOS33; #
+NET W_A<5> LOC  = Y24  |IOSTANDARD=LVCMOS33; #
+NET W_A<6> LOC  = Y23  |IOSTANDARD=LVCMOS33; #
+NET W_A<7> LOC  = W23  |IOSTANDARD=LVCMOS33; #
+NET W_A<8> LOC  = V25  |IOSTANDARD=LVCMOS33; #
+NET W_A<9> LOC  = V24  |IOSTANDARD=LVCMOS33; #
 # W5300 control signals
 # the signals W_INT, W_RD, W_WR and W_RES also go to testpoints T17
 # W_CS is also routed to testpoint JP7
-NET W_CS    LOC  = T20  | IOSTANDARD=LVCMOS33; # W5300 chip select
-NET W_INT   LOC  = U22  | IOSTANDARD=LVCMOS33; # interrupt
-NET W_RD    LOC  = R20  | IOSTANDARD=LVCMOS33; # read
-NET W_WR    LOC  = P22  | IOSTANDARD=LVCMOS33; # write
-NET W_RES   LOC  = U23  | IOSTANDARD=LVCMOS33; # reset W5300 chip
-
+NET W_CS    LOC  = T20  |IOSTANDARD=LVCMOS33; # W5300 chip select
+NET W_INT   LOC  = U22  |IOSTANDARD=LVCMOS33; # interrupt
+NET W_RD    LOC  = R20  |IOSTANDARD=LVCMOS33; # read
+NET W_WR    LOC  = P22  |IOSTANDARD=LVCMOS33; # write
+NET W_RES   LOC  = U23  |IOSTANDARD=LVCMOS33; # reset W5300 chip
 # W5300 buffer ready indicator
 # NET W_BRDY<0>   LOC  = AB26  | IOSTANDARD=LVCMOS33; #
@@ -65,5 +60,4 @@
 # NET W_BRDY<2>   LOC  = AC25  | IOSTANDARD=LVCMOS33; #
 # NET W_BRDY<3>   LOC  = AD26  | IOSTANDARD=LVCMOS33; #
-
 # W5300 associated testpoints
 # NET W_T<0>   LOC  = N21  | IOSTANDARD=LVCMOS33; #
@@ -72,5 +66,4 @@
 # NET W_T<3>   LOC  = R19  | IOSTANDARD=LVCMOS33; #
 
-
 # SPI Interface
 # connection to the EEPROM U36 (AL25L016M) and the temperature
@@ -79,10 +72,8 @@
 #######################################################
 # NET S_CLK  LOC  = U20  | IOSTANDARD=LVCMOS33;  # SPI clock
-
 # EEPROM
 # NET MOSI   LOC  = AA22 | IOSTANDARD=LVCMOS33;    # master out slave in
 # NET MISO   LOC  = V22  | IOSTANDARD=LVCMOS33;    # master in slave out
 # NET EE_CS  LOC  = G22  | IOSTANDARD=LVCMOS33;    # master out slave in
-
 # temperature sensors
 # NET SIO       LOC  = F22  | IOSTANDARD=LVCMOS33;  # serial IO
@@ -92,5 +83,4 @@
 # NET TS_CS<3>  LOC  = C26  | IOSTANDARD=LVCMOS33;  # temperature sensors chip select3
 
-
 # Trigger primitives inputs
 # on IO-Bank 2
@@ -98,97 +88,87 @@
 # crate 0 
 # crate A
-NET Trig_Prim_A<0>  LOC  = AC6  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<0>	
-NET Trig_Prim_A<1>  LOC  = AD6  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<1>
-NET Trig_Prim_A<2>  LOC  = AF3  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<2>
-NET Trig_Prim_A<3>  LOC  = AE4  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<3>
-NET Trig_Prim_A<4>  LOC  = AE6  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<4>
-NET Trig_Prim_A<5>  LOC  = AE7  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<5>
-NET Trig_Prim_A<6>  LOC  = AE8  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<6>
-NET Trig_Prim_A<7>  LOC  = AC8  | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<7>
-NET Trig_Prim_A<8>  LOC  = AC11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<8>
-NET Trig_Prim_A<9>  LOC  = AD11 | IOSTANDARD=LVCMOS33; # Trig_Prim_0_<9>
-
+NET Trig_Prim_A<0>  LOC  = AC6  |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<0>	
+NET Trig_Prim_A<1>  LOC  = AD6  |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<1>
+NET Trig_Prim_A<2>  LOC  = AF3  |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<2>
+NET Trig_Prim_A<3>  LOC  = AE4  |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<3>
+NET Trig_Prim_A<4>  LOC  = AE6  |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<4>
+NET Trig_Prim_A<5>  LOC  = AE7  |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<5>
+NET Trig_Prim_A<6>  LOC  = AE8  |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<6>
+NET Trig_Prim_A<7>  LOC  = AC8  |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<7>
+NET Trig_Prim_A<8>  LOC  = AC11 |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<8>
+NET Trig_Prim_A<9>  LOC  = AD11 |IOSTANDARD=LVCMOS33; # Trig_Prim_0_<9>
 # crate 1
 # crate B
-NET Trig_Prim_B<0>  LOC  = AB16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<0>	
-NET Trig_Prim_B<1>  LOC  = AC15 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<1>
-NET Trig_Prim_B<2>  LOC  = AC16 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<2>
-NET Trig_Prim_B<3>  LOC  = AE17 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<3>
-NET Trig_Prim_B<4>  LOC  = AD19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<4>
-NET Trig_Prim_B<5>  LOC  = AE19 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<5>
-NET Trig_Prim_B<6>  LOC  = AE20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<6>
-NET Trig_Prim_B<7>  LOC  = AF20 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<7>
-NET Trig_Prim_B<8>  LOC  = AD21 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<8>
-NET Trig_Prim_B<9>  LOC  = AE23 | IOSTANDARD=LVCMOS33; # Trig_Prim_1_<9>
-
+NET Trig_Prim_B<0>  LOC  = AB16 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<0>	
+NET Trig_Prim_B<1>  LOC  = AC15 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<1>
+NET Trig_Prim_B<2>  LOC  = AC16 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<2>
+NET Trig_Prim_B<3>  LOC  = AE17 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<3>
+NET Trig_Prim_B<4>  LOC  = AD19 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<4>
+NET Trig_Prim_B<5>  LOC  = AE19 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<5>
+NET Trig_Prim_B<6>  LOC  = AE20 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<6>
+NET Trig_Prim_B<7>  LOC  = AF20 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<7>
+NET Trig_Prim_B<8>  LOC  = AD21 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<8>
+NET Trig_Prim_B<9>  LOC  = AE23 |IOSTANDARD=LVCMOS33; # Trig_Prim_1_<9>
 # crate 2
 # crate C
-NET Trig_Prim_C<0>  LOC  = AF23 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<0>	
-NET Trig_Prim_C<1>  LOC  = AC21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<1>
-NET Trig_Prim_C<2>  LOC  = AE21 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<2>
-NET Trig_Prim_C<3>  LOC  = AD20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<3>
-NET Trig_Prim_C<4>  LOC  = AC20 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<4>
-NET Trig_Prim_C<5>  LOC  = AF19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<5>
-NET Trig_Prim_C<6>  LOC  = AC19 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<6>
-NET Trig_Prim_C<7>  LOC  = AD17 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<7>
-NET Trig_Prim_C<8>  LOC  = AD14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<8>
-NET Trig_Prim_C<9>  LOC  = AC14 | IOSTANDARD=LVCMOS33; # Trig_Prim_2_<9>
-
+NET Trig_Prim_C<0>  LOC  = AF23 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<0>	
+NET Trig_Prim_C<1>  LOC  = AC21 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<1>
+NET Trig_Prim_C<2>  LOC  = AE21 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<2>
+NET Trig_Prim_C<3>  LOC  = AD20 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<3>
+NET Trig_Prim_C<4>  LOC  = AC20 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<4>
+NET Trig_Prim_C<5>  LOC  = AF19 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<5>
+NET Trig_Prim_C<6>  LOC  = AC19 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<6>
+NET Trig_Prim_C<7>  LOC  = AD17 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<7>
+NET Trig_Prim_C<8>  LOC  = AD14 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<8>
+NET Trig_Prim_C<9>  LOC  = AC14 |IOSTANDARD=LVCMOS33; # Trig_Prim_2_<9>
 # crate 3
 # crate D
-NET Trig_Prim_D<0>  LOC  = AB12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<0>	
-NET Trig_Prim_D<1>  LOC  = AC12 | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<1>
-NET Trig_Prim_D<2>  LOC  = AC9  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<2>
-NET Trig_Prim_D<3>  LOC  = AB9  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<3>
-NET Trig_Prim_D<4>  LOC  = AB7  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<4>
-NET Trig_Prim_D<5>  LOC  = AF8  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<5>
-NET Trig_Prim_D<6>  LOC  = AF4  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<6>
-NET Trig_Prim_D<7>  LOC  = AF5  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<7>
-NET Trig_Prim_D<8>  LOC  = AD7  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<8>
-NET Trig_Prim_D<9>  LOC  = AE3  | IOSTANDARD=LVCMOS33; # Trig_Prim_3_<9>
-
+NET Trig_Prim_D<0>  LOC  = AB12 |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<0>	
+NET Trig_Prim_D<1>  LOC  = AC12 |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<1>
+NET Trig_Prim_D<2>  LOC  = AC9  |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<2>
+NET Trig_Prim_D<3>  LOC  = AB9  |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<3>
+NET Trig_Prim_D<4>  LOC  = AB7  |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<4>
+NET Trig_Prim_D<5>  LOC  = AF8  |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<5>
+NET Trig_Prim_D<6>  LOC  = AF4  |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<6>
+NET Trig_Prim_D<7>  LOC  = AF5  |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<7>
+NET Trig_Prim_D<8>  LOC  = AD7  |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<8>
+NET Trig_Prim_D<9>  LOC  = AE3  |IOSTANDARD=LVCMOS33; # Trig_Prim_3_<9>
 
 # NIM inputs
 #######################################################
 # on IO-Bank 3
-NET ext_Trig<1>  LOC  = B1  | IOSTANDARD=LVCMOS33; #	
-NET ext_Trig<2>  LOC  = B2  | IOSTANDARD=LVCMOS33; #
-NET Veto         LOC  = E4  | IOSTANDARD=LVCMOS33; #
+NET ext_Trig<1>  LOC  = B1  |IOSTANDARD=LVCMOS33; #	
+NET ext_Trig<2>  LOC  = B2  |IOSTANDARD=LVCMOS33; #
+NET Veto         LOC  = E4  |IOSTANDARD=LVCMOS33; #
 # NET NIM_In<0>    LOC  = D3  | IOSTANDARD=LVCMOS33; #
 # NET NIM_In<1>    LOC  = F4  | IOSTANDARD=LVCMOS33; #
 # NET NIM_In<2>    LOC  = E3  | IOSTANDARD=LVCMOS33; #
-
 # on IO-Bank 0
 # input pin with global clock buffer available
 # NET NIM_In3_GCLK  LOC  = K14  | IOSTANDARD=LVCMOS33;
 
-
 # LEDs
 # on IO-Banks 0 and 3
 #######################################################
 # red
-NET LED_red<0>  LOC  = D6  | IOSTANDARD=LVCMOS33; # IO-Bank 0	
-NET LED_red<1>  LOC  = A4  | IOSTANDARD=LVCMOS33; # IO-Bank 0	
-NET LED_red<2>  LOC  = E1  | IOSTANDARD=LVCMOS33; # IO-Bank 3	
-NET LED_red<3>  LOC  = J5  | IOSTANDARD=LVCMOS33; # IO-Bank 3	
-
+NET LED_red<0>  LOC  = D6  |IOSTANDARD=LVCMOS33; # IO-Bank 0	
+NET LED_red<1>  LOC  = A4  |IOSTANDARD=LVCMOS33; # IO-Bank 0	
+NET LED_red<2>  LOC  = E1  |IOSTANDARD=LVCMOS33; # IO-Bank 3	
+NET LED_red<3>  LOC  = J5  |IOSTANDARD=LVCMOS33; # IO-Bank 3	
 # yellow
-NET LED_ye<0>   LOC  = C5  | IOSTANDARD=LVCMOS33; # IO-Bank 0	
-NET LED_ye<1>   LOC  = B3  | IOSTANDARD=LVCMOS33; # IO-Bank 0
-
+NET LED_ye<0>   LOC  = C5  |IOSTANDARD=LVCMOS33; # IO-Bank 0	
+NET LED_ye<1>   LOC  = B3  |IOSTANDARD=LVCMOS33; # IO-Bank 0
 # green
-NET LED_gn<0>   LOC  = B4  | IOSTANDARD=LVCMOS33; # IO-Bank 0	
-NET LED_gn<1>   LOC  = A3  | IOSTANDARD=LVCMOS33; # IO-Bank 0
-
+NET LED_gn<0>   LOC  = B4  |IOSTANDARD=LVCMOS33; # IO-Bank 0	
+NET LED_gn<1>   LOC  = A3  |IOSTANDARD=LVCMOS33; # IO-Bank 0
 
 # Clock conditioner LMK03000
 # on IO-Bank 3
 #######################################################
-NET CLK_Clk_Cond    LOC  = G4  | IOSTANDARD=LVCMOS33; # IO-Bank 3
-NET LE_Clk_Cond     LOC  = F2  | IOSTANDARD=LVCMOS33; # IO-Bank 3
-NET LD_Clk_Cond     LOC  = J4  | IOSTANDARD=LVCMOS33; # IO-Bank 3
-NET DATA_Clk_Cond   LOC  = F3  | IOSTANDARD=LVCMOS33; # IO-Bank 3
-NET SYNC_Clk_Cond   LOC  = H2  | IOSTANDARD=LVCMOS33; # IO-Bank 3
-
+NET CLK_Clk_Cond    LOC  = G4  |IOSTANDARD=LVCMOS33; # IO-Bank 3
+NET LE_Clk_Cond     LOC  = F2  |IOSTANDARD=LVCMOS33; # IO-Bank 3
+NET LD_Clk_Cond     LOC  = J4  |IOSTANDARD=LVCMOS33; # IO-Bank 3
+NET DATA_Clk_Cond   LOC  = F3  |IOSTANDARD=LVCMOS33; # IO-Bank 3
+NET SYNC_Clk_Cond   LOC  = H2  |IOSTANDARD=LVCMOS33; # IO-Bank 3
 
 # various RS-485 Interfaces
@@ -196,44 +176,34 @@
 #######################################################
 # Bus 1: FTU slow control
-NET Bus1_Tx_En   LOC  = H1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 
-NET Bus1_Rx_En   LOC  = G3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
-
+NET Bus1_Tx_En   LOC  = H1  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; # 
+NET Bus1_Rx_En   LOC  = G3  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
 # crate 0
-NET Bus1_RxD_0   LOC  = K3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 
-NET Bus1_TxD_0   LOC  = L3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 
-
+NET Bus1_RxD_0   LOC  = K3  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; # 
+NET Bus1_TxD_0   LOC  = L3  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; # 
 # crate 1
-NET Bus1_RxD_1   LOC  = M2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 
-NET Bus1_TxD_1   LOC  = N4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
-
+NET Bus1_RxD_1   LOC  = M2  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; # 
+NET Bus1_TxD_1   LOC  = N4  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
 # crate 2
-NET Bus1_RxD_2   LOC  = P3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 
-NET Bus1_TxD_2   LOC  = P4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
-
+NET Bus1_RxD_2   LOC  = P3  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; # 
+NET Bus1_TxD_2   LOC  = P4  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
 # crate 3
-NET Bus1_RxD_3   LOC  = T4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 
-NET Bus1_TxD_3   LOC  = T3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
-
+NET Bus1_RxD_3   LOC  = T4  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; # 
+NET Bus1_TxD_3   LOC  = T3  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
 
 # Bus 2: Trigger-ID to FAD boards
-NET Bus2_Tx_En   LOC  = K2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 
-NET Bus2_Rx_En   LOC  = K4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 
-
+NET Bus2_Tx_En   LOC  = K2  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; # 
+NET Bus2_Rx_En   LOC  = K4  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; # 
 # crate 0
-NET Bus2_RxD_0   LOC  = L4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 
-NET Bus2_TxD_0   LOC  = M3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 
-
+NET Bus2_RxD_0   LOC  = L4  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; # 
+NET Bus2_TxD_0   LOC  = M3  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; # 
 # crate 1
-NET Bus2_RxD_1   LOC  = N2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 
-NET Bus2_TxD_1   LOC  = N1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 
-
+NET Bus2_RxD_1   LOC  = N2  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; # 
+NET Bus2_TxD_1   LOC  = N1  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; # 
 # crate 2
-NET Bus2_RxD_2   LOC  = R2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 
-NET Bus2_TxD_2   LOC  = R1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 
-
+NET Bus2_RxD_2   LOC  = R2  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; # 
+NET Bus2_TxD_2   LOC  = R1  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; # 
 # crate 3
-NET Bus2_RxD_3   LOC  = U4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 
-NET Bus2_TxD_3   LOC  = U2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 
-
+NET Bus2_RxD_3   LOC  = U4  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; # 
+NET Bus2_TxD_3   LOC  = U2  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; # 
 
 # auxiliary access
@@ -242,27 +212,23 @@
 # NET Aux_Rx_En    LOC  = W4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # Rx- and Tx enable 
 # NET Aux_Tx_En    LOC  = V1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # also for auxiliary Trigger-ID
-
 # auxiliary Trigger-ID (i.e. to send the Trigger-ID to the counting hut/house/container)
 # NET TrID_Rx_D    LOC  = U6  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 
 # NET TrID_Tx_D    LOC  = T7  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; # 
 
-
 # Crate-Resets
 # on IO-Bank 3
 #######################################################
-NET Crate_Res0    LOC  = M1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
-NET Crate_Res1    LOC  = P1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
-NET Crate_Res2    LOC  = R3  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
-NET Crate_Res3    LOC  = V2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
-
+NET Crate_Res0    LOC  = M1  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
+NET Crate_Res1    LOC  = P1  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
+NET Crate_Res2    LOC  = R3  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
+NET Crate_Res3    LOC  = V2  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
 
 # Busy signals from the FAD boards
 # on IO-Bank 3
 #######################################################
-NET Busy0    LOC  = M4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
-NET Busy1    LOC  = P2  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
-NET Busy2    LOC  = R4  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
-NET Busy3    LOC  = U1  | IOSTANDARD=LVCMOS33 | SLEW = SLOW ; #
-
+NET Busy0    LOC  = M4  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
+NET Busy1    LOC  = P2  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
+NET Busy2    LOC  = R4  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
+NET Busy3    LOC  = U1  |IOSTANDARD=LVCMOS33 |SLEW = SLOW ; #
 
 # NIM outputs
@@ -276,5 +242,4 @@
 # NET Cal_NIM2_p   LOC  = B18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; #  Cal_NIM2+ 
 # NET Cal_NIM2_n   LOC  = A18 | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; #  Cal_NIM2- 
-
 # auxiliarry / spare NIM outputs
 # NET NIM_Out0_p  LOC  = C17 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; #  NIM_Out0+
@@ -283,22 +248,16 @@
 # NET NIM_Out1_n  LOC  = C16 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # NIM_Out1-
 
-
 # fast control signal outputs
 # LVDS output at the FPGA followed by LVDS to NIM 
 # conversion stage
 #######################################################
-# NET RES_p       LOC  = D16  | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES+ Reset
-# NET RES_n       LOC  = C15  | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # RES- IO-Bank 0
-
-NET TRG_p       LOC  = B15  | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG+ Trigger
-NET TRG_n       LOC  = A15  | IOSTANDARD=LVDS_33 | DIFF_TERM="False"; # TRG- IO-Bank 0
-
-NET TIM_Run_p   LOC  = AF25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run+ Time Marker
-NET TIM_Run_n   LOC  = AE25 | IOSTANDARD=LVDS_33 | DIFF_TERM="False" ; # TIM_Run- on IO-Bank2
-
-NET TIM_Sel     LOC  = AD22 | IOSTANDARD=LVCMOS33;  # Time Marker selector IO-Bank 2
-
+NET RES_p       LOC  = D16  |IOSTANDARD=LVDS_33; # RES+ Reset
+NET RES_n       LOC  = C15  |IOSTANDARD=LVDS_33; # RES- IO-Bank 0
+NET TRG_p       LOC  = B15  |IOSTANDARD=LVDS_33; # TRG+ Trigger
+NET TRG_n       LOC  = A15  |IOSTANDARD=LVDS_33; # TRG- IO-Bank 0
+NET TIM_Run_p   LOC  = AF25 |IOSTANDARD=LVDS_33; # TIM_Run+ Time Marker
+NET TIM_Run_n   LOC  = AE25 |IOSTANDARD=LVDS_33; # TIM_Run- on IO-Bank2
+NET TIM_Sel     LOC  = AD22 |IOSTANDARD=LVCMOS33;  # Time Marker selector IO-Bank 2
 # NET CLD_FPGA    LOC  = AA14 | IOSTANDARD=LVCMOS33;  # DRS-Clock feedback into FPGA
-
 
 # LVDS calibration outputs
@@ -306,23 +265,21 @@
 #######################################################
 # to connector J13
-# NET Cal_0_p   LOC  = D22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0+
-# NET Cal_0_n   LOC  = C22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_0-
-# NET Cal_1_p   LOC  = D23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1+
-# NET Cal_1_n   LOC  = C23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_1-
-# NET Cal_2_p   LOC  = B23 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2+
-# NET Cal_2_n   LOC  = A22 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_2-
-# NET Cal_3_p   LOC  = C21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3+
-# NET Cal_3_n   LOC  = B21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_3-
-
+NET Cal_0_p   LOC  = D22 | IOSTANDARD=LVDS_33; # Cal_0+
+NET Cal_0_n   LOC  = C22 | IOSTANDARD=LVDS_33; # Cal_0-
+NET Cal_1_p   LOC  = D23 | IOSTANDARD=LVDS_33; # Cal_1+
+NET Cal_1_n   LOC  = C23 | IOSTANDARD=LVDS_33; # Cal_1-
+NET Cal_2_p   LOC  = B23 | IOSTANDARD=LVDS_33; # Cal_2+
+NET Cal_2_n   LOC  = A22 | IOSTANDARD=LVDS_33; # Cal_2-
+NET Cal_3_p   LOC  = C21 | IOSTANDARD=LVDS_33; # Cal_3+
+NET Cal_3_n   LOC  = B21 | IOSTANDARD=LVDS_33; # Cal_3-
 # to connector J12
-# NET Cal_4_p   LOC  = E21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4+   
-# NET Cal_4_n   LOC  = D21 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_4-   
-# NET Cal_5_p   LOC  = D20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5+   
-# NET Cal_5_n   LOC  = C20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_5-   
-# NET Cal_6_p   LOC  = B20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6+   
-# NET Cal_6_n   LOC  = A20 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_6-   
-# NET Cal_7_p   LOC  = B19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7+   
-# NET Cal_7_n   LOC  = A19 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # Cal_7-    
-
+NET Cal_4_p   LOC  = E21 | IOSTANDARD=LVDS_33; # Cal_4+   
+NET Cal_4_n   LOC  = D21 | IOSTANDARD=LVDS_33; # Cal_4-   
+NET Cal_5_p   LOC  = D20 | IOSTANDARD=LVDS_33; # Cal_5+   
+NET Cal_5_n   LOC  = C20 | IOSTANDARD=LVDS_33; # Cal_5-   
+NET Cal_6_p   LOC  = B20 | IOSTANDARD=LVDS_33; # Cal_6+   
+NET Cal_6_n   LOC  = A20 | IOSTANDARD=LVDS_33; # Cal_6-   
+NET Cal_7_p   LOC  = B19 | IOSTANDARD=LVDS_33; # Cal_7+   
+NET Cal_7_n   LOC  = A19 | IOSTANDARD=LVDS_33; # Cal_7-    
 
 # Testpoints
@@ -330,66 +287,56 @@
 # Connector T7
 # IO-Bank 0
-NET TP<0> LOC  = B14 | IOSTANDARD=LVCMOS33;  # 
-NET TP<1> LOC  = A14 | IOSTANDARD=LVCMOS33;  # 
-NET TP<2> LOC  = C13 | IOSTANDARD=LVCMOS33;  # 
-NET TP<3> LOC  = B13 | IOSTANDARD=LVCMOS33;  # 
-
+NET TP<0> LOC  = B14 |IOSTANDARD=LVCMOS33;  # 
+NET TP<1> LOC  = A14 |IOSTANDARD=LVCMOS33;  # 
+NET TP<2> LOC  = C13 |IOSTANDARD=LVCMOS33;  # 
+NET TP<3> LOC  = B13 |IOSTANDARD=LVCMOS33;  # 
 # Connector T10
 # IO-Bank 0
-NET TP<4> LOC  = D13 | IOSTANDARD=LVCMOS33;  # 
-NET TP<5> LOC  = C12 | IOSTANDARD=LVCMOS33;  # 
-NET TP<6> LOC  = B12 | IOSTANDARD=LVCMOS33;  # 
-NET TP<7> LOC  = A12 | IOSTANDARD=LVCMOS33;  # 
-
+NET TP<4> LOC  = D13 |IOSTANDARD=LVCMOS33;  # 
+NET TP<5> LOC  = C12 |IOSTANDARD=LVCMOS33;  # 
+NET TP<6> LOC  = B12 |IOSTANDARD=LVCMOS33;  # 
+NET TP<7> LOC  = A12 |IOSTANDARD=LVCMOS33;  # 
 # on Connector T12
 # IO-Bank 0
-NET TP<8> LOC  = D11 | IOSTANDARD=LVCMOS33;  # 
-NET TP<9> LOC  = C11 | IOSTANDARD=LVCMOS33;  #
-
+NET TP<8> LOC  = D11 |IOSTANDARD=LVCMOS33;  # 
+NET TP<9> LOC  = C11 |IOSTANDARD=LVCMOS33;  #
 # on Connector T14
 # IO-Bank 0
-NET TP<10> LOC  = D10 | IOSTANDARD=LVCMOS33;  # 
-NET TP<11> LOC  = C10 | IOSTANDARD=LVCMOS33;  # 
-NET TP<12> LOC  = A10 | IOSTANDARD=LVCMOS33;  # 
-NET TP<13> LOC  = B10 | IOSTANDARD=LVCMOS33;  # 
-
+NET TP<10> LOC  = D10 |IOSTANDARD=LVCMOS33;  # 
+NET TP<11> LOC  = C10 |IOSTANDARD=LVCMOS33;  # 
+NET TP<12> LOC  = A10 |IOSTANDARD=LVCMOS33;  # 
+NET TP<13> LOC  = B10 |IOSTANDARD=LVCMOS33;  # 
 # on Connector T16
 # IO-Bank 0
-NET TP<14> LOC  = A9 | IOSTANDARD=LVCMOS33;  # 
-NET TP<15> LOC  = B9 | IOSTANDARD=LVCMOS33;  # 
-NET TP<16> LOC  = A8 | IOSTANDARD=LVCMOS33;  # 
-NET TP<17> LOC  = B8 | IOSTANDARD=LVCMOS33;  # 
-
+NET TP<14> LOC  = A9 |IOSTANDARD=LVCMOS33;  # 
+NET TP<15> LOC  = B9 |IOSTANDARD=LVCMOS33;  # 
+NET TP<16> LOC  = A8 |IOSTANDARD=LVCMOS33;  # 
+NET TP<17> LOC  = B8 |IOSTANDARD=LVCMOS33;  # 
 # on Connector T8
 # IO-Bank 0
-NET TP<18> LOC  = C8 | IOSTANDARD=LVCMOS33;  # 
-NET TP<19> LOC  = D8 | IOSTANDARD=LVCMOS33;  # 
-NET TP<20> LOC  = C6 | IOSTANDARD=LVCMOS33;  # 
-NET TP<21> LOC  = B6 | IOSTANDARD=LVCMOS33;  # 
-
+NET TP<18> LOC  = C8 |IOSTANDARD=LVCMOS33;  # 
+NET TP<19> LOC  = D8 |IOSTANDARD=LVCMOS33;  # 
+NET TP<20> LOC  = C6 |IOSTANDARD=LVCMOS33;  # 
+NET TP<21> LOC  = B6 |IOSTANDARD=LVCMOS33;  # 
 # on Connector T9
 # IO-Bank 0
-NET TP<22> LOC  = C7 | IOSTANDARD=LVCMOS33;  # 
-NET TP<23> LOC  = B7 | IOSTANDARD=LVCMOS33;  #
-
+NET TP<22> LOC  = C7 |IOSTANDARD=LVCMOS33;  # 
+NET TP<23> LOC  = B7 |IOSTANDARD=LVCMOS33;  #
 # on Connector T11
 # IO-Bank 3
-NET TP<24> LOC  = Y1  | IOSTANDARD=LVCMOS33;  # 
-NET TP<25> LOC  = AA3 | IOSTANDARD=LVCMOS33;  # 
-NET TP<26> LOC  = AA2 | IOSTANDARD=LVCMOS33;  # 
-NET TP<27> LOC  = AC1 | IOSTANDARD=LVCMOS33;  #
-
+NET TP<24> LOC  = Y1  |IOSTANDARD=LVCMOS33;  # 
+NET TP<25> LOC  = AA3 |IOSTANDARD=LVCMOS33;  # 
+NET TP<26> LOC  = AA2 |IOSTANDARD=LVCMOS33;  # 
+NET TP<27> LOC  = AC1 |IOSTANDARD=LVCMOS33;  #
 # on Connector T13
 # IO-Bank 3
-NET TP<28> LOC  = AB1 | IOSTANDARD=LVCMOS33;  # 
-NET TP<29> LOC  = AC3 | IOSTANDARD=LVCMOS33;  # 
-NET TP<30> LOC  = AC2 | IOSTANDARD=LVCMOS33;  # 
-NET TP<31> LOC  = AD2 | IOSTANDARD=LVCMOS33;  #
-
+NET TP<28> LOC  = AB1 |IOSTANDARD=LVCMOS33;  # 
+NET TP<29> LOC  = AC3 |IOSTANDARD=LVCMOS33;  # 
+NET TP<30> LOC  = AC2 |IOSTANDARD=LVCMOS33;  # 
+NET TP<31> LOC  = AD2 |IOSTANDARD=LVCMOS33;  #
 # on Connector T15
-NET TP<32> LOC  = AD1 | IOSTANDARD=LVCMOS33;  # IO-Bank 3
+NET TP<32> LOC  = AD1 |IOSTANDARD=LVCMOS33;  # IO-Bank 3
 # NET TP_in<33> LOC  = AE2 | IOSTANDARD=LVCMOS33;  # input only
 # NET TP_in<34> LOC  = AE1 | IOSTANDARD=LVCMOS33;  # input only
-
 
 # Board ID - inputs 
@@ -405,2 +352,5 @@
 # NET brd_id<6> LOC  = H24 | IOSTANDARD=LVCMOS33; #
 # NET brd_id<7> LOC  = Y26 | IOSTANDARD=LVCMOS33; #
+
+NET "clk" TNM_NET = clk;
+TIMESPEC TS_clk = PERIOD "clk" 25 ns HIGH 50%;
Index: firmware/FTM/ftm_definitions.vhd
===================================================================
--- firmware/FTM/ftm_definitions.vhd	(revision 10857)
+++ firmware/FTM/ftm_definitions.vhd	(revision 10879)
@@ -342,8 +342,8 @@
       X"0000", -- SD_ADDR_lp_pt_ratio...    -- ratio between LP1, LP2 and pedestal triggers
       --X"0001", -- SD_ADDR_lp_pt_ratio...    -- ratio between LP1, LP2 and pedestal triggers
-      X"0004", -- SD_ADDR_lp1_amplitude     -- light pulser 1 amplitude
-      X"0005", -- SD_ADDR_lp2_amplitude     -- light pulser 2 amplitude
-      X"0006", -- SD_ADDR_lp1_delay         -- light pulser 1 delay
-      X"0007", -- SD_ADDR_lp2_delay         -- light pulser 2 delay
+      X"8020", -- SD_ADDR_lp1_amplitude     -- light pulser 1 amplitude
+      X"4001", -- SD_ADDR_lp2_amplitude     -- light pulser 2 amplitude
+      X"0000", -- SD_ADDR_lp1_delay         -- light pulser 1 delay
+      X"0000", -- SD_ADDR_lp2_delay         -- light pulser 2 delay
       X"0001", -- SD_ADDR_coin_n_p          -- majority coincidence n (for physics)
       X"001E", -- SD_ADDR_coin_n_c          -- majority coincidence n (for calibration)
@@ -399,10 +399,8 @@
   -- constant low_PLC : integer := 16;   -- minimal pulse duration in units of 4 ns
   -- constant width_PLC : integer := 6;  -- counter width pulse duration 
-  constant FLD_PULSE_LENGTH       : integer := 12;       
-  constant FLD_MIN_FREQ_DIV       : integer := 25;      
-  constant FLD_FD_MULT            : integer := 50;       
-  constant FLD_FD_MAX_RANGE       : integer := 64;
-
-
+  -- constant FLD_PULSE_LENGTH       : integer := 12;       
+  -- constant FLD_MIN_FREQ_DIV       : integer := 25;      
+  -- constant FLD_FD_MULT            : integer := 50;       
+  -- constant FLD_FD_MAX_RANGE       : integer := 64;
 
   -- --------------------------------------------------------------------------------------
@@ -414,7 +412,4 @@
   constant FLD_FD_MAX_RANGE_BASIC       : integer := 64;
 
-
-  
-  
   -- Timing counter
   constant TC_WIDTH         : integer := 48;