Changeset 10883 for firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl
- Timestamp:
- 05/27/11 17:51:42 (14 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl
- Files:
-
- 3 edited
-
fad_main_tb_struct.vhd (modified) (16 diffs)
-
trigger__generator_beha.vhd (modified) (1 diff)
-
w5300_emulator_beha.vhd (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
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firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/fad_main_tb_struct.vhd
r10225 r10883 3 3 -- Created: 4 4 -- by - daqct3.UNKNOWN (IHP110) 5 -- at - 18:33:01 02.03.20115 -- at - 22:55:01 26.05.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 21 21 -- Created: 22 22 -- by - daqct3.UNKNOWN (IHP110) 23 -- at - 18:33:01 02.03.201123 -- at - 22:55:01 26.05.2011 24 24 -- 25 25 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) … … 47 47 SIGNAL CLK_25_PS : std_logic; 48 48 SIGNAL CLK_50 : std_logic; 49 -- for debugging 50 SIGNAL DG_state : std_logic_vector(7 DOWNTO 0); 49 51 SIGNAL D_T_in : std_logic_vector(1 DOWNTO 0); 52 SIGNAL FTM_RS485_rx_d : std_logic; 53 SIGNAL FTM_RS485_rx_en : std_logic; 54 SIGNAL FTM_RS485_tx_d : std_logic; 55 SIGNAL FTM_RS485_tx_en : std_logic; 50 56 SIGNAL REF_CLK : STD_LOGIC := '0'; 51 57 SIGNAL RSRLOAD : std_logic := '0'; … … 69 75 SIGNAL crate_id : std_logic_vector(1 DOWNTO 0); 70 76 SIGNAL dac_cs : std_logic; 77 SIGNAL debug_data_ram_empty : std_logic; 78 SIGNAL debug_data_valid : std_logic; 71 79 SIGNAL denable : std_logic := '0'; -- default domino wave off 72 80 SIGNAL drs_channel_id : std_logic_vector(3 DOWNTO 0) := (others => '0'); … … 74 82 SIGNAL green : std_logic; 75 83 SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); 84 SIGNAL mem_manager_state : std_logic_vector(3 DOWNTO 0); -- state is encoded here ... useful for debugging. 76 85 SIGNAL mosi : std_logic := '0'; 77 86 SIGNAL plllock_in : std_logic_vector(3 DOWNTO 0); -- high level, if dominowave is running and DRS PLL locked … … 80 89 SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0); 81 90 SIGNAL sio : std_logic; 91 SIGNAL socket_tx_free_out : std_logic_vector(16 DOWNTO 0); -- 17bit value .. that's true 82 92 SIGNAL trigger : std_logic; 93 SIGNAL trigger_veto : std_logic := '1'; 94 SIGNAL w5300_state : std_logic_vector(7 DOWNTO 0); -- state is encoded here ... useful for debugging. 83 95 SIGNAL wiz_addr : std_logic_vector(9 DOWNTO 0); 84 96 SIGNAL wiz_cs : std_logic := '1'; … … 98 110 CLK : IN std_logic ; 99 111 D_T_in : IN std_logic_vector (1 DOWNTO 0); 112 FTM_RS485_rx_d : IN std_logic ; 100 113 SROUT_in_0 : IN std_logic ; 101 114 SROUT_in_1 : IN std_logic ; … … 113 126 CLK_25_PS : OUT std_logic ; 114 127 CLK_50 : OUT std_logic ; 128 -- for debugging 129 DG_state : OUT std_logic_vector (7 DOWNTO 0); 130 FTM_RS485_rx_en : OUT std_logic ; 131 FTM_RS485_tx_d : OUT std_logic ; 132 FTM_RS485_tx_en : OUT std_logic ; 115 133 RSRLOAD : OUT std_logic := '0'; 116 134 SRCLK : OUT std_logic := '0'; … … 122 140 counter_result : OUT std_logic_vector (11 DOWNTO 0); 123 141 dac_cs : OUT std_logic ; 142 debug_data_ram_empty : OUT std_logic ; 143 debug_data_valid : OUT std_logic ; 124 144 denable : OUT std_logic := '0'; -- default domino wave off 125 145 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); … … 127 147 green : OUT std_logic ; 128 148 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); 149 mem_manager_state : OUT std_logic_vector (3 DOWNTO 0); -- state is encoded here ... useful for debugging. 129 150 mosi : OUT std_logic := '0'; 130 151 red : OUT std_logic ; 131 152 sclk : OUT std_logic ; 132 153 sensor_cs : OUT std_logic_vector (3 DOWNTO 0); 154 socket_tx_free_out : OUT std_logic_vector (16 DOWNTO 0); -- 17bit value .. that's true 155 trigger_veto : OUT std_logic := '1'; 156 w5300_state : OUT std_logic_vector (7 DOWNTO 0); -- state is encoded here ... useful for debugging. 133 157 wiz_addr : OUT std_logic_vector (9 DOWNTO 0); 134 158 wiz_cs : OUT std_logic := '1'; … … 186 210 data : INOUT std_logic_vector (15 DOWNTO 0); 187 211 rd : IN std_logic ; 212 cs : IN std_logic ; 188 213 wr : IN std_logic 189 214 ); … … 237 262 CLK => clk, 238 263 D_T_in => D_T_in, 264 FTM_RS485_rx_d => FTM_RS485_rx_d, 239 265 SROUT_in_0 => SROUT_in_0, 240 266 SROUT_in_1 => SROUT_in_1, … … 252 278 CLK_25_PS => CLK_25_PS, 253 279 CLK_50 => CLK_50, 280 DG_state => DG_state, 281 FTM_RS485_rx_en => FTM_RS485_rx_en, 282 FTM_RS485_tx_d => FTM_RS485_tx_d, 283 FTM_RS485_tx_en => FTM_RS485_tx_en, 254 284 RSRLOAD => RSRLOAD, 255 285 SRCLK => SRCLK, … … 261 291 counter_result => counter_result, 262 292 dac_cs => dac_cs, 293 debug_data_ram_empty => debug_data_ram_empty, 294 debug_data_valid => debug_data_valid, 263 295 denable => denable, 264 296 drs_channel_id => drs_channel_id, … … 266 298 green => green, 267 299 led => led, 300 mem_manager_state => mem_manager_state, 268 301 mosi => mosi, 269 302 red => red, 270 303 sclk => sclk, 271 304 sensor_cs => sensor_cs, 305 socket_tx_free_out => socket_tx_free_out, 306 trigger_veto => trigger_veto, 307 w5300_state => w5300_state, 272 308 wiz_addr => wiz_addr, 273 309 wiz_cs => wiz_cs, … … 329 365 data => wiz_data, 330 366 rd => wiz_rd, 367 cs => wiz_cs, 331 368 wr => wiz_wr 332 369 ); -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/trigger__generator_beha.vhd
r9912 r10883 34 34 trigger <= '0'; 35 35 wait for TRIGGER_RATE; 36 --trigger <= '1';36 trigger <= '1'; 37 37 wait for PULSE_WIDTH; 38 38 trigger <= '0'; -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/w5300_emulator_beha.vhd
r10240 r10883 49 49 wait for 150 us; 50 50 RSR_1 <= X"0001"; 51 wait for 100 us;51 wait for 500 us; 52 52 RSR_1 <= X"0002"; 53 wait for 500 us;53 wait for 1000 us; 54 54 FIFOR_CNT <= 1; 55 wait for 100 us; 55 wait for 1000 us; 56 RSR_1 <= X"0004"; 57 56 58 FIFOR_CNT <= 2; 57 wait for 200 us;59 wait for 40 us; 58 60 FIFOR_CNT <= 3; 59 wait for 200 ns; 61 62 wait for 200000 us; 60 63 RSR_1 <= X"0000"; 61 wait for 2ms;62 RSR_1 <= X"0002";63 FIFOR_CNT <= 2;64 -- wait for 1 ms; 65 -- RSR_1 <= X"0002"; 66 -- FIFOR_CNT <= 2; 64 67 65 wait for 6 ms;66 int <= '0';68 -- wait for 6 ms; 69 -- int <= '0'; 67 70 68 71 -- wait for 1 ms; … … 95 98 96 99 elsif (FIFOR_CNT = 1) then 97 data_temp <= X" 2200";100 data_temp <= X"A000"; 98 101 99 102 elsif (FIFOR_CNT = 2) then
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