Changeset 10886
- Timestamp:
- 05/31/11 09:35:55 (14 years ago)
- File:
-
- 1 edited
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firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_interface.vhd
r10178 r10886 4 4 5 5 ENTITY w5300_modul IS 6 generic( 7 TIME_UNTIL_READ_READY : integer := 4; 8 TIME_UNTIL_READ_READY : integer := 4; 9 ); 6 10 PORT( 7 11 clk : IN std_logic; -- expecting 50MHz 8 12 9 wiz_reset _o : OUT std_logic := '1';10 cs _o : OUT std_logic := '1';11 wr _o : OUT std_logic := '1';12 rd _o : OUT std_logic := '1';13 int _o: IN std_logic;13 wiz_reset : OUT std_logic; 14 cs : OUT std_logic; 15 wr : OUT std_logic; 16 rd : OUT std_logic; 17 int : IN std_logic; 14 18 wiz_data : INOUT std_logic_vector (15 DOWNTO 0); 15 19 wiz_addr : OUT std_logic_vector (9 DOWNTO 0); 16 20 17 read_not_wirte : IN std_logic; 18 start_i : IN std_logic; 19 valid_next : OUT std_logic :='0'; 21 read_i : IN std_logic; 22 write_i : IN std_logic; 20 23 addr_i : IN std_logic_vector (9 DOWNTO 0); 21 24 data_o : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); … … 29 32 signal data_signal : std_logic_vector (15 DOWNTO 0) := (others => 'Z'); 30 33 signal addr_signal : std_logic_vector (9 DOWNTO 0) := (others => '0'); 34 35 36 -- this counter counts the time, the cs signal is low in units of 1/clk_period 37 -- since it is increased already in IDLE state, it really 38 signal wait_ctr : integer range 0 to 15 := 0; 39 31 40 32 41 main_process: process(clk) 33 begin 42 begin 43 if rising__edge(clk) then 44 -- synch in read & write commands 45 read_sr <= read_sr(0) & read_i; 46 write_sr <= write_sr(0) & write_i; 34 47 35 rd_o <= read_not_write_signal; 36 wr_o <= not read_not_write_signal; 37 wiz_data <= data_signal; 38 wiz_addr <= addr_signal; 48 case state is 49 -- this state seems to lose 20ns of worthy time, but this is only true for single transmissions 50 -- in case of continuous transmissions the W5300 datasheet demands min. 28ns time with CS high. 51 -- this means min. 2 states @ a 50MHz clock. 52 -- this is ensured by the IDLE state and a certain 'wait'-state and the end of each transmission. 53 when IDLE => 54 if (read_sr = "01" ) then 55 data_signal <= (others => 'Z'); 56 addr_sig <= addr_i; 57 wait_ctr <= wait_ctr + 1; 58 state <= READ_STATE; 59 elsif (write_sr = "01" ) then 60 data_signal <= data_i; 61 addr_sig <= addr_i; 62 wait_ctr <= wait_ctr + 1; 63 state <= WRITE_STATE; 64 end if; 65 66 when READ_STATE => 67 cs <= '0'; 68 wr <= '1'; 69 rd <= '0'; 70 wiz_addr <= addr_sig; 71 wiz_data <= data_signal; 72 wait_ctr <= wait_ctr + 1; 73 state <= READ_WAIT; 74 75 when WRITE_STATE => 76 cs <= '0'; 77 wr <= '0'; 78 rd <= '1'; 79 wiz_addr <= addr_sig; 80 wiz_data <= data_signal; 81 wait_ctr <= wait_ctr + 1; 82 state <= WRITE_WAIT; 39 83 40 if rising__edge(clk) then 41 42 case state is 43 44 when BEFORE DO SOMETING => 45 46 when CS_LOW => 47 cs_o <= '0'; 48 state <= WAIT_ONCE; 49 50 when AFTER_20ns => 51 state <= WAIT_TWICE; 52 53 when AFTER_40ns => 54 if (read_not_write_signal = '1') then 55 valid_next <= '1'; 56 state <= OUTPUT_DATA; 57 else 58 state <= INPUT_SAMPLING; 59 end if; 60 61 62 state <= DO_SOMETHING_ELSE; 63 64 when OUTPUT_DATA => 65 66 if (read_not_write_signal = '1') then 67 data_o <= wiz_data; 68 end if; 69 70 when INPUT_SAMPLING => 71 cs_o <= '1'; 72 addr_signal <= addr_i; 73 read_not_write_signal <= read_not_write; 74 if (read_not_write = '1') then 75 data_signal <= (others => 'Z'); 76 else 77 data_signal <= data_i; 78 end if; 79 wiz_addr <= addr_i; 80 81 if (start_i = '1') then 82 idle_next = '0'; 83 state <= CS_LOW; 84 else 85 state <= INPUT_SAMPLING; 86 87 when READ_REG => 88 case count is 89 when "000" => 90 cs <= '0'; 91 rd <= '0'; 92 wr <= '1'; 93 data <= (others => 'Z'); -- !!!!!!!!!! 94 count <= "001"; 95 addr <= par_addr; 96 97 1x WARTEN 98 99 1x WARTEN 100 101 when "100" => 102 data_read <= data; 103 count <= "110"; 104 105 1x WARTEN 106 107 when "111" => 108 cs <= '1'; 109 rd <= '1'; 110 count <= "000"; 111 state_init <= next_state; 112 113 when WRITE_REG => 114 case count is 115 when "000" => 116 cs <= '0'; 117 wr <= '0'; 118 rd <= '1'; 119 addr <= par_addr; 120 if (ram_access = '1') then 121 data <= ram_data; 122 else 123 data <= par_data; 124 end if; 125 count <= "100"; 126 127 1x WARTEN 128 129 1x WARTEN 130 131 when "110" => 132 cs <= '1'; 133 wr <= '1'; 134 state_init <= next_state; 135 count <= "000"; 136 when others => 137 null; 138 end case; 139 140 when others => 141 null; 142 enf if; -- rising_edge(clk) 84 -- actually WRITE ACCESS needs less time than READ access. 85 -- but in order to make an easy timed interface to this entity possible 86 -- I decided to wait exactly the same time. 87 -- anyway after min. 42ns (i.e. 60ns in case of 50MHz) the read reasult may be synched in. 88 89 when READ_WAIT => 90 if (wait_ctr = TIME_UNTIL_READ_READY - 1) then 91 wait_ctr = 0; 92 data_signal <= wiz_data; 93 state <= CLEANUP; 94 end if; 95 wait_ctr <= wait_ctr + 1; 96 97 when WRITE_WAIT 98 if (wait_ctr = TIME_UNTIL_WRITE_READY - 1) then 99 wait_ctr = 0; 100 state <= CLEANUP; 101 end if; 102 wait_ctr <= wait_ctr + 1; 103 104 when CLEANUP => 105 cs <= '1'; 106 wr <= '1'; 107 rd <= '1'; 108 data_o <= data_sigal; 109 wiz_addr <= (others => 'Z'); 110 wiz_data <= (others => 'Z'); 111 state <= IDLE; 112 113 end case; 114 115 end if; -- rising_edge(clk) 116 143 117 end process main_process;
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