Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_interface.vhd
===================================================================
--- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_interface.vhd	(revision 10885)
+++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_interface.vhd	(revision 10886)
@@ -4,18 +4,21 @@
 
 ENTITY w5300_modul IS
+  generic(
+    TIME_UNTIL_READ_READY : integer := 4;
+	TIME_UNTIL_READ_READY : integer := 4;
+  );
 PORT(
 	clk							: IN	std_logic;						-- expecting 50MHz
 	
-	wiz_reset_o					: OUT	std_logic						:= '1';
-	cs_o						: OUT	std_logic						:= '1';
-	wr_o						: OUT	std_logic						:= '1';
-	rd_o						: OUT	std_logic						:= '1';
-	int_o						: IN	std_logic;
+	wiz_reset					: OUT	std_logic;
+	cs							: OUT	std_logic;
+	wr							: OUT	std_logic;
+	rd							: OUT	std_logic;
+	int							: IN	std_logic;
 	wiz_data					: INOUT	std_logic_vector (15 DOWNTO 0);
 	wiz_addr					: OUT	std_logic_vector (9 DOWNTO 0);
 	
-	read_not_wirte				: IN	std_logic;
-	start_i						: IN	std_logic;
-	valid_next					: OUT	std_logic						:='0';
+	read_i						: IN	std_logic;
+	write_i						: IN	std_logic;
 	addr_i						: IN	std_logic_vector (9 DOWNTO 0);
 	data_o						: OUT	std_logic_vector (15 DOWNTO 0)	:= (others => '0');
@@ -29,115 +32,86 @@
 	signal data_signal : std_logic_vector (15 DOWNTO 0) := (others => 'Z');
 	signal addr_signal : std_logic_vector (9 DOWNTO 0) := (others => '0');
+
+	
+	-- this counter counts the time, the cs signal is low in units of 1/clk_period
+	-- since it is increased already in IDLE state, it really 
+	signal wait_ctr : integer range 0 to 15 := 0;  
+	
 	
 main_process: process(clk)
-begin
+	begin
+	if rising__edge(clk) then
+		-- synch in read & write commands
+		read_sr 	<= read_sr(0) 	& read_i;
+		write_sr 	<= write_sr(0) 	& write_i;
 
-rd_o <= read_not_write_signal;
-wr_o <= not read_not_write_signal;
-wiz_data <= data_signal;
-wiz_addr <= addr_signal;
+		case state is
+			-- this state seems to lose 20ns of worthy time, but this is only true for single transmissions
+			-- in case of continuous transmissions the W5300 datasheet demands min. 28ns time with CS high.
+			-- this means min. 2 states @ a 50MHz clock.
+			-- this is ensured by the IDLE state and a certain 'wait'-state and the end of each transmission.
+			when IDLE =>
+				if (read_sr = "01" ) then
+					data_signal <= (others => 'Z');
+					addr_sig <= addr_i;
+					wait_ctr <= wait_ctr + 1;
+					state <= READ_STATE;
+				elsif (write_sr = "01" ) then
+					data_signal <= data_i;	
+					addr_sig <= addr_i;
+					wait_ctr <= wait_ctr + 1;
+					state <= WRITE_STATE;
+				end if;
+			
+			when READ_STATE =>
+				cs <= '0';
+				wr <= '1';
+				rd <= '0';
+				wiz_addr <= addr_sig;
+				wiz_data <= data_signal;
+				wait_ctr <= wait_ctr + 1;
+				state <= READ_WAIT;
+				
+			when WRITE_STATE =>
+				cs <= '0';
+				wr <= '0';
+				rd <= '1';
+				wiz_addr <= addr_sig;
+				wiz_data <= data_signal;
+				wait_ctr <= wait_ctr + 1;
+				state <= WRITE_WAIT;
 
-if rising__edge(clk) then
-
-	case state is
-	
-	when BEFORE DO SOMETING		=>
-		
-	when CS_LOW	=>
-		cs_o <= '0';
-		state <= WAIT_ONCE;
-		
-	when AFTER_20ns	=>
-		state <= WAIT_TWICE;
-		
-	when AFTER_40ns	=>
-		if (read_not_write_signal = '1') then
-			valid_next <= '1';
-			state <= OUTPUT_DATA;
-		else
-			state <= INPUT_SAMPLING;
-		end if;
-		
-		
-		state <= DO_SOMETHING_ELSE;
-		
-	when OUTPUT_DATA	=>
-		
-		if (read_not_write_signal = '1') then
-			data_o <= wiz_data;
-		end if;
-		
-	when INPUT_SAMPLING	=>
-		cs_o <= '1';
-		addr_signal <= addr_i;
-		read_not_write_signal <= read_not_write;
-		if (read_not_write = '1') then
-			data_signal <= (others => 'Z');
-		else
-			data_signal <= data_i;
-		end if;
-		wiz_addr <= addr_i;
-	
-		if (start_i = '1') then
-			idle_next = '0';
-			state <= CS_LOW;
-		else
-			state <= INPUT_SAMPLING;
-	
-					when READ_REG =>
-						case count is
-							when "000" =>
-								cs <= '0';
-								rd <= '0';
-								wr <= '1';
-								data <= (others => 'Z'); -- !!!!!!!!!!
-								count <= "001";
-								addr <= par_addr;
-							
-							1x WARTEN
-							
-							1x WARTEN
-							
-							when "100" =>
-								data_read <= data;
-								count <= "110";
-							
-							1x WARTEN
-							
-							when "111" =>
-								cs <= '1';
-								rd <= '1';
-								count <= "000";
-								state_init <= next_state;
-
-					when WRITE_REG =>
-						case count is
-							when "000" =>
-								cs <= '0';
-								wr <= '0';
-								rd <= '1';
-								addr <= par_addr; 
-								if (ram_access = '1') then
-									data <= ram_data;
-								else
-									data <= par_data;
-								end if;
-								count <= "100";
-							
-							1x WARTEN
-							
-							1x WARTEN
-							
-							when "110" =>
-								cs <= '1';
-								wr <= '1';
-								state_init <= next_state;
-								count <= "000";
-							when others =>
-								null;
-						end case;
-					
-					when others =>
-						null;
-enf if; -- rising_edge(clk)						
+			-- actually WRITE ACCESS needs less time than READ access. 
+			-- but in order to make an easy timed interface to this entity possible 
+			-- I decided to wait exactly the same time.
+			-- anyway after min. 42ns (i.e. 60ns in case of 50MHz) the read reasult may be synched in.
+			
+			when READ_WAIT =>
+				if (wait_ctr = TIME_UNTIL_READ_READY - 1) then
+					wait_ctr = 0;
+					data_signal <= wiz_data;
+					state <= CLEANUP;
+				end if;
+				wait_ctr <= wait_ctr + 1;
+				
+			when WRITE_WAIT
+				if (wait_ctr = TIME_UNTIL_WRITE_READY - 1) then
+					wait_ctr = 0;
+					state <= CLEANUP;
+				end if;
+				wait_ctr <= wait_ctr + 1;
+			
+			when CLEANUP =>
+				cs <= '1';
+				wr <= '1';
+				rd <= '1';
+				data_o <= data_sigal;
+				wiz_addr <= (others => 'Z');
+				wiz_data <= (others => 'Z');
+				state <= IDLE;
+				
+			end case;
+			
+	end if; -- rising_edge(clk)
+						
 end process main_process;