Changeset 10888 for firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib

Timestamp:

05/31/11 17:00:37 (13 years ago)

Author:

neise

Message:

- not yet tested; not yet simulated - 
w5300_modul2.vhd implements the new w5300_interface entity.

it is not really getting simpler, but maybe we are on a good way anyway.

Location:

firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl

Files:

• fad_definitions.vhd (modified) (1 diff)
• w5300_interface.vhd (modified) (5 diffs)
• w5300_modul2.vhd (added)

firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd

@@ -182 +182 @@
 
 
+constant TIME_UNTIL_READ_READY : integer := 4;
+constant TIME_UNTIL_WRITE_READY : integer := 4;
+
+
+--      FUNCTION wait_if_started ( 
+--              signal sr : std_logic_vector(2 downto 0)
+--              ) RETURN std_logic;
+--
+
+
 end fad_definitions;
+
+--PACKAGE BODY fad_definitions is
+--
+--      FUNCTION wait_if_started ( 
+--              signal sr : std_logic_vector(2 downto 0)
+--              ) RETURN std_logic IS
+--              
+--      BEGIN
+--      
+--      
+--      
+--      END FUNCTION wait_if_started;
+--              
+--
+--END fad_definitions;

firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_interface.vhd

@@ -3 +3 @@
 use IEEE.NUMERIC_STD.all;
 
-ENTITY w5300_modul IS
-  generic(
-    TIME_UNTIL_READ_READY : integer := 4;
-        TIME_UNTIL_READ_READY : integer := 4;
-  );
+library FACT_FAD_lib;
+use FACT_FAD_lib.fad_definitions.ALL;
+
+ENTITY w5300_interface IS
 PORT(
         clk                                                     : IN    std_logic;                                              -- expecting 50MHz
@@ -24 +23 @@
         data_o                                          : OUT   std_logic_vector (15 DOWNTO 0)  := (others => '0');
         data_i                                          : IN    std_logic_vector (15 DOWNTO 0);
-        
+        ready_o                                         : OUT   std_logic := '0';
+        reset_i                                         : IN    std_logic
 );
-END w5300_modul ;
+END w5300_interface ;
 
-architecture Behavioral of w5300_modul is
-        signal read_not_write_signal : std_logic := '1';
+architecture Behavioral of w5300_interface is
+
+        type state_type is (
+                RESET_WIZ,
+                IDLE,
+                --READ_STATE, 
+                READ_WAIT,
+                --WRITE_STATE, 
+                WRITE_WAIT
+--              ,CLEANUP
+                
+        );
+        signal state : state_type;
+
         signal data_signal : std_logic_vector (15 DOWNTO 0) := (others => 'Z');
         signal addr_signal : std_logic_vector (9 DOWNTO 0) := (others => '0');
 
+    signal read_sr : std_logic_vector (1 DOWNTO 0) := (others => '0');
+    signal write_sr : std_logic_vector (1 DOWNTO 0) := (others => '0');
         
         -- this counter counts the time, the cs signal is low in units of 1/clk_period
         -- since it is increased already in IDLE state, it really 
         signal wait_ctr : integer range 0 to 15 := 0;  
+        signal RST_TIME : integer range 0 to 500000 := 500000;  
+
+        signal reset_counter : integer range 0 to RST_TIME := 0;  
+        signal ready : std_logic := '0';
+begin
         
+main_process : process(clk)
+        begin
         
-main_process: process(clk)
-        begin
-        if rising__edge(clk) then
+        ready_o <= ready and not write_i and not read_i;
+        
+        if rising_edge(clk) then
                 -- synch in read & write commands
                 read_sr         <= read_sr(0)   & read_i;
                 write_sr        <= write_sr(0)  & write_i;
+
+                --synthesis translate_off
+                RST_TIME <= 288;
+                --synthesis translate_on
+
 
                 case state is
@@ -52 +78 @@
                         -- this is ensured by the IDLE state and a certain 'wait'-state and the end of each transmission.
                         when IDLE =>
-                                if (read_sr = "01" ) then
-                                        data_signal <= (others => 'Z');
-                                        addr_sig <= addr_i;
-                                        wait_ctr <= wait_ctr + 1;
-                                        state <= READ_STATE;
-                                elsif (write_sr = "01" ) then
-                                        data_signal <= data_i;  
-                                        addr_sig <= addr_i;
-                                        wait_ctr <= wait_ctr + 1;
-                                        state <= WRITE_STATE;
+                                cs <= '1';
+                                wr <= '1';
+                                rd <= '1';
+                                ready <= '1';
+                                
+                                
+                                if (read_i = '1' ) then
+                                        cs <= '0';
+                                        wr <= '1';
+                                        rd <= '0';
+                                        ready <= '0';
+                                        
+                                        wiz_addr <= addr_i;
+                                        wiz_data <= (others => 'Z');
+                                        state <= READ_WAIT;
+                                        
+                                elsif (write_i = '1' ) then
+                                        cs <= '0';
+                                        wr <= '0';
+                                        rd <= '1';
+                                        ready <= '0';
+                                        
+                                        wiz_addr <= addr_i;
+                                        wiz_data <= data_i;
+
+                                        state <= WRITE_WAIT;
+                                end if;
+                                
+                                if (reset_i = '1') then
+                                        state <= RESET_WIZ;
                                 end if;
                         
-                        when READ_STATE =>
-                                cs <= '0';
-                                wr <= '1';
-                                rd <= '0';
-                                wiz_addr <= addr_sig;
-                                wiz_data <= data_signal;
-                                wait_ctr <= wait_ctr + 1;
-                                state <= READ_WAIT;
-                                
-                        when WRITE_STATE =>
-                                cs <= '0';
-                                wr <= '0';
-                                rd <= '1';
-                                wiz_addr <= addr_sig;
-                                wiz_data <= data_signal;
-                                wait_ctr <= wait_ctr + 1;
-                                state <= WRITE_WAIT;
-
+--                      when READ_STATE =>
+--                              cs <= '0';
+--                              wr <= '1';
+--                              rd <= '0';
+--                              wiz_addr <= addr_signal;
+--                              wiz_data <= data_signal;
+--                              wait_ctr <= wait_ctr + 1;
+--                              state <= READ_WAIT;
+--                              
+--                      when WRITE_STATE =>
+--                              cs <= '0';
+--                              wr <= '0';
+--                              rd <= '1';
+--                              wiz_addr <= addr_signal;
+--                              wiz_data <= data_signal;
+--                              wait_ctr <= wait_ctr + 1;
+--                              state <= WRITE_WAIT;
+--
                         -- actually WRITE ACCESS needs less time than READ access. 
                         -- but in order to make an easy timed interface to this entity possible 
@@ -88 +134 @@
                         
                         when READ_WAIT =>
+                                wait_ctr <= wait_ctr + 1;
                                 if (wait_ctr = TIME_UNTIL_READ_READY - 1) then
-                                        wait_ctr = 0;
-                                        data_signal <= wiz_data;
-                                        state <= CLEANUP;
+                                        cs <= '1';
+                                        wr <= '1';
+                                        rd <= '1';
+                                        ready <= '1';
+                                        
+                                        wait_ctr <= 0;
+                                        data_o <= wiz_data;
+
+                                        state <= IDLE;
                                 end if;
+                                
+                                
+                        when WRITE_WAIT =>
                                 wait_ctr <= wait_ctr + 1;
+                                if (wait_ctr = TIME_UNTIL_WRITE_READY - 1) then
+                                        cs <= '1';
+                                        wr <= '1';
+                                        rd <= '1';
+                                        ready <= '1';
+                                        
+                                        wait_ctr <= 0;
+                                        data_o <= (others => 'Z');
+
+                                        state <= IDLE;
+                                end if;
                                 
-                        when WRITE_WAIT
-                                if (wait_ctr = TIME_UNTIL_WRITE_READY - 1) then
-                                        wait_ctr = 0;
-                                        state <= CLEANUP;
-                                end if;
-                                wait_ctr <= wait_ctr + 1;
                         
-                        when CLEANUP =>
+--                      when CLEANUP =>
+--                              ready <= '1';
+--                              cs <= '1';
+--                              wr <= '1';
+--                              rd <= '1';
+--                              data_o <= data_signal;
+--                              wiz_addr <= (others => 'Z');
+--                              wiz_data <= (others => 'Z');
+--                              state <= IDLE;
+                                
+                        when RESET_WIZ => 
+                                ready <= '0';
                                 cs <= '1';
                                 wr <= '1';
                                 rd <= '1';
-                                data_o <= data_sigal;
-                                wiz_addr <= (others => 'Z');
-                                wiz_data <= (others => 'Z');
-                                state <= IDLE;
+                                
+                                reset_counter <= reset_counter + 1;
+                                wiz_reset <= '0';
+                                if (reset_counter >= 100) then -- wait 2µs
+                                        wiz_reset <= '1';
+                                end if; 
+                                if (reset_counter >= RST_TIME -1) then -- wait 10ms
+                                        reset_counter <= 0;
+                                        
+                                        state <= IDLE;
+                                end if;                         
                                 
                         end case;
@@ -116 +195 @@
                                                 
 end process main_process;
+
+end Behavioral;