- Timestamp:
- 06/01/11 08:09:24 (13 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul2.vhd
r10888 r10891 8 8 9 9 ENTITY w5300_modul2 IS 10 generic( 11 RAM_ADDR_WIDTH : integer := 14 12 ); 10 13 11 PORT( 14 12 state : OUT std_logic_vector (7 DOWNTO 0); -- state is encoded here ... useful for debugging. … … 16 14 debug_data_valid : OUT std_logic; 17 15 data_generator_idle_i : IN std_logic; 18 socket_tx_free_out : out std_logic_vector (16 DOWNTO 0); -- 17bit value .. that's true19 16 20 17 clk : IN std_logic; … … 27 24 rd : OUT std_logic := '1'; 28 25 29 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');30 26 31 27 int : IN std_logic; 32 28 write_length : IN std_logic_vector (16 DOWNTO 0); 33 ram_start_addr : IN std_logic_vector ( RAM_ADDR_WIDTH-1 DOWNTO 0);29 ram_start_addr : IN std_logic_vector (W5300_RAM_ADDR_WIDTH-1 DOWNTO 0); 34 30 ram_data : IN std_logic_vector (15 DOWNTO 0); 35 ram_addr : OUT std_logic_vector ( RAM_ADDR_WIDTH-1 DOWNTO 0);31 ram_addr : OUT std_logic_vector (W5300_RAM_ADDR_WIDTH-1 DOWNTO 0); 36 32 data_valid : IN std_logic; 37 33 data_valid_ack : OUT std_logic := '0'; … … 123 119 SI, SI1, SI1b, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, 124 120 125 CONFIG, WAIT_100NS, WAIT_UNTIL_DG_IDLE, WAIT_FOR_DATA_RAM_EMPTY, -- <-- this is THE deadlock state121 CONFIG, WAIT_100NS, WAIT_UNTIL_DG_IDLE, 126 122 CONFIG_MEMORY_MANAGER, WAIT_FOR_CONFIG_MEMORY_MANAGER, 127 123 CONFIG_DATA_GENERATOR, WAIT_FOR_CONFIG_DATA_GENERATOR, … … 130 126 MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA 131 127 ); 128 132 129 type state_write_type is ( 133 130 WR_START, … … 135 132 WR_MOD7_STARTED, WR_WAIT_FOR_MOD7, 136 133 WR_CHECK_FOR_FIFO_SPACE_01, WR_CHECK_FOR_FIFO_SPACE_02, WR_CHECK_FOR_FIFO_SPACE_03, WR_CHECK_FOR_FIFO_SPACE_04, 137 WR_05 , WR_05_PREPARE_LENGTH_INFO, WR_05_POSTPREPARE_LENGTH_INFO,138 WR_ 05a, WR_05b, WR_06, WR_07,134 WR_05_PREPARE_LENGTH_INFO, WR_05_POSTPREPARE_LENGTH_INFO, 135 WR_STRANGE_WAIT, 139 136 WR_ACK, WR_WAIT_FOR_ACK, 140 137 WR_HEADER_FETCH, WR_HEADER_WAIT, WR_HEADER, 141 142 138 WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2, 143 WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2 , WR_ENDFLAG3139 WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2 144 140 ); 145 141 type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04); 146 type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06); 142 type state_interrupt_2_type is ( 143 IR2_GET_IR, 144 IR2_CHECK_WHICH_SN_IRQ, 145 IR2_GET_SN_IR, 146 IR2_CLEAR_SN_IR, 147 IR2_SEND_DISCON, 148 IR2_GET_SOCKn_STATUS, 149 IR2_WAIT_SOCKn_CLOSED, 150 IR2_GOTO_RESET); 147 151 type state_read_data_type is ( 148 152 RD_1, … … 157 161 RD_END 158 162 ); 159 160 signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120"; 161 162 signal par_addr : std_logic_vector (9 downto 0) := (OTHERS => '0'); 163 signal par_data : std_logic_vector (15 downto 0) := (OTHERS => '0'); 164 signal data_read : std_logic_vector (15 downto 0) := (OTHERS => '0'); 165 signal adc_data_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); 166 167 signal state_init, next_state , next_state_tmp : state_init_type := RESET; 168 signal count : std_logic_vector (2 downto 0) := "000"; 163 signal state_init : state_init_type := RESET; 169 164 signal state_write : state_write_type := WR_START; 170 165 signal state_interrupt_1 : state_interrupt_1_type := IR1_01; 171 signal state_interrupt_2 : state_interrupt_2_type := IR2_ 01;166 signal state_interrupt_2 : state_interrupt_2_type := IR2_GET_IR; 172 167 signal state_read_data : state_read_data_type := RD_1; 168 169 signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120"; -- 0x7A120=500000 @50MHz --> 10ms 170 171 signal wiz_addr : std_logic_vector (9 downto 0) := (OTHERS => '0'); 172 signal wiz_data : std_logic_vector (15 downto 0) := (OTHERS => '0'); 173 signal data_read : std_logic_vector (15 downto 0) := (OTHERS => '0'); 174 signal adc_data_addr : std_logic_vector (W5300_RAM_ADDR_WIDTH-1 DOWNTO 0); 173 175 174 176 signal interrupt_ignore : std_logic := '1'; 175 177 signal int_flag : std_logic := '0'; 176 signal ram_access : std_logic := '0'; 177 178 signal zaehler : std_logic_vector (19 downto 0) := (OTHERS => '0'); 179 signal data_cnt : integer := 0; 180 signal drs_cnt : integer :=0; 178 179 signal data_cnt : integer range 0 to 7680 := 0; 180 signal data_end : integer range 0 to 7680 := 0; 181 signal drs_cnt : integer range 0 to 3 := 0; 181 182 signal channel_cnt : integer range 0 to 9 :=0; 182 signal socket_cnt : std_logic_vector (2 downto 0) := "000";183 signal roi_max : std_logic_vector (10 downto 0) ;184 signal data_end : integer := 0; 183 signal socket_cnt : integer range 0 to 7 := 0; 184 signal roi_max : std_logic_vector (10 downto 0) := (others => '0'); 185 185 186 186 187 signal socket_tx_free : std_logic_vector (16 downto 0) := (others => '0'); … … 204 205 205 206 signal local_write_length : std_logic_vector (16 DOWNTO 0); 206 signal local_ram_start_addr : std_logic_vector ( RAM_ADDR_WIDTH-1 DOWNTO 0);207 signal local_ram_addr : std_logic_vector ( RAM_ADDR_WIDTH-1 downto 0);207 signal local_ram_start_addr : std_logic_vector (W5300_RAM_ADDR_WIDTH-1 DOWNTO 0); 208 signal local_ram_addr : std_logic_vector (W5300_RAM_ADDR_WIDTH-1 downto 0); 208 209 signal local_socket_nr : std_logic_vector (2 DOWNTO 0); 209 210 signal local_write_header_flag, local_write_end_flag : std_logic; … … 352 353 read_i => read_wi, 353 354 write_i => write_wi, 354 addr_i => par_addr,355 addr_i => wiz_addr, 355 356 data_o => data_read, 356 data_i => par_data,357 data_i => wiz_data, 357 358 ready_o => ready_wi, 358 359 reset_i => reset_wi … … 390 391 write_wi <= '0'; 391 392 read_wi <= '0'; 392 --socket_tx_free_out <= socket_tx_free;393 393 394 395 -- synch asynchronous inputs in: 394 396 395 memory_manager_config_valid_i_sr <= memory_manager_config_valid_i_sr(0) & memory_manager_config_valid_i; 397 396 spi_interface_config_valid_i_sr <= spi_interface_config_valid_i_sr(0) & spi_interface_config_valid_i; 398 --data_generator_config_valid_i_sr <= data_generator_config_valid_i_sr(0) & data_generator_config_valid_i;399 397 data_ram_empty_sr <= data_ram_empty_sr(0) & data_ram_empty; 400 398 data_generator_idle_sr <= data_generator_idle_sr( 1 downto 0 ) & data_generator_idle_i; … … 413 411 case state_interrupt_1 is 414 412 when IR1_01 => 415 state_sig <= X"FF";416 413 int_flag <= '1'; 417 busy <= '1';418 414 state_interrupt_1 <= IR1_02; --wait one cycle 419 415 when IR1_02 => 420 state_sig <= X"FE";421 416 state_interrupt_1 <= IR1_03; 422 417 when IR1_03 => 423 state_sig <= X"FD";424 418 state_init <= INTERRUPT; 425 socket_cnt <= "000"; 426 ram_access <= '0'; 427 zaehler <= X"00000"; --what is this zaehler counting? 428 count <= "000"; --what is this count counting? 419 socket_cnt <= 0; 429 420 int_flag <= '0'; 430 421 interrupt_ignore <= '1'; 431 422 state_interrupt_1 <= IR1_04; --this state is not existing? bad coding habit??? 432 423 when others => 433 state_sig <= X"FC";434 424 null; 435 425 end case; … … 441 431 when INTERRUPT => 442 432 case state_interrupt_2 is 443 when IR2_ 01=>444 state_sig <= X"FB";445 par_addr <= W5300_IR;446 state_init <= READ_REG;447 next_state <= INTERRUPT;448 state_interrupt_2 <= IR2_02;433 when IR2_GET_IR => 434 if (ready_wi = '1') then 435 wiz_addr <= W5300_IR; 436 read_wi <= '1'; 437 state_interrupt_2 <= IR2_CHECK_WHICH_SN_IRQ; 438 end if; 449 439 450 440 -- check if it was a Sx Interrupt of Socket n 451 441 -- therfor: loop over all channel. 452 -- if the loop ended but no Sx Interrupt was found --> IR2_06 453 -- if an Sx Interrupt was found go to --> IR2_03 and check what happened. 454 when IR2_02 => 455 state_sig <= X"FA"; 456 if (data_read (conv_integer(socket_cnt)) = '1') then -- Sx Interrupt 457 state_interrupt_2 <= IR2_03; 458 else 442 -- if the loop ended but no Sx Interrupt was found --> IR2_GOTO_RESET 443 -- if an Sx Interrupt was found go to --> IR2_GET_SN_IR and check what happened. 444 when IR2_CHECK_WHICH_SN_IRQ => 445 if (ready_wi = '1') then 446 if (data_read(socket_cnt) = '1') then -- Sx Interrupt 447 state_interrupt_2 <= IR2_GET_SN_IR; 448 else 449 socket_cnt <= socket_cnt + 1; 450 if (socket_cnt = 7) then 451 state_interrupt_2 <= IR2_GOTO_RESET; 452 else 453 state_interrupt_2 <= IR2_CHECK_WHICH_SN_IRQ; -- go on with loop 454 end if; 455 end if; 456 end if; 457 458 -- check the Interrupt register of the Socket to be able to clear them 459 when IR2_GET_SN_IR => 460 if (ready_wi = '1') then 461 wiz_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register 462 read_wi <= '1'; 463 state_interrupt_2 <= IR2_CLEAR_SN_IR; 464 end if; 465 -- clear IRQs by writing ones. 466 when IR2_CLEAR_SN_IR => 467 if (ready_wi = '1') then 468 wiz_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; 469 wiz_data <= data_read; -- clear Interrupts 470 write_wi <= '1'; 471 state_interrupt_2 <= IR2_SEND_DISCON; 472 end if; 473 474 -- send the command to close this socket 475 -- then go back and read the main Interrupt register again, 476 -- if this was not Socket 7 ... if it was Socket 7, we're done anyway. 477 when IR2_SEND_DISCON => 478 if (ready_wi = '1') then 479 wiz_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; 480 wiz_data <= X"0008"; -- DISCON --> W5300 wil send FIN packet 481 write_wi <= '1'; 459 482 socket_cnt <= socket_cnt + 1; 483 460 484 if (socket_cnt = 7) then 461 state_interrupt_2 <= IR2_06; 485 socket_cnt = 0; 486 state_interrupt_2 <= IR2_WAIT_UNTIL_SOCKS_CLOSED; 462 487 else 463 state_interrupt_2 <= IR2_ 02; -- go on with loop488 state_interrupt_2 <= IR2_GET_IR; 464 489 end if; 465 490 end if; 466 491 467 -- check the Interrupt register of the Socket, which caused the Interrupt. 468 when IR2_03 => 469 state_sig <= X"F9"; 470 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register 471 state_init <= READ_REG; 472 next_state <= INTERRUPT; 473 state_interrupt_2 <= IR2_04; 474 -- before checking what happened, clear the Interrupt register, so we can proceed. 475 when IR2_04 => 476 state_sig <= X"F8"; 477 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; 478 par_data <= data_read; -- clear Interrupts 479 state_init <= WRITE_REG; 480 next_state <= INTERRUPT; 481 state_interrupt_2 <= IR2_05; 482 -- send the command to close this socket 483 -- then go back and read the main Interrupt register again, 484 -- if this was not Socket 7 ... if it was Socket 7, we're done anyway. 485 when IR2_05 => 486 state_sig <= X"F7"; 487 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; 488 par_data <= X"0010"; -- CLOSE 489 state_init <= WRITE_REG; 490 next_state <= INTERRUPT; 491 socket_cnt <= socket_cnt + 1; 492 if (socket_cnt = 7) then 493 state_interrupt_2 <= IR2_06; 494 else 495 state_interrupt_2 <= IR2_01; 496 end if; 497 498 -- we go on and reset, the W5300 and this entire state machine. 499 when IR2_06 => 492 when IR2_GET_SOCKn_STATUS => 493 if (ready_wi = '1') then 494 wiz_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; 495 read_wi = '1'; 496 state_interrupt_2 <= IR2_WAIT_SOCKn_CLOSED; 497 end if; 498 499 when IR2_WAIT_SOCKn_CLOSED => 500 if (ready_wi = '1') then 501 if (data_read = X"0000") then --closed 502 if (socket_cnt = 7) then 503 socket_cnt <= 0; 504 state_interrupt_2 <= IR2_GOTO_RESET; 505 else 506 socket_cnt <= socket_cnt + 1; 507 state_interrupt_2 <= IR2_GET_SOCKn_STATUS; 508 end if; 509 end if; 510 end if; 511 512 513 514 when IR2_GOTO_RESET => 500 515 state_sig <= X"F6"; 501 516 state_interrupt_1 <= IR1_01; 502 state_interrupt_2 <= IR2_ 01;503 socket_cnt <= "000";517 state_interrupt_2 <= IR2_GET_IR; 518 socket_cnt <= 0; 504 519 state_init <= RESET; 505 520 when others => 506 state_interrupt_1 <= IR1_01; 507 state_interrupt_2 <= IR2_01; 508 socket_cnt <= "000"; 509 state_init <= RESET; 510 end case; 521 null; 522 end case; 511 523 512 524 -- reset W5300 … … 518 530 socks_waiting <= '0'; 519 531 socks_connected <= '0'; 520 socket_cnt <= "000"; 521 count <= "000"; 522 ram_access <= '0'; 532 socket_cnt <= 0; 523 533 interrupt_ignore <= '0'; 524 534 … … 544 554 cid <= CrateID; 545 555 546 par_addr <= W5300_MR;547 par_data <= X"0000";556 wiz_addr <= W5300_MR; 557 wiz_data <= X"0000"; 548 558 if (ready_wi = '1') then 549 559 write_wi <= '1'; … … 606 616 when IM => 607 617 state_sig <= X"04"; 608 par_addr <= W5300_IMR;609 par_data <= X"00FF"; -- S0-S7 Interrupts618 wiz_addr <= W5300_IMR; 619 wiz_data <= X"00FF"; -- S0-S7 Interrupts 610 620 if (ready_wi = '1') then 611 621 write_wi <= '1'; … … 616 626 -- Memory Type 617 627 when MT => 618 par_addr <= W5300_MTYPER;619 par_data <= X"7FFF"; -- 8K RX, 120K TX-Buffer628 wiz_addr <= W5300_MTYPER; 629 wiz_data <= X"7FFF"; -- 8K RX, 120K TX-Buffer 620 630 if (ready_wi = '1') then 621 631 write_wi <= '1'; … … 625 635 -- Socket TX Memory Size 626 636 when STX0 => 627 par_addr <= W5300_TMS01R;628 par_data <= X"0F0F"; -- 15K TX637 wiz_addr <= W5300_TMS01R; 638 wiz_data <= X"0F0F"; -- 15K TX 629 639 if (ready_wi = '1') then 630 640 write_wi <= '1'; … … 632 642 end if; 633 643 when STX1 => 634 par_addr <= W5300_TMS23R;635 par_data <= X"0F0F"; -- 15K TX644 wiz_addr <= W5300_TMS23R; 645 wiz_data <= X"0F0F"; -- 15K TX 636 646 if (ready_wi = '1') then 637 647 write_wi <= '1'; … … 640 650 641 651 when STX2 => 642 par_addr <= W5300_TMS45R;643 par_data <= X"0F0F"; -- 15K TX652 wiz_addr <= W5300_TMS45R; 653 wiz_data <= X"0F0F"; -- 15K TX 644 654 if (ready_wi = '1') then 645 655 write_wi <= '1'; … … 648 658 649 659 when STX3 => 650 par_addr <= W5300_TMS67R;651 par_data <= X"0F0F"; -- 15K TX660 wiz_addr <= W5300_TMS67R; 661 wiz_data <= X"0F0F"; -- 15K TX 652 662 if (ready_wi = '1') then 653 663 write_wi <= '1'; … … 657 667 -- Socket RX Memory Size 658 668 when SRX0 => 659 par_data <= X"0101"; -- 1K RX660 par_addr <= W5300_RMS01R;669 wiz_data <= X"0101"; -- 1K RX 670 wiz_addr <= W5300_RMS01R; 661 671 if (ready_wi = '1') then 662 672 write_wi <= '1'; … … 664 674 end if; 665 675 when SRX1 => 666 par_data <= X"0101"; -- 1K RX667 par_addr <= W5300_RMS23R;676 wiz_data <= X"0101"; -- 1K RX 677 wiz_addr <= W5300_RMS23R; 668 678 if (ready_wi = '1') then 669 679 write_wi <= '1'; … … 671 681 end if; 672 682 when SRX2 => 673 par_data <= X"0101"; -- 1K RX674 par_addr <= W5300_RMS45R;683 wiz_data <= X"0101"; -- 1K RX 684 wiz_addr <= W5300_RMS45R; 675 685 if (ready_wi = '1') then 676 686 write_wi <= '1'; … … 678 688 end if; 679 689 when SRX3 => 680 par_data <= X"0101"; -- 1K RX681 par_addr <= W5300_RMS67R;690 wiz_data <= X"0101"; -- 1K RX 691 wiz_addr <= W5300_RMS67R; 682 692 if (ready_wi = '1') then 683 693 write_wi <= '1'; … … 687 697 -- MAC 688 698 when MAC0 => 689 par_addr <= W5300_SHAR;690 par_data <= mac_loc(0);699 wiz_addr <= W5300_SHAR; 700 wiz_data <= mac_loc(0); 691 701 if (ready_wi = '1') then 692 702 write_wi <= '1'; … … 695 705 696 706 when MAC1 => 697 par_addr <= W5300_SHAR + 2;698 par_data <= mac_loc(1);707 wiz_addr <= W5300_SHAR + 2; 708 wiz_data <= mac_loc(1); 699 709 if (ready_wi = '1') then 700 710 write_wi <= '1'; … … 702 712 end if; 703 713 when MAC2 => 704 par_addr <= W5300_SHAR + 4;705 par_data <= mac_loc(2);714 wiz_addr <= W5300_SHAR + 4; 715 wiz_data <= mac_loc(2); 706 716 if (ready_wi = '1') then 707 717 write_wi <= '1'; … … 711 721 -- Gateway 712 722 when GW0 => 713 par_addr <= W5300_GAR;714 par_data (15 downto 8) <= conv_std_logic_vector(gateway_loc(0),8);715 par_data (7 downto 0) <= conv_std_logic_vector(gateway_loc(1),8);723 wiz_addr <= W5300_GAR; 724 wiz_data (15 downto 8) <= conv_std_logic_vector(gateway_loc(0),8); 725 wiz_data (7 downto 0) <= conv_std_logic_vector(gateway_loc(1),8); 716 726 if (ready_wi = '1') then 717 727 write_wi <= '1'; … … 720 730 721 731 when GW1 => 722 par_addr <= W5300_GAR + 2;723 par_data (15 downto 8) <= conv_std_logic_vector(gateway_loc(2),8);724 par_data (7 downto 0) <= conv_std_logic_vector(gateway_loc(3),8);732 wiz_addr <= W5300_GAR + 2; 733 wiz_data (15 downto 8) <= conv_std_logic_vector(gateway_loc(2),8); 734 wiz_data (7 downto 0) <= conv_std_logic_vector(gateway_loc(3),8); 725 735 if (ready_wi = '1') then 726 736 write_wi <= '1'; … … 730 740 -- Subnet Mask 731 741 when SNM0 => 732 par_addr <= W5300_SUBR;733 par_data (15 downto 8) <= conv_std_logic_vector(netmask_loc(0),8);734 par_data (7 downto 0) <= conv_std_logic_vector(netmask_loc(1),8);742 wiz_addr <= W5300_SUBR; 743 wiz_data (15 downto 8) <= conv_std_logic_vector(netmask_loc(0),8); 744 wiz_data (7 downto 0) <= conv_std_logic_vector(netmask_loc(1),8); 735 745 if (ready_wi = '1') then 736 746 write_wi <= '1'; … … 738 748 end if; 739 749 when SNM1 => 740 par_addr <= W5300_SUBR + 2;741 par_data (15 downto 8) <= conv_std_logic_vector(netmask_loc(2),8);742 par_data (7 downto 0) <= conv_std_logic_vector(netmask_loc(3),8);750 wiz_addr <= W5300_SUBR + 2; 751 wiz_data (15 downto 8) <= conv_std_logic_vector(netmask_loc(2),8); 752 wiz_data (7 downto 0) <= conv_std_logic_vector(netmask_loc(3),8); 743 753 if (ready_wi = '1') then 744 754 write_wi <= '1'; … … 747 757 -- Own IP-Address 748 758 when IP0 => 749 par_addr <= W5300_SIPR;750 par_data (15 downto 8) <= conv_std_logic_vector(ip_loc(0),8);751 par_data (7 downto 0) <= conv_std_logic_vector(ip_loc(1),8);759 wiz_addr <= W5300_SIPR; 760 wiz_data (15 downto 8) <= conv_std_logic_vector(ip_loc(0),8); 761 wiz_data (7 downto 0) <= conv_std_logic_vector(ip_loc(1),8); 752 762 if (ready_wi = '1') then 753 763 write_wi <= '1'; … … 755 765 end if; 756 766 when IP1 => 757 par_addr <= W5300_SIPR + 2;758 par_data (15 downto 8) <= conv_std_logic_vector(ip_loc(2),8);759 par_data (7 downto 0) <= conv_std_logic_vector(ip_loc(3),8);767 wiz_addr <= W5300_SIPR + 2; 768 wiz_data (15 downto 8) <= conv_std_logic_vector(ip_loc(2),8); 769 wiz_data (7 downto 0) <= conv_std_logic_vector(ip_loc(3),8); 760 770 if (ready_wi = '1') then 761 771 write_wi <= '1'; … … 766 776 when SI_MR => 767 777 state_sig <= X"05"; 768 par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC;769 par_data <= X"0101"; -- ALIGN, TCP778 wiz_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC; 779 wiz_data <= X"0101"; -- ALIGN, TCP 770 780 if (ready_wi = '1') then 771 781 write_wi <= '1'; … … 774 784 -- Sx Interrupt Mask 775 785 when SI_IMR => 776 par_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC;777 par_data <= X"000A"; -- TIMEOUT, DISCON786 wiz_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC; 787 wiz_data <= X"000A"; -- TIMEOUT, DISCON 778 788 if (ready_wi = '1') then 779 789 write_wi <= '1'; … … 781 791 end if; 782 792 when SI_PORTOR => 783 par_addr <= W5300_S0_PORTOR + socket_cnt * W5300_S_INC;784 par_data <= X"0606"; -- send automatic KEEP ALIVE every 30s.793 wiz_addr <= W5300_S0_PORTOR + socket_cnt * W5300_S_INC; 794 wiz_data <= X"0606"; -- send automatic KEEP ALIVE every 30s. 785 795 if (ready_wi = '1') then 786 796 write_wi <= '1'; … … 788 798 end if; 789 799 when SI_PORT => 790 par_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC;791 par_data <= conv_std_logic_vector(FIRST_PORT + unsigned (socket_cnt), 16);800 wiz_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC; 801 wiz_data <= conv_std_logic_vector(FIRST_PORT + socket_cnt, 16); 792 802 if (ready_wi = '1') then 793 803 write_wi <= '1'; … … 795 805 end if; 796 806 when SI_CR_OPEN => 797 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;798 par_data <= X"0001"; -- OPEN807 wiz_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; 808 wiz_data <= X"0001"; -- OPEN 799 809 if (ready_wi = '1') then 800 810 write_wi <= '1'; … … 802 812 end if; 803 813 when SI_SSR => 804 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;814 wiz_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC; 805 815 if (ready_wi = '1') then 806 816 read_wi <= '1'; … … 816 826 end if; 817 827 when SI_CR_LISTEN => 818 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;819 par_data <= X"0002"; -- LISTEN828 wiz_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; 829 wiz_data <= X"0002"; -- LISTEN 820 830 if (ready_wi = '1') then 821 831 write_wi <= '1'; 822 832 socket_cnt <= socket_cnt + 1; 823 833 if (socket_cnt = 7) then 824 socket_cnt <= "000";834 socket_cnt <= 0; 825 835 state_init <= ESTABLISH; 826 836 else … … 836 846 socks_waiting <= '1'; 837 847 socks_connected <= '0'; 838 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;848 wiz_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC; 839 849 if (ready_wi = '1') then 840 850 read_wi <= '1'; … … 847 857 when X"17" => -- established 848 858 if (socket_cnt = 7) then 849 socket_cnt <= "000";859 socket_cnt <= 0; 850 860 busy <= '0'; 851 861 state_init <= MAIN; … … 866 876 state_init <= WAIT_100NS; 867 877 868 when WAIT_100NS => 878 -- this wait for 100ns is not entirely understood, maybe it is not even 879 -- necessary, but I guess under certain circumstances 880 -- DG might be triggered, just when I pull the trigger enable line low. 881 -- when I check no immediatly, if DG is in IDLE, it might *just* be. 882 -- but about to go into another state. 883 -- DG and WM live in different clock domains. 884 -- so I wait 100ns .. in order to let DG make one last transition out of IDLE 885 -- then in the next state I wait until Dg returns. 886 -- this must always happen, there is no way for DG to stay for a long time in any other state. 887 -- in order to ensure this, the DG MM 'data was just written into RAM' handshake was tweaked! 888 when WAIT_100NS => 869 889 state_sig <= X"15"; 870 890 wait_100ns_sig <= wait_100ns_sig + 1; … … 892 912 memory_manager_config_start_o <= '0'; 893 913 if (memory_manager_config_valid_i_sr(1) = '1') then 894 --state_init <= CONFIG_DATA_GENERATOR;914 trigger_enable_sig <= trigger_enable_storage_sig; 895 915 state_init <= MAIN; 896 916 end if; … … 978 998 -- needed for the check: if there is enough space in W5300 FIFO 979 999 write_length_bytes <= (local_write_length (15 downto 0) & '0') ; -- shift left (*2) 980 981 next_state <= MAIN;982 1000 state_init <= WRITE_DATA; 983 1001 … … 993 1011 state_sig <= X"30"; 994 1012 if (ready_wi = '1') then 995 par_addr <= W5300_S0_RX_RSR;1013 wiz_addr <= W5300_S0_RX_RSR; 996 1014 read_wi <= '1'; 997 1015 state_read_data <= RD_2; … … 1001 1019 state_sig <= X"31"; 1002 1020 if (ready_wi = '1') then 1003 par_addr <= W5300_S0_RX_RSR + X"2";1021 wiz_addr <= W5300_S0_RX_RSR + X"2"; 1004 1022 read_wi <= '1'; 1005 1023 socket_rx_received (16) <= data_read(0); … … 1032 1050 if (rx_packets_cnt > 0) then 1033 1051 if (ready_wi = '1') then 1034 par_addr <= W5300_S0_RX_FIFOR;1052 wiz_addr <= W5300_S0_RX_FIFOR; 1035 1053 read_wi <= '1'; 1036 1054 rx_packets_cnt <= rx_packets_cnt - '1'; … … 1138 1156 if (ready_wi = '1') then 1139 1157 rx_packets_cnt <= rx_packets_cnt - '1'; 1140 par_addr <= W5300_S0_RX_FIFOR;1158 wiz_addr <= W5300_S0_RX_FIFOR; 1141 1159 state_read_data <= PUT_COMMAND_DATA_SECTION; 1142 1160 end if; … … 1163 1181 1164 1182 if (ready_wi = '1') then 1165 par_addr <= W5300_S0_CR;1166 par_data <= X"0040"; -- RECV1183 wiz_addr <= W5300_S0_CR; 1184 wiz_data <= X"0040"; -- RECV 1167 1185 write_wi <= '1'; 1168 1186 state_read_data <= RD_1; … … 1219 1237 when WR_WAIT_FOR_MOD7 => 1220 1238 state_sig <= X"45"; 1221 next_state_tmp <= next_state;1222 1239 if (mod7_valid = '1') then 1223 1240 if (socket_send_mode = '1') then -- send via all sockets … … 1226 1243 local_socket_nr <= "000"; 1227 1244 end if; 1228 1229 1245 data_cnt <= 0; 1246 state_write <= WR_CHECK_FOR_FIFO_SPACE_01; 1230 1247 else 1231 1248 state_write <= WR_WAIT_FOR_MOD7; … … 1236 1253 state_sig <= X"46"; 1237 1254 if (ready_wi = '1') then 1238 par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC;1255 wiz_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC; 1239 1256 read_wi <= '1'; 1240 1257 state_write <= WR_CHECK_FOR_FIFO_SPACE_02; … … 1245 1262 if (ready_wi = '1') then 1246 1263 socket_tx_free (16) <= data_read(0); 1247 par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2";1264 wiz_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2"; 1248 1265 state_write <= WR_CHECK_FOR_FIFO_SPACE_03; 1249 1266 read_wi <= '1'; … … 1259 1276 when WR_CHECK_FOR_FIFO_SPACE_04 => 1260 1277 state_sig <= X"49"; 1261 socket_tx_free_out <= socket_tx_free;1262 1278 -- if (socket_tx_free (16 downto 0) < write_length_bytes) then 1263 1279 if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then … … 1294 1310 state_sig <= X"4B"; 1295 1311 if (ready_wi = '1') then 1296 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;1297 par_data <= ram_data;1312 wiz_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; 1313 wiz_data <= ram_data; 1298 1314 number_of_words_written_to_fifo <= number_of_words_written_to_fifo + 1; 1299 1315 data_cnt <= data_cnt + 1; … … 1312 1328 -- Write ADC 1313 1329 ------------------------------------------------ 1330 -- Writing of ADC data is performed in a manner such that, groups of DRS channels 1331 -- with equal channel indices fit completely into W5300 FIFO 1332 -- note: 1333 -- drs index : counts from 0 to 3 1334 -- channel index : counts from 0 to 9 1335 -- e.g. when the ROI is large, not the whole event data fits completly 1336 -- into the FIFO 1337 -- in this case the Header is written first, 1338 -- followed by the channels with index = 0 of all 4 DRS chips. 1339 -- and further followed by the channels, having index = 1 of all DRS chips. 1340 -- the channels are written 'side-by-side' into the data ram, using the 64bit input. 1341 -- but they are read out 'as if written consecutivly' 1342 -- so the address needs to be calculated like this 1343 -- addr(n+1) = addr(n) + 4; instead of 1344 -- addr(n+1) = addr(n) + 1 in case of the header. 1345 1314 1346 when WR_ADC => 1315 1347 state_sig <= X"4C"; 1348 1349 -- when this line is executed for the first time adc_data_address points 1350 -- to the beginning of a channel header. e.g. to 0x0000 or 0x0039 1316 1351 adc_data_addr <= local_ram_start_addr + local_ram_addr; 1317 drs_cnt <= 0; 1318 channel_cnt <= 1; 1319 data_cnt <= 0; 1352 1353 drs_cnt <= 0; -- counts the chis form 0..3 1354 data_cnt <= 0; -- counts the words in the ADC data channel group 1355 channel_cnt <= 1; -- counts the number of channels which fit into W5300 FIFO at once. 1356 1320 1357 roi_max <= (others => '0'); 1321 1358 data_end <= POSITION_OF_ROI_IN_CHANNEL_HEADER; 1322 1359 state_write <= WR_ADC1; 1323 1360 1324 1361 ---- Write Channel 1325 1362 when WR_ADC1 => 1326 1363 state_sig <= X"4D"; 1327 1364 -- read ROI and set end of Channel-Data 1365 1366 -- when this line is executed for the first time it points to 1367 -- the beginning of a channel header, as well. 1368 ram_addr <= adc_data_addr + drs_cnt + (data_cnt * 4); 1328 1369 if (data_cnt = POSITION_OF_ROI_IN_CHANNEL_HEADER) then 1329 1370 data_end <= conv_integer (ram_data) + CHANNEL_HEADER_SIZE; … … 1332 1373 end if; 1333 1374 end if; 1334 ram_addr <= adc_data_addr + drs_cnt + (data_cnt * 4);1335 1375 state_write <= WR_ADC2; 1376 1336 1377 when WR_ADC2 => 1337 1378 if (data_cnt < data_end) then 1338 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; 1339 ram_access <= '1'; 1340 state_init <= WRITE_REG; 1341 number_of_words_written_to_fifo <= number_of_words_written_to_fifo + 1; 1342 next_state <= WRITE_DATA; 1343 data_cnt <= data_cnt + 1; 1344 state_write <= WR_ADC1; 1379 if (ready_wi = '1') then 1380 wiz_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; 1381 wiz_data <= ram_data; 1382 write_wi = '1'; 1383 number_of_words_written_to_fifo <= number_of_words_written_to_fifo + 1; 1384 data_cnt <= data_cnt + 1; 1385 state_write <= WR_ADC1; 1386 end if; 1345 1387 else 1346 1388 -- Next DRS … … 1363 1405 -- Ready 1364 1406 if (local_write_end_flag = '1') then 1365 state_write <= WR_ENDFLAG; 1407 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + CHANNEL_HEADER_SIZE) * 4); 1408 state_write <= WR_ENDFLAG_WAIT; 1366 1409 else 1367 state_write <= WR_ 05a;1410 state_write <= WR_STRANGE_WAIT; 1368 1411 end if; 1369 1412 end if; … … 1372 1415 -- End Write ADC-Data 1373 1416 1374 -- Write End Package Flag 1375 when WR_ENDFLAG => 1376 state_sig <= X"4F"; 1377 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + CHANNEL_HEADER_SIZE) * 4); 1378 state_write <= WR_ENDFLAG1; 1379 when WR_ENDFLAG1 => 1380 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; 1381 ram_access <= '1'; 1382 state_init <= WRITE_REG; 1383 number_of_words_written_to_fifo <= number_of_words_written_to_fifo + 1; 1384 next_state <= WRITE_DATA; 1385 state_write <= WR_ENDFLAG2; 1386 when WR_ENDFLAG2 => 1387 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + CHANNEL_HEADER_SIZE) * 4) + 1; 1388 state_write <= WR_ENDFLAG3; 1389 when WR_ENDFLAG3 => 1390 state_init <= WRITE_REG; 1391 next_state <= WRITE_DATA; 1392 number_of_words_written_to_fifo <= number_of_words_written_to_fifo + 1; 1393 state_write <= WR_05a; 1417 -- Write End Package Flag 1418 when WR_ENDFLAG_WAIT => 1419 state_write <= WR_ENDFLAG; 1420 when WR_ENDFLAG => 1421 if (ready_wi = '1') then 1422 wiz_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; 1423 wiz_data <= ram_data; 1424 write_wi = '1'; 1425 number_of_words_written_to_fifo <= number_of_words_written_to_fifo + 1; 1426 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + CHANNEL_HEADER_SIZE) * 4) + 1; 1427 state_write <= WR_ENDFLAG2_WAIT; 1428 end if; 1429 when WR_ENDFLAG2_WAIT => 1430 state_write <= WR_ENDFLAG2; 1431 1432 when WR_ENDFLAG2 => 1433 if (ready_wi = '1') then 1434 wiz_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; 1435 wiz_data <= ram_data; 1436 write_wi = '1'; 1437 number_of_words_written_to_fifo <= number_of_words_written_to_fifo + 1; 1438 state_write <= WR_STRANGE_WAIT; 1439 end if; 1394 1440 1395 -- End Write End Package Flag 1396 1397 -- Wait???? 1398 when WR_05a => 1399 state_sig <= X"4E"; 1400 if (wait_cntr < 10) then -- 3000 works??? 1401 wait_cntr <= wait_cntr + 1; 1402 else 1403 wait_cntr <= 0; 1404 state_write <= WR_05b; 1405 end if; 1406 when WR_05b => 1407 state_write <= WR_05_PREPARE_LENGTH_INFO; 1408 1409 --Send FIFO 1410 when WR_05_PREPARE_LENGTH_INFO => 1411 --number_of_words_written_to_fifo <= number_of_words_written_to_fifo - 1; 1412 state_init <= WRITE_DATA; 1413 state_write <= WR_05_POSTPREPARE_LENGTH_INFO; 1441 when WR_STRANGE_WAIT => 1442 if (wait_cntr < 10) then -- 3000 works??? 1443 wait_cntr <= wait_cntr + 1; 1444 else 1445 wait_cntr <= 0; 1446 state_write <= WR_05_PREPARE_LENGTH_INFO; 1447 end if; 1448 --Send FIFO 1449 when WR_05_PREPARE_LENGTH_INFO => 1450 --number_of_words_written_to_fifo <= number_of_words_written_to_fifo - 1; 1451 state_write <= WR_05_POSTPREPARE_LENGTH_INFO; 1452 when WR_05_POSTPREPARE_LENGTH_INFO => 1453 number_of_bytes_written_to_fifo <= number_of_words_written_to_fifo(15 downto 0) & '0'; 1454 state_write <= WR_MESSAGE_LEN_HIGH_WORD; 1455 1456 when WR_MESSAGE_LEN_HIGH_WORD => 1457 if (ready_i = '1') then 1458 wiz_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC; 1459 wiz_data <= (0 => write_length_bytes (16), others => '0'); 1460 --wiz_data <= (0 => number_of_bytes_written_to_fifo(16), others => '0'); 1461 state_write <= WR_MESSAGE_LEN_LOW_WORD; 1462 end if; 1414 1463 1415 1416 when WR_05_POSTPREPARE_LENGTH_INFO => 1417 number_of_bytes_written_to_fifo <= number_of_words_written_to_fifo(15 downto 0) & '0'; 1418 state_init <= WRITE_DATA; 1419 state_write <= WR_05; 1420 1421 1422 when WR_05 => 1423 ram_access <= '0'; 1424 state_sig <= X"50"; 1425 par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC; 1426 par_data <= (0 => write_length_bytes (16), others => '0'); 1427 --par_data <= (0 => number_of_bytes_written_to_fifo(16), others => '0'); 1428 state_init <= WRITE_REG; 1429 state_write <= WR_06; 1430 when WR_06 => 1431 par_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2"; 1432 par_data <= write_length_bytes (15 downto 0); 1433 --par_data <= number_of_bytes_written_to_fifo(15 downto 0); 1464 when WR_MESSAGE_LEN_LOW_WORD => 1465 if (ready_wi= '1') then 1466 wiz_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2"; 1467 wiz_data <= write_length_bytes (15 downto 0); 1468 --wiz_data <= number_of_bytes_written_to_fifo(15 downto 0); 1469 state_write <= WR_SEND_COMMAND; 1470 end if; 1471 1472 when WR_SEND_COMMAND => 1473 number_of_words_written_to_fifo <= (others => '0'); 1474 if (ready_wi <= '1') then 1475 wiz_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC; 1476 wiz_data <= X"0020"; -- Send 1477 write_wi <= '1'; 1478 end if 1479 state_write <= WR_ACK; 1480 1481 when WR_ACK => 1482 data_valid_ack <= '1'; 1483 state_write <= WR_WAIT_FOR_ACK; 1484 1485 when WR_WAIT_FOR_ACK => 1486 state_write <= WR_WAIT_FOR_ACK; 1487 if (data_valid_sr(1) = '0') then 1488 data_valid_ack <= '0'; 1434 1489 1435 state_init <= WRITE_REG; 1436 state_write <= WR_07; 1437 when WR_07 => 1438 number_of_words_written_to_fifo <= (others => '0'); 1439 state_sig <= X"51"; 1440 par_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC; 1441 par_data <= X"0020"; -- Send 1442 state_init <= WRITE_REG; 1443 state_write <= WR_ACK; 1444 when WR_ACK => 1445 data_valid_ack <= '1'; 1446 state_write <= WR_WAIT_FOR_ACK; 1447 when WR_WAIT_FOR_ACK => 1448 state_write <= WR_WAIT_FOR_ACK; 1449 if (data_valid_sr(1) = '0') then 1450 data_valid_ack <= '0'; 1451 state_init <= next_state_tmp; 1452 state_write <= WR_START; 1453 end if; 1454 1455 1456 when others => 1457 state_sig <= X"4F"; 1490 state_write <= WR_START; 1491 state_init <= MAIN; 1492 -- maybe MAIN1 is better ?! 1493 end if; 1494 1495 1496 when others => 1497 null; 1458 1498 end case; 1459 1499 -- End WRITE_DATA … … 1461 1501 1462 1502 when others => 1463 state_sig <= X"F0";1464 1503 null; 1465 1504 end case;
Note:
See TracChangeset
for help on using the changeset viewer.
