Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul2.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul2.vhd (revision 10890) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul2.vhd (revision 10891) @@ -8,7 +8,5 @@ ENTITY w5300_modul2 IS - generic( - RAM_ADDR_WIDTH : integer := 14 - ); + PORT( state : OUT std_logic_vector (7 DOWNTO 0); -- state is encoded here ... useful for debugging. @@ -16,5 +14,4 @@ debug_data_valid : OUT std_logic; data_generator_idle_i : IN std_logic; - socket_tx_free_out : out std_logic_vector (16 DOWNTO 0); -- 17bit value .. that's true clk : IN std_logic; @@ -27,11 +24,10 @@ rd : OUT std_logic := '1'; - led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); int : IN std_logic; write_length : IN std_logic_vector (16 DOWNTO 0); - ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + ram_start_addr : IN std_logic_vector (W5300_RAM_ADDR_WIDTH-1 DOWNTO 0); ram_data : IN std_logic_vector (15 DOWNTO 0); - ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + ram_addr : OUT std_logic_vector (W5300_RAM_ADDR_WIDTH-1 DOWNTO 0); data_valid : IN std_logic; data_valid_ack : OUT std_logic := '0'; @@ -123,5 +119,5 @@ SI, SI1, SI1b, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, - CONFIG, WAIT_100NS, WAIT_UNTIL_DG_IDLE, WAIT_FOR_DATA_RAM_EMPTY, -- <-- this is THE deadlock state + CONFIG, WAIT_100NS, WAIT_UNTIL_DG_IDLE, CONFIG_MEMORY_MANAGER, WAIT_FOR_CONFIG_MEMORY_MANAGER, CONFIG_DATA_GENERATOR, WAIT_FOR_CONFIG_DATA_GENERATOR, @@ -130,4 +126,5 @@ MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA ); + type state_write_type is ( WR_START, @@ -135,14 +132,21 @@ WR_MOD7_STARTED, WR_WAIT_FOR_MOD7, WR_CHECK_FOR_FIFO_SPACE_01, WR_CHECK_FOR_FIFO_SPACE_02, WR_CHECK_FOR_FIFO_SPACE_03, WR_CHECK_FOR_FIFO_SPACE_04, - WR_05, WR_05_PREPARE_LENGTH_INFO, WR_05_POSTPREPARE_LENGTH_INFO, - WR_05a, WR_05b, WR_06, WR_07, + WR_05_PREPARE_LENGTH_INFO, WR_05_POSTPREPARE_LENGTH_INFO, + WR_STRANGE_WAIT, WR_ACK, WR_WAIT_FOR_ACK, WR_HEADER_FETCH, WR_HEADER_WAIT, WR_HEADER, - WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2, - WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3 + WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2 ); type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04); -type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06); +type state_interrupt_2_type is ( + IR2_GET_IR, + IR2_CHECK_WHICH_SN_IRQ, + IR2_GET_SN_IR, + IR2_CLEAR_SN_IR, + IR2_SEND_DISCON, + IR2_GET_SOCKn_STATUS, + IR2_WAIT_SOCKn_CLOSED, + IR2_GOTO_RESET); type state_read_data_type is ( RD_1, @@ -157,30 +161,27 @@ RD_END ); - -signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120"; - -signal par_addr : std_logic_vector (9 downto 0) := (OTHERS => '0'); -signal par_data : std_logic_vector (15 downto 0) := (OTHERS => '0'); -signal data_read : std_logic_vector (15 downto 0) := (OTHERS => '0'); -signal adc_data_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); - -signal state_init, next_state , next_state_tmp : state_init_type := RESET; -signal count : std_logic_vector (2 downto 0) := "000"; +signal state_init : state_init_type := RESET; signal state_write : state_write_type := WR_START; signal state_interrupt_1 : state_interrupt_1_type := IR1_01; -signal state_interrupt_2 : state_interrupt_2_type := IR2_01; +signal state_interrupt_2 : state_interrupt_2_type := IR2_GET_IR; signal state_read_data : state_read_data_type := RD_1; + +signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120"; -- 0x7A120=500000 @50MHz --> 10ms + +signal wiz_addr : std_logic_vector (9 downto 0) := (OTHERS => '0'); +signal wiz_data : std_logic_vector (15 downto 0) := (OTHERS => '0'); +signal data_read : std_logic_vector (15 downto 0) := (OTHERS => '0'); +signal adc_data_addr : std_logic_vector (W5300_RAM_ADDR_WIDTH-1 DOWNTO 0); signal interrupt_ignore : std_logic := '1'; signal int_flag : std_logic := '0'; -signal ram_access : std_logic := '0'; - -signal zaehler : std_logic_vector (19 downto 0) := (OTHERS => '0'); -signal data_cnt : integer := 0; -signal drs_cnt : integer :=0; + +signal data_cnt : integer range 0 to 7680 := 0; +signal data_end : integer range 0 to 7680 := 0; +signal drs_cnt : integer range 0 to 3 := 0; signal channel_cnt : integer range 0 to 9 :=0; -signal socket_cnt : std_logic_vector (2 downto 0) := "000"; -signal roi_max : std_logic_vector (10 downto 0); -signal data_end : integer := 0; +signal socket_cnt : integer range 0 to 7 := 0; +signal roi_max : std_logic_vector (10 downto 0) := (others => '0'); + signal socket_tx_free : std_logic_vector (16 downto 0) := (others => '0'); @@ -204,6 +205,6 @@ signal local_write_length : std_logic_vector (16 DOWNTO 0); -signal local_ram_start_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); -signal local_ram_addr : std_logic_vector (RAM_ADDR_WIDTH-1 downto 0); +signal local_ram_start_addr : std_logic_vector (W5300_RAM_ADDR_WIDTH-1 DOWNTO 0); +signal local_ram_addr : std_logic_vector (W5300_RAM_ADDR_WIDTH-1 downto 0); signal local_socket_nr : std_logic_vector (2 DOWNTO 0); signal local_write_header_flag, local_write_end_flag : std_logic; @@ -352,7 +353,7 @@ read_i => read_wi, write_i => write_wi, - addr_i => par_addr, + addr_i => wiz_addr, data_o => data_read, - data_i => par_data, + data_i => wiz_data, ready_o => ready_wi, reset_i => reset_wi @@ -390,11 +391,8 @@ write_wi <= '0'; read_wi <= '0'; - --socket_tx_free_out <= socket_tx_free; - - -- synch asynchronous inputs in: + memory_manager_config_valid_i_sr <= memory_manager_config_valid_i_sr(0) & memory_manager_config_valid_i; spi_interface_config_valid_i_sr <= spi_interface_config_valid_i_sr(0) & spi_interface_config_valid_i; - --data_generator_config_valid_i_sr <= data_generator_config_valid_i_sr(0) & data_generator_config_valid_i; data_ram_empty_sr <= data_ram_empty_sr(0) & data_ram_empty; data_generator_idle_sr <= data_generator_idle_sr( 1 downto 0 ) & data_generator_idle_i; @@ -413,23 +411,15 @@ case state_interrupt_1 is when IR1_01 => - state_sig <= X"FF"; int_flag <= '1'; - busy <= '1'; state_interrupt_1 <= IR1_02; --wait one cycle when IR1_02 => - state_sig <= X"FE"; state_interrupt_1 <= IR1_03; when IR1_03 => - state_sig <= X"FD"; state_init <= INTERRUPT; - socket_cnt <= "000"; - ram_access <= '0'; - zaehler <= X"00000"; --what is this zaehler counting? - count <= "000"; --what is this count counting? + socket_cnt <= 0; int_flag <= '0'; interrupt_ignore <= '1'; state_interrupt_1 <= IR1_04; --this state is not existing? bad coding habit??? when others => - state_sig <= X"FC"; null; end case; @@ -441,72 +431,94 @@ when INTERRUPT => case state_interrupt_2 is - when IR2_01 => - state_sig <= X"FB"; - par_addr <= W5300_IR; - state_init <= READ_REG; - next_state <= INTERRUPT; - state_interrupt_2 <= IR2_02; + when IR2_GET_IR => + if (ready_wi = '1') then + wiz_addr <= W5300_IR; + read_wi <= '1'; + state_interrupt_2 <= IR2_CHECK_WHICH_SN_IRQ; + end if; -- check if it was a Sx Interrupt of Socket n -- therfor: loop over all channel. - -- if the loop ended but no Sx Interrupt was found --> IR2_06 - -- if an Sx Interrupt was found go to --> IR2_03 and check what happened. - when IR2_02 => - state_sig <= X"FA"; - if (data_read (conv_integer(socket_cnt)) = '1') then -- Sx Interrupt - state_interrupt_2 <= IR2_03; - else + -- if the loop ended but no Sx Interrupt was found --> IR2_GOTO_RESET + -- if an Sx Interrupt was found go to --> IR2_GET_SN_IR and check what happened. + when IR2_CHECK_WHICH_SN_IRQ => + if (ready_wi = '1') then + if (data_read(socket_cnt) = '1') then -- Sx Interrupt + state_interrupt_2 <= IR2_GET_SN_IR; + else + socket_cnt <= socket_cnt + 1; + if (socket_cnt = 7) then + state_interrupt_2 <= IR2_GOTO_RESET; + else + state_interrupt_2 <= IR2_CHECK_WHICH_SN_IRQ; -- go on with loop + end if; + end if; + end if; + + -- check the Interrupt register of the Socket to be able to clear them + when IR2_GET_SN_IR => + if (ready_wi = '1') then + wiz_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register + read_wi <= '1'; + state_interrupt_2 <= IR2_CLEAR_SN_IR; + end if; + -- clear IRQs by writing ones. + when IR2_CLEAR_SN_IR => + if (ready_wi = '1') then + wiz_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; + wiz_data <= data_read; -- clear Interrupts + write_wi <= '1'; + state_interrupt_2 <= IR2_SEND_DISCON; + end if; + + -- send the command to close this socket + -- then go back and read the main Interrupt register again, + -- if this was not Socket 7 ... if it was Socket 7, we're done anyway. + when IR2_SEND_DISCON => + if (ready_wi = '1') then + wiz_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; + wiz_data <= X"0008"; -- DISCON --> W5300 wil send FIN packet + write_wi <= '1'; socket_cnt <= socket_cnt + 1; + if (socket_cnt = 7) then - state_interrupt_2 <= IR2_06; + socket_cnt = 0; + state_interrupt_2 <= IR2_WAIT_UNTIL_SOCKS_CLOSED; else - state_interrupt_2 <= IR2_02; -- go on with loop + state_interrupt_2 <= IR2_GET_IR; end if; end if; - -- check the Interrupt register of the Socket, which caused the Interrupt. - when IR2_03 => - state_sig <= X"F9"; - par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register - state_init <= READ_REG; - next_state <= INTERRUPT; - state_interrupt_2 <= IR2_04; - -- before checking what happened, clear the Interrupt register, so we can proceed. - when IR2_04 => - state_sig <= X"F8"; - par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; - par_data <= data_read; -- clear Interrupts - state_init <= WRITE_REG; - next_state <= INTERRUPT; - state_interrupt_2 <= IR2_05; - -- send the command to close this socket - -- then go back and read the main Interrupt register again, - -- if this was not Socket 7 ... if it was Socket 7, we're done anyway. - when IR2_05 => - state_sig <= X"F7"; - par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; - par_data <= X"0010"; -- CLOSE - state_init <= WRITE_REG; - next_state <= INTERRUPT; - socket_cnt <= socket_cnt + 1; - if (socket_cnt = 7) then - state_interrupt_2 <= IR2_06; - else - state_interrupt_2 <= IR2_01; - end if; - - -- we go on and reset, the W5300 and this entire state machine. - when IR2_06 => + when IR2_GET_SOCKn_STATUS => + if (ready_wi = '1') then + wiz_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; + read_wi = '1'; + state_interrupt_2 <= IR2_WAIT_SOCKn_CLOSED; + end if; + + when IR2_WAIT_SOCKn_CLOSED => + if (ready_wi = '1') then + if (data_read = X"0000") then --closed + if (socket_cnt = 7) then + socket_cnt <= 0; + state_interrupt_2 <= IR2_GOTO_RESET; + else + socket_cnt <= socket_cnt + 1; + state_interrupt_2 <= IR2_GET_SOCKn_STATUS; + end if; + end if; + end if; + + + + when IR2_GOTO_RESET => state_sig <= X"F6"; state_interrupt_1 <= IR1_01; - state_interrupt_2 <= IR2_01; - socket_cnt <= "000"; + state_interrupt_2 <= IR2_GET_IR; + socket_cnt <= 0; state_init <= RESET; when others => - state_interrupt_1 <= IR1_01; - state_interrupt_2 <= IR2_01; - socket_cnt <= "000"; - state_init <= RESET; - end case; + null; + end case; -- reset W5300 @@ -518,7 +530,5 @@ socks_waiting <= '0'; socks_connected <= '0'; - socket_cnt <= "000"; - count <= "000"; - ram_access <= '0'; + socket_cnt <= 0; interrupt_ignore <= '0'; @@ -544,6 +554,6 @@ cid <= CrateID; - par_addr <= W5300_MR; - par_data <= X"0000"; + wiz_addr <= W5300_MR; + wiz_data <= X"0000"; if (ready_wi = '1') then write_wi <= '1'; @@ -606,6 +616,6 @@ when IM => state_sig <= X"04"; - par_addr <= W5300_IMR; - par_data <= X"00FF"; -- S0-S7 Interrupts + wiz_addr <= W5300_IMR; + wiz_data <= X"00FF"; -- S0-S7 Interrupts if (ready_wi = '1') then write_wi <= '1'; @@ -616,6 +626,6 @@ -- Memory Type when MT => - par_addr <= W5300_MTYPER; - par_data <= X"7FFF"; -- 8K RX, 120K TX-Buffer + wiz_addr <= W5300_MTYPER; + wiz_data <= X"7FFF"; -- 8K RX, 120K TX-Buffer if (ready_wi = '1') then write_wi <= '1'; @@ -625,6 +635,6 @@ -- Socket TX Memory Size when STX0 => - par_addr <= W5300_TMS01R; - par_data <= X"0F0F"; -- 15K TX + wiz_addr <= W5300_TMS01R; + wiz_data <= X"0F0F"; -- 15K TX if (ready_wi = '1') then write_wi <= '1'; @@ -632,6 +642,6 @@ end if; when STX1 => - par_addr <= W5300_TMS23R; - par_data <= X"0F0F"; -- 15K TX + wiz_addr <= W5300_TMS23R; + wiz_data <= X"0F0F"; -- 15K TX if (ready_wi = '1') then write_wi <= '1'; @@ -640,6 +650,6 @@ when STX2 => - par_addr <= W5300_TMS45R; - par_data <= X"0F0F"; -- 15K TX + wiz_addr <= W5300_TMS45R; + wiz_data <= X"0F0F"; -- 15K TX if (ready_wi = '1') then write_wi <= '1'; @@ -648,6 +658,6 @@ when STX3 => - par_addr <= W5300_TMS67R; - par_data <= X"0F0F"; -- 15K TX + wiz_addr <= W5300_TMS67R; + wiz_data <= X"0F0F"; -- 15K TX if (ready_wi = '1') then write_wi <= '1'; @@ -657,6 +667,6 @@ -- Socket RX Memory Size when SRX0 => - par_data <= X"0101"; -- 1K RX - par_addr <= W5300_RMS01R; + wiz_data <= X"0101"; -- 1K RX + wiz_addr <= W5300_RMS01R; if (ready_wi = '1') then write_wi <= '1'; @@ -664,6 +674,6 @@ end if; when SRX1 => - par_data <= X"0101"; -- 1K RX - par_addr <= W5300_RMS23R; + wiz_data <= X"0101"; -- 1K RX + wiz_addr <= W5300_RMS23R; if (ready_wi = '1') then write_wi <= '1'; @@ -671,6 +681,6 @@ end if; when SRX2 => - par_data <= X"0101"; -- 1K RX - par_addr <= W5300_RMS45R; + wiz_data <= X"0101"; -- 1K RX + wiz_addr <= W5300_RMS45R; if (ready_wi = '1') then write_wi <= '1'; @@ -678,6 +688,6 @@ end if; when SRX3 => - par_data <= X"0101"; -- 1K RX - par_addr <= W5300_RMS67R; + wiz_data <= X"0101"; -- 1K RX + wiz_addr <= W5300_RMS67R; if (ready_wi = '1') then write_wi <= '1'; @@ -687,6 +697,6 @@ -- MAC when MAC0 => - par_addr <= W5300_SHAR; - par_data <= mac_loc(0); + wiz_addr <= W5300_SHAR; + wiz_data <= mac_loc(0); if (ready_wi = '1') then write_wi <= '1'; @@ -695,6 +705,6 @@ when MAC1 => - par_addr <= W5300_SHAR + 2; - par_data <= mac_loc(1); + wiz_addr <= W5300_SHAR + 2; + wiz_data <= mac_loc(1); if (ready_wi = '1') then write_wi <= '1'; @@ -702,6 +712,6 @@ end if; when MAC2 => - par_addr <= W5300_SHAR + 4; - par_data <= mac_loc(2); + wiz_addr <= W5300_SHAR + 4; + wiz_data <= mac_loc(2); if (ready_wi = '1') then write_wi <= '1'; @@ -711,7 +721,7 @@ -- Gateway when GW0 => - par_addr <= W5300_GAR; - par_data (15 downto 8) <= conv_std_logic_vector(gateway_loc(0),8); - par_data (7 downto 0) <= conv_std_logic_vector(gateway_loc(1),8); + wiz_addr <= W5300_GAR; + wiz_data (15 downto 8) <= conv_std_logic_vector(gateway_loc(0),8); + wiz_data (7 downto 0) <= conv_std_logic_vector(gateway_loc(1),8); if (ready_wi = '1') then write_wi <= '1'; @@ -720,7 +730,7 @@ when GW1 => - par_addr <= W5300_GAR + 2; - par_data (15 downto 8) <= conv_std_logic_vector(gateway_loc(2),8); - par_data (7 downto 0) <= conv_std_logic_vector(gateway_loc(3),8); + wiz_addr <= W5300_GAR + 2; + wiz_data (15 downto 8) <= conv_std_logic_vector(gateway_loc(2),8); + wiz_data (7 downto 0) <= conv_std_logic_vector(gateway_loc(3),8); if (ready_wi = '1') then write_wi <= '1'; @@ -730,7 +740,7 @@ -- Subnet Mask when SNM0 => - par_addr <= W5300_SUBR; - par_data (15 downto 8) <= conv_std_logic_vector(netmask_loc(0),8); - par_data (7 downto 0) <= conv_std_logic_vector(netmask_loc(1),8); + wiz_addr <= W5300_SUBR; + wiz_data (15 downto 8) <= conv_std_logic_vector(netmask_loc(0),8); + wiz_data (7 downto 0) <= conv_std_logic_vector(netmask_loc(1),8); if (ready_wi = '1') then write_wi <= '1'; @@ -738,7 +748,7 @@ end if; when SNM1 => - par_addr <= W5300_SUBR + 2; - par_data (15 downto 8) <= conv_std_logic_vector(netmask_loc(2),8); - par_data (7 downto 0) <= conv_std_logic_vector(netmask_loc(3),8); + wiz_addr <= W5300_SUBR + 2; + wiz_data (15 downto 8) <= conv_std_logic_vector(netmask_loc(2),8); + wiz_data (7 downto 0) <= conv_std_logic_vector(netmask_loc(3),8); if (ready_wi = '1') then write_wi <= '1'; @@ -747,7 +757,7 @@ -- Own IP-Address when IP0 => - par_addr <= W5300_SIPR; - par_data (15 downto 8) <= conv_std_logic_vector(ip_loc(0),8); - par_data (7 downto 0) <= conv_std_logic_vector(ip_loc(1),8); + wiz_addr <= W5300_SIPR; + wiz_data (15 downto 8) <= conv_std_logic_vector(ip_loc(0),8); + wiz_data (7 downto 0) <= conv_std_logic_vector(ip_loc(1),8); if (ready_wi = '1') then write_wi <= '1'; @@ -755,7 +765,7 @@ end if; when IP1 => - par_addr <= W5300_SIPR + 2; - par_data (15 downto 8) <= conv_std_logic_vector(ip_loc(2),8); - par_data (7 downto 0) <= conv_std_logic_vector(ip_loc(3),8); + wiz_addr <= W5300_SIPR + 2; + wiz_data (15 downto 8) <= conv_std_logic_vector(ip_loc(2),8); + wiz_data (7 downto 0) <= conv_std_logic_vector(ip_loc(3),8); if (ready_wi = '1') then write_wi <= '1'; @@ -766,6 +776,6 @@ when SI_MR => state_sig <= X"05"; - par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC; - par_data <= X"0101"; -- ALIGN, TCP + wiz_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC; + wiz_data <= X"0101"; -- ALIGN, TCP if (ready_wi = '1') then write_wi <= '1'; @@ -774,6 +784,6 @@ -- Sx Interrupt Mask when SI_IMR => - par_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC; - par_data <= X"000A"; -- TIMEOUT, DISCON + wiz_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC; + wiz_data <= X"000A"; -- TIMEOUT, DISCON if (ready_wi = '1') then write_wi <= '1'; @@ -781,6 +791,6 @@ end if; when SI_PORTOR => - par_addr <= W5300_S0_PORTOR + socket_cnt * W5300_S_INC; - par_data <= X"0606"; -- send automatic KEEP ALIVE every 30s. + wiz_addr <= W5300_S0_PORTOR + socket_cnt * W5300_S_INC; + wiz_data <= X"0606"; -- send automatic KEEP ALIVE every 30s. if (ready_wi = '1') then write_wi <= '1'; @@ -788,6 +798,6 @@ end if; when SI_PORT => - par_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC; - par_data <= conv_std_logic_vector(FIRST_PORT + unsigned (socket_cnt), 16); + wiz_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC; + wiz_data <= conv_std_logic_vector(FIRST_PORT + socket_cnt, 16); if (ready_wi = '1') then write_wi <= '1'; @@ -795,6 +805,6 @@ end if; when SI_CR_OPEN => - par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; - par_data <= X"0001"; -- OPEN + wiz_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; + wiz_data <= X"0001"; -- OPEN if (ready_wi = '1') then write_wi <= '1'; @@ -802,5 +812,5 @@ end if; when SI_SSR => - par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC; + wiz_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC; if (ready_wi = '1') then read_wi <= '1'; @@ -816,11 +826,11 @@ end if; when SI_CR_LISTEN => - par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; - par_data <= X"0002"; -- LISTEN + wiz_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; + wiz_data <= X"0002"; -- LISTEN if (ready_wi = '1') then write_wi <= '1'; socket_cnt <= socket_cnt + 1; if (socket_cnt = 7) then - socket_cnt <= "000"; + socket_cnt <= 0; state_init <= ESTABLISH; else @@ -836,5 +846,5 @@ socks_waiting <= '1'; socks_connected <= '0'; - par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC; + wiz_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC; if (ready_wi = '1') then read_wi <= '1'; @@ -847,5 +857,5 @@ when X"17" => -- established if (socket_cnt = 7) then - socket_cnt <= "000"; + socket_cnt <= 0; busy <= '0'; state_init <= MAIN; @@ -866,5 +876,15 @@ state_init <= WAIT_100NS; - when WAIT_100NS => + -- this wait for 100ns is not entirely understood, maybe it is not even + -- necessary, but I guess under certain circumstances + -- DG might be triggered, just when I pull the trigger enable line low. + -- when I check no immediatly, if DG is in IDLE, it might *just* be. + -- but about to go into another state. + -- DG and WM live in different clock domains. + -- so I wait 100ns .. in order to let DG make one last transition out of IDLE + -- then in the next state I wait until Dg returns. + -- this must always happen, there is no way for DG to stay for a long time in any other state. + -- in order to ensure this, the DG MM 'data was just written into RAM' handshake was tweaked! + when WAIT_100NS => state_sig <= X"15"; wait_100ns_sig <= wait_100ns_sig + 1; @@ -892,5 +912,5 @@ memory_manager_config_start_o <= '0'; if (memory_manager_config_valid_i_sr(1) = '1') then - --state_init <= CONFIG_DATA_GENERATOR; + trigger_enable_sig <= trigger_enable_storage_sig; state_init <= MAIN; end if; @@ -978,6 +998,4 @@ -- needed for the check: if there is enough space in W5300 FIFO write_length_bytes <= (local_write_length (15 downto 0) & '0') ; -- shift left (*2) - - next_state <= MAIN; state_init <= WRITE_DATA; @@ -993,5 +1011,5 @@ state_sig <= X"30"; if (ready_wi = '1') then - par_addr <= W5300_S0_RX_RSR; + wiz_addr <= W5300_S0_RX_RSR; read_wi <= '1'; state_read_data <= RD_2; @@ -1001,5 +1019,5 @@ state_sig <= X"31"; if (ready_wi = '1') then - par_addr <= W5300_S0_RX_RSR + X"2"; + wiz_addr <= W5300_S0_RX_RSR + X"2"; read_wi <= '1'; socket_rx_received (16) <= data_read(0); @@ -1032,5 +1050,5 @@ if (rx_packets_cnt > 0) then if (ready_wi = '1') then - par_addr <= W5300_S0_RX_FIFOR; + wiz_addr <= W5300_S0_RX_FIFOR; read_wi <= '1'; rx_packets_cnt <= rx_packets_cnt - '1'; @@ -1138,5 +1156,5 @@ if (ready_wi = '1') then rx_packets_cnt <= rx_packets_cnt - '1'; - par_addr <= W5300_S0_RX_FIFOR; + wiz_addr <= W5300_S0_RX_FIFOR; state_read_data <= PUT_COMMAND_DATA_SECTION; end if; @@ -1163,6 +1181,6 @@ if (ready_wi = '1') then - par_addr <= W5300_S0_CR; - par_data <= X"0040"; -- RECV + wiz_addr <= W5300_S0_CR; + wiz_data <= X"0040"; -- RECV write_wi <= '1'; state_read_data <= RD_1; @@ -1219,5 +1237,4 @@ when WR_WAIT_FOR_MOD7 => state_sig <= X"45"; - next_state_tmp <= next_state; if (mod7_valid = '1') then if (socket_send_mode = '1') then -- send via all sockets @@ -1226,6 +1243,6 @@ local_socket_nr <= "000"; end if; - data_cnt <= 0; - state_write <= WR_CHECK_FOR_FIFO_SPACE_01; + data_cnt <= 0; + state_write <= WR_CHECK_FOR_FIFO_SPACE_01; else state_write <= WR_WAIT_FOR_MOD7; @@ -1236,5 +1253,5 @@ state_sig <= X"46"; if (ready_wi = '1') then - par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC; + wiz_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC; read_wi <= '1'; state_write <= WR_CHECK_FOR_FIFO_SPACE_02; @@ -1245,5 +1262,5 @@ if (ready_wi = '1') then socket_tx_free (16) <= data_read(0); - par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2"; + wiz_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2"; state_write <= WR_CHECK_FOR_FIFO_SPACE_03; read_wi <= '1'; @@ -1259,5 +1276,4 @@ when WR_CHECK_FOR_FIFO_SPACE_04 => state_sig <= X"49"; - socket_tx_free_out <= socket_tx_free; -- if (socket_tx_free (16 downto 0) < write_length_bytes) then if (socket_tx_free (16 downto 0) < W5300_TX_FIFO_SIZE_8B) then @@ -1294,6 +1310,6 @@ state_sig <= X"4B"; if (ready_wi = '1') then - par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; - par_data <= ram_data; + wiz_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; + wiz_data <= ram_data; number_of_words_written_to_fifo <= number_of_words_written_to_fifo + 1; data_cnt <= data_cnt + 1; @@ -1312,18 +1328,43 @@ -- Write ADC ------------------------------------------------ + -- Writing of ADC data is performed in a manner such that, groups of DRS channels + -- with equal channel indices fit completely into W5300 FIFO + -- note: + -- drs index : counts from 0 to 3 + -- channel index : counts from 0 to 9 + -- e.g. when the ROI is large, not the whole event data fits completly + -- into the FIFO + -- in this case the Header is written first, + -- followed by the channels with index = 0 of all 4 DRS chips. + -- and further followed by the channels, having index = 1 of all DRS chips. + -- the channels are written 'side-by-side' into the data ram, using the 64bit input. + -- but they are read out 'as if written consecutivly' + -- so the address needs to be calculated like this + -- addr(n+1) = addr(n) + 4; instead of + -- addr(n+1) = addr(n) + 1 in case of the header. + when WR_ADC => state_sig <= X"4C"; + + -- when this line is executed for the first time adc_data_address points + -- to the beginning of a channel header. e.g. to 0x0000 or 0x0039 adc_data_addr <= local_ram_start_addr + local_ram_addr; - drs_cnt <= 0; - channel_cnt <= 1; - data_cnt <= 0; + + drs_cnt <= 0; -- counts the chis form 0..3 + data_cnt <= 0; -- counts the words in the ADC data channel group + channel_cnt <= 1; -- counts the number of channels which fit into W5300 FIFO at once. + roi_max <= (others => '0'); data_end <= POSITION_OF_ROI_IN_CHANNEL_HEADER; state_write <= WR_ADC1; - ---- Write Channel + ---- Write Channel when WR_ADC1 => state_sig <= X"4D"; -- read ROI and set end of Channel-Data + + -- when this line is executed for the first time it points to + -- the beginning of a channel header, as well. + ram_addr <= adc_data_addr + drs_cnt + (data_cnt * 4); if (data_cnt = POSITION_OF_ROI_IN_CHANNEL_HEADER) then data_end <= conv_integer (ram_data) + CHANNEL_HEADER_SIZE; @@ -1332,15 +1373,16 @@ end if; end if; - ram_addr <= adc_data_addr + drs_cnt + (data_cnt * 4); state_write <= WR_ADC2; + when WR_ADC2 => if (data_cnt < data_end) then - par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; - ram_access <= '1'; - state_init <= WRITE_REG; - number_of_words_written_to_fifo <= number_of_words_written_to_fifo + 1; - next_state <= WRITE_DATA; - data_cnt <= data_cnt + 1; - state_write <= WR_ADC1; + if (ready_wi = '1') then + wiz_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; + wiz_data <= ram_data; + write_wi = '1'; + number_of_words_written_to_fifo <= number_of_words_written_to_fifo + 1; + data_cnt <= data_cnt + 1; + state_write <= WR_ADC1; + end if; else -- Next DRS @@ -1363,7 +1405,8 @@ -- Ready if (local_write_end_flag = '1') then - state_write <= WR_ENDFLAG; + ram_addr <= adc_data_addr + ((conv_integer(roi_max) + CHANNEL_HEADER_SIZE) * 4); + state_write <= WR_ENDFLAG_WAIT; else - state_write <= WR_05a; + state_write <= WR_STRANGE_WAIT; end if; end if; @@ -1372,88 +1415,85 @@ -- End Write ADC-Data - -- Write End Package Flag - when WR_ENDFLAG => - state_sig <= X"4F"; - ram_addr <= adc_data_addr + ((conv_integer(roi_max) + CHANNEL_HEADER_SIZE) * 4); - state_write <= WR_ENDFLAG1; - when WR_ENDFLAG1 => - par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; - ram_access <= '1'; - state_init <= WRITE_REG; - number_of_words_written_to_fifo <= number_of_words_written_to_fifo + 1; - next_state <= WRITE_DATA; - state_write <= WR_ENDFLAG2; - when WR_ENDFLAG2 => - ram_addr <= adc_data_addr + ((conv_integer(roi_max) + CHANNEL_HEADER_SIZE) * 4) + 1; - state_write <= WR_ENDFLAG3; - when WR_ENDFLAG3 => - state_init <= WRITE_REG; - next_state <= WRITE_DATA; - number_of_words_written_to_fifo <= number_of_words_written_to_fifo + 1; - state_write <= WR_05a; + -- Write End Package Flag + when WR_ENDFLAG_WAIT => + state_write <= WR_ENDFLAG; + when WR_ENDFLAG => + if (ready_wi = '1') then + wiz_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; + wiz_data <= ram_data; + write_wi = '1'; + number_of_words_written_to_fifo <= number_of_words_written_to_fifo + 1; + ram_addr <= adc_data_addr + ((conv_integer(roi_max) + CHANNEL_HEADER_SIZE) * 4) + 1; + state_write <= WR_ENDFLAG2_WAIT; + end if; + when WR_ENDFLAG2_WAIT => + state_write <= WR_ENDFLAG2; + + when WR_ENDFLAG2 => + if (ready_wi = '1') then + wiz_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; + wiz_data <= ram_data; + write_wi = '1'; + number_of_words_written_to_fifo <= number_of_words_written_to_fifo + 1; + state_write <= WR_STRANGE_WAIT; + end if; - -- End Write End Package Flag - - -- Wait???? - when WR_05a => - state_sig <= X"4E"; - if (wait_cntr < 10) then -- 3000 works??? - wait_cntr <= wait_cntr + 1; - else - wait_cntr <= 0; - state_write <= WR_05b; - end if; - when WR_05b => - state_write <= WR_05_PREPARE_LENGTH_INFO; - - --Send FIFO - when WR_05_PREPARE_LENGTH_INFO => - --number_of_words_written_to_fifo <= number_of_words_written_to_fifo - 1; - state_init <= WRITE_DATA; - state_write <= WR_05_POSTPREPARE_LENGTH_INFO; + when WR_STRANGE_WAIT => + if (wait_cntr < 10) then -- 3000 works??? + wait_cntr <= wait_cntr + 1; + else + wait_cntr <= 0; + state_write <= WR_05_PREPARE_LENGTH_INFO; + end if; + --Send FIFO + when WR_05_PREPARE_LENGTH_INFO => + --number_of_words_written_to_fifo <= number_of_words_written_to_fifo - 1; + state_write <= WR_05_POSTPREPARE_LENGTH_INFO; + when WR_05_POSTPREPARE_LENGTH_INFO => + number_of_bytes_written_to_fifo <= number_of_words_written_to_fifo(15 downto 0) & '0'; + state_write <= WR_MESSAGE_LEN_HIGH_WORD; + + when WR_MESSAGE_LEN_HIGH_WORD => + if (ready_i = '1') then + wiz_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC; + wiz_data <= (0 => write_length_bytes (16), others => '0'); + --wiz_data <= (0 => number_of_bytes_written_to_fifo(16), others => '0'); + state_write <= WR_MESSAGE_LEN_LOW_WORD; + end if; - - when WR_05_POSTPREPARE_LENGTH_INFO => - number_of_bytes_written_to_fifo <= number_of_words_written_to_fifo(15 downto 0) & '0'; - state_init <= WRITE_DATA; - state_write <= WR_05; - - - when WR_05 => - ram_access <= '0'; - state_sig <= X"50"; - par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC; - par_data <= (0 => write_length_bytes (16), others => '0'); - --par_data <= (0 => number_of_bytes_written_to_fifo(16), others => '0'); - state_init <= WRITE_REG; - state_write <= WR_06; - when WR_06 => - par_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2"; - par_data <= write_length_bytes (15 downto 0); - --par_data <= number_of_bytes_written_to_fifo(15 downto 0); + when WR_MESSAGE_LEN_LOW_WORD => + if (ready_wi= '1') then + wiz_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2"; + wiz_data <= write_length_bytes (15 downto 0); + --wiz_data <= number_of_bytes_written_to_fifo(15 downto 0); + state_write <= WR_SEND_COMMAND; + end if; + + when WR_SEND_COMMAND => + number_of_words_written_to_fifo <= (others => '0'); + if (ready_wi <= '1') then + wiz_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC; + wiz_data <= X"0020"; -- Send + write_wi <= '1'; + end if + state_write <= WR_ACK; + + when WR_ACK => + data_valid_ack <= '1'; + state_write <= WR_WAIT_FOR_ACK; + + when WR_WAIT_FOR_ACK => + state_write <= WR_WAIT_FOR_ACK; + if (data_valid_sr(1) = '0') then + data_valid_ack <= '0'; - state_init <= WRITE_REG; - state_write <= WR_07; - when WR_07 => - number_of_words_written_to_fifo <= (others => '0'); - state_sig <= X"51"; - par_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC; - par_data <= X"0020"; -- Send - state_init <= WRITE_REG; - state_write <= WR_ACK; - when WR_ACK => - data_valid_ack <= '1'; - state_write <= WR_WAIT_FOR_ACK; - when WR_WAIT_FOR_ACK => - state_write <= WR_WAIT_FOR_ACK; - if (data_valid_sr(1) = '0') then - data_valid_ack <= '0'; - state_init <= next_state_tmp; - state_write <= WR_START; - end if; - - - when others => - state_sig <= X"4F"; + state_write <= WR_START; + state_init <= MAIN; + -- maybe MAIN1 is better ?! + end if; + + + when others => + null; end case; -- End WRITE_DATA @@ -1461,5 +1501,4 @@ when others => - state_sig <= X"F0"; null; end case;