Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd (revision 10899) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/clock_generator_var_ps_struct.vhd (revision 10900) @@ -2,8 +2,8 @@ -- -- Created: --- by - daqct3.UNKNOWN (IHP110) --- at - 17:35:41 03.03.2011 +-- by - dneise.UNKNOWN (E5B-LABOR6) +-- at - 13:20:47 01.06.2011 -- --- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) -- LIBRARY ieee; @@ -33,8 +33,8 @@ -- -- Created: --- by - daqct3.UNKNOWN (IHP110) --- at - 17:35:41 03.03.2011 +-- by - dneise.UNKNOWN (E5B-LABOR6) +-- at - 13:20:48 01.06.2011 -- --- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) -- LIBRARY ieee; Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd (revision 10899) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd (revision 10900) @@ -2,8 +2,8 @@ -- -- Created: --- by - daqct3.UNKNOWN (IHP110) --- at - 11:58:57 27.05.2011 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) +-- by - dneise.UNKNOWN (E5B-LABOR6) +-- at - 15:10:43 01.06.2011 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) -- LIBRARY ieee; @@ -74,8 +74,8 @@ -- -- Created: --- by - daqct3.UNKNOWN (IHP110) --- at - 11:58:58 27.05.2011 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) +-- by - dneise.UNKNOWN (E5B-LABOR6) +-- at - 15:10:44 01.06.2011 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) -- LIBRARY ieee; Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_with_5300_2_struct.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_with_5300_2_struct.vhd (revision 10900) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_with_5300_2_struct.vhd (revision 10900) @@ -0,0 +1,305 @@ +-- VHDL Entity FACT_FAD_lib.FAD_Board_with_5300_2.symbol +-- +-- Created: +-- by - dneise.UNKNOWN (E5B-LABOR6) +-- at - 14:21:08 01.06.2011 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; + +ENTITY FAD_Board_with_5300_2 IS + PORT( + A0_D : IN std_logic_vector (11 DOWNTO 0); + A1_D : IN std_logic_vector (11 DOWNTO 0); + A2_D : IN std_logic_vector (11 DOWNTO 0); + A3_D : IN std_logic_vector (11 DOWNTO 0); + A_OTR : IN std_logic_vector (3 DOWNTO 0); + D0_SROUT : IN std_logic; + D1_SROUT : IN std_logic; + D2_SROUT : IN std_logic; + D3_SROUT : IN std_logic; + D_PLLLCK : IN std_logic_vector (3 DOWNTO 0); + D_T_in : IN std_logic_vector (1 DOWNTO 0); + LINE : IN std_logic_vector ( 5 DOWNTO 0 ); + REFCLK : IN std_logic; + RS485_E_DI : IN std_logic; + TRG : IN STD_LOGIC; + W_INT : IN std_logic; + X_50M : IN STD_LOGIC; + A0_T : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); + A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + AMBER_LED : OUT std_logic; + A_CLK : OUT std_logic_vector (3 DOWNTO 0); + DAC_CS : OUT std_logic; + DENABLE : OUT std_logic := '0'; + DSRCLK : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); + DWRITE : OUT std_logic := '0'; + D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); + D_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + D_T2 : OUT std_logic_vector (1 DOWNTO 0) := (others => '0'); + EE_CS : OUT std_logic; + GREEN_LED : OUT std_logic; + MOSI : OUT std_logic := '0'; + OE_ADC : OUT STD_LOGIC; + RED_LED : OUT std_logic; + RS485_C_DE : OUT std_logic; + RS485_C_DO : OUT std_logic; + RS485_C_RE : OUT std_logic; + RS485_E_DE : OUT std_logic; + RS485_E_DO : OUT std_logic; + RS485_E_RE : OUT std_logic; + RSRLOAD : OUT std_logic := '0'; + SRIN : OUT std_logic := '0'; + S_CLK : OUT std_logic; + TCS : OUT std_logic_vector (3 DOWNTO 0); + TRG_V : OUT std_logic := '0'; + W_A : OUT std_logic_vector (9 DOWNTO 0); + W_CS : OUT std_logic := '1'; + W_RD : OUT std_logic := '1'; + W_RES : OUT std_logic := '1'; + W_WR : OUT std_logic := '1'; + MISO : INOUT std_logic; + W_D : INOUT std_logic_vector (15 DOWNTO 0) + ); + +-- Declarations + +END FAD_Board_with_5300_2 ; + +-- +-- VHDL Architecture FACT_FAD_lib.FAD_Board_with_5300_2.struct +-- +-- Created: +-- by - dneise.UNKNOWN (E5B-LABOR6) +-- at - 14:21:09 01.06.2011 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +USE IEEE.NUMERIC_STD.all; +USE ieee.std_logic_unsigned.all; + +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all; + +LIBRARY FACT_FAD_lib; + +ARCHITECTURE struct OF FAD_Board_with_5300_2 IS + + -- Architecture declarations + + -- Internal signal declarations + SIGNAL ADC_CLK : std_logic; + -- for debugging + SIGNAL DG_state : std_logic_vector(7 DOWNTO 0); + SIGNAL SRCLK : std_logic := '0'; + SIGNAL adc_data_array : adc_data_array_type; + SIGNAL alarm_refclk_too_high : std_logic := '0'; + SIGNAL alarm_refclk_too_low : std_logic := '0'; + SIGNAL board_id : std_logic_vector(3 DOWNTO 0); + SIGNAL counter_result : std_logic_vector(11 DOWNTO 0) := (others => '0'); + SIGNAL crate_id : std_logic_vector(1 DOWNTO 0); + SIGNAL debug_data_ram_empty : std_logic; + SIGNAL debug_data_valid : std_logic; + SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL mem_manager_state : std_logic_vector(3 DOWNTO 0); -- state is encoded here ... useful for debugging. + SIGNAL socket_tx_free_out : std_logic_vector(16 DOWNTO 0); -- 17bit value .. that's true + SIGNAL w5300_state : std_logic_vector(7 DOWNTO 0); -- state is encoded here ... useful for debugging. + + + -- Component Declarations + COMPONENT FAD_main_with_w53002 + GENERIC ( + RAMADDRWIDTH64b : integer := 12 + ); + PORT ( + CLK : IN std_logic ; + D_T_in : IN std_logic_vector (1 DOWNTO 0); + FTM_RS485_rx_d : IN std_logic ; + SROUT_in_0 : IN std_logic ; + SROUT_in_1 : IN std_logic ; + SROUT_in_2 : IN std_logic ; + SROUT_in_3 : IN std_logic ; + adc_data_array : IN adc_data_array_type ; + adc_otr_array : IN std_logic_vector (3 DOWNTO 0); + board_id : IN std_logic_vector (3 DOWNTO 0); + crate_id : IN std_logic_vector (1 DOWNTO 0); + drs_refclk_in : IN std_logic ; -- used TO check if DRS REFCLK exsists, if not DENABLE inhibit + plllock_in : IN std_logic_vector (3 DOWNTO 0); -- high level, if dominowave is running and DRS PLL locked + trigger : IN std_logic ; + wiz_int : IN std_logic ; + ADC_CLK : OUT std_logic ; + CLK_25_PS : OUT std_logic ; + CLK_50 : OUT std_logic ; + -- for debugging + DG_state : OUT std_logic_vector (7 DOWNTO 0); + FTM_RS485_rx_en : OUT std_logic ; + FTM_RS485_tx_d : OUT std_logic ; + FTM_RS485_tx_en : OUT std_logic ; + RSRLOAD : OUT std_logic := '0'; + SRCLK : OUT std_logic := '0'; + SRIN_out : OUT std_logic := '0'; + adc_oeb : OUT std_logic := '1'; + alarm_refclk_too_high : OUT std_logic ; + alarm_refclk_too_low : OUT std_logic ; + amber : OUT std_logic ; + counter_result : OUT std_logic_vector (11 DOWNTO 0); + dac_cs : OUT std_logic ; + debug_data_ram_empty : OUT std_logic ; + debug_data_valid : OUT std_logic ; + denable : OUT std_logic := '0'; -- default domino wave off + drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); + drs_dwrite : OUT std_logic := '1'; + green : OUT std_logic ; + led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + mem_manager_state : OUT std_logic_vector (3 DOWNTO 0); -- state is encoded here ... useful for debugging. + mosi : OUT std_logic := '0'; + red : OUT std_logic ; + sclk : OUT std_logic ; + sensor_cs : OUT std_logic_vector (3 DOWNTO 0); + socket_tx_free_out : OUT std_logic_vector (16 DOWNTO 0); -- 17bit value .. that's true + trigger_veto : OUT std_logic := '1'; + w5300_state : OUT std_logic_vector (7 DOWNTO 0); -- state is encoded here ... useful for debugging. + wiz_addr : OUT std_logic_vector (9 DOWNTO 0); + wiz_cs : OUT std_logic := '1'; + wiz_rd : OUT std_logic := '1'; + wiz_reset : OUT std_logic := '1'; + wiz_wr : OUT std_logic := '1'; + sio : INOUT std_logic ; + wiz_data : INOUT std_logic_vector (15 DOWNTO 0) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : FAD_main_with_w53002 USE ENTITY FACT_FAD_lib.FAD_main_with_w53002; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 SRCLK + DSRCLK <= ( SRCLK, SRCLK,SRCLK,SRCLK); + + -- HDL Embedded Text Block 2 ADC_CLK + A_CLK <= ( + ADC_CLK, + ADC_CLK, + ADC_CLK, + ADC_CLK + ); + + -- HDL Embedded Text Block 3 ADC_DATA + adc_data_array <= ( A0_D, A1_D, A2_D, A3_D ); + + -- HDL Embedded Text Block 4 eb_ID + -- hard-wired IDs + board_id <= LINE(5 downto 2); + crate_id <= LINE(1 downto 0); + + -- HDL Embedded Text Block 9 eb3 + -- testpins D_T2 are used as MAX3485 outputs. + + --D_T <= (others => '0'); + D_T <= w5300_state; + D_T2(0) <= debug_data_valid; + --D_T2(1) <= debug_data_ram_empty; + D_T2(1) <= socket_tx_free_out(16); + --D_T2 <= ( others => '0' ); + + + + + --A0_T <= DG_state; + --A1_T(3 downto 0) <= mem_manager_state; + --A1_T(7 downto 4) <= "1100"; + + A0_T <= socket_tx_free_out(7 downto 0); + A1_T <= socket_tx_free_out(15 downto 8); + + --D_T(3 downto 0) <= counter_result ( 11 downto 8); + --D_T(4) <= alarm_refclk_too_low; + --D_T(5) <= alarm_refclk_too_high; + --D_T(6) <= '0'; + --D_T(7) <= '0'; + + + + -- additional MAX3485 is switched to shutdown mode + RS485_C_RE <= '1'; --inverted logic + RS485_C_DE <= '0'; + RS485_C_DO <= '0'; + -- MAX3485 receiver out pit is fed out... should be HIGH-Z + + + -- EEPROM is not used on FAD. CS is always high. + EE_CS <= '1'; + + + -- Instance port mappings. + Inst_FAD_main_with_w5300_2 : FAD_main_with_w53002 + GENERIC MAP ( + RAMADDRWIDTH64b => 15 + ) + PORT MAP ( + CLK => X_50M, + D_T_in => D_T_in, + FTM_RS485_rx_d => RS485_E_DI, + SROUT_in_0 => D0_SROUT, + SROUT_in_1 => D1_SROUT, + SROUT_in_2 => D2_SROUT, + SROUT_in_3 => D3_SROUT, + adc_data_array => adc_data_array, + adc_otr_array => A_OTR, + board_id => board_id, + crate_id => crate_id, + drs_refclk_in => REFCLK, + plllock_in => D_PLLLCK, + trigger => TRG, + wiz_int => W_INT, + ADC_CLK => ADC_CLK, + CLK_25_PS => OPEN, + CLK_50 => OPEN, + DG_state => DG_state, + FTM_RS485_rx_en => RS485_E_RE, + FTM_RS485_tx_d => RS485_E_DO, + FTM_RS485_tx_en => RS485_E_DE, + RSRLOAD => RSRLOAD, + SRCLK => SRCLK, + SRIN_out => SRIN, + adc_oeb => OE_ADC, + alarm_refclk_too_high => alarm_refclk_too_high, + alarm_refclk_too_low => alarm_refclk_too_low, + amber => GREEN_LED, + counter_result => counter_result, + dac_cs => DAC_CS, + debug_data_ram_empty => debug_data_ram_empty, + debug_data_valid => debug_data_valid, + denable => DENABLE, + drs_channel_id => D_A, + drs_dwrite => DWRITE, + green => AMBER_LED, + led => led, + mem_manager_state => mem_manager_state, + mosi => MOSI, + red => RED_LED, + sclk => S_CLK, + sensor_cs => TCS, + socket_tx_free_out => socket_tx_free_out, + trigger_veto => TRG_V, + w5300_state => w5300_state, + wiz_addr => W_A, + wiz_cs => W_CS, + wiz_rd => W_RD, + wiz_reset => W_RES, + wiz_wr => W_WR, + sio => MISO, + wiz_data => W_D + ); + +END struct; Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd (revision 10899) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd (revision 10900) @@ -193,5 +193,5 @@ -- for W5300 modul2 -constant W5300_RAM_ADDR_WIDTH : integer := 14; +constant W5300_RAM_ADDR_WIDTH : integer := 17; -- not needed Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd (revision 10899) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd (revision 10900) @@ -2,8 +2,8 @@ -- -- Created: --- by - daqct3.UNKNOWN (IHP110) --- at - 11:58:56 27.05.2011 +-- by - dneise.UNKNOWN (E5B-LABOR6) +-- at - 13:22:03 01.06.2011 -- --- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) -- LIBRARY ieee; @@ -82,8 +82,8 @@ -- -- Created: --- by - daqct3.UNKNOWN (IHP110) --- at - 11:58:57 27.05.2011 +-- by - dneise.UNKNOWN (E5B-LABOR6) +-- at - 13:22:04 01.06.2011 -- --- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) -- library ieee; Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_with_w53002_struct.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_with_w53002_struct.vhd (revision 10900) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_with_w53002_struct.vhd (revision 10900) @@ -0,0 +1,932 @@ +-- VHDL Entity FACT_FAD_lib.FAD_main_with_w53002.symbol +-- +-- Created: +-- by - dneise.UNKNOWN (E5B-LABOR6) +-- at - 14:21:07 01.06.2011 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +LIBRARY FACT_FAD_lib; +USE FACT_FAD_lib.fad_definitions.all; + +ENTITY FAD_main_with_w53002 IS + GENERIC( + RAMADDRWIDTH64b : integer := 12 + ); + PORT( + CLK : IN std_logic; + D_T_in : IN std_logic_vector (1 DOWNTO 0); + FTM_RS485_rx_d : IN std_logic; + SROUT_in_0 : IN std_logic; + SROUT_in_1 : IN std_logic; + SROUT_in_2 : IN std_logic; + SROUT_in_3 : IN std_logic; + adc_data_array : IN adc_data_array_type; + adc_otr_array : IN std_logic_vector (3 DOWNTO 0); + board_id : IN std_logic_vector (3 DOWNTO 0); + crate_id : IN std_logic_vector (1 DOWNTO 0); + drs_refclk_in : IN std_logic; -- used to check if DRS REFCLK exsists, if not DENABLE inhibit + plllock_in : IN std_logic_vector (3 DOWNTO 0); -- high level, if dominowave is running and DRS PLL locked + trigger : IN std_logic; + wiz_int : IN std_logic; + ADC_CLK : OUT std_logic; + CLK_25_PS : OUT std_logic; + CLK_50 : OUT std_logic; + -- for debugging + DG_state : OUT std_logic_vector (7 DOWNTO 0); + FTM_RS485_rx_en : OUT std_logic; + FTM_RS485_tx_d : OUT std_logic; + FTM_RS485_tx_en : OUT std_logic; + RSRLOAD : OUT std_logic := '0'; + SRCLK : OUT std_logic := '0'; + SRIN_out : OUT std_logic := '0'; + adc_oeb : OUT std_logic := '1'; + alarm_refclk_too_high : OUT std_logic; + alarm_refclk_too_low : OUT std_logic; + amber : OUT std_logic; + counter_result : OUT std_logic_vector (11 DOWNTO 0); + dac_cs : OUT std_logic; + debug_data_ram_empty : OUT std_logic; + debug_data_valid : OUT std_logic; + denable : OUT std_logic := '0'; -- default domino wave off + drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); + drs_dwrite : OUT std_logic := '1'; + green : OUT std_logic; + led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + mem_manager_state : OUT std_logic_vector (3 DOWNTO 0); -- state is encoded here ... useful for debugging. + mosi : OUT std_logic := '0'; + red : OUT std_logic; + sclk : OUT std_logic; + sensor_cs : OUT std_logic_vector (3 DOWNTO 0); + socket_tx_free_out : OUT std_logic_vector (16 DOWNTO 0); -- 17bit value .. that's true + trigger_veto : OUT std_logic := '1'; + w5300_state : OUT std_logic_vector (7 DOWNTO 0); -- state is encoded here ... useful for debugging. + wiz_addr : OUT std_logic_vector (9 DOWNTO 0); + wiz_cs : OUT std_logic := '1'; + wiz_rd : OUT std_logic := '1'; + wiz_reset : OUT std_logic := '1'; + wiz_wr : OUT std_logic := '1'; + sio : INOUT std_logic; + wiz_data : INOUT std_logic_vector (15 DOWNTO 0) + ); + +-- Declarations + +END FAD_main_with_w53002 ; + +-- +-- VHDL Architecture FACT_FAD_lib.FAD_main_with_w53002.struct +-- +-- Created: +-- by - dneise.UNKNOWN (E5B-LABOR6) +-- at - 14:21:08 01.06.2011 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- +library ieee; +use ieee.std_logic_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use ieee.STD_LOGIC_UNSIGNED.all; + +library fact_fad_lib; +use fact_fad_lib.fad_definitions.all; + +library UNISIM; +--use UNISIM.VComponents.all; +USE IEEE.NUMERIC_STD.all; +USE IEEE.std_logic_signed.all; +USE fact_fad_lib.fad_rs485_constants.all; + +LIBRARY FACT_FAD_lib; + +ARCHITECTURE struct OF FAD_main_with_w53002 IS + + -- Architecture declarations + + -- Internal signal declarations + SIGNAL CLK_25 : std_logic; + SIGNAL DCM_PS_status : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DCM_locked_status : std_logic; + SIGNAL DCM_ready_status : std_logic; + -- + +-- EVT HEADER - part 2 --> FTM trigger informaton, comes in late ... +-- during EVT header wrinting, this field is left out ... and only written into event header, +-- when the DRS chip were read out already. + SIGNAL FTM_RS485_ready : std_logic; + SIGNAL I_really_want_dwrite : STD_LOGIC; + SIGNAL SRCLK1 : std_logic := '0'; + SIGNAL adc_clk_en : std_logic; + SIGNAL adc_data_array_int : adc_data_array_type; + SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0); + SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0); + SIGNAL c_trigger_enable : std_logic := '0'; + SIGNAL c_trigger_mult : std_logic_vector(15 DOWNTO 0); + SIGNAL cont_trigger : std_logic; + SIGNAL current_dac_array : dac_array_type := ( others => 0); + SIGNAL dac_setting : dac_array_type := DEFAULT_DAC; --<<-- default defined in fad_definitions.vhd + SIGNAL data_out : std_logic_vector(63 DOWNTO 0); + SIGNAL data_ram_empty : std_logic; + SIGNAL data_valid_ack : std_logic := '0'; + SIGNAL denable_prim : std_logic := '0'; -- default domino wave off + SIGNAL denable_sig : std_logic := '0'; -- default domino wave off + SIGNAL dg_config_done : std_logic; + SIGNAL dg_start_config : std_logic := '0'; + SIGNAL din1 : std_logic := '0'; -- default domino wave off + SIGNAL dna : STD_LOGIC_VECTOR(63 DOWNTO 0) := (others => '0'); + SIGNAL dout : STD_LOGIC; + SIGNAL dout0 : STD_LOGIC; + SIGNAL dout1 : STD_LOGIC; + SIGNAL dout2 : STD_LOGIC; + SIGNAL dout3 : STD_LOGIC; + SIGNAL dout4 : STD_LOGIC; + SIGNAL drs_clk_en : std_logic := '0'; + SIGNAL drs_read_s_cell : std_logic := '0'; + SIGNAL drs_read_s_cell_ready : std_logic; + -- -- +-- drs_dwrite : out std_logic := '1'; + SIGNAL drs_readout_ready : std_logic := '0'; + SIGNAL drs_readout_ready_ack : std_logic; + SIGNAL drs_readout_started : std_logic; + SIGNAL drs_s_cell_array : drs_s_cell_array_type; + SIGNAL drs_srin_data : std_logic_vector(7 DOWNTO 0) := (others => '0'); + SIGNAL dwrite_enable_w5300 : std_logic := '1'; + SIGNAL dwrite_global_enable : std_logic := '1'; + SIGNAL dwrite_trigger_manager : std_logic := '1'; + SIGNAL enable_i : std_logic; + SIGNAL enabled_trigger_or_s_trigger : std_logic; + SIGNAL is_idle : std_logic; + SIGNAL memory_manager_config_start : std_logic := '0'; + SIGNAL memory_manager_config_valid : std_logic; + SIGNAL package_length : std_logic_vector(15 DOWNTO 0); + SIGNAL ps_direction : std_logic := '1'; -- default phase shift upwards + SIGNAL ps_do_phase_shift : std_logic := '0'; --pulse this to phase shift once + SIGNAL ps_reset : std_logic := '0'; -- pulse this to reset the variable phase shift + SIGNAL ram_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0); + SIGNAL ram_data : std_logic_vector(15 DOWNTO 0); + SIGNAL ram_start_addr : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0); + SIGNAL ram_write_ea : std_logic; + SIGNAL ram_write_ready : std_logic := '0'; + SIGNAL ready : STD_LOGIC := '0'; + SIGNAL rec_timeout_occured : std_logic := '0'; + SIGNAL reset_synch_i : std_logic; + SIGNAL reset_trigger_id : std_logic := '0'; + SIGNAL roi_max : roi_max_type; + SIGNAL roi_setting : roi_array_type; + SIGNAL rs465_data : std_logic_vector(55 DOWNTO 0); --7 byte + -- EVT HEADER - part 6 + SIGNAL runnumber : std_logic_vector(31 DOWNTO 0); + SIGNAL s_trigger : std_logic; + SIGNAL s_trigger_or_cont_trigger : std_logic; + SIGNAL sclk_enable : std_logic; + SIGNAL sensor_array : sensor_array_type; + SIGNAL sensor_ready : std_logic; + SIGNAL socks_connected : std_logic; + SIGNAL socks_waiting : std_logic; + SIGNAL software_trigger_in : std_logic; + SIGNAL spi_interface_config_start : std_logic := '0'; + SIGNAL spi_interface_config_valid : std_logic; + SIGNAL srclk_enable : std_logic := '0'; + SIGNAL srin_write_ack : std_logic := '0'; + SIGNAL srin_write_ready : std_logic := '0'; + SIGNAL start_srin_write_8b : std_logic; + SIGNAL time : std_logic_vector(31 DOWNTO 0); + SIGNAL trigger_enable : std_logic; + SIGNAL trigger_id : std_logic_vector(31 DOWNTO 0); + SIGNAL trigger_or_s_trigger : std_logic; + SIGNAL trigger_out : std_logic; + SIGNAL wiz_number_of_channels : std_logic_vector(3 DOWNTO 0) := (others => '0'); + SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0'); + SIGNAL wiz_write_ea : std_logic := '0'; + SIGNAL wiz_write_end : std_logic := '0'; + SIGNAL wiz_write_header : std_logic := '0'; + SIGNAL wiz_write_length : std_logic_vector(16 DOWNTO 0) := (others => '0'); + SIGNAL write_ea : std_logic_vector(0 DOWNTO 0) := "0"; + + -- Implicit buffer signal declarations + SIGNAL CLK_25_PS_internal : std_logic; + SIGNAL CLK_50_internal : std_logic; + SIGNAL alarm_refclk_too_high_internal : std_logic; + SIGNAL alarm_refclk_too_low_internal : std_logic; + SIGNAL counter_result_internal : std_logic_vector (11 DOWNTO 0); + + + -- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'split' + SIGNAL mw_U_0temp_din : std_logic_vector(3 DOWNTO 0); + + -- Component Declarations + COMPONENT FAD_rs485_receiver + GENERIC ( + -- defined in fad_rs485_definitions.fad_rs485_constants + RX_BYTES : integer := RS485_MESSAGE_LEN_BYTES; -- no. of bytes to receive + RX_WIDTH : integer := RS485_MESSAGE_LEN_BYTES * 8 -- no. of bits to receive + ); + PORT ( + rec_clk : IN std_logic; + rec_start : IN std_logic; + rx_d : IN std_logic; + rec_dout : OUT std_logic_vector (RX_WIDTH - 1 DOWNTO 0) := (others => '0'); + rec_timeout_occured : OUT std_logic := '0'; + rec_valid : OUT std_logic := '0'; + rx_en : OUT std_logic; + tx_d : OUT std_logic; + tx_en : OUT std_logic + ); + END COMPONENT; + COMPONENT REFCLK_counter + PORT ( + clk : IN std_logic; + refclk_in : IN std_logic; + alarm_refclk_too_high : OUT std_logic := '0'; + alarm_refclk_too_low : OUT std_logic := '0'; + counter_result : OUT std_logic_vector (11 DOWNTO 0) := (others => '0') + ); + END COMPONENT; + COMPONENT adc_buffer + PORT ( + adc_data_array : IN adc_data_array_type; + adc_otr_array : IN std_logic_vector (3 DOWNTO 0); + clk_ps : IN std_logic; + adc_data_array_int : OUT adc_data_array_type; + adc_otr : OUT std_logic_vector (3 DOWNTO 0) + ); + END COMPONENT; + COMPONENT clock_generator_var_ps + PORT ( + CLK : IN std_logic ; + RST_IN : IN std_logic ; + direction : IN std_logic ; + do_shift : IN std_logic ; + CLK_25 : OUT std_logic ; + CLK_25_PS : OUT std_logic ; + CLK_50 : OUT std_logic ; + locked_status_o : OUT std_logic ; + offset : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + ready_status_o : OUT std_logic + ); + END COMPONENT; + COMPONENT continous_pulser + GENERIC ( + MINIMAL_TRIGGER_WAIT_TIME : integer := 250000; + TRIGGER_WIDTH : integer := 5 + ); + PORT ( + CLK : IN std_logic; + enable : IN std_logic; + multiplier : IN std_logic_vector (15 DOWNTO 0); + trigger : OUT std_logic + ); + END COMPONENT; + COMPONENT dataRAM_64b_16b_width14_5 + PORT ( + clka : IN std_logic ; + dina : IN std_logic_VECTOR (63 DOWNTO 0); + addra : IN std_logic_VECTOR (14 DOWNTO 0); + wea : IN std_logic_VECTOR (0 DOWNTO 0); + clkb : IN std_logic ; + addrb : IN std_logic_VECTOR (16 DOWNTO 0); + doutb : OUT std_logic_VECTOR (15 DOWNTO 0) + ); + END COMPONENT; + COMPONENT data_generator + GENERIC ( + RAM_ADDR_WIDTH : integer := 12 + ); + PORT ( + -- for debugging + state : OUT std_logic_vector (7 DOWNTO 0); + is_idle : OUT std_logic ; + clk : IN std_logic ; -- CLK_25. + data_out : OUT std_logic_vector (63 DOWNTO 0); + addr_out : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + dataRAM_write_ea_o : OUT std_logic_vector (0 DOWNTO 0) := "0"; + ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0); + ram_write_ea : IN std_logic ; + ram_write_ready : OUT std_logic := '0'; + roi_array : IN roi_array_type ; + roi_max : IN roi_max_type ; + sensor_array : IN sensor_array_type ; + sensor_ready : IN std_logic ; + dac_array : IN dac_array_type ; + config_start : IN std_logic ; + config_done : OUT std_logic := '0'; + -- EVT HEADER - part 1 + package_length : IN std_logic_vector (15 DOWNTO 0); + pll_lock : IN std_logic_vector ( 3 DOWNTO 0); + dwrite_enable_in : IN std_logic ; + denable_enable_in : IN std_logic ; + -- EVT HEADER - part 2 --> FTM trigger informaton, comes in late ... + -- during EVT header wrinting, this field is left out ... and only written into event header, + -- when the DRS chip were read out already. + FTM_RS485_ready : IN std_logic ; + FTM_trigger_info : IN std_logic_vector (55 DOWNTO 0); --7 byte + FTM_receiver_status : IN std_logic ; + -- EVT HEADER - part 3 + fad_event_counter : IN std_logic_vector (31 DOWNTO 0); + refclk_counter : IN std_logic_vector (11 DOWNTO 0); + refclk_too_high : IN std_logic ; + refclk_too_low : IN std_logic ; + -- EVT HEADER - part 4 + board_id : IN std_logic_vector (3 DOWNTO 0); + crate_id : IN std_logic_vector (1 DOWNTO 0); + DCM_PS_status : IN std_logic_vector (7 DOWNTO 0); + DCM_locked_status : IN std_logic ; + DCM_ready_status : IN std_logic ; + SPI_SCLK_enable_status : IN std_logic ; + TRG_GEN_div : IN std_logic_vector (15 DOWNTO 0); + -- EVT HEADER - part 5 + dna : IN std_logic_vector (63 DOWNTO 0); + -- EVT HEADER - part 6 + runnumber : IN std_logic_vector (31 DOWNTO 0); + timer_value : IN std_logic_vector (31 DOWNTO 0); -- time in units of 100us + hardware_trigger_in : IN std_logic ; + software_trigger_in : IN std_logic ; + adc_data_array : IN adc_data_array_type ; + adc_output_enable_inverted : OUT std_logic := '1'; + adc_clk_en : OUT std_logic := '0'; + adc_otr : IN std_logic_vector (3 DOWNTO 0); + drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); + --drs_dwrite : out std_logic := '1'; + drs_readout_ready : OUT std_logic := '0'; + drs_readout_ready_ack : IN std_logic ; + drs_clk_en : OUT std_logic := '0'; + start_read_drs_stop_cell : OUT std_logic := '0'; + drs_srin_write_8b : OUT std_logic := '0'; + drs_srin_write_ack : IN std_logic ; + drs_srin_data : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); + drs_srin_write_ready : IN std_logic ; + drs_read_s_cell_ready : IN std_logic ; + drs_s_cell_array : IN drs_s_cell_array_type ; + drs_readout_started : OUT std_logic := '0'; + trigger_veto : OUT std_logic := '1' + ); + END COMPONENT; + COMPONENT dna_gen + PORT ( + clk : IN STD_LOGIC ; + dna : OUT STD_LOGIC_VECTOR (63 DOWNTO 0) := (others => '0'); + ready : OUT STD_LOGIC := '0' + ); + END COMPONENT; + COMPONENT drs_pulser + PORT ( + CLK : IN std_logic; + SROUT_in_0 : IN std_logic; + SROUT_in_1 : IN std_logic; + SROUT_in_2 : IN std_logic; + SROUT_in_3 : IN std_logic; + srin_data : IN std_logic_vector (7 DOWNTO 0); + start_endless_mode : IN std_logic; + start_read_stop_pos_mode : IN std_logic; + start_srin_write_8b : IN std_logic; + RSRLOAD : OUT std_logic := '0'; + SRCLK : OUT std_logic := '0'; + SRIN_out : OUT std_logic := '0'; + srin_write_ack : OUT std_logic := '0'; + srin_write_ready : OUT std_logic := '0'; + stop_pos : OUT drs_s_cell_array_type; + stop_pos_valid : OUT std_logic := '0' + ); + END COMPONENT; + COMPONENT led_controller + GENERIC ( + HEARTBEAT_PWM_DIVIDER : integer := 500; + WAITING_DIVIDER : integer := 500000000 + ); + PORT ( + CLK : IN std_logic; + refclk_too_high : IN std_logic; + refclk_too_low : IN std_logic; + socks_connected : IN std_logic; + socks_waiting : IN std_logic; + trigger : IN std_logic; + additional_flasher_out : OUT std_logic; + amber : OUT std_logic; + green : OUT std_logic; + red : OUT std_logic + ); + END COMPONENT; + COMPONENT memory_manager_2 + GENERIC ( + RAM_ADDR_WIDTH_64B : integer := 12; + RAM_ADDR_WIDTH_16B : integer := 14 + ); + PORT ( + clk : IN std_logic; + config_start : IN std_logic; + dg_config_done : IN std_logic; + ram_write_ready : IN std_logic; + roi_array : IN roi_array_type; + wiz_read_done : IN std_logic; + config_ready : OUT std_logic := '1'; + data_ram_empty : OUT std_logic; + dg_start_config : OUT std_logic := '0'; + package_length : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_64B-1 DOWNTO 0) := (others => '0'); + ram_write_ea : OUT std_logic := '0'; + roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11)); + state : OUT std_logic_vector (3 DOWNTO 0); + wiz_number_of_channels : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); + wiz_ram_start_addr : OUT std_logic_vector (RAM_ADDR_WIDTH_16B-1 DOWNTO 0) := (others => '0'); + wiz_write_ea : OUT std_logic := '0'; + wiz_write_end : OUT std_logic := '0'; + wiz_write_header : OUT std_logic := '0'; + wiz_write_length : OUT std_logic_vector (16 DOWNTO 0) := (others => '0') + ); + END COMPONENT; + COMPONENT spi_interface + PORT ( + clk_50MHz : IN std_logic ; + config_start : IN std_logic ; + dac_array : IN dac_array_type ; + sclk_enable_i : IN std_logic ; + config_ready : OUT std_logic ; + current_dac_array : OUT dac_array_type := ( others => 0); + dac_cs : OUT std_logic ; + mosi : OUT std_logic := '0'; + sclk : OUT std_logic ; + sensor_array : OUT sensor_array_type ; + sensor_cs : OUT std_logic_vector (3 DOWNTO 0); + sensor_ready : OUT std_logic ; + miso : INOUT std_logic + ); + END COMPONENT; + COMPONENT timer + GENERIC ( + TIMER_WIDTH : integer := 32; + PRESCALER : integer := 5000 + ); + PORT ( + clk : IN std_logic; + enable_i : IN std_logic; + reset_synch_i : IN std_logic; + synch_i : IN std_logic; + synched_o : OUT std_logic := '0'; + time_o : OUT std_logic_vector ( TIMER_WIDTH-1 DOWNTO 0) + ); + END COMPONENT; + COMPONENT trigger_counter + PORT ( + trigger_id : OUT std_logic_vector (31 DOWNTO 0); + trigger : IN std_logic ; + reset : IN std_logic ; + clk : IN std_logic + ); + END COMPONENT; + COMPONENT trigger_manager + PORT ( + clk : IN std_logic; + drs_readout_ready : IN std_logic; + trigger_in : IN std_logic; + drs_readout_ready_ack : OUT std_logic := '0'; + drs_write : OUT std_logic := '1'; + trigger_out : OUT std_logic := '0' + ); + END COMPONENT; + COMPONENT w5300_modul2 + PORT ( + BoardID : IN std_logic_vector (3 DOWNTO 0); + CrateID : IN std_logic_vector (1 DOWNTO 0); + MAC_jumper : IN std_logic_vector (1 DOWNTO 0); + clk : IN std_logic; + data_generator_idle_i : IN std_logic; + data_ram_empty : IN std_logic; + data_valid : IN std_logic; + fifo_channels : IN std_logic_vector (3 DOWNTO 0); + int : IN std_logic; + memory_manager_config_valid_i : IN std_logic; + ps_ready : IN std_logic; + ram_data : IN std_logic_vector (15 DOWNTO 0); + ram_start_addr : IN std_logic_vector (W5300_RAM_ADDR_WIDTH-1 DOWNTO 0); + spi_interface_config_valid_i : IN std_logic; + write_end_flag : IN std_logic; + write_header_flag : IN std_logic; + write_length : IN std_logic_vector (16 DOWNTO 0); + addr : OUT std_logic_vector (9 DOWNTO 0); + busy : OUT std_logic := '1'; + c_trigger_enable : OUT std_logic := '0'; + c_trigger_mult : OUT std_logic_vector (15 DOWNTO 0) := conv_std_logic_vector(0 ,16); + cs : OUT std_logic := '1'; + dac_setting : OUT dac_array_type := DEFAULT_DAC; + data_valid_ack : OUT std_logic := '0'; + debug_data_ram_empty : OUT std_logic; + debug_data_valid : OUT std_logic; + denable : OUT std_logic := '0'; + dwrite_enable : OUT std_logic := '1'; + led : OUT std_logic_vector (7 DOWNTO 0) := X"00"; + memory_manager_config_start_o : OUT std_logic := '0'; + ps_direction : OUT std_logic := '1'; + ps_do_phase_shift : OUT std_logic := '0'; + ps_reset : OUT std_logic := '0'; + ram_addr : OUT std_logic_vector (W5300_RAM_ADDR_WIDTH-1 DOWNTO 0); + rd : OUT std_logic := '1'; + reset_trigger_id : OUT std_logic := '0'; + roi_setting : OUT roi_array_type := DEFAULT_ROI; + runnumber : OUT std_logic_vector (31 DOWNTO 0) := conv_std_logic_vector(0 ,32); + s_trigger : OUT std_logic := '0'; + sclk_enable : OUT std_logic := '1'; + socket_tx_free_out : OUT std_logic_vector (16 DOWNTO 0) := '0' & X"0000"; + socks_connected : OUT std_logic; + socks_waiting : OUT std_logic; + spi_interface_config_start_o : OUT std_logic := '0'; + srclk_enable : OUT std_logic := '1'; + state : OUT std_logic_vector (7 DOWNTO 0); + trigger_enable : OUT std_logic; + wiz_reset : OUT std_logic := '1'; + wr : OUT std_logic := '1'; + data : INOUT std_logic_vector (15 DOWNTO 0) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : FAD_rs485_receiver USE ENTITY FACT_FAD_lib.FAD_rs485_receiver; + FOR ALL : REFCLK_counter USE ENTITY FACT_FAD_lib.REFCLK_counter; + FOR ALL : adc_buffer USE ENTITY FACT_FAD_lib.adc_buffer; + FOR ALL : clock_generator_var_ps USE ENTITY FACT_FAD_lib.clock_generator_var_ps; + FOR ALL : continous_pulser USE ENTITY FACT_FAD_lib.continous_pulser; + FOR ALL : dataRAM_64b_16b_width14_5 USE ENTITY FACT_FAD_lib.dataRAM_64b_16b_width14_5; + FOR ALL : data_generator USE ENTITY FACT_FAD_lib.data_generator; + FOR ALL : dna_gen USE ENTITY FACT_FAD_lib.dna_gen; + FOR ALL : drs_pulser USE ENTITY FACT_FAD_lib.drs_pulser; + FOR ALL : led_controller USE ENTITY FACT_FAD_lib.led_controller; + FOR ALL : memory_manager_2 USE ENTITY FACT_FAD_lib.memory_manager_2; + FOR ALL : spi_interface USE ENTITY FACT_FAD_lib.spi_interface; + FOR ALL : timer USE ENTITY FACT_FAD_lib.timer; + FOR ALL : trigger_counter USE ENTITY FACT_FAD_lib.trigger_counter; + FOR ALL : trigger_manager USE ENTITY FACT_FAD_lib.trigger_manager; + FOR ALL : w5300_modul2 USE ENTITY FACT_FAD_lib.w5300_modul2; + -- pragma synthesis_on + + +BEGIN + + -- ModuleWare code(v1.9) for instance 'I6' of 'and' + SRCLK <= SRCLK1 AND srclk_enable; + + -- ModuleWare code(v1.9) for instance 'U_1' of 'and' + dout <= dout0 AND dout1 AND dout2 AND dout3; + + -- ModuleWare code(v1.9) for instance 'U_4' of 'and' + dwrite_global_enable <= dwrite_enable_w5300 AND dout4; + + -- ModuleWare code(v1.9) for instance 'and_1' of 'and' + ADC_CLK <= adc_clk_en AND CLK_25_PS_internal; + + -- ModuleWare code(v1.9) for instance 'and_2' of 'and' + denable_sig <= denable_prim AND din1; + + -- ModuleWare code(v1.9) for instance 'and_4' of 'and' + enabled_trigger_or_s_trigger <= trigger_or_s_trigger + AND trigger_enable; + + -- ModuleWare code(v1.9) for instance 'and_5' of 'and' + drs_dwrite <= dwrite_trigger_manager AND dwrite_global_enable; + + -- ModuleWare code(v1.9) for instance 'U_5' of 'assignment' + denable <= denable_sig; + + -- ModuleWare code(v1.9) for instance 'U_6' of 'gnd' + software_trigger_in <= '0'; + + -- ModuleWare code(v1.9) for instance 'U_15' of 'gnd' + reset_synch_i <= '0'; + + -- ModuleWare code(v1.9) for instance 'inverter_1' of 'inv' + din1 <= NOT(alarm_refclk_too_low_internal); + + -- ModuleWare code(v1.9) for instance 'U_2' of 'or' + dout4 <= dout OR I_really_want_dwrite; + + -- ModuleWare code(v1.9) for instance 'or_1' of 'or' + s_trigger_or_cont_trigger <= s_trigger OR cont_trigger; + + -- ModuleWare code(v1.9) for instance 'or_5' of 'or' + trigger_or_s_trigger <= s_trigger_or_cont_trigger OR trigger; + + -- ModuleWare code(v1.9) for instance 'U_0' of 'split' + mw_U_0temp_din <= plllock_in; + u_0combo_proc: PROCESS (mw_U_0temp_din) + VARIABLE temp_din: std_logic_vector(3 DOWNTO 0); + BEGIN + temp_din := mw_U_0temp_din(3 DOWNTO 0); + dout0 <= temp_din(0); + dout1 <= temp_din(1); + dout2 <= temp_din(2); + dout3 <= temp_din(3); + END PROCESS u_0combo_proc; + + -- ModuleWare code(v1.9) for instance 'U_3' of 'vdd' + I_really_want_dwrite <= '1'; + + -- ModuleWare code(v1.9) for instance 'U_14' of 'vdd' + enable_i <= '1'; + + -- Instance port mappings. + Inst_FAD_rs485_receiver : FAD_rs485_receiver + GENERIC MAP ( + RX_BYTES => RS485_MESSAGE_LEN_BYTES, -- no. of bytes to receive + RX_WIDTH => RS485_MESSAGE_LEN_BYTES * 8 -- no. of bits to receive + ) + PORT MAP ( + rec_clk => CLK_50_internal, + rx_d => FTM_RS485_rx_d, + rx_en => FTM_RS485_rx_en, + tx_d => FTM_RS485_tx_d, + tx_en => FTM_RS485_tx_en, + rec_start => drs_readout_started, + rec_timeout_occured => rec_timeout_occured, + rec_dout => rs465_data, + rec_valid => FTM_RS485_ready + ); + Inst_REFCLK_counter : REFCLK_counter + PORT MAP ( + clk => CLK_50_internal, + refclk_in => drs_refclk_in, + counter_result => counter_result_internal, + alarm_refclk_too_high => alarm_refclk_too_high_internal, + alarm_refclk_too_low => alarm_refclk_too_low_internal + ); + I_main_adc_buffer : adc_buffer + PORT MAP ( + clk_ps => CLK_25_PS_internal, + adc_data_array => adc_data_array, + adc_otr_array => adc_otr_array, + adc_data_array_int => adc_data_array_int, + adc_otr => adc_otr + ); + clock_generator_instance : clock_generator_var_ps + PORT MAP ( + CLK => CLK, + RST_IN => ps_reset, + direction => ps_direction, + do_shift => ps_do_phase_shift, + CLK_25 => CLK_25, + CLK_25_PS => CLK_25_PS_internal, + CLK_50 => CLK_50_internal, + locked_status_o => DCM_locked_status, + offset => DCM_PS_status, + ready_status_o => DCM_ready_status + ); + continous_pulser_instance : continous_pulser + GENERIC MAP ( + MINIMAL_TRIGGER_WAIT_TIME => 25000, + TRIGGER_WIDTH => 5 + ) + PORT MAP ( + CLK => CLK_25, + enable => c_trigger_enable, + multiplier => c_trigger_mult, + trigger => cont_trigger + ); + Inst_dataRAM : dataRAM_64b_16b_width14_5 + PORT MAP ( + clka => CLK_25, + dina => data_out, + addra => addr_out, + wea => write_ea, + clkb => CLK_50_internal, + addrb => ram_addr, + doutb => ram_data + ); + I_main_data_generator : data_generator + GENERIC MAP ( + RAM_ADDR_WIDTH => RAMADDRWIDTH64b + ) + PORT MAP ( + state => DG_state, + is_idle => is_idle, + clk => CLK_25, + data_out => data_out, + addr_out => addr_out, + dataRAM_write_ea_o => write_ea, + ram_start_addr => ram_start_addr, + ram_write_ea => ram_write_ea, + ram_write_ready => ram_write_ready, + roi_array => roi_setting, + roi_max => roi_max, + sensor_array => sensor_array, + sensor_ready => sensor_ready, + dac_array => current_dac_array, + config_start => dg_start_config, + config_done => dg_config_done, + package_length => package_length, + pll_lock => plllock_in, + dwrite_enable_in => dwrite_enable_w5300, + denable_enable_in => denable_sig, + FTM_RS485_ready => FTM_RS485_ready, + FTM_trigger_info => rs465_data, + FTM_receiver_status => rec_timeout_occured, + fad_event_counter => trigger_id, + refclk_counter => counter_result_internal, + refclk_too_high => alarm_refclk_too_high_internal, + refclk_too_low => alarm_refclk_too_low_internal, + board_id => board_id, + crate_id => crate_id, + DCM_PS_status => DCM_PS_status, + DCM_locked_status => DCM_locked_status, + DCM_ready_status => DCM_ready_status, + SPI_SCLK_enable_status => sclk_enable, + TRG_GEN_div => c_trigger_mult, + dna => dna, + runnumber => runnumber, + timer_value => time, + hardware_trigger_in => trigger_out, + software_trigger_in => software_trigger_in, + adc_data_array => adc_data_array_int, + adc_output_enable_inverted => adc_oeb, + adc_clk_en => adc_clk_en, + adc_otr => adc_otr, + drs_channel_id => drs_channel_id, + drs_readout_ready => drs_readout_ready, + drs_readout_ready_ack => drs_readout_ready_ack, + drs_clk_en => drs_clk_en, + start_read_drs_stop_cell => drs_read_s_cell, + drs_srin_write_8b => start_srin_write_8b, + drs_srin_write_ack => srin_write_ack, + drs_srin_data => drs_srin_data, + drs_srin_write_ready => srin_write_ready, + drs_read_s_cell_ready => drs_read_s_cell_ready, + drs_s_cell_array => drs_s_cell_array, + drs_readout_started => drs_readout_started, + trigger_veto => trigger_veto + ); + dna_gen_instance : dna_gen + PORT MAP ( + clk => CLK_25, + dna => dna, + ready => ready + ); + I_main_drs_pulser : drs_pulser + PORT MAP ( + CLK => CLK_25, + start_endless_mode => drs_clk_en, + start_read_stop_pos_mode => drs_read_s_cell, + SROUT_in_0 => SROUT_in_0, + SROUT_in_1 => SROUT_in_1, + SROUT_in_2 => SROUT_in_2, + SROUT_in_3 => SROUT_in_3, + stop_pos => drs_s_cell_array, + stop_pos_valid => drs_read_s_cell_ready, + start_srin_write_8b => start_srin_write_8b, + srin_write_ready => srin_write_ready, + srin_write_ack => srin_write_ack, + srin_data => drs_srin_data, + SRIN_out => SRIN_out, + RSRLOAD => RSRLOAD, + SRCLK => SRCLK1 + ); + Inst_led_controller : led_controller + GENERIC MAP ( + HEARTBEAT_PWM_DIVIDER => 50000, + WAITING_DIVIDER => 50000000 + ) + PORT MAP ( + CLK => CLK_50_internal, + green => green, + amber => amber, + red => red, + additional_flasher_out => OPEN, + trigger => drs_readout_started, + refclk_too_high => alarm_refclk_too_high_internal, + refclk_too_low => alarm_refclk_too_low_internal, + socks_waiting => socks_waiting, + socks_connected => socks_connected + ); + Inst_memory_manager_2 : memory_manager_2 + GENERIC MAP ( + RAM_ADDR_WIDTH_64B => RAMADDRWIDTH64b, + RAM_ADDR_WIDTH_16B => RAMADDRWIDTH64b+2 + ) + PORT MAP ( + state => mem_manager_state, + clk => CLK_25, + config_start => memory_manager_config_start, + config_ready => memory_manager_config_valid, + roi_array => roi_setting, + roi_max => roi_max, + package_length => package_length, + wiz_number_of_channels => wiz_number_of_channels, + dg_start_config => dg_start_config, + dg_config_done => dg_config_done, + ram_write_ready => ram_write_ready, + ram_write_ea => ram_write_ea, + ram_start_addr => ram_start_addr, + wiz_read_done => data_valid_ack, + wiz_write_ea => wiz_write_ea, + wiz_write_length => wiz_write_length, + wiz_ram_start_addr => wiz_ram_start_addr, + wiz_write_header => wiz_write_header, + wiz_write_end => wiz_write_end, + data_ram_empty => data_ram_empty + ); + I_main_SPI_interface : spi_interface + PORT MAP ( + clk_50MHz => CLK_50_internal, + config_start => spi_interface_config_start, + dac_array => dac_setting, + sclk_enable_i => sclk_enable, + config_ready => spi_interface_config_valid, + current_dac_array => current_dac_array, + dac_cs => dac_cs, + mosi => mosi, + sclk => sclk, + sensor_array => sensor_array, + sensor_cs => sensor_cs, + sensor_ready => sensor_ready, + miso => sio + ); + timer_instance : timer + GENERIC MAP ( + TIMER_WIDTH => 32, + PRESCALER => 5000 + ) + PORT MAP ( + clk => CLK_50_internal, + time_o => time, + synch_i => trigger_out, + synched_o => OPEN, + reset_synch_i => reset_synch_i, + enable_i => enable_i + ); + trigger_counter_instance : trigger_counter + PORT MAP ( + trigger_id => trigger_id, + trigger => trigger_out, + reset => reset_trigger_id, + clk => CLK_25_PS_internal + ); + trigger_manager_instance : trigger_manager + PORT MAP ( + clk => CLK_25, + trigger_in => enabled_trigger_or_s_trigger, + trigger_out => trigger_out, + drs_write => dwrite_trigger_manager, + drs_readout_ready => drs_readout_ready, + drs_readout_ready_ack => drs_readout_ready_ack + ); + Inst_w5300_modul2 : w5300_modul2 + PORT MAP ( + state => w5300_state, + debug_data_ram_empty => debug_data_ram_empty, + debug_data_valid => debug_data_valid, + data_generator_idle_i => is_idle, + clk => CLK_50_internal, + wiz_reset => wiz_reset, + addr => wiz_addr, + data => wiz_data, + cs => wiz_cs, + wr => wiz_wr, + rd => wiz_rd, + int => wiz_int, + write_length => wiz_write_length, + ram_start_addr => wiz_ram_start_addr, + ram_data => ram_data, + ram_addr => ram_addr, + data_valid => wiz_write_ea, + data_valid_ack => data_valid_ack, + busy => OPEN, + write_header_flag => wiz_write_header, + write_end_flag => wiz_write_end, + fifo_channels => wiz_number_of_channels, + s_trigger => s_trigger, + c_trigger_enable => c_trigger_enable, + c_trigger_mult => c_trigger_mult, + led => led, + socket_tx_free_out => socket_tx_free_out, + memory_manager_config_start_o => memory_manager_config_start, + memory_manager_config_valid_i => memory_manager_config_valid, + spi_interface_config_start_o => spi_interface_config_start, + spi_interface_config_valid_i => spi_interface_config_valid, + dac_setting => dac_setting, + roi_setting => roi_setting, + runnumber => runnumber, + reset_trigger_id => reset_trigger_id, + data_ram_empty => data_ram_empty, + MAC_jumper => D_T_in, + BoardID => board_id, + CrateID => crate_id, + trigger_enable => trigger_enable, + denable => denable_prim, + dwrite_enable => dwrite_enable_w5300, + sclk_enable => sclk_enable, + srclk_enable => srclk_enable, + ps_direction => ps_direction, + ps_do_phase_shift => ps_do_phase_shift, + ps_reset => ps_reset, + ps_ready => DCM_ready_status, + socks_waiting => socks_waiting, + socks_connected => socks_connected + ); + + -- Implicit buffered output assignments + CLK_25_PS <= CLK_25_PS_internal; + CLK_50 <= CLK_50_internal; + alarm_refclk_too_high <= alarm_refclk_too_high_internal; + alarm_refclk_too_low <= alarm_refclk_too_low_internal; + counter_result <= counter_result_internal; + +END struct; Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_interface_struct.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_interface_struct.vhd (revision 10899) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_interface_struct.vhd (revision 10900) @@ -2,8 +2,8 @@ -- -- Created: --- by - daqct3.UNKNOWN (IHP110) --- at - 08:31:16 18.05.2011 +-- by - dneise.UNKNOWN (E5B-LABOR6) +-- at - 13:20:48 01.06.2011 -- --- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) -- LIBRARY ieee; @@ -38,8 +38,8 @@ -- -- Created: --- by - daqct3.UNKNOWN (IHP110) --- at - 08:31:16 18.05.2011 +-- by - dneise.UNKNOWN (E5B-LABOR6) +-- at - 13:20:48 01.06.2011 -- --- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) -- LIBRARY ieee; Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_interface.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_interface.vhd (revision 10899) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_interface.vhd (revision 10900) @@ -53,5 +53,5 @@ signal RST_TIME : integer range 0 to 500000 := 500000; - signal reset_counter : integer range 0 to RST_TIME := 0; + signal reset_counter : integer range 0 to 500000 := 0; signal ready : std_logic := '0'; begin Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul2.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul2.vhd (revision 10899) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul2.vhd (revision 10900) @@ -41,4 +41,7 @@ + -- to be removed: + led : out std_logic_vector (7 downto 0) := X"00"; + socket_tx_free_out : out std_logic_vector (16 downto 0) := '0' & X"0000"; -- FAD configuration signals: @@ -105,37 +108,47 @@ type state_init_type is ( INTERRUPT, RESET, WAIT_FOR_RESET, - WRITE_REG, READ_REG, - WRITE_DATA, - INIT, LOCATE, IM, MT, - STX0, STX1, STX2, STX3, - SRX0, SRX1, SRX2, SRX3, - MAC0, MAC1, MAC2, - GW0, GW1, - SNM0, SNM1, - IP0, IP1, - --TIMEOUT, - RETRY, - SI_MR, SI_IMR, SI_PORTOR, SI_PORT, SI_SSR, SI_CR_OPEN, SI_IS_OPEN, SI_CR_LISTEN, - SI, SI1, SI1b, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, + INIT, + LOCATE, IM, MT, + STX0, STX1, STX2, STX3, + SRX0, SRX1, SRX2, SRX3, + MAC0, MAC1, MAC2, + GW0, GW1, + SNM0, SNM1, + IP0, IP1, + -- Socket initialisiation + SI_MR, SI_IMR, SI_PORTOR, SI_PORT, SI_SSR, SI_CR_OPEN, SI_IS_OPEN, SI_CR_LISTEN, + ESTABLISH, EST1, - CONFIG, WAIT_100NS, WAIT_UNTIL_DG_IDLE, - CONFIG_MEMORY_MANAGER, WAIT_FOR_CONFIG_MEMORY_MANAGER, - CONFIG_DATA_GENERATOR, WAIT_FOR_CONFIG_DATA_GENERATOR, - CONFIG_DAC_ONLY, WAIT_FOR_CONFIG_DAC_ONLY, + MAIN, + CONFIG, + WAIT_100NS, WAIT_UNTIL_DG_IDLE, + CONFIG_MEMORY_MANAGER, WAIT_FOR_CONFIG_MEMORY_MANAGER, + CONFIG_DAC_ONLY, WAIT_FOR_CONFIG_DAC_ONLY, + MAIN1, + READ_DATA, + MAIN2, MAIN3, + WRITE_DATA - MAIN, MAIN1, MAIN2, MAIN3, CHK_RECEIVED, READ_DATA +-- these states do not exist anymore. +-- WRITE_REG, READ_REG, +-- --TIMEOUT, +-- RETRY, +-- CONFIG_DATA_GENERATOR, WAIT_FOR_CONFIG_DATA_GENERATOR, +-- CHK_RECEIVED, ); type state_write_type is ( - WR_START, - WR_GET_EVT_ID_WAIT1, WR_GET_EVT_ID1, WR_GET_EVT_ID_WAIT2, WR_GET_EVT_ID2, - WR_MOD7_STARTED, WR_WAIT_FOR_MOD7, - WR_CHECK_FOR_FIFO_SPACE_01, WR_CHECK_FOR_FIFO_SPACE_02, WR_CHECK_FOR_FIFO_SPACE_03, WR_CHECK_FOR_FIFO_SPACE_04, - WR_05_PREPARE_LENGTH_INFO, WR_05_POSTPREPARE_LENGTH_INFO, - WR_STRANGE_WAIT, - WR_ACK, WR_WAIT_FOR_ACK, - WR_HEADER_FETCH, WR_HEADER_WAIT, WR_HEADER, - WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2, - WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2 + WR_START, + WR_GET_EVT_ID_WAIT1, WR_GET_EVT_ID1, WR_GET_EVT_ID_WAIT2, WR_GET_EVT_ID2, + WR_MOD7_STARTED, WR_WAIT_FOR_MOD7, + WR_CHECK_FOR_FIFO_SPACE_01, WR_CHECK_FOR_FIFO_SPACE_02, WR_CHECK_FOR_FIFO_SPACE_03, WR_CHECK_FOR_FIFO_SPACE_04, + WR_HEADER_FETCH, WR_HEADER_WAIT, WR_HEADER, + WR_ADC, WR_ADC1, WR_ADC2, + WR_STRANGE_WAIT, + WR_ENDFLAG_WAIT, WR_ENDFLAG, + WR_ENDFLAG2_WAIT, WR_ENDFLAG2, + WR_05_PREPARE_LENGTH_INFO, WR_05_POSTPREPARE_LENGTH_INFO, + WR_MESSAGE_LEN_HIGH_WORD, WR_MESSAGE_LEN_LOW_WORD, WR_SEND_COMMAND, + WR_ACK, WR_WAIT_FOR_ACK ); type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04); @@ -181,5 +194,6 @@ signal drs_cnt : integer range 0 to 3 := 0; signal channel_cnt : integer range 0 to 9 :=0; -signal socket_cnt : integer range 0 to 7 := 0; +signal socket_cnt : std_logic_vector (2 downto 0 ) := "000"; +-- should be integer range 0 to 7 := 0; , but I didn't manage to get it working... signal roi_max : std_logic_vector (10 downto 0) := (others => '0'); @@ -417,5 +431,5 @@ when IR1_03 => state_init <= INTERRUPT; - socket_cnt <= 0; + socket_cnt <= "000"; int_flag <= '0'; interrupt_ignore <= '1'; @@ -444,5 +458,5 @@ when IR2_CHECK_WHICH_SN_IRQ => if (ready_wi = '1') then - if (data_read(socket_cnt) = '1') then -- Sx Interrupt + if (data_read(conv_integer(socket_cnt)) = '1') then -- Sx Interrupt state_interrupt_2 <= IR2_GET_SN_IR; else @@ -483,6 +497,6 @@ if (socket_cnt = 7) then - socket_cnt = 0; - state_interrupt_2 <= IR2_WAIT_UNTIL_SOCKS_CLOSED; + socket_cnt <= "000"; + state_interrupt_2 <= IR2_WAIT_SOCKn_CLOSED; else state_interrupt_2 <= IR2_GET_IR; @@ -493,5 +507,5 @@ if (ready_wi = '1') then wiz_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; - read_wi = '1'; + read_wi <= '1'; state_interrupt_2 <= IR2_WAIT_SOCKn_CLOSED; end if; @@ -501,5 +515,5 @@ if (data_read = X"0000") then --closed if (socket_cnt = 7) then - socket_cnt <= 0; + socket_cnt <= "000"; state_interrupt_2 <= IR2_GOTO_RESET; else @@ -516,8 +530,8 @@ state_interrupt_1 <= IR1_01; state_interrupt_2 <= IR2_GET_IR; - socket_cnt <= 0; + socket_cnt <= "000"; state_init <= RESET; - when others => - null; + --when others => + --null; end case; @@ -530,5 +544,5 @@ socks_waiting <= '0'; socks_connected <= '0'; - socket_cnt <= 0; + socket_cnt <= "000"; interrupt_ignore <= '0'; @@ -799,5 +813,5 @@ when SI_PORT => wiz_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC; - wiz_data <= conv_std_logic_vector(FIRST_PORT + socket_cnt, 16); + wiz_data <= conv_std_logic_vector(FIRST_PORT + unsigned(socket_cnt), 16); if (ready_wi = '1') then write_wi <= '1'; @@ -832,5 +846,5 @@ socket_cnt <= socket_cnt + 1; if (socket_cnt = 7) then - socket_cnt <= 0; + socket_cnt <= "000"; state_init <= ESTABLISH; else @@ -857,5 +871,5 @@ when X"17" => -- established if (socket_cnt = 7) then - socket_cnt <= 0; + socket_cnt <= "000"; busy <= '0'; state_init <= MAIN; @@ -1188,6 +1202,6 @@ end if; - when others => - state_sig <= X"3F"; + --when others => + --state_sig <= X"3F"; end case; -- state_data_read @@ -1265,5 +1279,5 @@ state_write <= WR_CHECK_FOR_FIFO_SPACE_03; read_wi <= '1'; - end if + end if; when WR_CHECK_FOR_FIFO_SPACE_03 => @@ -1282,5 +1296,5 @@ else if (local_write_header_flag = '1') then - state_write <= WR_HEADER_FETCH_1ST; + state_write <= WR_HEADER_FETCH; else state_write <= WR_ADC; @@ -1302,5 +1316,5 @@ state_sig <= X"4A"; ram_addr <= local_ram_start_addr + local_ram_addr; - state_write <= WR_HEADER_WAIT_1ST; + state_write <= WR_HEADER_WAIT; when WR_HEADER_WAIT => @@ -1380,5 +1394,5 @@ wiz_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; wiz_data <= ram_data; - write_wi = '1'; + write_wi <= '1'; number_of_words_written_to_fifo <= number_of_words_written_to_fifo + 1; data_cnt <= data_cnt + 1; @@ -1422,5 +1436,5 @@ wiz_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; wiz_data <= ram_data; - write_wi = '1'; + write_wi <= '1'; number_of_words_written_to_fifo <= number_of_words_written_to_fifo + 1; ram_addr <= adc_data_addr + ((conv_integer(roi_max) + CHANNEL_HEADER_SIZE) * 4) + 1; @@ -1434,5 +1448,5 @@ wiz_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC; wiz_data <= ram_data; - write_wi = '1'; + write_wi <= '1'; number_of_words_written_to_fifo <= number_of_words_written_to_fifo + 1; state_write <= WR_STRANGE_WAIT; @@ -1455,5 +1469,5 @@ when WR_MESSAGE_LEN_HIGH_WORD => - if (ready_i = '1') then + if (ready_wi = '1') then wiz_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC; wiz_data <= (0 => write_length_bytes (16), others => '0'); @@ -1476,5 +1490,5 @@ wiz_data <= X"0020"; -- Send write_wi <= '1'; - end if + end if; state_write <= WR_ACK; @@ -1494,12 +1508,12 @@ - when others => - null; + --when others => + --null; end case; -- End WRITE_DATA - when others => - null; + --when others => + --null; end case; end if; -- int_flag = '0'