Changeset 10908
- Timestamp:
- 06/03/11 16:06:16 (13 years ago)
- Location:
- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd
r10902 r10908 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 2:11:2003.06.20115 -- at - 14:33:27 03.06.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 75 75 -- Created: 76 76 -- by - dneise.UNKNOWN (E5B-LABOR6) 77 -- at - 1 2:11:2003.06.201177 -- at - 14:33:27 03.06.2011 78 78 -- 79 79 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd
r10902 r10908 57 57 --constant SUBVERSION_NUMBER : std_logic_vector (15 downto 0) := conv_std_logic_vector(str_to_int(SUBVERSION_STRING),16); 58 58 constant PACKAGE_VERSION : std_logic_vector(7 downto 0) := X"01"; 59 constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"0 B";59 constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"0F"; 60 60 constant PACKAGE_HEADER_LENGTH : integer := 36; 61 61 constant PACKAGE_HEADER_ZEROS : integer := 0; … … 195 195 -- for W5300 modul2 196 196 constant W5300_RAM_ADDR_WIDTH : integer := 17; 197 constant TX_FIFO_MAX_FREE : std_logic_vector(16 downto 0) := conv_std_logic_vector(15360 ,16); 197 198 198 199 -- not needed -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd
r10902 r10908 3 3 -- Created: 4 4 -- by - dneise.UNKNOWN (E5B-LABOR6) 5 -- at - 1 2:11:1903.06.20115 -- at - 14:33:25 03.06.2011 6 6 -- 7 7 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) … … 83 83 -- Created: 84 84 -- by - dneise.UNKNOWN (E5B-LABOR6) 85 -- at - 1 2:11:2003.06.201185 -- at - 14:33:26 03.06.2011 86 86 -- 87 87 -- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) -
firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd
r10902 r10908 122 122 WR_CHECK_FOR_FIFO_SPACE_01, WR_CHECK_FOR_FIFO_SPACE_02, WR_CHECK_FOR_FIFO_SPACE_03, WR_CHECK_FOR_FIFO_SPACE_04, 123 123 WR_05, WR_05_PREPARE_LENGTH_INFO, WR_05_POSTPREPARE_LENGTH_INFO, 124 WORKAROUND_CHECK_FIFO_SPACE_01, WORKAROUND_CHECK_FIFO_SPACE_02, WORKAROUND_CHECK_FIFO_SPACE_03, WORKAROUND_CHECK_FIFO_SPACE_04, 124 125 WR_05a, WR_05b, WR_06, WR_07, 125 126 WR_ACK, WR_WAIT_FOR_ACK, … … 1298 1299 number_of_bytes_written_to_fifo <= number_of_words_written_to_fifo(15 downto 0) & '0'; 1299 1300 state_init <= WRITE_DATA; 1301 state_write <= WORKAROUND_CHECK_FIFO_SPACE_01; 1302 1303 1304 when WORKAROUND_CHECK_FIFO_SPACE_01 => 1305 par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC; 1306 state_init <= READ_REG; 1307 next_state <= WRITE_DATA; 1308 state_write <= WORKAROUND_CHECK_FIFO_SPACE_02; 1309 when WORKAROUND_CHECK_FIFO_SPACE_02 => 1310 socket_tx_free (16) <= data_read(0); 1311 par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2"; 1312 state_init <= READ_REG; 1313 next_state <= WRITE_DATA; 1314 state_write <= WORKAROUND_CHECK_FIFO_SPACE_03; 1315 when WORKAROUND_CHECK_FIFO_SPACE_03 => 1316 socket_tx_free (15 downto 0) <= data_read; 1317 state_write <= WORKAROUND_CHECK_FIFO_SPACE_04; 1318 when WORKAROUND_CHECK_FIFO_SPACE_04 => 1319 write_length_bytes <= TX_FIFO_MAX_FREE - socket_tx_free; 1300 1320 state_write <= WR_05; 1321 1322 1323 1324 1301 1325 1302 1326
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