Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD.hdp
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD.hdp	(revision 10908)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD.hdp	(revision 10914)
@@ -8,6 +8,6 @@
 simprim = C:/FPGAdv82PS/Xilinx_Lib/simprim
 unimacro = C:/FPGAdv82PS/Xilinx_Lib/unimacro
-unisim = D:\unisim\unisim
-XilinxCoreLib = D:\unisim\xilinxcorelib
+unisim = C:/FPGAdv82PS/Xilinx_Lib/unisim
+XilinxCoreLib = C:/FPGAdv82PS/Xilinx_Lib/XilinxCoreLib
 [QuestaSim]
 secureip = D:/unisim/secureip
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/clock_generator_beha.vhd
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/clock_generator_beha.vhd	(revision 10908)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/clock_generator_beha.vhd	(revision 10914)
@@ -26,5 +26,5 @@
 ENTITY clock_generator IS
    GENERIC( 
-      clock_period : time := 20 ns;
+      clock_period : time := 50 ns;
       reset_time   : time := 50 ns
    );
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/fad_main_tb_struct.vhd
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/fad_main_tb_struct.vhd	(revision 10908)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/fad_main_tb_struct.vhd	(revision 10914)
@@ -2,8 +2,8 @@
 --
 -- Created:
---          by - daqct3.UNKNOWN (IHP110)
---          at - 22:55:01 26.05.2011
---
--- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
+--          by - dneise.UNKNOWN (E5B-LABOR6)
+--          at - 13:22:05 01.06.2011
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
 --
 LIBRARY ieee;
@@ -20,8 +20,8 @@
 --
 -- Created:
---          by - daqct3.UNKNOWN (IHP110)
---          at - 22:55:01 26.05.2011
---
--- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
+--          by - dneise.UNKNOWN (E5B-LABOR6)
+--          at - 13:22:05 01.06.2011
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
 --
 LIBRARY ieee;
@@ -177,5 +177,5 @@
    COMPONENT clock_generator
    GENERIC (
-      clock_period : time := 20 ns;
+      clock_period : time := 50 ns;
       reset_time   : time := 50 ns
    );
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/fad_main_tb_w5300_2_struct.vhd
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/fad_main_tb_w5300_2_struct.vhd	(revision 10914)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/fad_main_tb_w5300_2_struct.vhd	(revision 10914)
@@ -0,0 +1,371 @@
+-- VHDL Entity FACT_FAD_TB_lib.fad_main_tb_w5300_2.symbol
+--
+-- Created:
+--          by - dneise.UNKNOWN (E5B-LABOR6)
+--          at - 13:20:50 01.06.2011
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+
+ENTITY fad_main_tb_w5300_2 IS
+-- Declarations
+
+END fad_main_tb_w5300_2 ;
+
+--
+-- VHDL Architecture FACT_FAD_TB_lib.fad_main_tb_w5300_2.struct
+--
+-- Created:
+--          by - dneise.UNKNOWN (E5B-LABOR6)
+--          at - 13:20:50 01.06.2011
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+USE ieee.std_logic_unsigned.all;
+
+LIBRARY FACT_FAD_lib;
+USE FACT_FAD_lib.fad_definitions.all;
+USE ieee.std_logic_textio.all;
+LIBRARY std;
+USE std.textio.all;
+
+LIBRARY FACT_FAD_lib;
+LIBRARY FACT_FAD_TB_lib;
+
+ARCHITECTURE struct OF fad_main_tb_w5300_2 IS
+
+   -- Architecture declarations
+
+   -- Internal signal declarations
+   SIGNAL ADC_CLK               : std_logic;
+   SIGNAL CLK_25_PS             : std_logic;
+   SIGNAL CLK_50                : std_logic;
+   -- for debugging
+   SIGNAL DG_state              : std_logic_vector(7 DOWNTO 0);
+   SIGNAL D_T_in                : std_logic_vector(1 DOWNTO 0);
+   SIGNAL FTM_RS485_rx_d        : std_logic;
+   SIGNAL FTM_RS485_rx_en       : std_logic;
+   SIGNAL FTM_RS485_tx_d        : std_logic;
+   SIGNAL FTM_RS485_tx_en       : std_logic;
+   SIGNAL REF_CLK               : STD_LOGIC                    := '0';
+   SIGNAL RSRLOAD               : std_logic                    := '0';
+   SIGNAL SRCLK                 : std_logic                    := '0';
+   SIGNAL SRIN_out              : std_logic                    := '0';
+   SIGNAL SROUT_in_0            : std_logic;
+   SIGNAL SROUT_in_1            : std_logic;
+   SIGNAL SROUT_in_2            : std_logic;
+   SIGNAL SROUT_in_3            : std_logic;
+   SIGNAL adc_data              : std_logic_vector(11 DOWNTO 0);
+   SIGNAL adc_data_array        : adc_data_array_type;
+   SIGNAL adc_oeb               : std_logic;
+   SIGNAL adc_otr               : STD_LOGIC;
+   SIGNAL adc_otr_array         : std_logic_vector(3 DOWNTO 0);
+   SIGNAL alarm_refclk_too_high : std_logic;
+   SIGNAL alarm_refclk_too_low  : std_logic;
+   SIGNAL amber                 : std_logic;
+   SIGNAL board_id              : std_logic_vector(3 DOWNTO 0);
+   SIGNAL clk                   : STD_LOGIC;
+   SIGNAL counter_result        : std_logic_vector(11 DOWNTO 0);
+   SIGNAL crate_id              : std_logic_vector(1 DOWNTO 0);
+   SIGNAL dac_cs                : std_logic;
+   SIGNAL debug_data_ram_empty  : std_logic;
+   SIGNAL debug_data_valid      : std_logic;
+   SIGNAL denable               : std_logic                    := '0';                -- default domino wave off
+   SIGNAL drs_channel_id        : std_logic_vector(3 DOWNTO 0) := (others => '0');
+   SIGNAL drs_dwrite            : std_logic                    := '1';
+   SIGNAL green                 : std_logic;
+   SIGNAL led                   : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
+   SIGNAL mem_manager_state     : std_logic_vector(3 DOWNTO 0);                       -- state is encoded here ... useful for debugging.
+   SIGNAL mosi                  : std_logic                    := '0';
+   SIGNAL plllock_in            : std_logic_vector(3 DOWNTO 0);                       -- high level, if dominowave is running and DRS PLL locked
+   SIGNAL red                   : std_logic;
+   SIGNAL sclk                  : std_logic;
+   SIGNAL sensor_cs             : std_logic_vector(3 DOWNTO 0);
+   SIGNAL sio                   : std_logic;
+   SIGNAL socket_tx_free_out    : std_logic_vector(16 DOWNTO 0);                      -- 17bit value .. that's true
+   SIGNAL trigger               : std_logic;
+   SIGNAL trigger_veto          : std_logic                    := '1';
+   SIGNAL w5300_state           : std_logic_vector(7 DOWNTO 0);                       -- state is encoded here ... useful for debugging.
+   SIGNAL wiz_addr              : std_logic_vector(9 DOWNTO 0);
+   SIGNAL wiz_cs                : std_logic                    := '1';
+   SIGNAL wiz_data              : std_logic_vector(15 DOWNTO 0);
+   SIGNAL wiz_int               : std_logic;
+   SIGNAL wiz_rd                : std_logic                    := '1';
+   SIGNAL wiz_reset             : std_logic                    := '1';
+   SIGNAL wiz_wr                : std_logic                    := '1';
+
+
+   -- Component Declarations
+   COMPONENT FAD_main_with_w53002
+   GENERIC (
+      RAMADDRWIDTH64b : integer := 12
+   );
+   PORT (
+      CLK                   : IN     std_logic ;
+      D_T_in                : IN     std_logic_vector (1 DOWNTO 0);
+      FTM_RS485_rx_d        : IN     std_logic ;
+      SROUT_in_0            : IN     std_logic ;
+      SROUT_in_1            : IN     std_logic ;
+      SROUT_in_2            : IN     std_logic ;
+      SROUT_in_3            : IN     std_logic ;
+      adc_data_array        : IN     adc_data_array_type ;
+      adc_otr_array         : IN     std_logic_vector (3 DOWNTO 0);
+      board_id              : IN     std_logic_vector (3 DOWNTO 0);
+      crate_id              : IN     std_logic_vector (1 DOWNTO 0);
+      drs_refclk_in         : IN     std_logic ;                                     -- used TO check if DRS REFCLK exsists, if not DENABLE inhibit
+      plllock_in            : IN     std_logic_vector (3 DOWNTO 0);                  -- high level, if dominowave is running and DRS PLL locked
+      trigger               : IN     std_logic ;
+      wiz_int               : IN     std_logic ;
+      ADC_CLK               : OUT    std_logic ;
+      CLK_25_PS             : OUT    std_logic ;
+      CLK_50                : OUT    std_logic ;
+      -- for debugging
+      DG_state              : OUT    std_logic_vector (7 DOWNTO 0);
+      FTM_RS485_rx_en       : OUT    std_logic ;
+      FTM_RS485_tx_d        : OUT    std_logic ;
+      FTM_RS485_tx_en       : OUT    std_logic ;
+      RSRLOAD               : OUT    std_logic                     := '0';
+      SRCLK                 : OUT    std_logic                     := '0';
+      SRIN_out              : OUT    std_logic                     := '0';
+      adc_oeb               : OUT    std_logic                     := '1';
+      alarm_refclk_too_high : OUT    std_logic ;
+      alarm_refclk_too_low  : OUT    std_logic ;
+      amber                 : OUT    std_logic ;
+      counter_result        : OUT    std_logic_vector (11 DOWNTO 0);
+      dac_cs                : OUT    std_logic ;
+      debug_data_ram_empty  : OUT    std_logic ;
+      debug_data_valid      : OUT    std_logic ;
+      denable               : OUT    std_logic                     := '0';           -- default domino wave off
+      drs_channel_id        : OUT    std_logic_vector (3 DOWNTO 0) := (others => '0');
+      drs_dwrite            : OUT    std_logic                     := '1';
+      green                 : OUT    std_logic ;
+      led                   : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
+      mem_manager_state     : OUT    std_logic_vector (3 DOWNTO 0);                  -- state is encoded here ... useful for debugging.
+      mosi                  : OUT    std_logic                     := '0';
+      red                   : OUT    std_logic ;
+      sclk                  : OUT    std_logic ;
+      sensor_cs             : OUT    std_logic_vector (3 DOWNTO 0);
+      socket_tx_free_out    : OUT    std_logic_vector (16 DOWNTO 0);                 -- 17bit value .. that's true
+      trigger_veto          : OUT    std_logic                     := '1';
+      w5300_state           : OUT    std_logic_vector (7 DOWNTO 0);                  -- state is encoded here ... useful for debugging.
+      wiz_addr              : OUT    std_logic_vector (9 DOWNTO 0);
+      wiz_cs                : OUT    std_logic                     := '1';
+      wiz_rd                : OUT    std_logic                     := '1';
+      wiz_reset             : OUT    std_logic                     := '1';
+      wiz_wr                : OUT    std_logic                     := '1';
+      sio                   : INOUT  std_logic ;
+      wiz_data              : INOUT  std_logic_vector (15 DOWNTO 0)
+   );
+   END COMPONENT;
+   COMPONENT adc_emulator
+   GENERIC (
+      INPUT_FILE : string := "filename"
+   );
+   PORT (
+      clk  : IN     STD_LOGIC ;
+      data : OUT    STD_LOGIC_VECTOR (11 DOWNTO 0);
+      otr  : OUT    STD_LOGIC ;
+      oeb  : IN     STD_LOGIC 
+   );
+   END COMPONENT;
+   COMPONENT clock_generator
+   GENERIC (
+      clock_period : time := 50 ns;
+      reset_time   : time := 50 ns
+   );
+   PORT (
+      clk : OUT    std_logic  := '0';
+      rst : OUT    std_logic  := '0'
+   );
+   END COMPONENT;
+   COMPONENT max6662_emulator
+   GENERIC (
+      DRS_TEMPERATURE : integer := 51
+   );
+   PORT (
+      sclk      : IN     std_logic ;
+      sio       : INOUT  std_logic ;
+      sensor_cs : IN     std_logic_vector (3 DOWNTO 0)
+   );
+   END COMPONENT;
+   COMPONENT trigger_generator
+   GENERIC (
+      TRIGGER_RATE : time := 1 ms;
+      PULSE_WIDTH  : time := 20 ns
+   );
+   PORT (
+      trigger : OUT    std_logic 
+   );
+   END COMPONENT;
+   COMPONENT w5300_emulator
+   PORT (
+      int  : OUT    std_logic  := '1';
+      addr : IN     std_logic_vector (9 DOWNTO 0);
+      data : INOUT  std_logic_vector (15 DOWNTO 0);
+      rd   : IN     std_logic ;
+      cs   : IN     std_logic ;
+      wr   : IN     std_logic 
+   );
+   END COMPONENT;
+
+   -- Optional embedded configurations
+   -- pragma synthesis_off
+   FOR ALL : FAD_main_with_w53002 USE ENTITY FACT_FAD_lib.FAD_main_with_w53002;
+   FOR ALL : adc_emulator USE ENTITY FACT_FAD_TB_lib.adc_emulator;
+   FOR ALL : clock_generator USE ENTITY FACT_FAD_TB_lib.clock_generator;
+   FOR ALL : max6662_emulator USE ENTITY FACT_FAD_TB_lib.max6662_emulator;
+   FOR ALL : trigger_generator USE ENTITY FACT_FAD_TB_lib.trigger_generator;
+   FOR ALL : w5300_emulator USE ENTITY FACT_FAD_TB_lib.w5300_emulator;
+   -- pragma synthesis_on
+
+
+BEGIN
+   -- Architecture concurrent statements
+   -- HDL Embedded Text Block 1 eb_mainTB_ID
+   -- eb_ID 1: hard-wired IDs
+   board_id <= "0101";
+   crate_id <= "01";
+
+   -- HDL Embedded Text Block 2 eb_mainTB_adc
+   -- eb_adc 2: ADC routing
+   adc_data_array(0) <= adc_data;
+   adc_data_array(1) <= adc_data;
+   adc_data_array(2) <= adc_data;
+   adc_data_array(3) <= adc_data;
+   adc_otr_array(0) <= adc_otr;
+   adc_otr_array(1) <= adc_otr;
+   adc_otr_array(2) <= adc_otr;
+   adc_otr_array(3) <= adc_otr;
+
+   -- HDL Embedded Text Block 3 eb_mainTB_adc1
+   
+   D_T_in(1 downto 0) <= "00";
+   plllock_in(3 downto 0) <= "1111";
+   SROUT_in_0 <= '1';
+   SROUT_in_1 <= '0';
+   SROUT_in_2 <= '1';
+   SROUT_in_3 <= '0';
+
+
+   -- Instance port mappings.
+   I0 : FAD_main_with_w53002
+      GENERIC MAP (
+         RAMADDRWIDTH64b => 15
+      )
+      PORT MAP (
+         CLK                   => clk,
+         D_T_in                => D_T_in,
+         FTM_RS485_rx_d        => FTM_RS485_rx_d,
+         SROUT_in_0            => SROUT_in_0,
+         SROUT_in_1            => SROUT_in_1,
+         SROUT_in_2            => SROUT_in_2,
+         SROUT_in_3            => SROUT_in_3,
+         adc_data_array        => adc_data_array,
+         adc_otr_array         => adc_otr_array,
+         board_id              => board_id,
+         crate_id              => crate_id,
+         drs_refclk_in         => REF_CLK,
+         plllock_in            => plllock_in,
+         trigger               => trigger,
+         wiz_int               => wiz_int,
+         ADC_CLK               => ADC_CLK,
+         CLK_25_PS             => CLK_25_PS,
+         CLK_50                => CLK_50,
+         DG_state              => DG_state,
+         FTM_RS485_rx_en       => FTM_RS485_rx_en,
+         FTM_RS485_tx_d        => FTM_RS485_tx_d,
+         FTM_RS485_tx_en       => FTM_RS485_tx_en,
+         RSRLOAD               => RSRLOAD,
+         SRCLK                 => SRCLK,
+         SRIN_out              => SRIN_out,
+         adc_oeb               => adc_oeb,
+         alarm_refclk_too_high => alarm_refclk_too_high,
+         alarm_refclk_too_low  => alarm_refclk_too_low,
+         amber                 => amber,
+         counter_result        => counter_result,
+         dac_cs                => dac_cs,
+         debug_data_ram_empty  => debug_data_ram_empty,
+         debug_data_valid      => debug_data_valid,
+         denable               => denable,
+         drs_channel_id        => drs_channel_id,
+         drs_dwrite            => drs_dwrite,
+         green                 => green,
+         led                   => led,
+         mem_manager_state     => mem_manager_state,
+         mosi                  => mosi,
+         red                   => red,
+         sclk                  => sclk,
+         sensor_cs             => sensor_cs,
+         socket_tx_free_out    => socket_tx_free_out,
+         trigger_veto          => trigger_veto,
+         w5300_state           => w5300_state,
+         wiz_addr              => wiz_addr,
+         wiz_cs                => wiz_cs,
+         wiz_rd                => wiz_rd,
+         wiz_reset             => wiz_reset,
+         wiz_wr                => wiz_wr,
+         sio                   => sio,
+         wiz_data              => wiz_data
+      );
+   I_mainTB_adc : adc_emulator
+      GENERIC MAP (
+         INPUT_FILE => "../memory_files/analog_input_ch0.txt"
+      )
+      PORT MAP (
+         clk  => ADC_CLK,
+         data => adc_data,
+         otr  => adc_otr,
+         oeb  => adc_oeb
+      );
+   I_mainTB_clock : clock_generator
+      GENERIC MAP (
+         clock_period => 20 ns,
+         reset_time   => 50 ns
+      )
+      PORT MAP (
+         clk => clk,
+         rst => OPEN
+      );
+   I_mainTB_clock1 : clock_generator
+      GENERIC MAP (
+         clock_period => 1 us,
+         reset_time   => 1 us
+      )
+      PORT MAP (
+         clk => REF_CLK,
+         rst => OPEN
+      );
+   I_mainTB_max6662 : max6662_emulator
+      GENERIC MAP (
+         DRS_TEMPERATURE => 51
+      )
+      PORT MAP (
+         sclk      => sclk,
+         sio       => sio,
+         sensor_cs => sensor_cs
+      );
+   I_mainTB_trigger : trigger_generator
+      GENERIC MAP (
+         TRIGGER_RATE => 1 ms,
+         PULSE_WIDTH  => 20 ns
+      )
+      PORT MAP (
+         trigger => trigger
+      );
+   I_mainTB_w5300 : w5300_emulator
+      PORT MAP (
+         int  => wiz_int,
+         addr => wiz_addr,
+         data => wiz_data,
+         rd   => wiz_rd,
+         cs   => wiz_cs,
+         wr   => wiz_wr
+      );
+
+END struct;
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/w5300_interface_tester_beha.vhd
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/w5300_interface_tester_beha.vhd	(revision 10914)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/w5300_interface_tester_beha.vhd	(revision 10914)
@@ -0,0 +1,104 @@
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE ieee.std_logic_unsigned.all;
+
+ENTITY w5300_interface_tester IS
+   PORT( 
+   		clk    : IN     std_logic;
+
+
+      -- interface to W5300 chip ports:
+	  cs        : IN     std_logic;
+	  rd        : IN     std_logic;
+	  wiz_addr  : IN     std_logic_vector (9 DOWNTO 0);
+	  wiz_data  : INOUT  std_logic_vector (15 DOWNTO 0);
+	  wiz_reset : IN     std_logic;
+	  wr        : IN     std_logic;
+	  int       : OUT    std_logic;
+      
+      
+      data_o    : IN     std_logic_vector (15 DOWNTO 0);
+      addr_i    : OUT    std_logic_vector (9 DOWNTO 0);
+      data_i    : OUT    std_logic_vector (15 DOWNTO 0);
+      read_i    : OUT    std_logic;
+      ready_o			: IN 			std_logic;
+      write_i   : OUT    std_logic
+
+   );
+
+-- Declarations
+
+END w5300_interface_tester ;
+
+--
+ARCHITECTURE beha OF w5300_interface_tester IS
+	type state_t is (
+	PRESTART,
+	WRITE_TEST, WRITING,
+	READ_TEST, READING
+	--FINAL
+	);
+
+	signal state : state_t;
+	
+	signal write : std_logic;
+	signal read : std_logic;
+	
+BEGIN
+
+	write_i <= write;
+	read_i <= read;
+	wiz_data <= X"1234";
+	
+	process(clk)
+		begin
+			
+			if rising_edge(clk) then
+				case state is
+				when 	PRESTART =>
+					read <= '0';
+					write <= '0';
+					if (ready_o = '1') then
+						state <= WRITE_TEST;
+					end if;
+				
+				when WRITE_TEST =>
+					if (ready_o = '1') then
+	    					addr_i <= "0000111100";
+	    					data_i <= X"ABCD";
+	    					write <= '1';
+	    					state <= WRITING;
+					end if;					
+
+				when WRITING =>
+					if (ready_o = '0') then
+						write <= '0';
+						state <= READ_TEST;
+					end if;
+					
+				when READ_TEST =>
+					if (ready_o = '1') then
+						addr_i <= "0100110101";
+						read <= '1';
+						state <= READING;
+					end if;					
+					
+				when READING =>
+					if (ready_o = '0') then
+						read <= '0';
+						state <= WRITE_TEST;
+				end if;
+	
+
+				
+	
+				end case;
+				
+			end if; --clk
+			
+		end process;
+	
+END ARCHITECTURE beha;
+
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/w5300_modul2_tester_beha.vhd
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/w5300_modul2_tester_beha.vhd	(revision 10914)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hdl/w5300_modul2_tester_beha.vhd	(revision 10914)
@@ -0,0 +1,81 @@
+--
+-- VHDL Architecture FACT_FAD_TB_lib.w5300_modul2_tester.beha
+--
+-- Created:
+--          by - dneise.UNKNOWN (E5B-LABOR6)
+--          at - 14:18:31 31.05.2011
+--
+-- using Mentor Graphics HDL Designer(TM) 2009.2 (Build 10)
+--
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+LIBRARY FACT_FAD_lib;
+USE FACT_FAD_lib.fad_definitions.ALL;
+
+ENTITY w5300_modul2_tester IS
+   PORT( 
+   		clk                           : IN    std_logic;
+   		
+
+      busy                          : IN     std_logic;
+      c_trigger_enable              : IN     std_logic;
+      c_trigger_mult                : IN     std_logic_vector (15 DOWNTO 0);
+
+      dac_setting                   : IN     dac_array_type;
+      data_valid_ack                : IN     std_logic;
+      debug_data_ram_empty          : IN     std_logic;
+      debug_data_valid              : IN     std_logic;
+      denable                       : IN     std_logic;
+      dwrite_enable                 : IN     std_logic;
+
+      memory_manager_config_start_o : IN     std_logic;
+      ps_direction                  : IN     std_logic;
+      ps_do_phase_shift             : IN     std_logic;
+      ps_reset                      : IN     std_logic;
+      ram_addr                      : IN     std_logic_vector (13 DOWNTO 0);
+
+      reset_trigger_id              : IN     std_logic;
+      roi_setting                   : IN     roi_array_type;
+      runnumber                     : IN     std_logic_vector (31 DOWNTO 0);
+      s_trigger                     : IN     std_logic;
+      sclk_enable                   : IN     std_logic;
+
+      socks_connected               : IN     std_logic;
+      socks_waiting                 : IN     std_logic;
+      spi_interface_config_start_o  : IN     std_logic;
+      srclk_enable                  : IN     std_logic;
+      state                         : IN     std_logic_vector (7 DOWNTO 0);
+      trigger_enable                : IN     std_logic;
+      wiz_reset                     : IN     std_logic;
+
+      BoardID                       : OUT    std_logic_vector (3 DOWNTO 0);
+      CrateID                       : OUT    std_logic_vector (1 DOWNTO 0);
+      MAC_jumper                    : OUT    std_logic_vector (1 DOWNTO 0);
+      
+      data_generator_idle_i         : OUT    std_logic;
+      data_ram_empty                : OUT    std_logic;
+      data_valid                    : OUT    std_logic;
+      fifo_channels                 : OUT    std_logic_vector (3 DOWNTO 0);
+
+      memory_manager_config_valid_i : OUT    std_logic;
+      ps_ready                      : OUT    std_logic;
+      ram_data                      : OUT    std_logic_vector (15 DOWNTO 0);
+      ram_start_addr                : OUT    std_logic_vector (13 DOWNTO 0);
+      spi_interface_config_valid_i  : OUT    std_logic;
+      write_end_flag                : OUT    std_logic;
+      write_header_flag             : OUT    std_logic;
+      write_length                  : OUT    std_logic_vector (16 DOWNTO 0)
+
+   );
+
+-- Declarations
+
+END w5300_modul2_tester ;
+
+--
+ARCHITECTURE beha OF w5300_modul2_tester IS
+BEGIN
+END ARCHITECTURE beha;
+
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/_fad_main_tb_w5300_2._epf
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/_fad_main_tb_w5300_2._epf	(revision 10914)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/_fad_main_tb_w5300_2._epf	(revision 10914)
@@ -0,0 +1,3 @@
+DEFAULT_FILE atom fad_main_tb_w5300_2/struct.bd
+DEFAULT_ARCHITECTURE atom struct
+TOP_MARKER atom 1
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/_w5300_interface_tb._epf
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/_w5300_interface_tb._epf	(revision 10914)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/_w5300_interface_tb._epf	(revision 10914)
@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom struct
+DEFAULT_FILE atom w5300_interface_tb/struct.bd
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/_w5300_interface_tester._epf
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/_w5300_interface_tester._epf	(revision 10914)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/_w5300_interface_tester._epf	(revision 10914)
@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom beha
+DEFAULT_FILE atom w5300_interface_tester_beha.vhd
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/_w5300_modul2_tb._epf
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/_w5300_modul2_tb._epf	(revision 10914)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/_w5300_modul2_tb._epf	(revision 10914)
@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom struct
+DEFAULT_FILE atom w5300_modul2_tb/struct.bd
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/_w5300_modul2_tester._epf
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/_w5300_modul2_tester._epf	(revision 10914)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/_w5300_modul2_tester._epf	(revision 10914)
@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom beha
+DEFAULT_FILE atom w5300_modul2_tester_beha.vhd
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/clock_generator/symbol.sb
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/clock_generator/symbol.sb	(revision 10908)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/clock_generator/symbol.sb	(revision 10914)
@@ -265,7 +265,7 @@
 name "clock_period"
 type "time"
-value "20 ns"
-)
-uid 156,0
+value "50 ns"
+)
+uid 183,0
 )
 *44 (LogGeneric
@@ -275,5 +275,5 @@
 value "50 ns"
 )
-uid 158,0
+uid 185,0
 )
 ]
@@ -331,5 +331,5 @@
 pos 0
 dimension 20
-uid 157,0
+uid 184,0
 )
 *51 (MRCItem
@@ -337,5 +337,5 @@
 pos 1
 dimension 20
-uid 159,0
+uid 186,0
 )
 ]
@@ -410,21 +410,21 @@
 (vvPair
 variable "HDLDir"
-value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hdl"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
 )
 (vvPair
 variable "HDSDir"
-value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
 )
 (vvPair
 variable "SideDataDesignDir"
-value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\clock_generator\\symbol.sb.info"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\clock_generator\\symbol.sb.info"
 )
 (vvPair
 variable "SideDataUserDir"
-value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\clock_generator\\symbol.sb.user"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\clock_generator\\symbol.sb.user"
 )
 (vvPair
 variable "SourceDir"
-value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
 )
 (vvPair
@@ -438,17 +438,17 @@
 (vvPair
 variable "config"
-value "%(unit)_config"
+value "%(unit)_%(view)_config"
 )
 (vvPair
 variable "d"
-value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\clock_generator"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\clock_generator"
 )
 (vvPair
 variable "d_logical"
-value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\clock_generator"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\clock_generator"
 )
 (vvPair
 variable "date"
-value "23.06.2010"
+value "01.06.2011"
 )
 (vvPair
@@ -462,5 +462,5 @@
 (vvPair
 variable "dd"
-value "23"
+value "01"
 )
 (vvPair
@@ -490,5 +490,5 @@
 (vvPair
 variable "host"
-value "EEPC8"
+value "E5B-LABOR6"
 )
 (vvPair
@@ -501,4 +501,24 @@
 )
 (vvPair
+variable "library_downstream_HdsLintPlugin"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/designcheck"
+)
+(vvPair
+variable "library_downstream_ISEPARInvoke"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
+)
+(vvPair
+variable "library_downstream_ImpactInvoke"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
+)
+(vvPair
+variable "library_downstream_ModelSimCompiler"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/work"
+)
+(vvPair
+variable "library_downstream_XSTDataPrep"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
+)
+(vvPair
 variable "mm"
 value "06"
@@ -518,9 +538,9 @@
 (vvPair
 variable "p"
-value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\clock_generator\\symbol.sb"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\clock_generator\\symbol.sb"
 )
 (vvPair
 variable "p_logical"
-value "D:\\E5b\\E5b_09_189\\FPGA\\FAD_repos\\unstable\\FACT_FAD\\FACT_FAD_TB_lib\\hds\\clock_generator\\symbol.sb"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\clock_generator\\symbol.sb"
 )
 (vvPair
@@ -546,5 +566,5 @@
 (vvPair
 variable "task_ModelSimPath"
-value "$HDS_HOME/../Modeltech/win32"
+value "C:\\modeltech_6.6a\\win32"
 )
 (vvPair
@@ -554,5 +574,5 @@
 (vvPair
 variable "task_PrecisionRTLPath"
-value "$HDS_HOME/../Precision/Mgc_home/bin"
+value "<TBD>"
 )
 (vvPair
@@ -578,5 +598,5 @@
 (vvPair
 variable "time"
-value "10:52:12"
+value "12:57:51"
 )
 (vvPair
@@ -586,5 +606,5 @@
 (vvPair
 variable "user"
-value "Benjamin Krumm"
+value "dneise"
 )
 (vvPair
@@ -598,9 +618,9 @@
 (vvPair
 variable "year"
-value "2010"
+value "2011"
 )
 (vvPair
 variable "yy"
-value "10"
+value "11"
 )
 ]
@@ -787,5 +807,5 @@
 st "Generic Declarations
 
-clock_period time 20 ns  
+clock_period time 50 ns  
 reset_time   time 50 ns  
 "
@@ -798,5 +818,5 @@
 name "clock_period"
 type "time"
-value "20 ns"
+value "50 ns"
 )
 (GiElement
@@ -1448,5 +1468,5 @@
 )
 )
-lastUid 159,0
+lastUid 186,0
 activeModelName "Symbol:CDM"
 )
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/fad_main_tb/struct.bd
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/fad_main_tb/struct.bd	(revision 10908)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/fad_main_tb/struct.bd	(revision 10914)
@@ -159,5 +159,5 @@
 )
 version "29.1"
-appVersion "2009.1 (Build 12)"
+appVersion "2009.2 (Build 10)"
 noEmbeddedEditors 1
 model (BlockDiag
@@ -166,21 +166,21 @@
 (vvPair
 variable "HDLDir"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
 )
 (vvPair
 variable "HDSDir"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
 )
 (vvPair
 variable "SideDataDesignDir"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.info"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.info"
 )
 (vvPair
 variable "SideDataUserDir"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.user"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.user"
 )
 (vvPair
 variable "SourceDir"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
 )
 (vvPair
@@ -198,13 +198,13 @@
 (vvPair
 variable "d"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb"
 )
 (vvPair
 variable "d_logical"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb"
 )
 (vvPair
 variable "date"
-value "25.05.2011"
+value "01.06.2011"
 )
 (vvPair
@@ -218,5 +218,5 @@
 (vvPair
 variable "dd"
-value "25"
+value "01"
 )
 (vvPair
@@ -246,5 +246,5 @@
 (vvPair
 variable "host"
-value "IHP110"
+value "E5B-LABOR6"
 )
 (vvPair
@@ -278,5 +278,5 @@
 (vvPair
 variable "mm"
-value "05"
+value "06"
 )
 (vvPair
@@ -286,17 +286,17 @@
 (vvPair
 variable "month"
-value "Mai"
+value "Jun"
 )
 (vvPair
 variable "month_long"
-value "Mai"
+value "Juni"
 )
 (vvPair
 variable "p"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"
 )
 (vvPair
 variable "p_logical"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"
 )
 (vvPair
@@ -322,5 +322,5 @@
 (vvPair
 variable "task_ModelSimPath"
-value "D:\\modeltech_6.5e\\win32"
+value "C:\\modeltech_6.6a\\win32"
 )
 (vvPair
@@ -354,5 +354,5 @@
 (vvPair
 variable "time"
-value "17:24:50"
+value "13:20:42"
 )
 (vvPair
@@ -362,9 +362,9 @@
 (vvPair
 variable "user"
-value "daqct3"
+value "dneise"
 )
 (vvPair
 variable "version"
-value "2009.1 (Build 12)"
+value "2009.2 (Build 10)"
 )
 (vvPair
@@ -406,5 +406,5 @@
 bg "0,0,32768"
 )
-xt "109200,97000,120000,98000"
+xt "109200,97000,118700,98000"
 st "
 by %user on %dd %month %year
@@ -437,5 +437,5 @@
 bg "0,0,32768"
 )
-xt "126200,93000,129500,94000"
+xt "126200,93000,129200,94000"
 st "
 Project:
@@ -468,5 +468,5 @@
 bg "0,0,32768"
 )
-xt "109200,95000,120100,96000"
+xt "109200,95000,119200,96000"
 st "
 <enter diagram title here>
@@ -499,5 +499,5 @@
 bg "0,0,32768"
 )
-xt "105200,95000,107500,96000"
+xt "105200,95000,107300,96000"
 st "
 Title:
@@ -530,5 +530,5 @@
 bg "0,0,32768"
 )
-xt "126200,94200,136000,95200"
+xt "126200,94200,135400,95200"
 st "
 <enter comments here>
@@ -560,5 +560,5 @@
 bg "0,0,32768"
 )
-xt "130200,93000,134900,94000"
+xt "130200,93000,134700,94000"
 st "
 %project_name
@@ -590,5 +590,5 @@
 fg "32768,0,0"
 )
-xt "112450,93000,118550,95000"
+xt "112700,93000,118300,95000"
 st "
 TU Dortmund 
@@ -623,5 +623,5 @@
 bg "0,0,32768"
 )
-xt "105200,96000,107500,97000"
+xt "105200,96000,107300,97000"
 st "
 Path:
@@ -654,5 +654,5 @@
 bg "0,0,32768"
 )
-xt "105200,97000,108300,98000"
+xt "105200,97000,107900,98000"
 st "
 Edited:
@@ -685,5 +685,5 @@
 bg "0,0,32768"
 )
-xt "109200,96000,125800,97000"
+xt "109200,96000,123400,97000"
 st "
 %library/%unit/%view
@@ -3432,5 +3432,5 @@
 va (VaSet
 )
-xt "50200,45200,58200,49200"
+xt "50200,45200,60200,48200"
 st "
 -- eb_ID 1: hard-wired IDs
@@ -3806,5 +3806,5 @@
 va (VaSet
 )
-xt "50200,57200,60900,67200"
+xt "50200,57200,62100,66200"
 st "
 -- eb_adc 2: ADC routing
@@ -4449,5 +4449,5 @@
 va (VaSet
 )
-xt "27200,72200,40200,77200"
+xt "27200,72200,39400,77200"
 st "
 
@@ -7443,5 +7443,5 @@
 va (VaSet
 )
-xt "-87000,1000,-70900,11000"
+xt "-87000,1000,-72500,11000"
 st "LIBRARY ieee;
 USE ieee.std_logic_1164.all;
@@ -7487,5 +7487,5 @@
 isHidden 1
 )
-xt "20000,2000,28200,4000"
+xt "20000,2000,27500,4000"
 st "`resetall
 `timescale 1ns/10ps"
@@ -7531,6 +7531,6 @@
 associable 1
 )
-windowSize "0,20,1681,1050"
-viewArea "69200,38600,161306,94544"
+windowSize "0,0,1281,1024"
+viewArea "53418,13863,168802,105975"
 cachedDiagramExtent "-92000,0,146000,98000"
 pageSetupInfo (PageSetupInfo
@@ -7545,5 +7545,5 @@
 hasePageBreakOrigin 1
 pageBreakOrigin "-146000,0"
-lastUid 2951,0
+lastUid 3294,0
 defaultCommentText (CommentText
 shape (Rectangle
@@ -7560,5 +7560,5 @@
 fg "0,0,32768"
 )
-xt "200,200,2400,1200"
+xt "200,200,2000,1200"
 st "
 Text
@@ -7978,5 +7978,5 @@
 va (VaSet
 )
-xt "200,200,2400,1200"
+xt "200,200,2000,1200"
 st "
 Text
@@ -8316,5 +8316,5 @@
 va (VaSet
 )
-xt "0,-1100,12900,-100"
+xt "0,-1100,12600,-100"
 st "g0: FOR i IN 0 TO n GENERATE"
 tm "FrameTitleTextMgr"
@@ -8376,5 +8376,5 @@
 va (VaSet
 )
-xt "0,-1100,7700,-100"
+xt "0,-1100,7400,-100"
 st "b0: BLOCK (guard)"
 tm "FrameTitleTextMgr"
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/fad_main_tb/struct.bd.bak
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/fad_main_tb/struct.bd.bak	(revision 10908)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/fad_main_tb/struct.bd.bak	(revision 10914)
@@ -137,4 +137,18 @@
 uid 2336,0
 )
+(Instance
+name "I0"
+duLibraryName "FACT_FAD_lib"
+duName "FAD_main_with_w53002"
+elements [
+(GiElement
+name "RAMADDRWIDTH64b"
+type "integer"
+value "15"
+)
+]
+mwi 0
+uid 3285,0
+)
 ]
 embeddedInstances [
@@ -159,5 +173,5 @@
 )
 version "29.1"
-appVersion "2009.1 (Build 12)"
+appVersion "2009.2 (Build 10)"
 noEmbeddedEditors 1
 model (BlockDiag
@@ -166,21 +180,21 @@
 (vvPair
 variable "HDLDir"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
 )
 (vvPair
 variable "HDSDir"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
 )
 (vvPair
 variable "SideDataDesignDir"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.info"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.info"
 )
 (vvPair
 variable "SideDataUserDir"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.user"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd.user"
 )
 (vvPair
 variable "SourceDir"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
 )
 (vvPair
@@ -198,25 +212,25 @@
 (vvPair
 variable "d"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb"
 )
 (vvPair
 variable "d_logical"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb"
 )
 (vvPair
 variable "date"
-value "23.05.2011"
+value "01.06.2011"
 )
 (vvPair
 variable "day"
-value "Mo"
+value "Mi"
 )
 (vvPair
 variable "day_long"
-value "Montag"
+value "Mittwoch"
 )
 (vvPair
 variable "dd"
-value "23"
+value "01"
 )
 (vvPair
@@ -246,5 +260,5 @@
 (vvPair
 variable "host"
-value "IHP110"
+value "E5B-LABOR6"
 )
 (vvPair
@@ -278,5 +292,5 @@
 (vvPair
 variable "mm"
-value "05"
+value "06"
 )
 (vvPair
@@ -286,17 +300,17 @@
 (vvPair
 variable "month"
-value "Mai"
+value "Jun"
 )
 (vvPair
 variable "month_long"
-value "Mai"
+value "Juni"
 )
 (vvPair
 variable "p"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"
 )
 (vvPair
 variable "p_logical"
-value "D:\\firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\fad_main_tb\\struct.bd"
 )
 (vvPair
@@ -322,5 +336,5 @@
 (vvPair
 variable "task_ModelSimPath"
-value "D:\\modeltech_6.5e\\win32"
+value "C:\\modeltech_6.6a\\win32"
 )
 (vvPair
@@ -354,5 +368,5 @@
 (vvPair
 variable "time"
-value "18:19:57"
+value "13:20:01"
 )
 (vvPair
@@ -362,9 +376,9 @@
 (vvPair
 variable "user"
-value "daqct3"
+value "dneise"
 )
 (vvPair
 variable "version"
-value "2009.1 (Build 12)"
+value "2009.2 (Build 10)"
 )
 (vvPair
@@ -406,5 +420,5 @@
 bg "0,0,32768"
 )
-xt "109200,97000,120300,98000"
+xt "109200,97000,118900,98000"
 st "
 by %user on %dd %month %year
@@ -437,5 +451,5 @@
 bg "0,0,32768"
 )
-xt "126200,93000,129500,94000"
+xt "126200,93000,129200,94000"
 st "
 Project:
@@ -468,5 +482,5 @@
 bg "0,0,32768"
 )
-xt "109200,95000,120100,96000"
+xt "109200,95000,119200,96000"
 st "
 <enter diagram title here>
@@ -499,5 +513,5 @@
 bg "0,0,32768"
 )
-xt "105200,95000,107500,96000"
+xt "105200,95000,107300,96000"
 st "
 Title:
@@ -530,5 +544,5 @@
 bg "0,0,32768"
 )
-xt "126200,94200,136000,95200"
+xt "126200,94200,135400,95200"
 st "
 <enter comments here>
@@ -560,5 +574,5 @@
 bg "0,0,32768"
 )
-xt "130200,93000,134900,94000"
+xt "130200,93000,134700,94000"
 st "
 %project_name
@@ -590,5 +604,5 @@
 fg "32768,0,0"
 )
-xt "112450,93000,118550,95000"
+xt "112700,93000,118300,95000"
 st "
 TU Dortmund 
@@ -623,5 +637,5 @@
 bg "0,0,32768"
 )
-xt "105200,96000,107500,97000"
+xt "105200,96000,107300,97000"
 st "
 Path:
@@ -654,5 +668,5 @@
 bg "0,0,32768"
 )
-xt "105200,97000,108300,98000"
+xt "105200,97000,107900,98000"
 st "
 Edited:
@@ -685,5 +699,5 @@
 bg "0,0,32768"
 )
-xt "109200,96000,125800,97000"
+xt "109200,96000,123400,97000"
 st "
 %library/%unit/%view
@@ -745,5 +759,5 @@
 n "wiz_reset"
 t "std_logic"
-o 49
+o 50
 suid 2,0
 i "'1'"
@@ -964,5 +978,5 @@
 t "std_logic_vector"
 b "(9 DOWNTO 0)"
-o 46
+o 47
 suid 26,0
 )
@@ -1001,5 +1015,5 @@
 t "std_logic_vector"
 b "(15 DOWNTO 0)"
-o 52
+o 53
 suid 27,0
 )
@@ -1037,5 +1051,5 @@
 n "wiz_cs"
 t "std_logic"
-o 47
+o 48
 suid 28,0
 i "'1'"
@@ -1074,5 +1088,5 @@
 n "wiz_wr"
 t "std_logic"
-o 50
+o 51
 suid 29,0
 i "'1'"
@@ -1111,5 +1125,5 @@
 n "wiz_rd"
 t "std_logic"
-o 48
+o 49
 suid 30,0
 i "'1'"
@@ -1677,5 +1691,5 @@
 preAdd 0
 posAdd 0
-o 51
+o 52
 suid 63,0
 )
@@ -2550,5 +2564,5 @@
 n "trigger_veto"
 t "std_logic"
-o 44
+o 45
 suid 98,0
 i "'1'"
@@ -2590,6 +2604,45 @@
 eolc "-- state is encoded here ... useful for debugging."
 posAdd 0
-o 45
+o 46
 suid 103,0
+)
+)
+)
+*65 (CptPort
+uid 2924,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 2925,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "109000,89625,109750,90375"
+)
+tg (CPTG
+uid 2926,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 2927,0
+va (VaSet
+)
+xt "96100,89500,108000,90500"
+st "socket_tx_free_out : (16:0)"
+ju 2
+blo "108000,90300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "socket_tx_free_out"
+t "std_logic_vector"
+b "(16 DOWNTO 0)"
+eolc "-- 17bit value .. that's true"
+posAdd 0
+o 44
+suid 109,0
 )
 )
@@ -2604,5 +2657,5 @@
 lineWidth 2
 )
-xt "81000,19000,109000,90000"
+xt "81000,19000,109000,91000"
 )
 oxt "15000,-8000,43000,46000"
@@ -2612,5 +2665,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*65 (Text
+*66 (Text
 uid 236,0
 va (VaSet
@@ -2622,5 +2675,5 @@
 tm "BdLibraryNameMgr"
 )
-*66 (Text
+*67 (Text
 uid 237,0
 va (VaSet
@@ -2632,5 +2685,5 @@
 tm "CptNameMgr"
 )
-*67 (Text
+*68 (Text
 uid 238,0
 va (VaSet
@@ -2674,5 +2727,5 @@
 fg "49152,49152,49152"
 )
-xt "81250,88250,82750,89750"
+xt "81250,89250,82750,90750"
 iconName "BlockDiagram.png"
 iconMaskName "BlockDiagram.msk"
@@ -2684,8 +2737,8 @@
 archFileType "UNKNOWN"
 )
-*68 (SaComponent
+*69 (SaComponent
 uid 274,0
 optionalChildren [
-*69 (CptPort
+*70 (CptPort
 uid 266,0
 ps "OnEdgeStrategy"
@@ -2723,5 +2776,5 @@
 )
 )
-*70 (CptPort
+*71 (CptPort
 uid 270,0
 ps "OnEdgeStrategy"
@@ -2776,5 +2829,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*71 (Text
+*72 (Text
 uid 277,0
 va (VaSet
@@ -2786,5 +2839,5 @@
 tm "BdLibraryNameMgr"
 )
-*72 (Text
+*73 (Text
 uid 278,0
 va (VaSet
@@ -2796,5 +2849,5 @@
 tm "CptNameMgr"
 )
-*73 (Text
+*74 (Text
 uid 279,0
 va (VaSet
@@ -2855,5 +2908,5 @@
 archFileType "UNKNOWN"
 )
-*74 (Net
+*75 (Net
 uid 284,0
 decl (Decl
@@ -2871,9 +2924,8 @@
 )
 xt "-90000,46200,-68000,47000"
-st "SIGNAL clk                   : STD_LOGIC
-"
-)
-)
-*75 (Net
+st "SIGNAL clk                   : STD_LOGIC"
+)
+)
+*76 (Net
 uid 316,0
 decl (Decl
@@ -2889,10 +2941,9 @@
 font "Courier New,8,0"
 )
-xt "-90000,63000,-58500,63800"
-st "SIGNAL wiz_addr              : std_logic_vector(9 DOWNTO 0)
-"
-)
-)
-*76 (Net
+xt "-90000,63800,-58500,64600"
+st "SIGNAL wiz_addr              : std_logic_vector(9 DOWNTO 0)"
+)
+)
+*77 (Net
 uid 322,0
 decl (Decl
@@ -2908,10 +2959,9 @@
 font "Courier New,8,0"
 )
-xt "-90000,64600,-58000,65400"
-st "SIGNAL wiz_data              : std_logic_vector(15 DOWNTO 0)
-"
-)
-)
-*77 (Net
+xt "-90000,65400,-58000,66200"
+st "SIGNAL wiz_data              : std_logic_vector(15 DOWNTO 0)"
+)
+)
+*78 (Net
 uid 328,0
 decl (Decl
@@ -2927,10 +2977,9 @@
 font "Courier New,8,0"
 )
-xt "-90000,66200,-55000,67000"
-st "SIGNAL wiz_rd                : std_logic                    := '1'
-"
-)
-)
-*78 (Net
+xt "-90000,67000,-55000,67800"
+st "SIGNAL wiz_rd                : std_logic                    := '1'"
+)
+)
+*79 (Net
 uid 334,0
 decl (Decl
@@ -2946,13 +2995,12 @@
 font "Courier New,8,0"
 )
-xt "-90000,67800,-55000,68600"
-st "SIGNAL wiz_wr                : std_logic                    := '1'
-"
-)
-)
-*79 (SaComponent
+xt "-90000,68600,-55000,69400"
+st "SIGNAL wiz_wr                : std_logic                    := '1'"
+)
+)
+*80 (SaComponent
 uid 362,0
 optionalChildren [
-*80 (CptPort
+*81 (CptPort
 uid 350,0
 ps "OnEdgeStrategy"
@@ -2990,5 +3038,5 @@
 )
 )
-*81 (CptPort
+*82 (CptPort
 uid 354,0
 ps "OnEdgeStrategy"
@@ -3027,5 +3075,5 @@
 )
 )
-*82 (CptPort
+*83 (CptPort
 uid 358,0
 ps "OnEdgeStrategy"
@@ -3081,5 +3129,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*83 (Text
+*84 (Text
 uid 365,0
 va (VaSet
@@ -3091,5 +3139,5 @@
 tm "BdLibraryNameMgr"
 )
-*84 (Text
+*85 (Text
 uid 366,0
 va (VaSet
@@ -3101,5 +3149,5 @@
 tm "CptNameMgr"
 )
-*85 (Text
+*86 (Text
 uid 367,0
 va (VaSet
@@ -3155,5 +3203,5 @@
 archFileType "UNKNOWN"
 )
-*86 (Net
+*87 (Net
 uid 372,0
 decl (Decl
@@ -3170,9 +3218,8 @@
 )
 xt "-90000,59000,-58500,59800"
-st "SIGNAL sensor_cs             : std_logic_vector(3 DOWNTO 0)
-"
-)
-)
-*87 (Net
+st "SIGNAL sensor_cs             : std_logic_vector(3 DOWNTO 0)"
+)
+)
+*88 (Net
 uid 378,0
 decl (Decl
@@ -3188,9 +3235,8 @@
 )
 xt "-90000,58200,-68000,59000"
-st "SIGNAL sclk                  : std_logic
-"
-)
-)
-*88 (Net
+st "SIGNAL sclk                  : std_logic"
+)
+)
+*89 (Net
 uid 384,0
 decl (Decl
@@ -3208,12 +3254,11 @@
 )
 xt "-90000,59800,-68000,60600"
-st "SIGNAL sio                   : std_logic
-"
-)
-)
-*89 (SaComponent
+st "SIGNAL sio                   : std_logic"
+)
+)
+*90 (SaComponent
 uid 414,0
 optionalChildren [
-*90 (CptPort
+*91 (CptPort
 uid 410,0
 ps "OnEdgeStrategy"
@@ -3270,5 +3315,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*91 (Text
+*92 (Text
 uid 417,0
 va (VaSet
@@ -3280,5 +3325,5 @@
 tm "BdLibraryNameMgr"
 )
-*92 (Text
+*93 (Text
 uid 418,0
 va (VaSet
@@ -3290,5 +3335,5 @@
 tm "CptNameMgr"
 )
-*93 (Text
+*94 (Text
 uid 419,0
 va (VaSet
@@ -3350,5 +3395,5 @@
 archFileType "UNKNOWN"
 )
-*94 (Net
+*95 (Net
 uid 424,0
 decl (Decl
@@ -3365,13 +3410,12 @@
 font "Courier New,8,0"
 )
-xt "-90000,60600,-68000,61400"
-st "SIGNAL trigger               : std_logic
-"
-)
-)
-*95 (HdlText
+xt "-90000,61400,-68000,62200"
+st "SIGNAL trigger               : std_logic"
+)
+)
+*96 (HdlText
 uid 430,0
 optionalChildren [
-*96 (EmbeddedText
+*97 (EmbeddedText
 uid 436,0
 commentText (CommentText
@@ -3393,5 +3437,5 @@
 va (VaSet
 )
-xt "50200,45200,58200,49200"
+xt "50200,45200,60200,48200"
 st "
 -- eb_ID 1: hard-wired IDs
@@ -3424,5 +3468,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*97 (Text
+*98 (Text
 uid 433,0
 va (VaSet
@@ -3434,5 +3478,5 @@
 tm "HdlTextNameMgr"
 )
-*98 (Text
+*99 (Text
 uid 434,0
 va (VaSet
@@ -3460,5 +3504,5 @@
 viewiconposition 0
 )
-*99 (Net
+*100 (Net
 uid 440,0
 decl (Decl
@@ -3477,9 +3521,8 @@
 )
 xt "-90000,45400,-58500,46200"
-st "SIGNAL board_id              : std_logic_vector(3 downto 0)
-"
-)
-)
-*100 (Net
+st "SIGNAL board_id              : std_logic_vector(3 downto 0)"
+)
+)
+*101 (Net
 uid 448,0
 decl (Decl
@@ -3496,12 +3539,11 @@
 )
 xt "-90000,47800,-58500,48600"
-st "SIGNAL crate_id              : std_logic_vector(1 downto 0)
-"
-)
-)
-*101 (SaComponent
+st "SIGNAL crate_id              : std_logic_vector(1 downto 0)"
+)
+)
+*102 (SaComponent
 uid 508,0
 optionalChildren [
-*102 (CptPort
+*103 (CptPort
 uid 489,0
 ps "OnEdgeStrategy"
@@ -3539,5 +3581,5 @@
 )
 )
-*103 (CptPort
+*104 (CptPort
 uid 493,0
 ps "OnEdgeStrategy"
@@ -3578,5 +3620,5 @@
 )
 )
-*104 (CptPort
+*105 (CptPort
 uid 497,0
 ps "OnEdgeStrategy"
@@ -3616,5 +3658,5 @@
 )
 )
-*105 (CptPort
+*106 (CptPort
 uid 501,0
 ps "OnEdgeStrategy"
@@ -3670,5 +3712,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*106 (Text
+*107 (Text
 uid 511,0
 va (VaSet
@@ -3680,5 +3722,5 @@
 tm "BdLibraryNameMgr"
 )
-*107 (Text
+*108 (Text
 uid 512,0
 va (VaSet
@@ -3690,5 +3732,5 @@
 tm "CptNameMgr"
 )
-*108 (Text
+*109 (Text
 uid 513,0
 va (VaSet
@@ -3744,8 +3786,8 @@
 archFileType "UNKNOWN"
 )
-*109 (HdlText
+*110 (HdlText
 uid 518,0
 optionalChildren [
-*110 (EmbeddedText
+*111 (EmbeddedText
 uid 524,0
 commentText (CommentText
@@ -3767,5 +3809,5 @@
 va (VaSet
 )
-xt "50200,57200,60900,67200"
+xt "50200,57200,62100,66200"
 st "
 -- eb_adc 2: ADC routing
@@ -3804,5 +3846,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*111 (Text
+*112 (Text
 uid 521,0
 va (VaSet
@@ -3814,5 +3856,5 @@
 tm "HdlTextNameMgr"
 )
-*112 (Text
+*113 (Text
 uid 522,0
 va (VaSet
@@ -3840,5 +3882,5 @@
 viewiconposition 0
 )
-*113 (Net
+*114 (Net
 uid 528,0
 decl (Decl
@@ -3855,9 +3897,8 @@
 )
 xt "-90000,42200,-58500,43000"
-st "SIGNAL adc_otr_array         : std_logic_vector(3 DOWNTO 0)
-"
-)
-)
-*114 (Net
+st "SIGNAL adc_otr_array         : std_logic_vector(3 DOWNTO 0)"
+)
+)
+*115 (Net
 uid 536,0
 decl (Decl
@@ -3873,9 +3914,8 @@
 )
 xt "-90000,39800,-63000,40600"
-st "SIGNAL adc_data_array        : adc_data_array_type
-"
-)
-)
-*115 (Net
+st "SIGNAL adc_data_array        : adc_data_array_type"
+)
+)
+*116 (Net
 uid 544,0
 decl (Decl
@@ -3893,9 +3933,8 @@
 )
 xt "-90000,40600,-68000,41400"
-st "SIGNAL adc_oeb               : std_logic
-"
-)
-)
-*116 (Net
+st "SIGNAL adc_oeb               : std_logic"
+)
+)
+*117 (Net
 uid 560,0
 decl (Decl
@@ -3913,9 +3952,8 @@
 )
 xt "-90000,41400,-68000,42200"
-st "SIGNAL adc_otr               : STD_LOGIC
-"
-)
-)
-*117 (Net
+st "SIGNAL adc_otr               : STD_LOGIC"
+)
+)
+*118 (Net
 uid 568,0
 decl (Decl
@@ -3934,9 +3972,8 @@
 )
 xt "-90000,39000,-58000,39800"
-st "SIGNAL adc_data              : std_logic_vector(11 DOWNTO 0)
-"
-)
-)
-*118 (Net
+st "SIGNAL adc_data              : std_logic_vector(11 DOWNTO 0)"
+)
+)
+*119 (Net
 uid 767,0
 decl (Decl
@@ -3952,10 +3989,9 @@
 font "Courier New,8,0"
 )
-xt "-90000,67000,-55000,67800"
-st "SIGNAL wiz_reset             : std_logic                    := '1'
-"
-)
-)
-*119 (Net
+xt "-90000,67800,-55000,68600"
+st "SIGNAL wiz_reset             : std_logic                    := '1'"
+)
+)
+*120 (Net
 uid 775,0
 decl (Decl
@@ -3974,9 +4010,8 @@
 )
 xt "-90000,54200,-49000,55000"
-st "SIGNAL led                   : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')
-"
-)
-)
-*120 (Net
+st "SIGNAL led                   : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0')"
+)
+)
+*121 (Net
 uid 783,0
 decl (Decl
@@ -3992,10 +4027,9 @@
 font "Courier New,8,0"
 )
-xt "-90000,63800,-55000,64600"
-st "SIGNAL wiz_cs                : std_logic                    := '1'
-"
-)
-)
-*121 (Net
+xt "-90000,64600,-55000,65400"
+st "SIGNAL wiz_cs                : std_logic                    := '1'"
+)
+)
+*122 (Net
 uid 791,0
 decl (Decl
@@ -4010,10 +4044,9 @@
 font "Courier New,8,0"
 )
-xt "-90000,65400,-68000,66200"
-st "SIGNAL wiz_int               : std_logic
-"
-)
-)
-*122 (Net
+xt "-90000,66200,-68000,67000"
+st "SIGNAL wiz_int               : std_logic"
+)
+)
+*123 (Net
 uid 799,0
 decl (Decl
@@ -4029,9 +4062,8 @@
 )
 xt "-90000,48600,-68000,49400"
-st "SIGNAL dac_cs                : std_logic
-"
-)
-)
-*123 (Net
+st "SIGNAL dac_cs                : std_logic"
+)
+)
+*124 (Net
 uid 807,0
 decl (Decl
@@ -4048,9 +4080,8 @@
 )
 xt "-90000,55800,-55000,56600"
-st "SIGNAL mosi                  : std_logic                    := '0'
-"
-)
-)
-*124 (Net
+st "SIGNAL mosi                  : std_logic                    := '0'"
+)
+)
+*125 (Net
 uid 815,0
 decl (Decl
@@ -4069,9 +4100,8 @@
 )
 xt "-90000,51000,-41500,51800"
-st "SIGNAL denable               : std_logic                    := '0' -- default domino wave off
-"
-)
-)
-*125 (Net
+st "SIGNAL denable               : std_logic                    := '0' -- default domino wave off"
+)
+)
+*126 (Net
 uid 823,0
 decl (Decl
@@ -4087,9 +4117,8 @@
 )
 xt "-90000,25400,-68000,26200"
-st "SIGNAL CLK_25_PS             : std_logic
-"
-)
-)
-*126 (Net
+st "SIGNAL CLK_25_PS             : std_logic"
+)
+)
+*127 (Net
 uid 831,0
 decl (Decl
@@ -4105,9 +4134,8 @@
 )
 xt "-90000,26200,-68000,27000"
-st "SIGNAL CLK_50                : std_logic
-"
-)
-)
-*127 (Net
+st "SIGNAL CLK_50                : std_logic"
+)
+)
+*128 (Net
 uid 839,0
 decl (Decl
@@ -4125,9 +4153,8 @@
 )
 xt "-90000,51800,-49000,52600"
-st "SIGNAL drs_channel_id        : std_logic_vector(3 downto 0) := (others => '0')
-"
-)
-)
-*128 (Net
+st "SIGNAL drs_channel_id        : std_logic_vector(3 downto 0) := (others => '0')"
+)
+)
+*129 (Net
 uid 847,0
 decl (Decl
@@ -4144,9 +4171,8 @@
 )
 xt "-90000,52600,-55000,53400"
-st "SIGNAL drs_dwrite            : std_logic                    := '1'
-"
-)
-)
-*129 (Net
+st "SIGNAL drs_dwrite            : std_logic                    := '1'"
+)
+)
+*130 (Net
 uid 855,0
 decl (Decl
@@ -4163,9 +4189,8 @@
 )
 xt "-90000,33400,-55000,34200"
-st "SIGNAL RSRLOAD               : std_logic                    := '0'
-"
-)
-)
-*130 (Net
+st "SIGNAL RSRLOAD               : std_logic                    := '0'"
+)
+)
+*131 (Net
 uid 863,0
 decl (Decl
@@ -4182,9 +4207,8 @@
 )
 xt "-90000,34200,-55000,35000"
-st "SIGNAL SRCLK                 : std_logic                    := '0'
-"
-)
-)
-*131 (Net
+st "SIGNAL SRCLK                 : std_logic                    := '0'"
+)
+)
+*132 (Net
 uid 871,0
 decl (Decl
@@ -4200,9 +4224,8 @@
 )
 xt "-90000,35800,-68000,36600"
-st "SIGNAL SROUT_in_0            : std_logic
-"
-)
-)
-*132 (Net
+st "SIGNAL SROUT_in_0            : std_logic"
+)
+)
+*133 (Net
 uid 879,0
 decl (Decl
@@ -4218,9 +4241,8 @@
 )
 xt "-90000,36600,-68000,37400"
-st "SIGNAL SROUT_in_1            : std_logic
-"
-)
-)
-*133 (Net
+st "SIGNAL SROUT_in_1            : std_logic"
+)
+)
+*134 (Net
 uid 887,0
 decl (Decl
@@ -4236,9 +4258,8 @@
 )
 xt "-90000,37400,-68000,38200"
-st "SIGNAL SROUT_in_2            : std_logic
-"
-)
-)
-*134 (Net
+st "SIGNAL SROUT_in_2            : std_logic"
+)
+)
+*135 (Net
 uid 895,0
 decl (Decl
@@ -4254,9 +4275,8 @@
 )
 xt "-90000,38200,-68000,39000"
-st "SIGNAL SROUT_in_3            : std_logic
-"
-)
-)
-*135 (Net
+st "SIGNAL SROUT_in_3            : std_logic"
+)
+)
+*136 (Net
 uid 1435,0
 decl (Decl
@@ -4273,9 +4293,8 @@
 )
 xt "-90000,35000,-55000,35800"
-st "SIGNAL SRIN_out              : std_logic                    := '0'
-"
-)
-)
-*136 (Net
+st "SIGNAL SRIN_out              : std_logic                    := '0'"
+)
+)
+*137 (Net
 uid 1443,0
 decl (Decl
@@ -4291,9 +4310,8 @@
 )
 xt "-90000,44600,-68000,45400"
-st "SIGNAL amber                 : std_logic
-"
-)
-)
-*137 (Net
+st "SIGNAL amber                 : std_logic"
+)
+)
+*138 (Net
 uid 1451,0
 decl (Decl
@@ -4309,9 +4327,8 @@
 )
 xt "-90000,57400,-68000,58200"
-st "SIGNAL red                   : std_logic
-"
-)
-)
-*138 (Net
+st "SIGNAL red                   : std_logic"
+)
+)
+*139 (Net
 uid 1459,0
 decl (Decl
@@ -4327,9 +4344,8 @@
 )
 xt "-90000,53400,-68000,54200"
-st "SIGNAL green                 : std_logic
-"
-)
-)
-*139 (Net
+st "SIGNAL green                 : std_logic"
+)
+)
+*140 (Net
 uid 1467,0
 decl (Decl
@@ -4346,9 +4362,8 @@
 )
 xt "-90000,47000,-58000,47800"
-st "SIGNAL counter_result        : std_logic_vector(11 DOWNTO 0)
-"
-)
-)
-*140 (Net
+st "SIGNAL counter_result        : std_logic_vector(11 DOWNTO 0)"
+)
+)
+*141 (Net
 uid 1475,0
 decl (Decl
@@ -4365,9 +4380,8 @@
 )
 xt "-90000,43800,-68000,44600"
-st "SIGNAL alarm_refclk_too_low  : std_logic
-"
-)
-)
-*141 (Net
+st "SIGNAL alarm_refclk_too_low  : std_logic"
+)
+)
+*142 (Net
 uid 1483,0
 decl (Decl
@@ -4383,12 +4397,11 @@
 )
 xt "-90000,43000,-68000,43800"
-st "SIGNAL alarm_refclk_too_high : std_logic
-"
-)
-)
-*142 (HdlText
+st "SIGNAL alarm_refclk_too_high : std_logic"
+)
+)
+*143 (HdlText
 uid 1491,0
 optionalChildren [
-*143 (EmbeddedText
+*144 (EmbeddedText
 uid 1497,0
 commentText (CommentText
@@ -4410,5 +4423,5 @@
 va (VaSet
 )
-xt "27200,72200,40200,77200"
+xt "27200,72200,39400,77200"
 st "
 
@@ -4445,5 +4458,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*144 (Text
+*145 (Text
 uid 1494,0
 va (VaSet
@@ -4455,5 +4468,5 @@
 tm "HdlTextNameMgr"
 )
-*145 (Text
+*146 (Text
 uid 1495,0
 va (VaSet
@@ -4481,5 +4494,5 @@
 viewiconposition 0
 )
-*146 (Net
+*147 (Net
 uid 1501,0
 decl (Decl
@@ -4496,12 +4509,11 @@
 )
 xt "-90000,28600,-58500,29400"
-st "SIGNAL D_T_in                : std_logic_vector(1 DOWNTO 0)
-"
-)
-)
-*147 (SaComponent
+st "SIGNAL D_T_in                : std_logic_vector(1 DOWNTO 0)"
+)
+)
+*148 (SaComponent
 uid 1509,0
 optionalChildren [
-*148 (CptPort
+*149 (CptPort
 uid 1519,0
 ps "OnEdgeStrategy"
@@ -4539,5 +4551,5 @@
 )
 )
-*149 (CptPort
+*150 (CptPort
 uid 1523,0
 ps "OnEdgeStrategy"
@@ -4592,5 +4604,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*150 (Text
+*151 (Text
 uid 1512,0
 va (VaSet
@@ -4602,5 +4614,5 @@
 tm "BdLibraryNameMgr"
 )
-*151 (Text
+*152 (Text
 uid 1513,0
 va (VaSet
@@ -4612,5 +4624,5 @@
 tm "CptNameMgr"
 )
-*152 (Text
+*153 (Text
 uid 1514,0
 va (VaSet
@@ -4671,5 +4683,5 @@
 archFileType "UNKNOWN"
 )
-*153 (Net
+*154 (Net
 uid 1559,0
 decl (Decl
@@ -4687,9 +4699,8 @@
 )
 xt "-90000,56600,-29000,57400"
-st "SIGNAL plllock_in            : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked
-"
-)
-)
-*154 (Net
+st "SIGNAL plllock_in            : std_logic_vector(3 DOWNTO 0) -- high level, if dominowave is running and DRS PLL locked"
+)
+)
+*155 (Net
 uid 1682,0
 lang 2
@@ -4706,9 +4717,8 @@
 )
 xt "-90000,24600,-68000,25400"
-st "SIGNAL ADC_CLK               : std_logic
-"
-)
-)
-*155 (Net
+st "SIGNAL ADC_CLK               : std_logic"
+)
+)
+*156 (Net
 uid 2001,0
 decl (Decl
@@ -4725,12 +4735,11 @@
 )
 xt "-90000,32600,-55000,33400"
-st "SIGNAL REF_CLK               : STD_LOGIC                    := '0'
-"
-)
-)
-*156 (SaComponent
+st "SIGNAL REF_CLK               : STD_LOGIC                    := '0'"
+)
+)
+*157 (SaComponent
 uid 2336,0
 optionalChildren [
-*157 (CptPort
+*158 (CptPort
 uid 2315,0
 ps "OnEdgeStrategy"
@@ -4769,5 +4778,5 @@
 )
 )
-*158 (CptPort
+*159 (CptPort
 uid 2319,0
 ps "OnEdgeStrategy"
@@ -4807,5 +4816,5 @@
 )
 )
-*159 (CptPort
+*160 (CptPort
 uid 2323,0
 ps "OnEdgeStrategy"
@@ -4843,5 +4852,5 @@
 )
 )
-*160 (CptPort
+*161 (CptPort
 uid 2327,0
 ps "OnEdgeStrategy"
@@ -4879,5 +4888,5 @@
 )
 )
-*161 (CptPort
+*162 (CptPort
 uid 2331,0
 ps "OnEdgeStrategy"
@@ -4915,5 +4924,5 @@
 )
 )
-*162 (CptPort
+*163 (CptPort
 uid 2548,0
 ps "OnEdgeStrategy"
@@ -4966,5 +4975,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*163 (Text
+*164 (Text
 uid 2339,0
 va (VaSet
@@ -4976,5 +4985,5 @@
 tm "BdLibraryNameMgr"
 )
-*164 (Text
+*165 (Text
 uid 2340,0
 va (VaSet
@@ -4986,5 +4995,5 @@
 tm "CptNameMgr"
 )
-*165 (Text
+*166 (Text
 uid 2341,0
 va (VaSet
@@ -5033,5 +5042,5 @@
 archFileType "UNKNOWN"
 )
-*166 (Net
+*167 (Net
 uid 2705,0
 decl (Decl
@@ -5047,9 +5056,8 @@
 )
 xt "-90000,49400,-68000,50200"
-st "SIGNAL debug_data_ram_empty  : std_logic
-"
-)
-)
-*167 (Net
+st "SIGNAL debug_data_ram_empty  : std_logic"
+)
+)
+*168 (Net
 uid 2713,0
 decl (Decl
@@ -5065,9 +5073,8 @@
 )
 xt "-90000,50200,-68000,51000"
-st "SIGNAL debug_data_valid      : std_logic
-"
-)
-)
-*168 (Net
+st "SIGNAL debug_data_valid      : std_logic"
+)
+)
+*169 (Net
 uid 2721,0
 decl (Decl
@@ -5087,9 +5094,8 @@
 xt "-90000,27000,-58500,28600"
 st "-- for debugging
-SIGNAL DG_state              : std_logic_vector(7 downto 0)
-"
-)
-)
-*169 (Net
+SIGNAL DG_state              : std_logic_vector(7 downto 0)"
+)
+)
+*170 (Net
 uid 2729,0
 decl (Decl
@@ -5105,9 +5111,8 @@
 )
 xt "-90000,30200,-68000,31000"
-st "SIGNAL FTM_RS485_rx_en       : std_logic
-"
-)
-)
-*170 (Net
+st "SIGNAL FTM_RS485_rx_en       : std_logic"
+)
+)
+*171 (Net
 uid 2737,0
 decl (Decl
@@ -5123,9 +5128,8 @@
 )
 xt "-90000,31000,-68000,31800"
-st "SIGNAL FTM_RS485_tx_d        : std_logic
-"
-)
-)
-*171 (Net
+st "SIGNAL FTM_RS485_tx_d        : std_logic"
+)
+)
+*172 (Net
 uid 2745,0
 decl (Decl
@@ -5141,9 +5145,8 @@
 )
 xt "-90000,31800,-68000,32600"
-st "SIGNAL FTM_RS485_tx_en       : std_logic
-"
-)
-)
-*172 (Net
+st "SIGNAL FTM_RS485_tx_en       : std_logic"
+)
+)
+*173 (Net
 uid 2753,0
 lang 2
@@ -5163,9 +5166,8 @@
 )
 xt "-90000,55000,-33000,55800"
-st "SIGNAL mem_manager_state     : std_logic_vector(3 DOWNTO 0) -- state is encoded here ... useful for debugging.
-"
-)
-)
-*173 (Net
+st "SIGNAL mem_manager_state     : std_logic_vector(3 DOWNTO 0) -- state is encoded here ... useful for debugging."
+)
+)
+*174 (Net
 uid 2761,0
 decl (Decl
@@ -5181,10 +5183,9 @@
 font "Courier New,8,0"
 )
-xt "-90000,61400,-55000,62200"
-st "SIGNAL trigger_veto          : std_logic                    := '1'
-"
-)
-)
-*174 (Net
+xt "-90000,62200,-55000,63000"
+st "SIGNAL trigger_veto          : std_logic                    := '1'"
+)
+)
+*175 (Net
 uid 2769,0
 decl (Decl
@@ -5202,10 +5203,9 @@
 font "Courier New,8,0"
 )
-xt "-90000,62200,-33000,63000"
-st "SIGNAL w5300_state           : std_logic_vector(7 DOWNTO 0) -- state is encoded here ... useful for debugging.
-"
-)
-)
-*175 (Net
+xt "-90000,63000,-33000,63800"
+st "SIGNAL w5300_state           : std_logic_vector(7 DOWNTO 0) -- state is encoded here ... useful for debugging."
+)
+)
+*176 (Net
 uid 2777,0
 decl (Decl
@@ -5221,9 +5221,2041 @@
 )
 xt "-90000,29400,-68000,30200"
-st "SIGNAL FTM_RS485_rx_d        : std_logic
+st "SIGNAL FTM_RS485_rx_d        : std_logic"
+)
+)
+*177 (Net
+uid 2942,0
+decl (Decl
+n "socket_tx_free_out"
+t "std_logic_vector"
+b "(16 DOWNTO 0)"
+eolc "-- 17bit value .. that's true"
+posAdd 0
+o 55
+suid 64,0
+)
+declText (MLText
+uid 2943,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "-90000,60600,-43000,61400"
+st "SIGNAL socket_tx_free_out    : std_logic_vector(16 DOWNTO 0) -- 17bit value .. that's true"
+)
+)
+*178 (SaComponent
+uid 3285,0
+optionalChildren [
+*179 (CptPort
+uid 3073,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3074,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,19625,168750,20375"
+)
+tg (CPTG
+uid 3075,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3076,0
+va (VaSet
+)
+xt "163400,19500,167000,20500"
+st "wiz_reset"
+ju 2
+blo "167000,20300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "wiz_reset"
+t "std_logic"
+o 50
+suid 2,0
+i "'1'"
+)
+)
+)
+*180 (CptPort
+uid 3077,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3078,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,65625,168750,66375"
+)
+tg (CPTG
+uid 3079,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3080,0
+va (VaSet
+)
+xt "163000,65500,167000,66500"
+st "led : (7:0)"
+ju 2
+blo "167000,66300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "led"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+posAdd 0
+o 38
+suid 7,0
+i "(OTHERS => '0')"
+)
+)
+)
+*181 (CptPort
+uid 3081,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3082,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,27625,140000,28375"
+)
+tg (CPTG
+uid 3083,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3084,0
+va (VaSet
+)
+xt "141000,27500,143800,28500"
+st "trigger"
+blo "141000,28300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "trigger"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 14
+suid 18,0
+)
+)
+)
+*182 (CptPort
+uid 3085,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3086,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,38625,140000,39375"
+)
+tg (CPTG
+uid 3087,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3088,0
+va (VaSet
+)
+xt "141000,38500,144200,39500"
+st "adc_oeb"
+blo "141000,39300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "adc_oeb"
+t "std_logic"
+o 26
+suid 21,0
+i "'1'"
+)
+)
+)
+*183 (CptPort
+uid 3089,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3090,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,29625,140000,30375"
+)
+tg (CPTG
+uid 3091,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3092,0
+va (VaSet
+)
+xt "141000,29500,146900,30500"
+st "board_id : (3:0)"
+blo "141000,30300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "board_id"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 10
+suid 24,0
+)
+)
+)
+*184 (CptPort
+uid 3093,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3094,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,30625,140000,31375"
+)
+tg (CPTG
+uid 3095,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3096,0
+va (VaSet
+)
+xt "141000,30500,146700,31500"
+st "crate_id : (1:0)"
+blo "141000,31300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "crate_id"
+t "std_logic_vector"
+b "(1 DOWNTO 0)"
+o 11
+suid 25,0
+)
+)
+)
+*185 (CptPort
+uid 3097,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3098,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,16625,168750,17375"
+)
+tg (CPTG
+uid 3099,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3100,0
+va (VaSet
+)
+xt "161000,16500,167000,17500"
+st "wiz_addr : (9:0)"
+ju 2
+blo "167000,17300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "wiz_addr"
+t "std_logic_vector"
+b "(9 DOWNTO 0)"
+o 47
+suid 26,0
+)
+)
+)
+*186 (CptPort
+uid 3101,0
+ps "OnEdgeStrategy"
+shape (Diamond
+uid 3102,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,17625,168750,18375"
+)
+tg (CPTG
+uid 3103,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3104,0
+va (VaSet
+)
+xt "160700,17500,167000,18500"
+st "wiz_data : (15:0)"
+ju 2
+blo "167000,18300"
+)
+)
+thePort (LogicalPort
+m 2
+decl (Decl
+n "wiz_data"
+t "std_logic_vector"
+b "(15 DOWNTO 0)"
+o 53
+suid 27,0
+)
+)
+)
+*187 (CptPort
+uid 3105,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3106,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,23625,168750,24375"
+)
+tg (CPTG
+uid 3107,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3108,0
+va (VaSet
+)
+xt "164300,23500,167000,24500"
+st "wiz_cs"
+ju 2
+blo "167000,24300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "wiz_cs"
+t "std_logic"
+o 48
+suid 28,0
+i "'1'"
+)
+)
+)
+*188 (CptPort
+uid 3109,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3110,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,21625,168750,22375"
+)
+tg (CPTG
+uid 3111,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3112,0
+va (VaSet
+)
+xt "164300,21500,167000,22500"
+st "wiz_wr"
+ju 2
+blo "167000,22300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "wiz_wr"
+t "std_logic"
+o 51
+suid 29,0
+i "'1'"
+)
+)
+)
+*189 (CptPort
+uid 3113,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3114,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,20625,168750,21375"
+)
+tg (CPTG
+uid 3115,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3116,0
+va (VaSet
+)
+xt "164400,20500,167000,21500"
+st "wiz_rd"
+ju 2
+blo "167000,21300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "wiz_rd"
+t "std_logic"
+o 49
+suid 30,0
+i "'1'"
+)
+)
+)
+*190 (CptPort
+uid 3117,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3118,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,22625,168750,23375"
+)
+tg (CPTG
+uid 3119,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3120,0
+va (VaSet
+)
+xt "164300,22500,167000,23500"
+st "wiz_int"
+ju 2
+blo "167000,23300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "wiz_int"
+t "std_logic"
+o 15
+suid 31,0
+)
+)
+)
+*191 (CptPort
+uid 3121,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3122,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,18625,140000,19375"
+)
+tg (CPTG
+uid 3123,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3124,0
+va (VaSet
+)
+xt "141000,18500,145500,19500"
+st "CLK_25_PS"
+blo "141000,19300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "CLK_25_PS"
+t "std_logic"
+o 17
+suid 35,0
+)
+)
+)
+*192 (CptPort
+uid 3125,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3126,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,17625,140000,18375"
+)
+tg (CPTG
+uid 3127,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3128,0
+va (VaSet
+)
+xt "141000,17500,144100,18500"
+st "CLK_50"
+blo "141000,18300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "CLK_50"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 18
+suid 37,0
+)
+)
+)
+*193 (CptPort
+uid 3129,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3130,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,16625,140000,17375"
+)
+tg (CPTG
+uid 3131,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3132,0
+va (VaSet
+)
+xt "141000,16500,142900,17500"
+st "CLK"
+blo "141000,17300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "CLK"
+t "std_logic"
+o 1
+suid 38,0
+)
+)
+)
+*194 (CptPort
+uid 3133,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3134,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,37625,140000,38375"
+)
+tg (CPTG
+uid 3135,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3136,0
+va (VaSet
+)
+xt "141000,37500,149000,38500"
+st "adc_otr_array : (3:0)"
+blo "141000,38300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "adc_otr_array"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 9
+suid 40,0
+)
+)
+)
+*195 (CptPort
+uid 3137,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3138,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,43625,140000,44375"
+)
+tg (CPTG
+uid 3139,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3140,0
+va (VaSet
+)
+xt "141000,43500,146900,44500"
+st "adc_data_array"
+blo "141000,44300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "adc_data_array"
+t "adc_data_array_type"
+o 8
+suid 41,0
+)
+)
+)
+*196 (CptPort
+uid 3141,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3142,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,57625,140000,58375"
+)
+tg (CPTG
+uid 3143,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3144,0
+va (VaSet
+)
+xt "141000,57500,149500,58500"
+st "drs_channel_id : (3:0)"
+blo "141000,58300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "drs_channel_id"
+t "std_logic_vector"
+b "(3 downto 0)"
+o 35
+suid 48,0
+i "(others => '0')"
+)
+)
+)
+*197 (CptPort
+uid 3145,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3146,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,62625,140000,63375"
+)
+tg (CPTG
+uid 3147,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3148,0
+va (VaSet
+)
+xt "141000,62500,145300,63500"
+st "drs_dwrite"
+blo "141000,63300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "drs_dwrite"
+t "std_logic"
+o 36
+suid 49,0
+i "'1'"
+)
+)
+)
+*198 (CptPort
+uid 3149,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3150,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,53625,140000,54375"
+)
+tg (CPTG
+uid 3151,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3152,0
+va (VaSet
+)
+xt "141000,53500,146400,54500"
+st "SROUT_in_0"
+blo "141000,54300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "SROUT_in_0"
+t "std_logic"
+o 4
+suid 52,0
+)
+)
+)
+*199 (CptPort
+uid 3153,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3154,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,54625,140000,55375"
+)
+tg (CPTG
+uid 3155,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3156,0
+va (VaSet
+)
+xt "141000,54500,146400,55500"
+st "SROUT_in_1"
+blo "141000,55300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "SROUT_in_1"
+t "std_logic"
+o 5
+suid 53,0
+)
+)
+)
+*200 (CptPort
+uid 3157,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3158,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,55625,140000,56375"
+)
+tg (CPTG
+uid 3159,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3160,0
+va (VaSet
+)
+xt "141000,55500,146400,56500"
+st "SROUT_in_2"
+blo "141000,56300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "SROUT_in_2"
+t "std_logic"
+o 6
+suid 54,0
+)
+)
+)
+*201 (CptPort
+uid 3161,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3162,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,56625,140000,57375"
+)
+tg (CPTG
+uid 3163,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3164,0
+va (VaSet
+)
+xt "141000,56500,146400,57500"
+st "SROUT_in_3"
+blo "141000,57300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "SROUT_in_3"
+t "std_logic"
+o 7
+suid 55,0
+)
+)
+)
+*202 (CptPort
+uid 3165,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3166,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,59625,140000,60375"
+)
+tg (CPTG
+uid 3167,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3168,0
+va (VaSet
+)
+xt "141000,59500,145200,60500"
+st "RSRLOAD"
+blo "141000,60300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "RSRLOAD"
+t "std_logic"
+o 23
+suid 56,0
+i "'0'"
+)
+)
+)
+*203 (CptPort
+uid 3169,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3170,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,60625,140000,61375"
+)
+tg (CPTG
+uid 3171,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3172,0
+va (VaSet
+)
+xt "141000,60500,144000,61500"
+st "SRCLK"
+blo "141000,61300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "SRCLK"
+t "std_logic"
+o 24
+suid 57,0
+i "'0'"
+)
+)
+)
+*204 (CptPort
+uid 3173,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3174,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,46625,168750,47375"
+)
+tg (CPTG
+uid 3175,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3176,0
+va (VaSet
+)
+xt "165300,46500,167000,47500"
+st "sclk"
+ju 2
+blo "167000,47300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "sclk"
+t "std_logic"
+o 42
+suid 62,0
+)
+)
+)
+*205 (CptPort
+uid 3177,0
+ps "OnEdgeStrategy"
+shape (Diamond
+uid 3178,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,47625,168750,48375"
+)
+tg (CPTG
+uid 3179,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3180,0
+va (VaSet
+)
+xt "165600,47500,167000,48500"
+st "sio"
+ju 2
+blo "167000,48300"
+)
+)
+thePort (LogicalPort
+m 2
+decl (Decl
+n "sio"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 52
+suid 63,0
+)
+)
+)
+*206 (CptPort
+uid 3181,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3182,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,35625,168750,36375"
+)
+tg (CPTG
+uid 3183,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3184,0
+va (VaSet
+)
+xt "164200,35500,167000,36500"
+st "dac_cs"
+ju 2
+blo "167000,36300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "dac_cs"
+t "std_logic"
+o 31
+suid 64,0
+)
+)
+)
+*207 (CptPort
+uid 3185,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3186,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,37625,168750,38375"
+)
+tg (CPTG
+uid 3187,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3188,0
+va (VaSet
+)
+xt "160500,37500,167000,38500"
+st "sensor_cs : (3:0)"
+ju 2
+blo "167000,38300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "sensor_cs"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 43
+suid 65,0
+)
+)
+)
+*208 (CptPort
+uid 3189,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3190,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,48625,168750,49375"
+)
+tg (CPTG
+uid 3191,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3192,0
+va (VaSet
+)
+xt "165000,48500,167000,49500"
+st "mosi"
+ju 2
+blo "167000,49300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "mosi"
+t "std_logic"
+o 40
+suid 66,0
+i "'0'"
+)
+)
+)
+*209 (CptPort
+uid 3193,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3194,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,61625,140000,62375"
+)
+tg (CPTG
+uid 3195,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3196,0
+va (VaSet
+)
+xt "141000,61500,144000,62500"
+st "denable"
+blo "141000,62300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "denable"
+t "std_logic"
+eolc "-- default domino wave off"
+posAdd 0
+o 34
+suid 67,0
+i "'0'"
+)
+)
+)
+*210 (CptPort
+uid 3197,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3198,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,67625,140000,68375"
+)
+tg (CPTG
+uid 3199,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3200,0
+va (VaSet
+)
+xt "141000,67500,144700,68500"
+st "SRIN_out"
+blo "141000,68300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "SRIN_out"
+t "std_logic"
+o 25
+suid 85,0
+i "'0'"
+)
+)
+)
+*211 (CptPort
+uid 3201,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3202,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,73625,168750,74375"
+)
+tg (CPTG
+uid 3203,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3204,0
+va (VaSet
+)
+xt "164600,73500,167000,74500"
+st "green"
+ju 2
+blo "167000,74300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "green"
+t "std_logic"
+o 37
+suid 86,0
+)
+)
+)
+*212 (CptPort
+uid 3205,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3206,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,75625,168750,76375"
+)
+tg (CPTG
+uid 3207,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3208,0
+va (VaSet
+)
+xt "164500,75500,167000,76500"
+st "amber"
+ju 2
+blo "167000,76300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "amber"
+t "std_logic"
+o 29
+suid 87,0
+)
+)
+)
+*213 (CptPort
+uid 3209,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3210,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,74625,168750,75375"
+)
+tg (CPTG
+uid 3211,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3212,0
+va (VaSet
+)
+xt "165500,74500,167000,75500"
+st "red"
+ju 2
+blo "167000,75300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "red"
+t "std_logic"
+o 41
+suid 88,0
+)
+)
+)
+*214 (CptPort
+uid 3213,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3214,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,70625,140000,71375"
+)
+tg (CPTG
+uid 3215,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3216,0
+va (VaSet
+)
+xt "141000,70500,146500,71500"
+st "D_T_in : (1:0)"
+blo "141000,71300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "D_T_in"
+t "std_logic_vector"
+b "(1 DOWNTO 0)"
+o 2
+suid 91,0
+)
+)
+)
+*215 (CptPort
+uid 3217,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3218,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,71625,140000,72375"
+)
+tg (CPTG
+uid 3219,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3220,0
+va (VaSet
+)
+xt "141000,71500,146100,72500"
+st "drs_refclk_in"
+blo "141000,72300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "drs_refclk_in"
+t "std_logic"
+eolc "-- used to check if DRS REFCLK exsists, if not DENABLE inhibit"
+o 12
+suid 92,0
+)
+)
+)
+*216 (CptPort
+uid 3221,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3222,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,72625,140000,73375"
+)
+tg (CPTG
+uid 3223,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3224,0
+va (VaSet
+)
+xt "141000,72500,147100,73500"
+st "plllock_in : (3:0)"
+blo "141000,73300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "plllock_in"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+eolc "-- high level, if dominowave is running and DRS PLL locked"
+o 13
+suid 93,0
+)
+)
+)
+*217 (CptPort
+uid 3225,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3226,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,72625,168750,73375"
+)
+tg (CPTG
+uid 3227,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3228,0
+va (VaSet
+)
+xt "158400,72500,167000,73500"
+st "counter_result : (11:0)"
+ju 2
+blo "167000,73300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "counter_result"
+t "std_logic_vector"
+b "(11 DOWNTO 0)"
+o 30
+suid 94,0
+)
+)
+)
+*218 (CptPort
+uid 3229,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3230,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,69625,168750,70375"
+)
+tg (CPTG
+uid 3231,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3232,0
+va (VaSet
+)
+xt "158400,69500,167000,70500"
+st "alarm_refclk_too_high"
+ju 2
+blo "167000,70300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "alarm_refclk_too_high"
+t "std_logic"
+o 27
+suid 95,0
+)
+)
+)
+*219 (CptPort
+uid 3233,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3234,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,70625,168750,71375"
+)
+tg (CPTG
+uid 3235,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3236,0
+va (VaSet
+)
+xt "158800,70500,167000,71500"
+st "alarm_refclk_too_low"
+ju 2
+blo "167000,71300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "alarm_refclk_too_low"
+t "std_logic"
+posAdd 0
+o 28
+suid 96,0
+)
+)
+)
+*220 (CptPort
+uid 3237,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3238,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,19625,140000,20375"
+)
+tg (CPTG
+uid 3239,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3240,0
+va (VaSet
+)
+xt "141000,19500,145000,20500"
+st "ADC_CLK"
+blo "141000,20300"
+)
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "ADC_CLK"
+t "std_logic"
+o 16
+suid 97,0
+)
+)
+)
+*221 (CptPort
+uid 3241,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3242,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,83625,168750,84375"
+)
+tg (CPTG
+uid 3243,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3244,0
+va (VaSet
+)
+xt "162100,83500,167000,84500"
+st "trigger_veto"
+ju 2
+blo "167000,84300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "trigger_veto"
+t "std_logic"
+o 45
+suid 98,0
+i "'1'"
+)
+)
+)
+*222 (CptPort
+uid 3245,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3246,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "139250,73625,140000,74375"
+)
+tg (CPTG
+uid 3247,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 3248,0
+va (VaSet
+)
+xt "141000,73500,148000,74500"
+st "FTM_RS485_rx_d"
+blo "141000,74300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "FTM_RS485_rx_d"
+t "std_logic"
+o 3
+suid 99,0
+)
+)
+)
+*223 (CptPort
+uid 3249,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3250,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,80625,168750,81375"
+)
+tg (CPTG
+uid 3251,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3252,0
+va (VaSet
+)
+xt "160100,80500,167000,81500"
+st "FTM_RS485_tx_d"
+ju 2
+blo "167000,81300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "FTM_RS485_tx_d"
+t "std_logic"
+o 21
+suid 100,0
+)
+)
+)
+*224 (CptPort
+uid 3253,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3254,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,79625,168750,80375"
+)
+tg (CPTG
+uid 3255,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3256,0
+va (VaSet
+)
+xt "159600,79500,167000,80500"
+st "FTM_RS485_rx_en"
+ju 2
+blo "167000,80300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "FTM_RS485_rx_en"
+t "std_logic"
+o 20
+suid 101,0
+)
+)
+)
+*225 (CptPort
+uid 3257,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3258,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,81625,168750,82375"
+)
+tg (CPTG
+uid 3259,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3260,0
+va (VaSet
+)
+xt "159700,81500,167000,82500"
+st "FTM_RS485_tx_en"
+ju 2
+blo "167000,82300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "FTM_RS485_tx_en"
+t "std_logic"
+o 22
+suid 102,0
+)
+)
+)
+*226 (CptPort
+uid 3261,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3262,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,84625,168750,85375"
+)
+tg (CPTG
+uid 3263,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3264,0
+va (VaSet
+)
+xt "159900,84500,167000,85500"
+st "w5300_state : (7:0)"
+ju 2
+blo "167000,85300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "w5300_state"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+eolc "-- state is encoded here ... useful for debugging."
+posAdd 0
+o 46
+suid 103,0
+)
+)
+)
+*227 (CptPort
+uid 3265,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3266,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,76625,168750,77375"
+)
+tg (CPTG
+uid 3267,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3268,0
+va (VaSet
+)
+xt "157900,76500,167000,77500"
+st "debug_data_ram_empty"
+ju 2
+blo "167000,77300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "debug_data_ram_empty"
+t "std_logic"
+o 32
+suid 104,0
+)
+)
+)
+*228 (CptPort
+uid 3269,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3270,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,77625,168750,78375"
+)
+tg (CPTG
+uid 3271,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3272,0
+va (VaSet
+)
+xt "160400,77500,167000,78500"
+st "debug_data_valid"
+ju 2
+blo "167000,78300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "debug_data_valid"
+t "std_logic"
+o 33
+suid 105,0
+)
+)
+)
+*229 (CptPort
+uid 3273,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3274,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,82625,168750,83375"
+)
+tg (CPTG
+uid 3275,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3276,0
+va (VaSet
+)
+xt "156600,82500,167000,83500"
+st "mem_manager_state : (3:0)"
+ju 2
+blo "167000,83300"
+)
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "mem_manager_state"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+eolc "-- state is encoded here ... useful for debugging."
+posAdd 0
+o 39
+suid 106,0
+)
+)
+)
+*230 (CptPort
+uid 3277,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3278,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,78625,168750,79375"
+)
+tg (CPTG
+uid 3279,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3280,0
+va (VaSet
+)
+xt "160800,78500,167000,79500"
+st "DG_state : (7:0)"
+ju 2
+blo "167000,79300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "DG_state"
+t "std_logic_vector"
+b "(7 downto 0)"
+prec "-- for debugging"
+preAdd 0
+o 19
+suid 108,0
+)
+)
+)
+*231 (CptPort
+uid 3281,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 3282,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "168000,85625,168750,86375"
+)
+tg (CPTG
+uid 3283,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 3284,0
+va (VaSet
+)
+xt "157100,85500,167000,86500"
+st "socket_tx_free_out : (16:0)"
+ju 2
+blo "167000,86300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "socket_tx_free_out"
+t "std_logic_vector"
+b "(16 DOWNTO 0)"
+eolc "-- 17bit value .. that's true"
+posAdd 0
+o 44
+suid 109,0
+)
+)
+)
+]
+shape (Rectangle
+uid 3286,0
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+lineColor "0,32896,0"
+lineWidth 2
+)
+xt "140000,15000,168000,87000"
+)
+oxt "15000,-8000,43000,80000"
+ttg (MlTextGroup
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+ps "CenterOffsetStrategy"
+stg "VerticalLayoutStrategy"
+textVec [
+*232 (Text
+uid 3288,0
+va (VaSet
+font "Arial,8,1"
+)
+xt "144200,80000,150400,81000"
+st "FACT_FAD_lib"
+blo "144200,80800"
+tm "BdLibraryNameMgr"
+)
+*233 (Text
+uid 3289,0
+va (VaSet
+font "Arial,8,1"
+)
+xt "144200,81000,154000,82000"
+st "FAD_main_with_w53002"
+blo "144200,81800"
+tm "CptNameMgr"
+)
+*234 (Text
+uid 3290,0
+va (VaSet
+font "Arial,8,1"
+)
+xt "144200,82000,145200,83000"
+st "I0"
+blo "144200,82800"
+tm "InstanceNameMgr"
+)
+]
+)
+ga (GenericAssociation
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+ps "EdgeToEdgeStrategy"
+matrix (Matrix
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+text (MLText
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+va (VaSet
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+)
+xt "142000,14200,162000,15000"
+st "RAMADDRWIDTH64b = 15    ( integer )  
 "
 )
-)
-*176 (Wire
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+)
+elements [
+(GiElement
+name "RAMADDRWIDTH64b"
+type "integer"
+value "15"
+)
+]
+)
+viewicon (ZoomableIcon
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+sl 0
+va (VaSet
+vasetType 1
+fg "49152,49152,49152"
+)
+xt "140250,85250,141750,86750"
+iconName "BlockDiagram.png"
+iconMaskName "BlockDiagram.msk"
+ftype 1
+)
+viewiconposition 0
+portVis (PortSigDisplay
+)
+archFileType "UNKNOWN"
+)
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@@ -5259,7 +7291,7 @@
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-)
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-)
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+)
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-)
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+)
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 )
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-)
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+)
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-)
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+)
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 )
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-)
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-)
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-)
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-)
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+)
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 eat 2
@@ -5634,7 +7666,7 @@
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 )
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-)
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-)
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+)
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-)
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 )
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-)
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-)
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-start &104
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 eat 1
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-)
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-)
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-)
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-)
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@@ -6001,7 +8033,7 @@
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 )
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-)
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@@ -6037,7 +8069,7 @@
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-)
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 )
-on &146
-)
-*221 (Wire
+on &147
+)
+*280 (Wire
 uid 1561,0
 shape (OrthoPolyLine
@@ -6889,7 +8921,7 @@
 )
 )
-on &153
-)
-*222 (Wire
+on &154
+)
+*281 (Wire
 uid 1567,0
 shape (OrthoPolyLine
@@ -6904,5 +8936,5 @@
 ]
 )
-start &142
+start &143
 sat 2
 eat 16
@@ -6924,7 +8956,7 @@
 )
 )
-on &153
-)
-*223 (Wire
+on &154
+)
+*282 (Wire
 uid 1684,0
 shape (OrthoPolyLine
@@ -6959,7 +8991,7 @@
 )
 )
-on &154
-)
-*224 (Wire
+on &155
+)
+*283 (Wire
 uid 2707,0
 shape (OrthoPolyLine
@@ -6994,7 +9026,7 @@
 )
 )
-on &166
-)
-*225 (Wire
+on &167
+)
+*284 (Wire
 uid 2715,0
 shape (OrthoPolyLine
@@ -7029,7 +9061,7 @@
 )
 )
-on &167
-)
-*226 (Wire
+on &168
+)
+*285 (Wire
 uid 2723,0
 shape (OrthoPolyLine
@@ -7066,7 +9098,7 @@
 )
 )
-on &168
-)
-*227 (Wire
+on &169
+)
+*286 (Wire
 uid 2731,0
 shape (OrthoPolyLine
@@ -7101,7 +9133,7 @@
 )
 )
-on &169
-)
-*228 (Wire
+on &170
+)
+*287 (Wire
 uid 2739,0
 shape (OrthoPolyLine
@@ -7136,7 +9168,7 @@
 )
 )
-on &170
-)
-*229 (Wire
+on &171
+)
+*288 (Wire
 uid 2747,0
 shape (OrthoPolyLine
@@ -7171,7 +9203,7 @@
 )
 )
-on &171
-)
-*230 (Wire
+on &172
+)
+*289 (Wire
 uid 2755,0
 shape (OrthoPolyLine
@@ -7208,7 +9240,7 @@
 )
 )
-on &172
-)
-*231 (Wire
+on &173
+)
+*290 (Wire
 uid 2763,0
 shape (OrthoPolyLine
@@ -7243,7 +9275,7 @@
 )
 )
-on &173
-)
-*232 (Wire
+on &174
+)
+*291 (Wire
 uid 2771,0
 shape (OrthoPolyLine
@@ -7280,7 +9312,7 @@
 )
 )
-on &174
-)
-*233 (Wire
+on &175
+)
+*292 (Wire
 uid 2779,0
 shape (OrthoPolyLine
@@ -7315,5 +9347,42 @@
 )
 )
-on &175
+on &176
+)
+*293 (Wire
+uid 2944,0
+shape (OrthoPolyLine
+uid 2945,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "109750,90000,124000,90000"
+pts [
+"109750,90000"
+"124000,90000"
+]
+)
+start &65
+sat 32
+eat 16
+sty 1
+st 0
+sf 1
+si 0
+tg (WTG
+uid 2948,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 2949,0
+va (VaSet
+)
+xt "111000,89000,122900,90000"
+st "socket_tx_free_out : (16:0)"
+blo "111000,89800"
+tm "WireNameMgr"
+)
+)
+on &177
 )
 ]
@@ -7329,9 +9398,9 @@
 color "26368,26368,26368"
 )
-packageList *234 (PackageList
+packageList *294 (PackageList
 uid 41,0
 stg "VerticalLayoutStrategy"
 textVec [
-*235 (Text
+*295 (Text
 uid 42,0
 va (VaSet
@@ -7342,9 +9411,9 @@
 blo "-87000,800"
 )
-*236 (MLText
+*296 (MLText
 uid 43,0
 va (VaSet
 )
-xt "-87000,1000,-70900,11000"
+xt "-87000,1000,-72500,11000"
 st "LIBRARY ieee;
 USE ieee.std_logic_1164.all;
@@ -7365,5 +9434,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*237 (Text
+*297 (Text
 uid 45,0
 va (VaSet
@@ -7375,5 +9444,5 @@
 blo "20000,800"
 )
-*238 (Text
+*298 (Text
 uid 46,0
 va (VaSet
@@ -7385,15 +9454,15 @@
 blo "20000,1800"
 )
-*239 (MLText
+*299 (MLText
 uid 47,0
 va (VaSet
 isHidden 1
 )
-xt "20000,2000,28200,4000"
+xt "20000,2000,27500,4000"
 st "`resetall
 `timescale 1ns/10ps"
 tm "BdCompilerDirectivesTextMgr"
 )
-*240 (Text
+*300 (Text
 uid 48,0
 va (VaSet
@@ -7405,5 +9474,5 @@
 blo "20000,4800"
 )
-*241 (MLText
+*301 (MLText
 uid 49,0
 va (VaSet
@@ -7413,5 +9482,5 @@
 tm "BdCompilerDirectivesTextMgr"
 )
-*242 (Text
+*302 (Text
 uid 50,0
 va (VaSet
@@ -7423,5 +9492,5 @@
 blo "20000,5800"
 )
-*243 (MLText
+*303 (MLText
 uid 51,0
 va (VaSet
@@ -7434,7 +9503,7 @@
 associable 1
 )
-windowSize "0,20,1681,1050"
-viewArea "69198,38598,161304,96306"
-cachedDiagramExtent "-92000,0,146000,98000"
+windowSize "0,0,1281,1024"
+viewArea "53418,13863,168802,105975"
+cachedDiagramExtent "-92000,0,168750,98000"
 pageSetupInfo (PageSetupInfo
 ptrCmd ""
@@ -7448,5 +9517,5 @@
 hasePageBreakOrigin 1
 pageBreakOrigin "-146000,0"
-lastUid 2804,0
+lastUid 3294,0
 defaultCommentText (CommentText
 shape (Rectangle
@@ -7463,5 +9532,5 @@
 fg "0,0,32768"
 )
-xt "200,200,2400,1200"
+xt "200,200,2000,1200"
 st "
 Text
@@ -7510,5 +9579,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*244 (Text
+*304 (Text
 va (VaSet
 font "Arial,8,1"
@@ -7519,5 +9588,5 @@
 tm "BdLibraryNameMgr"
 )
-*245 (Text
+*305 (Text
 va (VaSet
 font "Arial,8,1"
@@ -7528,5 +9597,5 @@
 tm "BlkNameMgr"
 )
-*246 (Text
+*306 (Text
 va (VaSet
 font "Arial,8,1"
@@ -7579,5 +9648,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*247 (Text
+*307 (Text
 va (VaSet
 font "Arial,8,1"
@@ -7587,5 +9656,5 @@
 blo "550,4300"
 )
-*248 (Text
+*308 (Text
 va (VaSet
 font "Arial,8,1"
@@ -7595,5 +9664,5 @@
 blo "550,5300"
 )
-*249 (Text
+*309 (Text
 va (VaSet
 font "Arial,8,1"
@@ -7644,5 +9713,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*250 (Text
+*310 (Text
 va (VaSet
 font "Arial,8,1"
@@ -7653,5 +9722,5 @@
 tm "BdLibraryNameMgr"
 )
-*251 (Text
+*311 (Text
 va (VaSet
 font "Arial,8,1"
@@ -7662,5 +9731,5 @@
 tm "CptNameMgr"
 )
-*252 (Text
+*312 (Text
 va (VaSet
 font "Arial,8,1"
@@ -7716,5 +9785,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*253 (Text
+*313 (Text
 va (VaSet
 font "Arial,8,1"
@@ -7724,5 +9793,5 @@
 blo "500,4300"
 )
-*254 (Text
+*314 (Text
 va (VaSet
 font "Arial,8,1"
@@ -7732,5 +9801,5 @@
 blo "500,5300"
 )
-*255 (Text
+*315 (Text
 va (VaSet
 font "Arial,8,1"
@@ -7777,5 +9846,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*256 (Text
+*316 (Text
 va (VaSet
 font "Arial,8,1"
@@ -7785,5 +9854,5 @@
 blo "50,4300"
 )
-*257 (Text
+*317 (Text
 va (VaSet
 font "Arial,8,1"
@@ -7793,5 +9862,5 @@
 blo "50,5300"
 )
-*258 (Text
+*318 (Text
 va (VaSet
 font "Arial,8,1"
@@ -7834,5 +9903,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*259 (Text
+*319 (Text
 va (VaSet
 font "Arial,8,1"
@@ -7843,5 +9912,5 @@
 tm "HdlTextNameMgr"
 )
-*260 (Text
+*320 (Text
 va (VaSet
 font "Arial,8,1"
@@ -7881,5 +9950,5 @@
 va (VaSet
 )
-xt "200,200,2400,1200"
+xt "200,200,2000,1200"
 st "
 Text
@@ -8219,5 +10288,5 @@
 va (VaSet
 )
-xt "0,-1100,12900,-100"
+xt "0,-1100,12600,-100"
 st "g0: FOR i IN 0 TO n GENERATE"
 tm "FrameTitleTextMgr"
@@ -8246,5 +10315,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*261 (Text
+*321 (Text
 va (VaSet
 font "Arial,8,1"
@@ -8254,5 +10323,5 @@
 blo "14100,20800"
 )
-*262 (MLText
+*322 (MLText
 va (VaSet
 )
@@ -8279,5 +10348,5 @@
 va (VaSet
 )
-xt "0,-1100,7700,-100"
+xt "0,-1100,7400,-100"
 st "b0: BLOCK (guard)"
 tm "FrameTitleTextMgr"
@@ -8306,5 +10375,5 @@
 stg "VerticalLayoutStrategy"
 textVec [
-*263 (Text
+*323 (Text
 va (VaSet
 font "Arial,8,1"
@@ -8314,5 +10383,5 @@
 blo "14100,20800"
 )
-*264 (MLText
+*324 (MLText
 va (VaSet
 )
@@ -8458,44 +10527,44 @@
 commonDM (CommonDM
 ldm (LogicalDM
-suid 62,0
+suid 64,0
 usingSuid 1
-emptyRow *265 (LEmptyRow
+emptyRow *325 (LEmptyRow
 )
 uid 54,0
 optionalChildren [
-*266 (RefLabelRowHdr
-)
-*267 (TitleRowHdr
-)
-*268 (FilterRowHdr
-)
-*269 (RefLabelColHdr
+*326 (RefLabelRowHdr
+)
+*327 (TitleRowHdr
+)
+*328 (FilterRowHdr
+)
+*329 (RefLabelColHdr
 tm "RefLabelColHdrMgr"
 )
-*270 (RowExpandColHdr
+*330 (RowExpandColHdr
 tm "RowExpandColHdrMgr"
 )
-*271 (GroupColHdr
+*331 (GroupColHdr
 tm "GroupColHdrMgr"
 )
-*272 (NameColHdr
+*332 (NameColHdr
 tm "BlockDiagramNameColHdrMgr"
 )
-*273 (ModeColHdr
+*333 (ModeColHdr
 tm "BlockDiagramModeColHdrMgr"
 )
-*274 (TypeColHdr
+*334 (TypeColHdr
 tm "BlockDiagramTypeColHdrMgr"
 )
-*275 (BoundsColHdr
+*335 (BoundsColHdr
 tm "BlockDiagramBoundsColHdrMgr"
 )
-*276 (InitColHdr
+*336 (InitColHdr
 tm "BlockDiagramInitColHdrMgr"
 )
-*277 (EolColHdr
+*337 (EolColHdr
 tm "BlockDiagramEolColHdrMgr"
 )
-*278 (LeafLogPort
+*338 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8511,5 +10580,5 @@
 uid 340,0
 )
-*279 (LeafLogPort
+*339 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8524,5 +10593,5 @@
 uid 342,0
 )
-*280 (LeafLogPort
+*340 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8537,5 +10606,5 @@
 uid 344,0
 )
-*281 (LeafLogPort
+*341 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8550,5 +10619,5 @@
 uid 346,0
 )
-*282 (LeafLogPort
+*342 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8563,5 +10632,5 @@
 uid 348,0
 )
-*283 (LeafLogPort
+*343 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8576,5 +10645,5 @@
 uid 404,0
 )
-*284 (LeafLogPort
+*344 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8588,5 +10657,5 @@
 uid 406,0
 )
-*285 (LeafLogPort
+*345 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8602,5 +10671,5 @@
 uid 408,0
 )
-*286 (LeafLogPort
+*346 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8616,5 +10685,5 @@
 uid 456,0
 )
-*287 (LeafLogPort
+*347 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8631,5 +10700,5 @@
 uid 458,0
 )
-*288 (LeafLogPort
+*348 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8644,5 +10713,5 @@
 uid 460,0
 )
-*289 (LeafLogPort
+*349 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8657,5 +10726,5 @@
 uid 584,0
 )
-*290 (LeafLogPort
+*350 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8669,5 +10738,5 @@
 uid 586,0
 )
-*291 (LeafLogPort
+*351 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8683,5 +10752,5 @@
 uid 588,0
 )
-*292 (LeafLogPort
+*352 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8697,5 +10766,5 @@
 uid 590,0
 )
-*293 (LeafLogPort
+*353 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8712,5 +10781,5 @@
 uid 592,0
 )
-*294 (LeafLogPort
+*354 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8725,5 +10794,5 @@
 uid 903,0
 )
-*295 (LeafLogPort
+*355 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8740,5 +10809,5 @@
 uid 905,0
 )
-*296 (LeafLogPort
+*356 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8753,5 +10822,5 @@
 uid 907,0
 )
-*297 (LeafLogPort
+*357 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8765,5 +10834,5 @@
 uid 909,0
 )
-*298 (LeafLogPort
+*358 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8777,5 +10846,5 @@
 uid 911,0
 )
-*299 (LeafLogPort
+*359 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8790,5 +10859,5 @@
 uid 913,0
 )
-*300 (LeafLogPort
+*360 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8805,5 +10874,5 @@
 uid 915,0
 )
-*301 (LeafLogPort
+*361 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8817,5 +10886,5 @@
 uid 917,0
 )
-*302 (LeafLogPort
+*362 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8829,5 +10898,5 @@
 uid 919,0
 )
-*303 (LeafLogPort
+*363 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8843,5 +10912,5 @@
 uid 921,0
 )
-*304 (LeafLogPort
+*364 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8856,5 +10925,5 @@
 uid 923,0
 )
-*305 (LeafLogPort
+*365 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8869,5 +10938,5 @@
 uid 925,0
 )
-*306 (LeafLogPort
+*366 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8882,5 +10951,5 @@
 uid 927,0
 )
-*307 (LeafLogPort
+*367 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8894,5 +10963,5 @@
 uid 929,0
 )
-*308 (LeafLogPort
+*368 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8906,5 +10975,5 @@
 uid 931,0
 )
-*309 (LeafLogPort
+*369 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8918,5 +10987,5 @@
 uid 933,0
 )
-*310 (LeafLogPort
+*370 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8930,5 +10999,5 @@
 uid 935,0
 )
-*311 (LeafLogPort
+*371 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8943,5 +11012,5 @@
 uid 1541,0
 )
-*312 (LeafLogPort
+*372 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8955,5 +11024,5 @@
 uid 1543,0
 )
-*313 (LeafLogPort
+*373 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8967,5 +11036,5 @@
 uid 1545,0
 )
-*314 (LeafLogPort
+*374 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8979,5 +11048,5 @@
 uid 1547,0
 )
-*315 (LeafLogPort
+*375 (LeafLogPort
 port (LogicalPort
 m 4
@@ -8992,5 +11061,5 @@
 uid 1549,0
 )
-*316 (LeafLogPort
+*376 (LeafLogPort
 port (LogicalPort
 m 4
@@ -9005,5 +11074,5 @@
 uid 1551,0
 )
-*317 (LeafLogPort
+*377 (LeafLogPort
 port (LogicalPort
 m 4
@@ -9017,5 +11086,5 @@
 uid 1553,0
 )
-*318 (LeafLogPort
+*378 (LeafLogPort
 port (LogicalPort
 m 4
@@ -9030,5 +11099,5 @@
 uid 1555,0
 )
-*319 (LeafLogPort
+*379 (LeafLogPort
 port (LogicalPort
 m 4
@@ -9044,5 +11113,5 @@
 uid 1575,0
 )
-*320 (LeafLogPort
+*380 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -9057,5 +11126,5 @@
 uid 1690,0
 )
-*321 (LeafLogPort
+*381 (LeafLogPort
 port (LogicalPort
 m 4
@@ -9070,5 +11139,5 @@
 uid 2003,0
 )
-*322 (LeafLogPort
+*382 (LeafLogPort
 port (LogicalPort
 m 4
@@ -9082,5 +11151,5 @@
 uid 2785,0
 )
-*323 (LeafLogPort
+*383 (LeafLogPort
 port (LogicalPort
 m 4
@@ -9094,5 +11163,5 @@
 uid 2787,0
 )
-*324 (LeafLogPort
+*384 (LeafLogPort
 port (LogicalPort
 m 4
@@ -9109,5 +11178,5 @@
 uid 2789,0
 )
-*325 (LeafLogPort
+*385 (LeafLogPort
 port (LogicalPort
 m 4
@@ -9121,5 +11190,5 @@
 uid 2791,0
 )
-*326 (LeafLogPort
+*386 (LeafLogPort
 port (LogicalPort
 m 4
@@ -9133,5 +11202,5 @@
 uid 2793,0
 )
-*327 (LeafLogPort
+*387 (LeafLogPort
 port (LogicalPort
 m 4
@@ -9145,5 +11214,5 @@
 uid 2795,0
 )
-*328 (LeafLogPort
+*388 (LeafLogPort
 port (LogicalPort
 lang 2
@@ -9161,5 +11230,5 @@
 uid 2797,0
 )
-*329 (LeafLogPort
+*389 (LeafLogPort
 port (LogicalPort
 m 4
@@ -9174,5 +11243,5 @@
 uid 2799,0
 )
-*330 (LeafLogPort
+*390 (LeafLogPort
 port (LogicalPort
 m 4
@@ -9189,5 +11258,5 @@
 uid 2801,0
 )
-*331 (LeafLogPort
+*391 (LeafLogPort
 port (LogicalPort
 m 4
@@ -9200,4 +11269,19 @@
 )
 uid 2803,0
+)
+*392 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "socket_tx_free_out"
+t "std_logic_vector"
+b "(16 DOWNTO 0)"
+eolc "-- 17bit value .. that's true"
+posAdd 0
+o 55
+suid 64,0
+)
+)
+uid 2950,0
 )
 ]
@@ -9208,5 +11292,5 @@
 uid 67,0
 optionalChildren [
-*332 (Sheet
+*393 (Sheet
 sheetRow (SheetRow
 headerVa (MVa
@@ -9225,25 +11309,25 @@
 font "Tahoma,10,0"
 )
-emptyMRCItem *333 (MRCItem
-litem &265
-pos 54
+emptyMRCItem *394 (MRCItem
+litem &325
+pos 55
 dimension 20
 )
 uid 69,0
 optionalChildren [
-*334 (MRCItem
-litem &266
+*395 (MRCItem
+litem &326
 pos 0
 dimension 20
 uid 70,0
 )
-*335 (MRCItem
-litem &267
+*396 (MRCItem
+litem &327
 pos 1
 dimension 23
 uid 71,0
 )
-*336 (MRCItem
-litem &268
+*397 (MRCItem
+litem &328
 pos 2
 hidden 1
@@ -9251,327 +11335,333 @@
 uid 72,0
 )
-*337 (MRCItem
-litem &278
+*398 (MRCItem
+litem &338
 pos 0
 dimension 20
 uid 341,0
 )
-*338 (MRCItem
-litem &279
+*399 (MRCItem
+litem &339
 pos 1
 dimension 20
 uid 343,0
 )
-*339 (MRCItem
-litem &280
+*400 (MRCItem
+litem &340
 pos 2
 dimension 20
 uid 345,0
 )
-*340 (MRCItem
-litem &281
+*401 (MRCItem
+litem &341
 pos 3
 dimension 20
 uid 347,0
 )
-*341 (MRCItem
-litem &282
+*402 (MRCItem
+litem &342
 pos 4
 dimension 20
 uid 349,0
 )
-*342 (MRCItem
-litem &283
+*403 (MRCItem
+litem &343
 pos 5
 dimension 20
 uid 405,0
 )
-*343 (MRCItem
-litem &284
+*404 (MRCItem
+litem &344
 pos 6
 dimension 20
 uid 407,0
 )
-*344 (MRCItem
-litem &285
+*405 (MRCItem
+litem &345
 pos 7
 dimension 20
 uid 409,0
 )
-*345 (MRCItem
-litem &286
+*406 (MRCItem
+litem &346
 pos 8
 dimension 20
 uid 457,0
 )
-*346 (MRCItem
-litem &287
+*407 (MRCItem
+litem &347
 pos 9
 dimension 20
 uid 459,0
 )
-*347 (MRCItem
-litem &288
+*408 (MRCItem
+litem &348
 pos 10
 dimension 20
 uid 461,0
 )
-*348 (MRCItem
-litem &289
+*409 (MRCItem
+litem &349
 pos 11
 dimension 20
 uid 585,0
 )
-*349 (MRCItem
-litem &290
+*410 (MRCItem
+litem &350
 pos 12
 dimension 20
 uid 587,0
 )
-*350 (MRCItem
-litem &291
+*411 (MRCItem
+litem &351
 pos 13
 dimension 20
 uid 589,0
 )
-*351 (MRCItem
-litem &292
+*412 (MRCItem
+litem &352
 pos 14
 dimension 20
 uid 591,0
 )
-*352 (MRCItem
-litem &293
+*413 (MRCItem
+litem &353
 pos 15
 dimension 20
 uid 593,0
 )
-*353 (MRCItem
-litem &294
+*414 (MRCItem
+litem &354
 pos 16
 dimension 20
 uid 904,0
 )
-*354 (MRCItem
-litem &295
+*415 (MRCItem
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 pos 17
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 pos 18
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 dimension 20
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 dimension 20
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 dimension 20
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 dimension 20
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 dimension 20
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 pos 51
 dimension 20
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 pos 52
 dimension 20
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 pos 53
 dimension 20
 uid 2804,0
+)
+*452 (MRCItem
+litem &392
+pos 54
+dimension 20
+uid 2951,0
 )
 ]
@@ -9586,48 +11676,48 @@
 uid 73,0
 optionalChildren [
-*391 (MRCItem
-litem &269
+*453 (MRCItem
+litem &329
 pos 0
 dimension 20
 uid 74,0
 )
-*392 (MRCItem
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 pos 1
 dimension 50
 uid 75,0
 )
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 pos 2
 dimension 100
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 pos 3
 dimension 50
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 pos 4
 dimension 100
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 pos 5
 dimension 100
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 pos 6
 dimension 50
 uid 80,0
 )
-*398 (MRCItem
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+*460 (MRCItem
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 pos 7
 dimension 80
@@ -9649,36 +11739,36 @@
 genericsCommonDM (CommonDM
 ldm (LogicalDM
-emptyRow *399 (LEmptyRow
+emptyRow *461 (LEmptyRow
 )
 uid 83,0
 optionalChildren [
-*400 (RefLabelRowHdr
-)
-*401 (TitleRowHdr
-)
-*402 (FilterRowHdr
-)
-*403 (RefLabelColHdr
+*462 (RefLabelRowHdr
+)
+*463 (TitleRowHdr
+)
+*464 (FilterRowHdr
+)
+*465 (RefLabelColHdr
 tm "RefLabelColHdrMgr"
 )
-*404 (RowExpandColHdr
+*466 (RowExpandColHdr
 tm "RowExpandColHdrMgr"
 )
-*405 (GroupColHdr
+*467 (GroupColHdr
 tm "GroupColHdrMgr"
 )
-*406 (NameColHdr
+*468 (NameColHdr
 tm "GenericNameColHdrMgr"
 )
-*407 (TypeColHdr
+*469 (TypeColHdr
 tm "GenericTypeColHdrMgr"
 )
-*408 (InitColHdr
+*470 (InitColHdr
 tm "GenericValueColHdrMgr"
 )
-*409 (PragmaColHdr
+*471 (PragmaColHdr
 tm "GenericPragmaColHdrMgr"
 )
-*410 (EolColHdr
+*472 (EolColHdr
 tm "GenericEolColHdrMgr"
 )
@@ -9690,5 +11780,5 @@
 uid 95,0
 optionalChildren [
-*411 (Sheet
+*473 (Sheet
 sheetRow (SheetRow
 headerVa (MVa
@@ -9707,6 +11797,6 @@
 font "Tahoma,10,0"
 )
-emptyMRCItem *412 (MRCItem
-litem &399
+emptyMRCItem *474 (MRCItem
+litem &461
 pos 0
 dimension 20
@@ -9714,18 +11804,18 @@
 uid 97,0
 optionalChildren [
-*413 (MRCItem
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 pos 0
 dimension 20
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 )
-*414 (MRCItem
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 pos 1
 dimension 23
 uid 99,0
 )
-*415 (MRCItem
-litem &402
+*477 (MRCItem
+litem &464
 pos 2
 hidden 1
@@ -9744,42 +11834,42 @@
 uid 101,0
 optionalChildren [
-*416 (MRCItem
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 pos 0
 dimension 20
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 )
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 pos 1
 dimension 50
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 )
-*418 (MRCItem
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 pos 2
 dimension 100
 uid 104,0
 )
-*419 (MRCItem
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 pos 3
 dimension 100
 uid 105,0
 )
-*420 (MRCItem
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 pos 4
 dimension 50
 uid 106,0
 )
-*421 (MRCItem
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 pos 5
 dimension 50
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 )
-*422 (MRCItem
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 pos 6
 dimension 80
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/w5300_interface_tb/struct.bd
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/w5300_interface_tb/struct.bd	(revision 10914)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/w5300_interface_tb/struct.bd	(revision 10914)
@@ -0,0 +1,4470 @@
+DocumentHdrVersion "1.1"
+Header (DocumentHdr
+version 2
+dmPackageRefs [
+(DmPackageRef
+library "IEEE"
+unitName "STD_LOGIC_1164"
+itemName "ALL"
+)
+(DmPackageRef
+library "IEEE"
+unitName "NUMERIC_STD"
+itemName "ALL"
+)
+(DmPackageRef
+library "ieee"
+unitName "std_logic_unsigned"
+)
+]
+instances [
+(Instance
+name "Inst_W5300_Interface"
+duLibraryName "FACT_FAD_lib"
+duName "w5300_interface"
+elements [
+]
+mwi 0
+uid 65,0
+)
+(Instance
+name "U_1"
+duLibraryName "FACT_FAD_TB_lib"
+duName "w5300_interface_tester"
+elements [
+]
+mwi 0
+uid 179,0
+)
+(Instance
+name "U_2"
+duLibraryName "FACT_FAD_TB_lib"
+duName "clock_generator"
+elements [
+(GiElement
+name "clock_period"
+type "time"
+value "20 ns"
+)
+(GiElement
+name "reset_time"
+type "time"
+value "50 ns"
+)
+]
+mwi 0
+uid 617,0
+)
+]
+libraryRefs [
+"IEEE"
+]
+)
+version "29.1"
+appVersion "2009.2 (Build 10)"
+noEmbeddedEditors 1
+model (BlockDiag
+VExpander (VariableExpander
+vvMap [
+(vvPair
+variable "HDLDir"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
+)
+(vvPair
+variable "HDSDir"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
+)
+(vvPair
+variable "SideDataDesignDir"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_interface_tb\\struct.bd.info"
+)
+(vvPair
+variable "SideDataUserDir"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_interface_tb\\struct.bd.user"
+)
+(vvPair
+variable "SourceDir"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
+)
+(vvPair
+variable "appl"
+value "HDL Designer"
+)
+(vvPair
+variable "arch_name"
+value "struct"
+)
+(vvPair
+variable "config"
+value "%(unit)_%(view)_config"
+)
+(vvPair
+variable "d"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_interface_tb"
+)
+(vvPair
+variable "d_logical"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_interface_tb"
+)
+(vvPair
+variable "date"
+value "31.05.2011"
+)
+(vvPair
+variable "day"
+value "Di"
+)
+(vvPair
+variable "day_long"
+value "Dienstag"
+)
+(vvPair
+variable "dd"
+value "31"
+)
+(vvPair
+variable "entity_name"
+value "w5300_interface_tb"
+)
+(vvPair
+variable "ext"
+value "<TBD>"
+)
+(vvPair
+variable "f"
+value "struct.bd"
+)
+(vvPair
+variable "f_logical"
+value "struct.bd"
+)
+(vvPair
+variable "f_noext"
+value "struct"
+)
+(vvPair
+variable "group"
+value "UNKNOWN"
+)
+(vvPair
+variable "host"
+value "E5B-LABOR6"
+)
+(vvPair
+variable "language"
+value "VHDL"
+)
+(vvPair
+variable "library"
+value "FACT_FAD_TB_lib"
+)
+(vvPair
+variable "library_downstream_HdsLintPlugin"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/designcheck"
+)
+(vvPair
+variable "library_downstream_ISEPARInvoke"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
+)
+(vvPair
+variable "library_downstream_ImpactInvoke"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
+)
+(vvPair
+variable "library_downstream_ModelSimCompiler"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/work"
+)
+(vvPair
+variable "library_downstream_XSTDataPrep"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
+)
+(vvPair
+variable "mm"
+value "05"
+)
+(vvPair
+variable "module_name"
+value "w5300_interface_tb"
+)
+(vvPair
+variable "month"
+value "Mai"
+)
+(vvPair
+variable "month_long"
+value "Mai"
+)
+(vvPair
+variable "p"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_interface_tb\\struct.bd"
+)
+(vvPair
+variable "p_logical"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_interface_tb\\struct.bd"
+)
+(vvPair
+variable "package_name"
+value "<Undefined Variable>"
+)
+(vvPair
+variable "project_name"
+value "FACT_FAD"
+)
+(vvPair
+variable "series"
+value "HDL Designer Series"
+)
+(vvPair
+variable "task_DesignCompilerPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_LeonardoPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_ModelSimPath"
+value "C:\\modeltech_6.6a\\win32"
+)
+(vvPair
+variable "task_NC-SimPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_PrecisionRTLPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_QuestaSimPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_VCSPath"
+value "<TBD>"
+)
+(vvPair
+variable "this_ext"
+value "bd"
+)
+(vvPair
+variable "this_file"
+value "struct"
+)
+(vvPair
+variable "this_file_logical"
+value "struct"
+)
+(vvPair
+variable "time"
+value "13:38:18"
+)
+(vvPair
+variable "unit"
+value "w5300_interface_tb"
+)
+(vvPair
+variable "user"
+value "dneise"
+)
+(vvPair
+variable "version"
+value "2009.2 (Build 10)"
+)
+(vvPair
+variable "view"
+value "struct"
+)
+(vvPair
+variable "year"
+value "2011"
+)
+(vvPair
+variable "yy"
+value "11"
+)
+]
+)
+LanguageMgr "VhdlLangMgr"
+uid 362,0
+optionalChildren [
+*1 (SaComponent
+uid 65,0
+optionalChildren [
+*2 (CptPort
+uid 13,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 14,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,20625,0,21375"
+)
+tg (CPTG
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+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 16,0
+va (VaSet
+)
+xt "1000,20500,2300,21500"
+st "clk"
+blo "1000,21300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "clk"
+t "std_logic"
+o 1
+)
+)
+)
+*3 (CptPort
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+uid 18,0
+ro 90
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+)
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+)
+tg (CPTG
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+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 20,0
+va (VaSet
+)
+xt "10400,20500,14000,21500"
+st "wiz_reset"
+ju 2
+blo "14000,21300"
+)
+)
+thePort (LogicalPort
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+t "std_logic"
+o 2
+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+blo "14000,23300"
+)
+)
+thePort (LogicalPort
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+t "std_logic"
+o 4
+)
+)
+)
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+ps "OnEdgeStrategy"
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+ro 90
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+)
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+)
+tg (CPTG
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+f (Text
+uid 32,0
+va (VaSet
+)
+xt "12900,23500,14000,24500"
+st "rd"
+ju 2
+blo "14000,24300"
+)
+)
+thePort (LogicalPort
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+decl (Decl
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+t "std_logic"
+o 5
+)
+)
+)
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+ro 90
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+)
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+)
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+f (Text
+uid 36,0
+va (VaSet
+)
+xt "1000,21500,2200,22500"
+st "int"
+blo "1000,22300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "int"
+t "std_logic"
+o 6
+)
+)
+)
+*8 (CptPort
+uid 37,0
+ps "OnEdgeStrategy"
+shape (Diamond
+uid 38,0
+ro 90
+va (VaSet
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+fg "0,65535,0"
+)
+xt "15000,24625,15750,25375"
+)
+tg (CPTG
+uid 39,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 40,0
+va (VaSet
+)
+xt "7700,24500,14000,25500"
+st "wiz_data : (15:0)"
+ju 2
+blo "14000,25300"
+)
+)
+thePort (LogicalPort
+m 2
+decl (Decl
+n "wiz_data"
+t "std_logic_vector"
+b "(15 DOWNTO 0)"
+o 7
+)
+)
+)
+*9 (CptPort
+uid 41,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 42,0
+ro 90
+va (VaSet
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+)
+xt "15000,25625,15750,26375"
+)
+tg (CPTG
+uid 43,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 44,0
+va (VaSet
+)
+xt "8000,25500,14000,26500"
+st "wiz_addr : (9:0)"
+ju 2
+blo "14000,26300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "wiz_addr"
+t "std_logic_vector"
+b "(9 DOWNTO 0)"
+o 8
+)
+)
+)
+*10 (CptPort
+uid 45,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 46,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,22625,0,23375"
+)
+tg (CPTG
+uid 47,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 48,0
+va (VaSet
+)
+xt "1000,22500,3500,23500"
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+)
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/w5300_interface_tb/struct.bd.bak
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/w5300_interface_tb/struct.bd.bak	(revision 10914)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/w5300_interface_tb/struct.bd.bak	(revision 10914)
@@ -0,0 +1,4470 @@
+DocumentHdrVersion "1.1"
+Header (DocumentHdr
+version 2
+dmPackageRefs [
+(DmPackageRef
+library "IEEE"
+unitName "STD_LOGIC_1164"
+itemName "ALL"
+)
+(DmPackageRef
+library "IEEE"
+unitName "NUMERIC_STD"
+itemName "ALL"
+)
+(DmPackageRef
+library "ieee"
+unitName "std_logic_unsigned"
+)
+]
+instances [
+(Instance
+name "Inst_W5300_Interface"
+duLibraryName "FACT_FAD_lib"
+duName "w5300_interface"
+elements [
+]
+mwi 0
+uid 65,0
+)
+(Instance
+name "U_1"
+duLibraryName "FACT_FAD_TB_lib"
+duName "w5300_interface_tester"
+elements [
+]
+mwi 0
+uid 179,0
+)
+(Instance
+name "U_2"
+duLibraryName "FACT_FAD_TB_lib"
+duName "clock_generator"
+elements [
+(GiElement
+name "clock_period"
+type "time"
+value "20 ns"
+)
+(GiElement
+name "reset_time"
+type "time"
+value "50 ns"
+)
+]
+mwi 0
+uid 617,0
+)
+]
+libraryRefs [
+"IEEE"
+]
+)
+version "29.1"
+appVersion "2009.2 (Build 10)"
+noEmbeddedEditors 1
+model (BlockDiag
+VExpander (VariableExpander
+vvMap [
+(vvPair
+variable "HDLDir"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
+)
+(vvPair
+variable "HDSDir"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
+)
+(vvPair
+variable "SideDataDesignDir"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_interface_tb\\struct.bd.info"
+)
+(vvPair
+variable "SideDataUserDir"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_interface_tb\\struct.bd.user"
+)
+(vvPair
+variable "SourceDir"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
+)
+(vvPair
+variable "appl"
+value "HDL Designer"
+)
+(vvPair
+variable "arch_name"
+value "struct"
+)
+(vvPair
+variable "config"
+value "%(unit)_%(view)_config"
+)
+(vvPair
+variable "d"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_interface_tb"
+)
+(vvPair
+variable "d_logical"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_interface_tb"
+)
+(vvPair
+variable "date"
+value "31.05.2011"
+)
+(vvPair
+variable "day"
+value "Di"
+)
+(vvPair
+variable "day_long"
+value "Dienstag"
+)
+(vvPair
+variable "dd"
+value "31"
+)
+(vvPair
+variable "entity_name"
+value "w5300_interface_tb"
+)
+(vvPair
+variable "ext"
+value "<TBD>"
+)
+(vvPair
+variable "f"
+value "struct.bd"
+)
+(vvPair
+variable "f_logical"
+value "struct.bd"
+)
+(vvPair
+variable "f_noext"
+value "struct"
+)
+(vvPair
+variable "group"
+value "UNKNOWN"
+)
+(vvPair
+variable "host"
+value "E5B-LABOR6"
+)
+(vvPair
+variable "language"
+value "VHDL"
+)
+(vvPair
+variable "library"
+value "FACT_FAD_TB_lib"
+)
+(vvPair
+variable "library_downstream_HdsLintPlugin"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/designcheck"
+)
+(vvPair
+variable "library_downstream_ISEPARInvoke"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
+)
+(vvPair
+variable "library_downstream_ImpactInvoke"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
+)
+(vvPair
+variable "library_downstream_ModelSimCompiler"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/work"
+)
+(vvPair
+variable "library_downstream_XSTDataPrep"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
+)
+(vvPair
+variable "mm"
+value "05"
+)
+(vvPair
+variable "module_name"
+value "w5300_interface_tb"
+)
+(vvPair
+variable "month"
+value "Mai"
+)
+(vvPair
+variable "month_long"
+value "Mai"
+)
+(vvPair
+variable "p"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_interface_tb\\struct.bd"
+)
+(vvPair
+variable "p_logical"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_interface_tb\\struct.bd"
+)
+(vvPair
+variable "package_name"
+value "<Undefined Variable>"
+)
+(vvPair
+variable "project_name"
+value "FACT_FAD"
+)
+(vvPair
+variable "series"
+value "HDL Designer Series"
+)
+(vvPair
+variable "task_DesignCompilerPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_LeonardoPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_ModelSimPath"
+value "C:\\modeltech_6.6a\\win32"
+)
+(vvPair
+variable "task_NC-SimPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_PrecisionRTLPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_QuestaSimPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_VCSPath"
+value "<TBD>"
+)
+(vvPair
+variable "this_ext"
+value "bd"
+)
+(vvPair
+variable "this_file"
+value "struct"
+)
+(vvPair
+variable "this_file_logical"
+value "struct"
+)
+(vvPair
+variable "time"
+value "13:38:11"
+)
+(vvPair
+variable "unit"
+value "w5300_interface_tb"
+)
+(vvPair
+variable "user"
+value "dneise"
+)
+(vvPair
+variable "version"
+value "2009.2 (Build 10)"
+)
+(vvPair
+variable "view"
+value "struct"
+)
+(vvPair
+variable "year"
+value "2011"
+)
+(vvPair
+variable "yy"
+value "11"
+)
+]
+)
+LanguageMgr "VhdlLangMgr"
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+)
+)
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+)
+)
+)
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+xt "10400,20500,14000,21500"
+st "wiz_reset"
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+blo "14000,21300"
+)
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+thePort (LogicalPort
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+)
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+)
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+)
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+)
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+)
+)
+thePort (LogicalPort
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+)
+)
+)
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+)
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+)
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Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/w5300_interface_tb/symbol.sb
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/w5300_interface_tb/symbol.sb	(revision 10914)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/w5300_interface_tb/symbol.sb	(revision 10914)
@@ -0,0 +1,1235 @@
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Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/w5300_interface_tb/symbol.sb.bak
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/w5300_interface_tb/symbol.sb.bak	(revision 10914)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/w5300_interface_tb/symbol.sb.bak	(revision 10914)
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Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/w5300_interface_tester/interface
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/w5300_interface_tester/interface	(revision 10914)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/w5300_interface_tester/interface	(revision 10914)
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+)
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+)
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+)
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+)
+(vvPair
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+)
+(vvPair
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+)
+(vvPair
+variable "SideDataUserDir"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_interface_tester\\interface.user"
+)
+(vvPair
+variable "SourceDir"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
+)
+(vvPair
+variable "appl"
+value "HDL Designer"
+)
+(vvPair
+variable "arch_name"
+value "interface"
+)
+(vvPair
+variable "config"
+value "%(unit)_%(view)_config"
+)
+(vvPair
+variable "d"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_interface_tester"
+)
+(vvPair
+variable "d_logical"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_interface_tester"
+)
+(vvPair
+variable "date"
+value "31.05.2011"
+)
+(vvPair
+variable "day"
+value "Di"
+)
+(vvPair
+variable "day_long"
+value "Dienstag"
+)
+(vvPair
+variable "dd"
+value "31"
+)
+(vvPair
+variable "entity_name"
+value "w5300_interface_tester"
+)
+(vvPair
+variable "ext"
+value "<TBD>"
+)
+(vvPair
+variable "f"
+value "interface"
+)
+(vvPair
+variable "f_logical"
+value "interface"
+)
+(vvPair
+variable "f_noext"
+value "interface"
+)
+(vvPair
+variable "group"
+value "UNKNOWN"
+)
+(vvPair
+variable "host"
+value "E5B-LABOR6"
+)
+(vvPair
+variable "language"
+value "VHDL"
+)
+(vvPair
+variable "library"
+value "FACT_FAD_TB_lib"
+)
+(vvPair
+variable "library_downstream_HdsLintPlugin"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/designcheck"
+)
+(vvPair
+variable "library_downstream_ISEPARInvoke"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
+)
+(vvPair
+variable "library_downstream_ImpactInvoke"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
+)
+(vvPair
+variable "library_downstream_ModelSimCompiler"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/work"
+)
+(vvPair
+variable "library_downstream_XSTDataPrep"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
+)
+(vvPair
+variable "mm"
+value "05"
+)
+(vvPair
+variable "module_name"
+value "w5300_interface_tester"
+)
+(vvPair
+variable "month"
+value "Mai"
+)
+(vvPair
+variable "month_long"
+value "Mai"
+)
+(vvPair
+variable "p"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_interface_tester\\interface"
+)
+(vvPair
+variable "p_logical"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_interface_tester\\interface"
+)
+(vvPair
+variable "package_name"
+value "<Undefined Variable>"
+)
+(vvPair
+variable "project_name"
+value "FACT_FAD"
+)
+(vvPair
+variable "series"
+value "HDL Designer Series"
+)
+(vvPair
+variable "task_DesignCompilerPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_LeonardoPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_ModelSimPath"
+value "C:\\modeltech_6.6a\\win32"
+)
+(vvPair
+variable "task_NC-SimPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_PrecisionRTLPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_QuestaSimPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_VCSPath"
+value "<TBD>"
+)
+(vvPair
+variable "this_ext"
+value "<TBD>"
+)
+(vvPair
+variable "this_file"
+value "interface"
+)
+(vvPair
+variable "this_file_logical"
+value "interface"
+)
+(vvPair
+variable "time"
+value "13:38:06"
+)
+(vvPair
+variable "unit"
+value "w5300_interface_tester"
+)
+(vvPair
+variable "user"
+value "dneise"
+)
+(vvPair
+variable "version"
+value "2009.2 (Build 10)"
+)
+(vvPair
+variable "view"
+value "interface"
+)
+(vvPair
+variable "year"
+value "2011"
+)
+(vvPair
+variable "yy"
+value "11"
+)
+]
+)
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+)
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+)
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Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/w5300_modul2_tb/struct.bd
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/w5300_modul2_tb/struct.bd	(revision 10914)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/w5300_modul2_tb/struct.bd	(revision 10914)
@@ -0,0 +1,9396 @@
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+(vvPair
+variable "SourceDir"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
+)
+(vvPair
+variable "appl"
+value "HDL Designer"
+)
+(vvPair
+variable "arch_name"
+value "struct"
+)
+(vvPair
+variable "config"
+value "%(unit)_%(view)_config"
+)
+(vvPair
+variable "d"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tb"
+)
+(vvPair
+variable "d_logical"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tb"
+)
+(vvPair
+variable "date"
+value "01.06.2011"
+)
+(vvPair
+variable "day"
+value "Mi"
+)
+(vvPair
+variable "day_long"
+value "Mittwoch"
+)
+(vvPair
+variable "dd"
+value "01"
+)
+(vvPair
+variable "entity_name"
+value "w5300_modul2_tb"
+)
+(vvPair
+variable "ext"
+value "<TBD>"
+)
+(vvPair
+variable "f"
+value "struct.bd"
+)
+(vvPair
+variable "f_logical"
+value "struct.bd"
+)
+(vvPair
+variable "f_noext"
+value "struct"
+)
+(vvPair
+variable "group"
+value "UNKNOWN"
+)
+(vvPair
+variable "host"
+value "E5B-LABOR6"
+)
+(vvPair
+variable "language"
+value "VHDL"
+)
+(vvPair
+variable "library"
+value "FACT_FAD_TB_lib"
+)
+(vvPair
+variable "library_downstream_HdsLintPlugin"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/designcheck"
+)
+(vvPair
+variable "library_downstream_ISEPARInvoke"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
+)
+(vvPair
+variable "library_downstream_ImpactInvoke"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
+)
+(vvPair
+variable "library_downstream_ModelSimCompiler"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/work"
+)
+(vvPair
+variable "library_downstream_XSTDataPrep"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
+)
+(vvPair
+variable "mm"
+value "06"
+)
+(vvPair
+variable "module_name"
+value "w5300_modul2_tb"
+)
+(vvPair
+variable "month"
+value "Jun"
+)
+(vvPair
+variable "month_long"
+value "Juni"
+)
+(vvPair
+variable "p"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tb\\struct.bd"
+)
+(vvPair
+variable "p_logical"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tb\\struct.bd"
+)
+(vvPair
+variable "package_name"
+value "<Undefined Variable>"
+)
+(vvPair
+variable "project_name"
+value "FACT_FAD"
+)
+(vvPair
+variable "series"
+value "HDL Designer Series"
+)
+(vvPair
+variable "task_DesignCompilerPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_LeonardoPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_ModelSimPath"
+value "C:\\modeltech_6.6a\\win32"
+)
+(vvPair
+variable "task_NC-SimPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_PrecisionRTLPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_QuestaSimPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_VCSPath"
+value "<TBD>"
+)
+(vvPair
+variable "this_ext"
+value "bd"
+)
+(vvPair
+variable "this_file"
+value "struct"
+)
+(vvPair
+variable "this_file_logical"
+value "struct"
+)
+(vvPair
+variable "time"
+value "09:27:27"
+)
+(vvPair
+variable "unit"
+value "w5300_modul2_tb"
+)
+(vvPair
+variable "user"
+value "dneise"
+)
+(vvPair
+variable "version"
+value "2009.2 (Build 10)"
+)
+(vvPair
+variable "view"
+value "struct"
+)
+(vvPair
+variable "year"
+value "2011"
+)
+(vvPair
+variable "yy"
+value "11"
+)
+]
+)
+LanguageMgr "VhdlLangMgr"
+uid 1174,0
+optionalChildren [
+*1 (SaComponent
+uid 211,0
+optionalChildren [
+*2 (CptPort
+uid 11,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 12,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,46625,34750,47375"
+)
+tg (CPTG
+uid 13,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 14,0
+va (VaSet
+)
+xt "28400,46500,33000,47500"
+st "state : (7:0)"
+ju 2
+blo "33000,47300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "state"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+o 1
+)
+)
+)
+*3 (CptPort
+uid 15,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 16,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,47625,34750,48375"
+)
+tg (CPTG
+uid 17,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 18,0
+va (VaSet
+)
+xt "23900,47500,33000,48500"
+st "debug_data_ram_empty"
+ju 2
+blo "33000,48300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "debug_data_ram_empty"
+t "std_logic"
+o 2
+)
+)
+)
+*4 (CptPort
+uid 19,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 20,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,48625,34750,49375"
+)
+tg (CPTG
+uid 21,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 22,0
+va (VaSet
+)
+xt "26400,48500,33000,49500"
+st "debug_data_valid"
+ju 2
+blo "33000,49300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "debug_data_valid"
+t "std_logic"
+o 3
+)
+)
+)
+*5 (CptPort
+uid 23,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 24,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,46625,0,47375"
+)
+tg (CPTG
+uid 25,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 26,0
+va (VaSet
+)
+xt "1000,46500,9500,47500"
+st "data_generator_idle_i"
+blo "1000,47300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "data_generator_idle_i"
+t "std_logic"
+o 4
+)
+)
+)
+*6 (CptPort
+uid 31,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 32,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,47625,0,48375"
+)
+tg (CPTG
+uid 33,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 34,0
+va (VaSet
+)
+xt "1000,47500,2300,48500"
+st "clk"
+blo "1000,48300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "clk"
+t "std_logic"
+o 5
+)
+)
+)
+*7 (CptPort
+uid 35,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 36,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,50625,34750,51375"
+)
+tg (CPTG
+uid 37,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 38,0
+va (VaSet
+)
+xt "29400,50500,33000,51500"
+st "wiz_reset"
+ju 2
+blo "33000,51300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "wiz_reset"
+t "std_logic"
+o 6
+i "'1'"
+)
+)
+)
+*8 (CptPort
+uid 39,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 40,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,51625,34750,52375"
+)
+tg (CPTG
+uid 41,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 42,0
+va (VaSet
+)
+xt "28500,51500,33000,52500"
+st "addr : (9:0)"
+ju 2
+blo "33000,52300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "addr"
+t "std_logic_vector"
+b "(9 DOWNTO 0)"
+o 7
+)
+)
+)
+*9 (CptPort
+uid 43,0
+ps "OnEdgeStrategy"
+shape (Diamond
+uid 44,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,52625,34750,53375"
+)
+tg (CPTG
+uid 45,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 46,0
+va (VaSet
+)
+xt "28200,52500,33000,53500"
+st "data : (15:0)"
+ju 2
+blo "33000,53300"
+)
+)
+thePort (LogicalPort
+m 2
+decl (Decl
+n "data"
+t "std_logic_vector"
+b "(15 DOWNTO 0)"
+o 8
+)
+)
+)
+*10 (CptPort
+uid 47,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 48,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,53625,34750,54375"
+)
+tg (CPTG
+uid 49,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 50,0
+va (VaSet
+)
+xt "31800,53500,33000,54500"
+st "cs"
+ju 2
+blo "33000,54300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "cs"
+t "std_logic"
+o 9
+i "'1'"
+)
+)
+)
+*11 (CptPort
+uid 51,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 52,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,54625,34750,55375"
+)
+tg (CPTG
+uid 53,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 54,0
+va (VaSet
+)
+xt "31800,54500,33000,55500"
+st "wr"
+ju 2
+blo "33000,55300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "wr"
+t "std_logic"
+o 10
+i "'1'"
+)
+)
+)
+*12 (CptPort
+uid 55,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 56,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,55625,34750,56375"
+)
+tg (CPTG
+uid 57,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 58,0
+va (VaSet
+)
+xt "31900,55500,33000,56500"
+st "rd"
+ju 2
+blo "33000,56300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "rd"
+t "std_logic"
+o 11
+i "'1'"
+)
+)
+)
+*13 (CptPort
+uid 63,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 64,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,48625,0,49375"
+)
+tg (CPTG
+uid 65,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 66,0
+va (VaSet
+)
+xt "1000,48500,2200,49500"
+st "int"
+blo "1000,49300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "int"
+t "std_logic"
+o 12
+)
+)
+)
+*14 (CptPort
+uid 67,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 68,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,49625,0,50375"
+)
+tg (CPTG
+uid 69,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 70,0
+va (VaSet
+)
+xt "1000,49500,8900,50500"
+st "write_length : (16:0)"
+blo "1000,50300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "write_length"
+t "std_logic_vector"
+b "(16 DOWNTO 0)"
+o 13
+)
+)
+)
+*15 (CptPort
+uid 71,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 72,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,50625,0,51375"
+)
+tg (CPTG
+uid 73,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 74,0
+va (VaSet
+)
+xt "1000,50500,20400,51500"
+st "ram_start_addr : (W5300_RAM_ADDR_WIDTH-1:0)"
+blo "1000,51300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ram_start_addr"
+t "std_logic_vector"
+b "(W5300_RAM_ADDR_WIDTH-1 DOWNTO 0)"
+o 14
+)
+)
+)
+*16 (CptPort
+uid 75,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 76,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,51625,0,52375"
+)
+tg (CPTG
+uid 77,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 78,0
+va (VaSet
+)
+xt "1000,51500,7500,52500"
+st "ram_data : (15:0)"
+blo "1000,52300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ram_data"
+t "std_logic_vector"
+b "(15 DOWNTO 0)"
+o 15
+)
+)
+)
+*17 (CptPort
+uid 79,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 80,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,57625,34750,58375"
+)
+tg (CPTG
+uid 81,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 82,0
+va (VaSet
+)
+xt "15900,57500,33000,58500"
+st "ram_addr : (W5300_RAM_ADDR_WIDTH-1:0)"
+ju 2
+blo "33000,58300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "ram_addr"
+t "std_logic_vector"
+b "(W5300_RAM_ADDR_WIDTH-1 DOWNTO 0)"
+o 16
+)
+)
+)
+*18 (CptPort
+uid 83,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 84,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,52625,0,53375"
+)
+tg (CPTG
+uid 85,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 86,0
+va (VaSet
+)
+xt "1000,52500,5100,53500"
+st "data_valid"
+blo "1000,53300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "data_valid"
+t "std_logic"
+o 17
+)
+)
+)
+*19 (CptPort
+uid 87,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 88,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,58625,34750,59375"
+)
+tg (CPTG
+uid 89,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 90,0
+va (VaSet
+)
+xt "27400,58500,33000,59500"
+st "data_valid_ack"
+ju 2
+blo "33000,59300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "data_valid_ack"
+t "std_logic"
+o 18
+i "'0'"
+)
+)
+)
+*20 (CptPort
+uid 91,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 92,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,59625,34750,60375"
+)
+tg (CPTG
+uid 93,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 94,0
+va (VaSet
+)
+xt "31100,59500,33000,60500"
+st "busy"
+ju 2
+blo "33000,60300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "busy"
+t "std_logic"
+o 19
+i "'1'"
+)
+)
+)
+*21 (CptPort
+uid 95,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 96,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,53625,0,54375"
+)
+tg (CPTG
+uid 97,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 98,0
+va (VaSet
+)
+xt "1000,53500,7800,54500"
+st "write_header_flag"
+blo "1000,54300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "write_header_flag"
+t "std_logic"
+o 20
+)
+)
+)
+*22 (CptPort
+uid 99,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 100,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,54625,0,55375"
+)
+tg (CPTG
+uid 101,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 102,0
+va (VaSet
+)
+xt "1000,54500,6700,55500"
+st "write_end_flag"
+blo "1000,55300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "write_end_flag"
+t "std_logic"
+o 21
+)
+)
+)
+*23 (CptPort
+uid 103,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 104,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,55625,0,56375"
+)
+tg (CPTG
+uid 105,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 106,0
+va (VaSet
+)
+xt "1000,55500,8800,56500"
+st "fifo_channels : (3:0)"
+blo "1000,56300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "fifo_channels"
+t "std_logic_vector"
+b "(3 downto 0)"
+o 22
+)
+)
+)
+*24 (CptPort
+uid 107,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 108,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,60625,34750,61375"
+)
+tg (CPTG
+uid 109,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 110,0
+va (VaSet
+)
+xt "29400,60500,33000,61500"
+st "s_trigger"
+ju 2
+blo "33000,61300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "s_trigger"
+t "std_logic"
+o 23
+i "'0'"
+)
+)
+)
+*25 (CptPort
+uid 111,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 112,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,61625,34750,62375"
+)
+tg (CPTG
+uid 113,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 114,0
+va (VaSet
+)
+xt "26400,61500,33000,62500"
+st "c_trigger_enable"
+ju 2
+blo "33000,62300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "c_trigger_enable"
+t "std_logic"
+o 24
+i "'0'"
+)
+)
+)
+*26 (CptPort
+uid 115,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 116,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,62625,34750,63375"
+)
+tg (CPTG
+uid 117,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 118,0
+va (VaSet
+)
+xt "24200,62500,33000,63500"
+st "c_trigger_mult : (15:0)"
+ju 2
+blo "33000,63300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "c_trigger_mult"
+t "std_logic_vector"
+b "(15 DOWNTO 0)"
+o 25
+i "conv_std_logic_vector(0 ,16)"
+)
+)
+)
+*27 (CptPort
+uid 119,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 120,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,63625,34750,64375"
+)
+tg (CPTG
+uid 121,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 122,0
+va (VaSet
+)
+xt "20600,63500,33000,64500"
+st "memory_manager_config_start_o"
+ju 2
+blo "33000,64300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "memory_manager_config_start_o"
+t "std_logic"
+o 26
+i "'0'"
+)
+)
+)
+*28 (CptPort
+uid 123,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 124,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,56625,0,57375"
+)
+tg (CPTG
+uid 125,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 126,0
+va (VaSet
+)
+xt "1000,56500,13200,57500"
+st "memory_manager_config_valid_i"
+blo "1000,57300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "memory_manager_config_valid_i"
+t "std_logic"
+o 27
+)
+)
+)
+*29 (CptPort
+uid 127,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 128,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,64625,34750,65375"
+)
+tg (CPTG
+uid 129,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 130,0
+va (VaSet
+)
+xt "22300,64500,33000,65500"
+st "spi_interface_config_start_o"
+ju 2
+blo "33000,65300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "spi_interface_config_start_o"
+t "std_logic"
+o 28
+i "'0'"
+)
+)
+)
+*30 (CptPort
+uid 131,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 132,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,57625,0,58375"
+)
+tg (CPTG
+uid 133,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 134,0
+va (VaSet
+)
+xt "1000,57500,11500,58500"
+st "spi_interface_config_valid_i"
+blo "1000,58300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "spi_interface_config_valid_i"
+t "std_logic"
+o 29
+)
+)
+)
+*31 (CptPort
+uid 135,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 136,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,65625,34750,66375"
+)
+tg (CPTG
+uid 137,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 138,0
+va (VaSet
+)
+xt "28300,65500,33000,66500"
+st "dac_setting"
+ju 2
+blo "33000,66300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "dac_setting"
+t "dac_array_type"
+o 30
+i "DEFAULT_DAC"
+)
+)
+)
+*32 (CptPort
+uid 139,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 140,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,66625,34750,67375"
+)
+tg (CPTG
+uid 141,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 142,0
+va (VaSet
+)
+xt "28600,66500,33000,67500"
+st "roi_setting"
+ju 2
+blo "33000,67300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "roi_setting"
+t "roi_array_type"
+o 31
+i "DEFAULT_ROI"
+)
+)
+)
+*33 (CptPort
+uid 143,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 144,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,67625,34750,68375"
+)
+tg (CPTG
+uid 145,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 146,0
+va (VaSet
+)
+xt "26000,67500,33000,68500"
+st "runnumber : (31:0)"
+ju 2
+blo "33000,68300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "runnumber"
+t "std_logic_vector"
+b "(31 DOWNTO 0)"
+o 32
+i "conv_std_logic_vector(0 ,32)"
+)
+)
+)
+*34 (CptPort
+uid 147,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 148,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,68625,34750,69375"
+)
+tg (CPTG
+uid 149,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 150,0
+va (VaSet
+)
+xt "26700,68500,33000,69500"
+st "reset_trigger_id"
+ju 2
+blo "33000,69300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "reset_trigger_id"
+t "std_logic"
+o 33
+i "'0'"
+)
+)
+)
+*35 (CptPort
+uid 151,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 152,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,58625,0,59375"
+)
+tg (CPTG
+uid 153,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 154,0
+va (VaSet
+)
+xt "1000,58500,7200,59500"
+st "data_ram_empty"
+blo "1000,59300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "data_ram_empty"
+t "std_logic"
+o 34
+)
+)
+)
+*36 (CptPort
+uid 155,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 156,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,59625,0,60375"
+)
+tg (CPTG
+uid 157,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 158,0
+va (VaSet
+)
+xt "1000,59500,8500,60500"
+st "MAC_jumper : (1:0)"
+blo "1000,60300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "MAC_jumper"
+t "std_logic_vector"
+b "(1 downto 0)"
+o 35
+)
+)
+)
+*37 (CptPort
+uid 159,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 160,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,60625,0,61375"
+)
+tg (CPTG
+uid 161,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 162,0
+va (VaSet
+)
+xt "1000,60500,6800,61500"
+st "BoardID : (3:0)"
+blo "1000,61300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "BoardID"
+t "std_logic_vector"
+b "(3 downto 0)"
+o 36
+)
+)
+)
+*38 (CptPort
+uid 163,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 164,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,61625,0,62375"
+)
+tg (CPTG
+uid 165,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 166,0
+va (VaSet
+)
+xt "1000,61500,6700,62500"
+st "CrateID : (1:0)"
+blo "1000,62300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "CrateID"
+t "std_logic_vector"
+b "(1 downto 0)"
+o 37
+)
+)
+)
+*39 (CptPort
+uid 167,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 168,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,69625,34750,70375"
+)
+tg (CPTG
+uid 169,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 170,0
+va (VaSet
+)
+xt "27200,69500,33000,70500"
+st "trigger_enable"
+ju 2
+blo "33000,70300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "trigger_enable"
+t "std_logic"
+o 38
+)
+)
+)
+*40 (CptPort
+uid 171,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 172,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,70625,34750,71375"
+)
+tg (CPTG
+uid 173,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 174,0
+va (VaSet
+)
+xt "30000,70500,33000,71500"
+st "denable"
+ju 2
+blo "33000,71300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "denable"
+t "std_logic"
+o 39
+i "'0'"
+)
+)
+)
+*41 (CptPort
+uid 175,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 176,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,71625,34750,72375"
+)
+tg (CPTG
+uid 177,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 178,0
+va (VaSet
+)
+xt "27600,71500,33000,72500"
+st "dwrite_enable"
+ju 2
+blo "33000,72300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "dwrite_enable"
+t "std_logic"
+o 40
+i "'1'"
+)
+)
+)
+*42 (CptPort
+uid 179,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 180,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,72625,34750,73375"
+)
+tg (CPTG
+uid 181,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 182,0
+va (VaSet
+)
+xt "28300,72500,33000,73500"
+st "sclk_enable"
+ju 2
+blo "33000,73300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "sclk_enable"
+t "std_logic"
+o 41
+i "'1'"
+)
+)
+)
+*43 (CptPort
+uid 183,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 184,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,73625,34750,74375"
+)
+tg (CPTG
+uid 185,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 186,0
+va (VaSet
+)
+xt "28000,73500,33000,74500"
+st "srclk_enable"
+ju 2
+blo "33000,74300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "srclk_enable"
+t "std_logic"
+o 42
+i "'1'"
+)
+)
+)
+*44 (CptPort
+uid 187,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 188,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,74625,34750,75375"
+)
+tg (CPTG
+uid 189,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 190,0
+va (VaSet
+)
+xt "28100,74500,33000,75500"
+st "ps_direction"
+ju 2
+blo "33000,75300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "ps_direction"
+t "std_logic"
+o 43
+i "'1'"
+)
+)
+)
+*45 (CptPort
+uid 191,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 192,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,75625,34750,76375"
+)
+tg (CPTG
+uid 193,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 194,0
+va (VaSet
+)
+xt "26000,75500,33000,76500"
+st "ps_do_phase_shift"
+ju 2
+blo "33000,76300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "ps_do_phase_shift"
+t "std_logic"
+o 44
+i "'0'"
+)
+)
+)
+*46 (CptPort
+uid 195,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 196,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,76625,34750,77375"
+)
+tg (CPTG
+uid 197,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 198,0
+va (VaSet
+)
+xt "29700,76500,33000,77500"
+st "ps_reset"
+ju 2
+blo "33000,77300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "ps_reset"
+t "std_logic"
+o 45
+i "'0'"
+)
+)
+)
+*47 (CptPort
+uid 199,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 200,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,62625,0,63375"
+)
+tg (CPTG
+uid 201,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 202,0
+va (VaSet
+)
+xt "1000,62500,4400,63500"
+st "ps_ready"
+blo "1000,63300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ps_ready"
+t "std_logic"
+o 46
+)
+)
+)
+*48 (CptPort
+uid 203,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 204,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,77625,34750,78375"
+)
+tg (CPTG
+uid 205,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 206,0
+va (VaSet
+)
+xt "27500,77500,33000,78500"
+st "socks_waiting"
+ju 2
+blo "33000,78300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "socks_waiting"
+t "std_logic"
+o 47
+)
+)
+)
+*49 (CptPort
+uid 207,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 208,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,78625,34750,79375"
+)
+tg (CPTG
+uid 209,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 210,0
+va (VaSet
+)
+xt "26500,78500,33000,79500"
+st "socks_connected"
+ju 2
+blo "33000,79300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "socks_connected"
+t "std_logic"
+o 48
+)
+)
+)
+]
+shape (Rectangle
+uid 212,0
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+lineColor "0,32896,0"
+lineWidth 2
+)
+xt "0,46000,34000,80000"
+)
+ttg (MlTextGroup
+uid 213,0
+ps "CenterOffsetStrategy"
+stg "VerticalLayoutStrategy"
+textVec [
+*50 (Text
+uid 214,0
+va (VaSet
+font "Arial,8,1"
+)
+xt "13900,80000,20100,81000"
+st "FACT_FAD_lib"
+blo "13900,80800"
+tm "BdLibraryNameMgr"
+)
+*51 (Text
+uid 215,0
+va (VaSet
+font "Arial,8,1"
+)
+xt "13900,81000,20000,82000"
+st "w5300_modul2"
+blo "13900,81800"
+tm "CptNameMgr"
+)
+*52 (Text
+uid 216,0
+va (VaSet
+font "Arial,8,1"
+)
+xt "13900,82000,21100,83000"
+st "inst_w5300_mod2"
+blo "13900,82800"
+tm "InstanceNameMgr"
+)
+]
+)
+ga (GenericAssociation
+uid 217,0
+ps "EdgeToEdgeStrategy"
+matrix (Matrix
+uid 218,0
+text (MLText
+uid 219,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "7250,45200,26750,46000"
+)
+header ""
+)
+elements [
+]
+)
+viewicon (ZoomableIcon
+uid 220,0
+sl 0
+va (VaSet
+vasetType 1
+fg "49152,49152,49152"
+)
+xt "250,78250,1750,79750"
+iconName "VhdlFileViewIcon.png"
+iconMaskName "VhdlFileViewIcon.msk"
+ftype 10
+)
+ordering 1
+viewiconposition 0
+portVis (PortSigDisplay
+)
+archType 1
+archFileType "UNKNOWN"
+)
+*53 (Net
+uid 221,0
+decl (Decl
+n "state"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+o 1
+suid 1,0
+)
+declText (MLText
+uid 222,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "22000,35800,57500,36600"
+st "SIGNAL state                         : std_logic_vector(7 DOWNTO 0)"
+)
+)
+*54 (Net
+uid 229,0
+decl (Decl
+n "debug_data_ram_empty"
+t "std_logic"
+o 2
+suid 2,0
+)
+declText (MLText
+uid 230,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "22000,15000,48000,15800"
+st "SIGNAL debug_data_ram_empty          : std_logic"
+)
+)
+*55 (Net
+uid 237,0
+decl (Decl
+n "debug_data_valid"
+t "std_logic"
+o 3
+suid 3,0
+)
+declText (MLText
+uid 238,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "22000,15800,48000,16600"
+st "SIGNAL debug_data_valid              : std_logic"
+)
+)
+*56 (Net
+uid 253,0
+lang 10
+decl (Decl
+n "wiz_reset"
+t "std_logic"
+o 5
+suid 5,0
+)
+declText (MLText
+uid 254,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "22000,37400,48000,38200"
+st "SIGNAL wiz_reset                     : std_logic"
+)
+)
+*57 (Net
+uid 261,0
+decl (Decl
+n "addr"
+t "std_logic_vector"
+b "(9 DOWNTO 0)"
+o 6
+suid 6,0
+)
+declText (MLText
+uid 262,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "22000,5400,57500,6200"
+st "SIGNAL addr                          : std_logic_vector(9 DOWNTO 0)"
+)
+)
+*58 (Net
+uid 269,0
+lang 10
+decl (Decl
+n "data"
+t "std_logic_vector"
+b "(15 DOWNTO 0)"
+o 7
+suid 7,0
+i "(others => 'Z')"
+)
+declText (MLText
+uid 270,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "22000,11000,67500,11800"
+st "SIGNAL data                          : std_logic_vector(15 DOWNTO 0) := (others => 'Z')"
+)
+)
+*59 (Net
+uid 277,0
+lang 10
+decl (Decl
+n "cs"
+t "std_logic"
+o 8
+suid 8,0
+)
+declText (MLText
+uid 278,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "22000,9400,48000,10200"
+st "SIGNAL cs                            : std_logic"
+)
+)
+*60 (Net
+uid 285,0
+lang 10
+decl (Decl
+n "wr"
+t "std_logic"
+o 9
+suid 9,0
+)
+declText (MLText
+uid 286,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "22000,38200,48000,39000"
+st "SIGNAL wr                            : std_logic"
+)
+)
+*61 (Net
+uid 293,0
+lang 10
+decl (Decl
+n "rd"
+t "std_logic"
+o 10
+suid 10,0
+)
+declText (MLText
+uid 294,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "22000,27000,48000,27800"
+st "SIGNAL rd                            : std_logic"
+)
+)
+*62 (Net
+uid 309,0
+lang 10
+decl (Decl
+n "ram_addr"
+t "std_logic_vector"
+b "(13 DOWNTO 0)"
+o 12
+suid 12,0
+)
+declText (MLText
+uid 310,0
+va (VaSet
+font "Courier New,8,0"
+)
+xt "22000,24600,58000,25400"
+st "SIGNAL ram_addr                      : std_logic_vector(13 DOWNTO 0)"
+)
+)
+*63 (Net
+uid 317,0
+lang 10
+decl (Decl
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+)
+)
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+)
+)
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+)
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+)
+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+"51000,51000"
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+)
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+)
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+)
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+"51000,53000"
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+)
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+)
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+"51000,54000"
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+)
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+)
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+"51000,55000"
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+)
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+)
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+"51000,56000"
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+)
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+)
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+)
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+)
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+"51000,59000"
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+)
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+)
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+"51000,60000"
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+)
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+)
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+"34750,61000"
+"51000,61000"
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+)
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+)
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+"34750,62000"
+"51000,62000"
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+)
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+)
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+"34750,63000"
+"51000,63000"
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+)
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+)
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+)
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+"51000,64000"
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+)
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+)
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+"51000,65000"
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+)
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+)
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+)
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+"51000,66000"
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+)
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+)
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+)
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+"51000,67000"
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+)
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+"34750,68000"
+"51000,68000"
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+)
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+"34750,69000"
+"51000,69000"
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+)
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+"51000,72000"
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+)
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+)
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+)
+)
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+)
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+)
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+"34750,73000"
+"51000,73000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"34750,74000"
+"51000,74000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"34750,75000"
+"51000,75000"
+]
+)
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+)
+)
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+)
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+)
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+"34750,76000"
+"51000,76000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"34750,77000"
+"51000,77000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"34750,78000"
+"51000,78000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"34750,79000"
+"51000,79000"
+]
+)
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+)
+xt "36000,78000,42500,79000"
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+)
+)
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+)
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+)
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+"-19000,47000"
+"-750,47000"
+]
+)
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+)
+)
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+)
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+)
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+"-19000,48000"
+"-750,48000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"-19000,49000"
+"-750,49000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"-19000,50000"
+"-750,50000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"-19000,51000"
+"-750,51000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"-19000,52000"
+"-750,52000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"-19000,53000"
+"-750,53000"
+]
+)
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+)
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+)
+)
+on &90
+)
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+)
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+"-19000,54000"
+"-750,54000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"-19000,55000"
+"-750,55000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"-19000,56000"
+"-750,56000"
+]
+)
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+)
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+)
+)
+on &93
+)
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+)
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+"-19000,57000"
+"-750,57000"
+]
+)
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+)
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+)
+)
+on &94
+)
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+)
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+"-19000,58000"
+"-750,58000"
+]
+)
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+)
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+)
+)
+on &95
+)
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+)
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+"-19000,59000"
+"-750,59000"
+]
+)
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+)
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+)
+)
+on &96
+)
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+)
+xt "-19000,60000,-750,60000"
+pts [
+"-19000,60000"
+"-750,60000"
+]
+)
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+)
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+st "MAC_jumper : (1:0)"
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+)
+)
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+)
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+)
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+"-19000,61000"
+"-750,61000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"-19000,62000"
+"-750,62000"
+]
+)
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+)
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+)
+)
+on &99
+)
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+)
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+"-19000,63000"
+"-750,63000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"108000,58000"
+"125000,58000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"108000,50000"
+"125000,50000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"68000,33000"
+"93250,29000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+pts [
+"108000,59000"
+"125000,59000"
+]
+)
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+)
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+)
+)
+on &64
+)
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+)
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+pts [
+"108000,63000"
+"125000,63000"
+]
+)
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+va (VaSet
+)
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+st "memory_manager_config_start_o"
+blo "109000,62800"
+tm "WireNameMgr"
+)
+)
+on &68
+)
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+)
+xt "108000,47000,125000,47000"
+pts [
+"108000,47000"
+"125000,47000"
+]
+)
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+sf 1
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+va (VaSet
+)
+xt "109000,46000,118100,47000"
+st "debug_data_ram_empty"
+blo "109000,46800"
+tm "WireNameMgr"
+)
+)
+on &54
+)
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+lineWidth 2
+)
+xt "108000,46000,125000,46000"
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+"108000,46000"
+"125000,46000"
+]
+)
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+)
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+)
+)
+on &53
+)
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+)
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+pts [
+"108000,61000"
+"125000,61000"
+]
+)
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+va (VaSet
+)
+xt "109000,60000,115600,61000"
+st "c_trigger_enable"
+blo "109000,60800"
+tm "WireNameMgr"
+)
+)
+on &66
+)
+*178 (Wire
+uid 711,0
+shape (OrthoPolyLine
+uid 712,0
+va (VaSet
+vasetType 3
+)
+xt "108000,48000,125000,48000"
+pts [
+"108000,48000"
+"125000,48000"
+]
+)
+start &101
+sat 1
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 717,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 718,0
+va (VaSet
+)
+xt "109000,47000,115600,48000"
+st "debug_data_valid"
+blo "109000,47800"
+tm "WireNameMgr"
+)
+)
+on &55
+)
+*179 (Wire
+uid 719,0
+shape (OrthoPolyLine
+uid 720,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "108000,57000,125000,57000"
+pts [
+"108000,57000"
+"125000,57000"
+]
+)
+start &101
+sat 1
+eat 16
+sty 1
+st 0
+sf 1
+si 0
+tg (WTG
+uid 725,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 726,0
+va (VaSet
+)
+xt "110000,56000,116600,57000"
+st "ram_addr : (13:0)"
+blo "110000,56800"
+tm "WireNameMgr"
+)
+)
+on &62
+)
+*180 (Wire
+uid 727,0
+shape (OrthoPolyLine
+uid 728,0
+va (VaSet
+vasetType 3
+)
+xt "108000,60000,125000,60000"
+pts [
+"108000,60000"
+"125000,60000"
+]
+)
+start &101
+sat 1
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 733,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 734,0
+va (VaSet
+)
+xt "109000,59000,112600,60000"
+st "s_trigger"
+blo "109000,59800"
+tm "WireNameMgr"
+)
+)
+on &65
+)
+*181 (Wire
+uid 735,0
+shape (OrthoPolyLine
+uid 736,0
+va (VaSet
+vasetType 3
+)
+xt "71000,33000,93250,34000"
+pts [
+"71000,34000"
+"93250,33000"
+]
+)
+end &116
+sat 16
+eat 32
+st 0
+sf 1
+si 0
+tg (WTG
+uid 741,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 742,0
+va (VaSet
+)
+xt "72000,33000,73200,34000"
+st "wr"
+blo "72000,33800"
+tm "WireNameMgr"
+)
+)
+on &60
+)
+*182 (Wire
+uid 743,0
+shape (OrthoPolyLine
+uid 744,0
+va (VaSet
+vasetType 3
+)
+xt "63000,32000,93250,35000"
+pts [
+"63000,35000"
+"93250,32000"
+]
+)
+end &115
+es 0
+sat 16
+eat 32
+st 0
+sf 1
+si 0
+tg (WTG
+uid 749,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 750,0
+va (VaSet
+)
+xt "64000,34000,65100,35000"
+st "rd"
+blo "64000,34800"
+tm "WireNameMgr"
+)
+)
+on &61
+)
+*183 (Wire
+uid 751,0
+shape (OrthoPolyLine
+uid 752,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "70000,28000,93250,30000"
+pts [
+"70000,30000"
+"93250,28000"
+]
+)
+end &113
+es 0
+sat 16
+eat 32
+sty 1
+st 0
+sf 1
+si 0
+tg (WTG
+uid 757,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 758,0
+va (VaSet
+)
+xt "71000,29000,75500,30000"
+st "addr : (9:0)"
+blo "71000,29800"
+tm "WireNameMgr"
+)
+)
+on &57
+)
+*184 (Wire
+uid 759,0
+shape (OrthoPolyLine
+uid 760,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "108000,67000,125000,67000"
+pts [
+"108000,67000"
+"125000,67000"
+]
+)
+start &101
+sat 1
+eat 16
+sty 1
+st 0
+sf 1
+si 0
+tg (WTG
+uid 765,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 766,0
+va (VaSet
+)
+xt "109000,66000,116000,67000"
+st "runnumber : (31:0)"
+blo "109000,66800"
+tm "WireNameMgr"
+)
+)
+on &72
+)
+*185 (Wire
+uid 767,0
+shape (OrthoPolyLine
+uid 768,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "55000,49000,74000,49000"
+pts [
+"55000,49000"
+"74000,49000"
+]
+)
+end &101
+sat 16
+eat 2
+sty 1
+st 0
+sf 1
+si 0
+tg (WTG
+uid 773,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 774,0
+va (VaSet
+)
+xt "56000,48000,63900,49000"
+st "write_length : (16:0)"
+blo "56000,48800"
+tm "WireNameMgr"
+)
+)
+on &87
+)
+*186 (Wire
+uid 775,0
+shape (OrthoPolyLine
+uid 776,0
+va (VaSet
+vasetType 3
+)
+xt "108000,70000,125000,70000"
+pts [
+"108000,70000"
+"125000,70000"
+]
+)
+start &101
+sat 1
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 781,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 782,0
+va (VaSet
+)
+xt "109000,69000,112000,70000"
+st "denable"
+blo "109000,69800"
+tm "WireNameMgr"
+)
+)
+on &75
+)
+*187 (Wire
+uid 783,0
+shape (OrthoPolyLine
+uid 784,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "55000,50000,74000,50000"
+pts [
+"55000,50000"
+"74000,50000"
+]
+)
+end &101
+sat 16
+eat 2
+sty 1
+st 0
+sf 1
+si 0
+tg (WTG
+uid 789,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 790,0
+va (VaSet
+)
+xt "57000,49000,65900,50000"
+st "ram_start_addr : (13:0)"
+blo "57000,49800"
+tm "WireNameMgr"
+)
+)
+on &88
+)
+*188 (Wire
+uid 791,0
+shape (OrthoPolyLine
+uid 792,0
+va (VaSet
+vasetType 3
+)
+xt "108000,71000,125000,71000"
+pts [
+"108000,71000"
+"125000,71000"
+]
+)
+start &101
+sat 1
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 797,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 798,0
+va (VaSet
+)
+xt "109000,70000,114400,71000"
+st "dwrite_enable"
+blo "109000,70800"
+tm "WireNameMgr"
+)
+)
+on &76
+)
+*189 (Wire
+uid 799,0
+shape (OrthoPolyLine
+uid 800,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "55000,51000,74000,51000"
+pts [
+"55000,51000"
+"74000,51000"
+]
+)
+end &101
+sat 16
+eat 2
+sty 1
+st 0
+sf 1
+si 0
+tg (WTG
+uid 805,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 806,0
+va (VaSet
+)
+xt "56000,50000,62500,51000"
+st "ram_data : (15:0)"
+blo "56000,50800"
+tm "WireNameMgr"
+)
+)
+on &89
+)
+*190 (Wire
+uid 807,0
+shape (OrthoPolyLine
+uid 808,0
+va (VaSet
+vasetType 3
+)
+xt "108000,73000,125000,73000"
+pts [
+"108000,73000"
+"125000,73000"
+]
+)
+start &101
+sat 1
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 813,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 814,0
+va (VaSet
+)
+xt "109000,72000,114000,73000"
+st "srclk_enable"
+blo "109000,72800"
+tm "WireNameMgr"
+)
+)
+on &78
+)
+*191 (Wire
+uid 815,0
+shape (OrthoPolyLine
+uid 816,0
+va (VaSet
+vasetType 3
+)
+xt "108000,68000,125000,68000"
+pts [
+"108000,68000"
+"125000,68000"
+]
+)
+start &101
+sat 1
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 821,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 822,0
+va (VaSet
+)
+xt "109000,67000,115300,68000"
+st "reset_trigger_id"
+blo "109000,67800"
+tm "WireNameMgr"
+)
+)
+on &73
+)
+*192 (Wire
+uid 823,0
+shape (OrthoPolyLine
+uid 824,0
+va (VaSet
+vasetType 3
+)
+xt "108000,74000,125000,74000"
+pts [
+"108000,74000"
+"125000,74000"
+]
+)
+start &101
+sat 1
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 829,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 830,0
+va (VaSet
+)
+xt "109000,73000,113900,74000"
+st "ps_direction"
+blo "109000,73800"
+tm "WireNameMgr"
+)
+)
+on &79
+)
+*193 (Wire
+uid 831,0
+shape (OrthoPolyLine
+uid 832,0
+va (VaSet
+vasetType 3
+)
+xt "108000,65000,125000,65000"
+pts [
+"108000,65000"
+"125000,65000"
+]
+)
+start &101
+sat 1
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 837,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 838,0
+va (VaSet
+)
+xt "109000,64000,113700,65000"
+st "dac_setting"
+blo "109000,64800"
+tm "WireNameMgr"
+)
+)
+on &70
+)
+*194 (Wire
+uid 839,0
+shape (OrthoPolyLine
+uid 840,0
+va (VaSet
+vasetType 3
+)
+xt "108000,69000,125000,69000"
+pts [
+"108000,69000"
+"125000,69000"
+]
+)
+start &101
+sat 1
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 845,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 846,0
+va (VaSet
+)
+xt "109000,68000,114800,69000"
+st "trigger_enable"
+blo "109000,68800"
+tm "WireNameMgr"
+)
+)
+on &74
+)
+*195 (Wire
+uid 847,0
+shape (OrthoPolyLine
+uid 848,0
+va (VaSet
+vasetType 3
+)
+xt "108000,72000,125000,72000"
+pts [
+"108000,72000"
+"125000,72000"
+]
+)
+start &101
+sat 1
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 853,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 854,0
+va (VaSet
+)
+xt "109000,71000,113700,72000"
+st "sclk_enable"
+blo "109000,71800"
+tm "WireNameMgr"
+)
+)
+on &77
+)
+*196 (Wire
+uid 855,0
+shape (OrthoPolyLine
+uid 856,0
+va (VaSet
+vasetType 3
+)
+xt "108000,75000,125000,75000"
+pts [
+"108000,75000"
+"125000,75000"
+]
+)
+start &101
+sat 1
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 861,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 862,0
+va (VaSet
+)
+xt "109000,74000,116000,75000"
+st "ps_do_phase_shift"
+blo "109000,74800"
+tm "WireNameMgr"
+)
+)
+on &80
+)
+*197 (Wire
+uid 863,0
+shape (OrthoPolyLine
+uid 864,0
+va (VaSet
+vasetType 3
+)
+xt "108000,64000,125000,64000"
+pts [
+"108000,64000"
+"125000,64000"
+]
+)
+start &101
+sat 1
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 869,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 870,0
+va (VaSet
+)
+xt "109000,63000,119700,64000"
+st "spi_interface_config_start_o"
+blo "109000,63800"
+tm "WireNameMgr"
+)
+)
+on &69
+)
+*198 (Wire
+uid 871,0
+shape (OrthoPolyLine
+uid 872,0
+va (VaSet
+vasetType 3
+)
+xt "68000,35000,93250,38000"
+pts [
+"68000,38000"
+"93250,35000"
+]
+)
+end &118
+es 0
+sat 16
+eat 32
+st 0
+sf 1
+si 0
+tg (WTG
+uid 877,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 878,0
+va (VaSet
+)
+xt "69000,37000,70200,38000"
+st "cs"
+blo "69000,37800"
+tm "WireNameMgr"
+)
+)
+on &59
+)
+*199 (Wire
+uid 879,0
+shape (OrthoPolyLine
+uid 880,0
+va (VaSet
+vasetType 3
+)
+xt "108000,66000,125000,66000"
+pts [
+"108000,66000"
+"125000,66000"
+]
+)
+start &101
+sat 1
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 885,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 886,0
+va (VaSet
+)
+xt "109000,65000,113400,66000"
+st "roi_setting"
+blo "109000,65800"
+tm "WireNameMgr"
+)
+)
+on &71
+)
+*200 (Wire
+uid 887,0
+shape (OrthoPolyLine
+uid 888,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "108000,62000,125000,62000"
+pts [
+"108000,62000"
+"125000,62000"
+]
+)
+start &101
+sat 1
+eat 16
+sty 1
+st 0
+sf 1
+si 0
+tg (WTG
+uid 893,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 894,0
+va (VaSet
+)
+xt "109000,61000,117800,62000"
+st "c_trigger_mult : (15:0)"
+blo "109000,61800"
+tm "WireNameMgr"
+)
+)
+on &67
+)
+*201 (Wire
+uid 895,0
+shape (OrthoPolyLine
+uid 896,0
+va (VaSet
+vasetType 3
+)
+xt "55000,46000,74000,46000"
+pts [
+"55000,46000"
+"74000,46000"
+]
+)
+end &101
+sat 16
+eat 2
+st 0
+sf 1
+si 0
+tg (WTG
+uid 901,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 902,0
+va (VaSet
+)
+xt "56000,45000,64500,46000"
+st "data_generator_idle_i"
+blo "56000,45800"
+tm "WireNameMgr"
+)
+)
+on &84
+)
+*202 (Wire
+uid 903,0
+shape (OrthoPolyLine
+uid 904,0
+va (VaSet
+vasetType 3
+)
+xt "55000,52000,74000,52000"
+pts [
+"55000,52000"
+"74000,52000"
+]
+)
+end &101
+sat 16
+eat 2
+st 0
+sf 1
+si 0
+tg (WTG
+uid 909,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 910,0
+va (VaSet
+)
+xt "56000,51000,60100,52000"
+st "data_valid"
+blo "56000,51800"
+tm "WireNameMgr"
+)
+)
+on &90
+)
+*203 (Wire
+uid 911,0
+shape (OrthoPolyLine
+uid 912,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "55000,55000,74000,55000"
+pts [
+"55000,55000"
+"74000,55000"
+]
+)
+end &101
+sat 16
+eat 2
+sty 1
+st 0
+sf 1
+si 0
+tg (WTG
+uid 917,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 918,0
+va (VaSet
+)
+xt "56000,54000,63800,55000"
+st "fifo_channels : (3:0)"
+blo "56000,54800"
+tm "WireNameMgr"
+)
+)
+on &93
+)
+*204 (Wire
+uid 919,0
+shape (OrthoPolyLine
+uid 920,0
+va (VaSet
+vasetType 3
+)
+xt "55000,54000,74000,54000"
+pts [
+"55000,54000"
+"74000,54000"
+]
+)
+end &101
+sat 16
+eat 2
+st 0
+sf 1
+si 0
+tg (WTG
+uid 925,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 926,0
+va (VaSet
+)
+xt "56000,53000,61700,54000"
+st "write_end_flag"
+blo "56000,53800"
+tm "WireNameMgr"
+)
+)
+on &92
+)
+*205 (Wire
+uid 927,0
+shape (OrthoPolyLine
+uid 928,0
+va (VaSet
+vasetType 3
+)
+xt "55000,56000,74000,56000"
+pts [
+"55000,56000"
+"74000,56000"
+]
+)
+end &101
+sat 16
+eat 2
+st 0
+sf 1
+si 0
+tg (WTG
+uid 933,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 934,0
+va (VaSet
+)
+xt "56000,55000,68200,56000"
+st "memory_manager_config_valid_i"
+blo "56000,55800"
+tm "WireNameMgr"
+)
+)
+on &94
+)
+*206 (Wire
+uid 935,0
+shape (OrthoPolyLine
+uid 936,0
+va (VaSet
+vasetType 3
+)
+xt "55000,58000,74000,58000"
+pts [
+"55000,58000"
+"74000,58000"
+]
+)
+end &101
+sat 16
+eat 2
+st 0
+sf 1
+si 0
+tg (WTG
+uid 941,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 942,0
+va (VaSet
+)
+xt "56000,57000,62200,58000"
+st "data_ram_empty"
+blo "56000,57800"
+tm "WireNameMgr"
+)
+)
+on &96
+)
+*207 (Wire
+uid 943,0
+shape (OrthoPolyLine
+uid 944,0
+va (VaSet
+vasetType 3
+)
+xt "55000,57000,74000,57000"
+pts [
+"55000,57000"
+"74000,57000"
+]
+)
+end &101
+sat 16
+eat 2
+st 0
+sf 1
+si 0
+tg (WTG
+uid 949,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 950,0
+va (VaSet
+)
+xt "56000,56000,66500,57000"
+st "spi_interface_config_valid_i"
+blo "56000,56800"
+tm "WireNameMgr"
+)
+)
+on &95
+)
+*208 (Wire
+uid 951,0
+shape (OrthoPolyLine
+uid 952,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "55000,59000,74000,59000"
+pts [
+"55000,59000"
+"74000,59000"
+]
+)
+end &101
+sat 16
+eat 2
+sty 1
+st 0
+sf 1
+si 0
+tg (WTG
+uid 957,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 958,0
+va (VaSet
+)
+xt "56000,58000,63500,59000"
+st "MAC_jumper : (1:0)"
+blo "56000,58800"
+tm "WireNameMgr"
+)
+)
+on &97
+)
+*209 (Wire
+uid 959,0
+shape (OrthoPolyLine
+uid 960,0
+va (VaSet
+vasetType 3
+)
+xt "108000,76000,125000,76000"
+pts [
+"108000,76000"
+"125000,76000"
+]
+)
+start &101
+sat 1
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 965,0
+ps "ConnStartEndStrategy"
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+)
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+)
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+)
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+)
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+)
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+)
+sheetCol (SheetCol
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+fontColor "0,0,0"
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+pos 7
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+uid 1203,0
+)
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+)
+fixedCol 4
+fixedRow 2
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+vaOverrides [
+]
+)
+]
+)
+uid 1175,0
+)
+genericsCommonDM (CommonDM
+ldm (LogicalDM
+emptyRow *372 (LEmptyRow
+)
+uid 1205,0
+optionalChildren [
+*373 (RefLabelRowHdr
+)
+*374 (TitleRowHdr
+)
+*375 (FilterRowHdr
+)
+*376 (RefLabelColHdr
+tm "RefLabelColHdrMgr"
+)
+*377 (RowExpandColHdr
+tm "RowExpandColHdrMgr"
+)
+*378 (GroupColHdr
+tm "GroupColHdrMgr"
+)
+*379 (NameColHdr
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+)
+*380 (TypeColHdr
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+)
+*381 (InitColHdr
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+)
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+)
+*383 (EolColHdr
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
+]
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+]
+)
+]
+)
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+)
+activeModelName "BlockDiag"
+)
Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/w5300_modul2_tb/struct.bd.bak
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/w5300_modul2_tb/struct.bd.bak	(revision 10914)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/w5300_modul2_tb/struct.bd.bak	(revision 10914)
@@ -0,0 +1,9455 @@
+DocumentHdrVersion "1.1"
+Header (DocumentHdr
+version 2
+dmPackageRefs [
+(DmPackageRef
+library "IEEE"
+unitName "STD_LOGIC_1164"
+itemName "ALL"
+)
+(DmPackageRef
+library "IEEE"
+unitName "STD_LOGIC_ARITH"
+itemName "ALL"
+)
+(DmPackageRef
+library "IEEE"
+unitName "STD_LOGIC_UNSIGNED"
+itemName "ALL"
+)
+(DmPackageRef
+library "FACT_FAD_lib"
+unitName "fad_definitions"
+itemName "ALL"
+)
+]
+instances [
+(Instance
+name "inst_w5300_mod2"
+duLibraryName "FACT_FAD_lib"
+duName "w5300_modul2"
+elements [
+(GiElement
+name "RAM_ADDR_WIDTH"
+type "integer"
+value "14"
+)
+]
+mwi 0
+uid 211,0
+)
+(Instance
+name "U_1"
+duLibraryName "FACT_FAD_TB_lib"
+duName "w5300_modul2_tester"
+elements [
+]
+mwi 0
+uid 621,0
+)
+(Instance
+name "U_2"
+duLibraryName "FACT_FAD_TB_lib"
+duName "clock_generator"
+elements [
+(GiElement
+name "clock_period"
+type "time"
+value "20 ns"
+)
+(GiElement
+name "reset_time"
+type "time"
+value "50 ns"
+)
+]
+mwi 0
+uid 1542,0
+)
+(Instance
+name "U_0"
+duLibraryName "FACT_FAD_TB_lib"
+duName "w5300_emulator"
+elements [
+]
+mwi 0
+uid 2558,0
+)
+]
+libraryRefs [
+"IEEE"
+"FACT_FAD_lib"
+]
+)
+version "29.1"
+appVersion "2009.2 (Build 10)"
+noEmbeddedEditors 1
+model (BlockDiag
+VExpander (VariableExpander
+vvMap [
+(vvPair
+variable "HDLDir"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hdl"
+)
+(vvPair
+variable "HDSDir"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
+)
+(vvPair
+variable "SideDataDesignDir"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tb\\struct.bd.info"
+)
+(vvPair
+variable "SideDataUserDir"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tb\\struct.bd.user"
+)
+(vvPair
+variable "SourceDir"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
+)
+(vvPair
+variable "appl"
+value "HDL Designer"
+)
+(vvPair
+variable "arch_name"
+value "struct"
+)
+(vvPair
+variable "config"
+value "%(unit)_%(view)_config"
+)
+(vvPair
+variable "d"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tb"
+)
+(vvPair
+variable "d_logical"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tb"
+)
+(vvPair
+variable "date"
+value "01.06.2011"
+)
+(vvPair
+variable "day"
+value "Mi"
+)
+(vvPair
+variable "day_long"
+value "Mittwoch"
+)
+(vvPair
+variable "dd"
+value "01"
+)
+(vvPair
+variable "entity_name"
+value "w5300_modul2_tb"
+)
+(vvPair
+variable "ext"
+value "<TBD>"
+)
+(vvPair
+variable "f"
+value "struct.bd"
+)
+(vvPair
+variable "f_logical"
+value "struct.bd"
+)
+(vvPair
+variable "f_noext"
+value "struct"
+)
+(vvPair
+variable "group"
+value "UNKNOWN"
+)
+(vvPair
+variable "host"
+value "E5B-LABOR6"
+)
+(vvPair
+variable "language"
+value "VHDL"
+)
+(vvPair
+variable "library"
+value "FACT_FAD_TB_lib"
+)
+(vvPair
+variable "library_downstream_HdsLintPlugin"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/designcheck"
+)
+(vvPair
+variable "library_downstream_ISEPARInvoke"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
+)
+(vvPair
+variable "library_downstream_ImpactInvoke"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
+)
+(vvPair
+variable "library_downstream_ModelSimCompiler"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/work"
+)
+(vvPair
+variable "library_downstream_XSTDataPrep"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
+)
+(vvPair
+variable "mm"
+value "06"
+)
+(vvPair
+variable "module_name"
+value "w5300_modul2_tb"
+)
+(vvPair
+variable "month"
+value "Jun"
+)
+(vvPair
+variable "month_long"
+value "Juni"
+)
+(vvPair
+variable "p"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tb\\struct.bd"
+)
+(vvPair
+variable "p_logical"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tb\\struct.bd"
+)
+(vvPair
+variable "package_name"
+value "<Undefined Variable>"
+)
+(vvPair
+variable "project_name"
+value "FACT_FAD"
+)
+(vvPair
+variable "series"
+value "HDL Designer Series"
+)
+(vvPair
+variable "task_DesignCompilerPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_LeonardoPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_ModelSimPath"
+value "C:\\modeltech_6.6a\\win32"
+)
+(vvPair
+variable "task_NC-SimPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_PrecisionRTLPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_QuestaSimPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_VCSPath"
+value "<TBD>"
+)
+(vvPair
+variable "this_ext"
+value "bd"
+)
+(vvPair
+variable "this_file"
+value "struct"
+)
+(vvPair
+variable "this_file_logical"
+value "struct"
+)
+(vvPair
+variable "time"
+value "09:27:01"
+)
+(vvPair
+variable "unit"
+value "w5300_modul2_tb"
+)
+(vvPair
+variable "user"
+value "dneise"
+)
+(vvPair
+variable "version"
+value "2009.2 (Build 10)"
+)
+(vvPair
+variable "view"
+value "struct"
+)
+(vvPair
+variable "year"
+value "2011"
+)
+(vvPair
+variable "yy"
+value "11"
+)
+]
+)
+LanguageMgr "VhdlLangMgr"
+uid 1174,0
+optionalChildren [
+*1 (SaComponent
+uid 211,0
+optionalChildren [
+*2 (CptPort
+uid 11,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 12,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,46625,34750,47375"
+)
+tg (CPTG
+uid 13,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 14,0
+va (VaSet
+)
+xt "28400,46500,33000,47500"
+st "state : (7:0)"
+ju 2
+blo "33000,47300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "state"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+o 1
+)
+)
+)
+*3 (CptPort
+uid 15,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 16,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,47625,34750,48375"
+)
+tg (CPTG
+uid 17,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 18,0
+va (VaSet
+)
+xt "23900,47500,33000,48500"
+st "debug_data_ram_empty"
+ju 2
+blo "33000,48300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "debug_data_ram_empty"
+t "std_logic"
+o 2
+)
+)
+)
+*4 (CptPort
+uid 19,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 20,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,48625,34750,49375"
+)
+tg (CPTG
+uid 21,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 22,0
+va (VaSet
+)
+xt "26400,48500,33000,49500"
+st "debug_data_valid"
+ju 2
+blo "33000,49300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "debug_data_valid"
+t "std_logic"
+o 3
+)
+)
+)
+*5 (CptPort
+uid 23,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 24,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,46625,0,47375"
+)
+tg (CPTG
+uid 25,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 26,0
+va (VaSet
+)
+xt "1000,46500,9500,47500"
+st "data_generator_idle_i"
+blo "1000,47300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "data_generator_idle_i"
+t "std_logic"
+o 4
+)
+)
+)
+*6 (CptPort
+uid 31,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 32,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,47625,0,48375"
+)
+tg (CPTG
+uid 33,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 34,0
+va (VaSet
+)
+xt "1000,47500,2300,48500"
+st "clk"
+blo "1000,48300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "clk"
+t "std_logic"
+o 5
+)
+)
+)
+*7 (CptPort
+uid 35,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 36,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,50625,34750,51375"
+)
+tg (CPTG
+uid 37,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 38,0
+va (VaSet
+)
+xt "29400,50500,33000,51500"
+st "wiz_reset"
+ju 2
+blo "33000,51300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "wiz_reset"
+t "std_logic"
+o 6
+i "'1'"
+)
+)
+)
+*8 (CptPort
+uid 39,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 40,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,51625,34750,52375"
+)
+tg (CPTG
+uid 41,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 42,0
+va (VaSet
+)
+xt "28500,51500,33000,52500"
+st "addr : (9:0)"
+ju 2
+blo "33000,52300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "addr"
+t "std_logic_vector"
+b "(9 DOWNTO 0)"
+o 7
+)
+)
+)
+*9 (CptPort
+uid 43,0
+ps "OnEdgeStrategy"
+shape (Diamond
+uid 44,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,52625,34750,53375"
+)
+tg (CPTG
+uid 45,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 46,0
+va (VaSet
+)
+xt "28200,52500,33000,53500"
+st "data : (15:0)"
+ju 2
+blo "33000,53300"
+)
+)
+thePort (LogicalPort
+m 2
+decl (Decl
+n "data"
+t "std_logic_vector"
+b "(15 DOWNTO 0)"
+o 8
+)
+)
+)
+*10 (CptPort
+uid 47,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 48,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,53625,34750,54375"
+)
+tg (CPTG
+uid 49,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 50,0
+va (VaSet
+)
+xt "31800,53500,33000,54500"
+st "cs"
+ju 2
+blo "33000,54300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "cs"
+t "std_logic"
+o 9
+i "'1'"
+)
+)
+)
+*11 (CptPort
+uid 51,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 52,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,54625,34750,55375"
+)
+tg (CPTG
+uid 53,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 54,0
+va (VaSet
+)
+xt "31800,54500,33000,55500"
+st "wr"
+ju 2
+blo "33000,55300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "wr"
+t "std_logic"
+o 10
+i "'1'"
+)
+)
+)
+*12 (CptPort
+uid 55,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 56,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,55625,34750,56375"
+)
+tg (CPTG
+uid 57,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 58,0
+va (VaSet
+)
+xt "31900,55500,33000,56500"
+st "rd"
+ju 2
+blo "33000,56300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "rd"
+t "std_logic"
+o 11
+i "'1'"
+)
+)
+)
+*13 (CptPort
+uid 63,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 64,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,48625,0,49375"
+)
+tg (CPTG
+uid 65,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 66,0
+va (VaSet
+)
+xt "1000,48500,2200,49500"
+st "int"
+blo "1000,49300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "int"
+t "std_logic"
+o 12
+)
+)
+)
+*14 (CptPort
+uid 67,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 68,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,49625,0,50375"
+)
+tg (CPTG
+uid 69,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 70,0
+va (VaSet
+)
+xt "1000,49500,8900,50500"
+st "write_length : (16:0)"
+blo "1000,50300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "write_length"
+t "std_logic_vector"
+b "(16 DOWNTO 0)"
+o 13
+)
+)
+)
+*15 (CptPort
+uid 71,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 72,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,50625,0,51375"
+)
+tg (CPTG
+uid 73,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 74,0
+va (VaSet
+)
+xt "1000,50500,20400,51500"
+st "ram_start_addr : (W5300_RAM_ADDR_WIDTH-1:0)"
+blo "1000,51300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ram_start_addr"
+t "std_logic_vector"
+b "(W5300_RAM_ADDR_WIDTH-1 DOWNTO 0)"
+o 14
+)
+)
+)
+*16 (CptPort
+uid 75,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 76,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,51625,0,52375"
+)
+tg (CPTG
+uid 77,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 78,0
+va (VaSet
+)
+xt "1000,51500,7500,52500"
+st "ram_data : (15:0)"
+blo "1000,52300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ram_data"
+t "std_logic_vector"
+b "(15 DOWNTO 0)"
+o 15
+)
+)
+)
+*17 (CptPort
+uid 79,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 80,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,57625,34750,58375"
+)
+tg (CPTG
+uid 81,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 82,0
+va (VaSet
+)
+xt "15900,57500,33000,58500"
+st "ram_addr : (W5300_RAM_ADDR_WIDTH-1:0)"
+ju 2
+blo "33000,58300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "ram_addr"
+t "std_logic_vector"
+b "(W5300_RAM_ADDR_WIDTH-1 DOWNTO 0)"
+o 16
+)
+)
+)
+*18 (CptPort
+uid 83,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 84,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,52625,0,53375"
+)
+tg (CPTG
+uid 85,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 86,0
+va (VaSet
+)
+xt "1000,52500,5100,53500"
+st "data_valid"
+blo "1000,53300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "data_valid"
+t "std_logic"
+o 17
+)
+)
+)
+*19 (CptPort
+uid 87,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 88,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,58625,34750,59375"
+)
+tg (CPTG
+uid 89,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 90,0
+va (VaSet
+)
+xt "27400,58500,33000,59500"
+st "data_valid_ack"
+ju 2
+blo "33000,59300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "data_valid_ack"
+t "std_logic"
+o 18
+i "'0'"
+)
+)
+)
+*20 (CptPort
+uid 91,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 92,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,59625,34750,60375"
+)
+tg (CPTG
+uid 93,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 94,0
+va (VaSet
+)
+xt "31100,59500,33000,60500"
+st "busy"
+ju 2
+blo "33000,60300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "busy"
+t "std_logic"
+o 19
+i "'1'"
+)
+)
+)
+*21 (CptPort
+uid 95,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 96,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,53625,0,54375"
+)
+tg (CPTG
+uid 97,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 98,0
+va (VaSet
+)
+xt "1000,53500,7800,54500"
+st "write_header_flag"
+blo "1000,54300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "write_header_flag"
+t "std_logic"
+o 20
+)
+)
+)
+*22 (CptPort
+uid 99,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 100,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,54625,0,55375"
+)
+tg (CPTG
+uid 101,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 102,0
+va (VaSet
+)
+xt "1000,54500,6700,55500"
+st "write_end_flag"
+blo "1000,55300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "write_end_flag"
+t "std_logic"
+o 21
+)
+)
+)
+*23 (CptPort
+uid 103,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 104,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,55625,0,56375"
+)
+tg (CPTG
+uid 105,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 106,0
+va (VaSet
+)
+xt "1000,55500,8800,56500"
+st "fifo_channels : (3:0)"
+blo "1000,56300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "fifo_channels"
+t "std_logic_vector"
+b "(3 downto 0)"
+o 22
+)
+)
+)
+*24 (CptPort
+uid 107,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 108,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,60625,34750,61375"
+)
+tg (CPTG
+uid 109,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 110,0
+va (VaSet
+)
+xt "29400,60500,33000,61500"
+st "s_trigger"
+ju 2
+blo "33000,61300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "s_trigger"
+t "std_logic"
+o 23
+i "'0'"
+)
+)
+)
+*25 (CptPort
+uid 111,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 112,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,61625,34750,62375"
+)
+tg (CPTG
+uid 113,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 114,0
+va (VaSet
+)
+xt "26400,61500,33000,62500"
+st "c_trigger_enable"
+ju 2
+blo "33000,62300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "c_trigger_enable"
+t "std_logic"
+o 24
+i "'0'"
+)
+)
+)
+*26 (CptPort
+uid 115,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 116,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,62625,34750,63375"
+)
+tg (CPTG
+uid 117,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 118,0
+va (VaSet
+)
+xt "24200,62500,33000,63500"
+st "c_trigger_mult : (15:0)"
+ju 2
+blo "33000,63300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "c_trigger_mult"
+t "std_logic_vector"
+b "(15 DOWNTO 0)"
+o 25
+i "conv_std_logic_vector(0 ,16)"
+)
+)
+)
+*27 (CptPort
+uid 119,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 120,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,63625,34750,64375"
+)
+tg (CPTG
+uid 121,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 122,0
+va (VaSet
+)
+xt "20600,63500,33000,64500"
+st "memory_manager_config_start_o"
+ju 2
+blo "33000,64300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "memory_manager_config_start_o"
+t "std_logic"
+o 26
+i "'0'"
+)
+)
+)
+*28 (CptPort
+uid 123,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 124,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,56625,0,57375"
+)
+tg (CPTG
+uid 125,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 126,0
+va (VaSet
+)
+xt "1000,56500,13200,57500"
+st "memory_manager_config_valid_i"
+blo "1000,57300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "memory_manager_config_valid_i"
+t "std_logic"
+o 27
+)
+)
+)
+*29 (CptPort
+uid 127,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 128,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,64625,34750,65375"
+)
+tg (CPTG
+uid 129,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 130,0
+va (VaSet
+)
+xt "22300,64500,33000,65500"
+st "spi_interface_config_start_o"
+ju 2
+blo "33000,65300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "spi_interface_config_start_o"
+t "std_logic"
+o 28
+i "'0'"
+)
+)
+)
+*30 (CptPort
+uid 131,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 132,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,57625,0,58375"
+)
+tg (CPTG
+uid 133,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 134,0
+va (VaSet
+)
+xt "1000,57500,11500,58500"
+st "spi_interface_config_valid_i"
+blo "1000,58300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "spi_interface_config_valid_i"
+t "std_logic"
+o 29
+)
+)
+)
+*31 (CptPort
+uid 135,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 136,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,65625,34750,66375"
+)
+tg (CPTG
+uid 137,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 138,0
+va (VaSet
+)
+xt "28300,65500,33000,66500"
+st "dac_setting"
+ju 2
+blo "33000,66300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "dac_setting"
+t "dac_array_type"
+o 30
+i "DEFAULT_DAC"
+)
+)
+)
+*32 (CptPort
+uid 139,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 140,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,66625,34750,67375"
+)
+tg (CPTG
+uid 141,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 142,0
+va (VaSet
+)
+xt "28600,66500,33000,67500"
+st "roi_setting"
+ju 2
+blo "33000,67300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "roi_setting"
+t "roi_array_type"
+o 31
+i "DEFAULT_ROI"
+)
+)
+)
+*33 (CptPort
+uid 143,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 144,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,67625,34750,68375"
+)
+tg (CPTG
+uid 145,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 146,0
+va (VaSet
+)
+xt "26000,67500,33000,68500"
+st "runnumber : (31:0)"
+ju 2
+blo "33000,68300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "runnumber"
+t "std_logic_vector"
+b "(31 DOWNTO 0)"
+o 32
+i "conv_std_logic_vector(0 ,32)"
+)
+)
+)
+*34 (CptPort
+uid 147,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 148,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,68625,34750,69375"
+)
+tg (CPTG
+uid 149,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 150,0
+va (VaSet
+)
+xt "26700,68500,33000,69500"
+st "reset_trigger_id"
+ju 2
+blo "33000,69300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "reset_trigger_id"
+t "std_logic"
+o 33
+i "'0'"
+)
+)
+)
+*35 (CptPort
+uid 151,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 152,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,58625,0,59375"
+)
+tg (CPTG
+uid 153,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 154,0
+va (VaSet
+)
+xt "1000,58500,7200,59500"
+st "data_ram_empty"
+blo "1000,59300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "data_ram_empty"
+t "std_logic"
+o 34
+)
+)
+)
+*36 (CptPort
+uid 155,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 156,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,59625,0,60375"
+)
+tg (CPTG
+uid 157,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 158,0
+va (VaSet
+)
+xt "1000,59500,8500,60500"
+st "MAC_jumper : (1:0)"
+blo "1000,60300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "MAC_jumper"
+t "std_logic_vector"
+b "(1 downto 0)"
+o 35
+)
+)
+)
+*37 (CptPort
+uid 159,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 160,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,60625,0,61375"
+)
+tg (CPTG
+uid 161,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 162,0
+va (VaSet
+)
+xt "1000,60500,6800,61500"
+st "BoardID : (3:0)"
+blo "1000,61300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "BoardID"
+t "std_logic_vector"
+b "(3 downto 0)"
+o 36
+)
+)
+)
+*38 (CptPort
+uid 163,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 164,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "-750,61625,0,62375"
+)
+tg (CPTG
+uid 165,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 166,0
+va (VaSet
+)
+xt "1000,61500,6700,62500"
+st "CrateID : (1:0)"
+blo "1000,62300"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "CrateID"
+t "std_logic_vector"
+b "(1 downto 0)"
+o 37
+)
+)
+)
+*39 (CptPort
+uid 167,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 168,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,69625,34750,70375"
+)
+tg (CPTG
+uid 169,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 170,0
+va (VaSet
+)
+xt "27200,69500,33000,70500"
+st "trigger_enable"
+ju 2
+blo "33000,70300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "trigger_enable"
+t "std_logic"
+o 38
+)
+)
+)
+*40 (CptPort
+uid 171,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 172,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,70625,34750,71375"
+)
+tg (CPTG
+uid 173,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 174,0
+va (VaSet
+)
+xt "30000,70500,33000,71500"
+st "denable"
+ju 2
+blo "33000,71300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "denable"
+t "std_logic"
+o 39
+i "'0'"
+)
+)
+)
+*41 (CptPort
+uid 175,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 176,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,71625,34750,72375"
+)
+tg (CPTG
+uid 177,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 178,0
+va (VaSet
+)
+xt "27600,71500,33000,72500"
+st "dwrite_enable"
+ju 2
+blo "33000,72300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "dwrite_enable"
+t "std_logic"
+o 40
+i "'1'"
+)
+)
+)
+*42 (CptPort
+uid 179,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 180,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,72625,34750,73375"
+)
+tg (CPTG
+uid 181,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 182,0
+va (VaSet
+)
+xt "28300,72500,33000,73500"
+st "sclk_enable"
+ju 2
+blo "33000,73300"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "sclk_enable"
+t "std_logic"
+o 41
+i "'1'"
+)
+)
+)
+*43 (CptPort
+uid 183,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 184,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "34000,73625,34750,74375"
+)
+tg (CPTG
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+)
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+i "'1'"
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+)
+)
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+)
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+)
+)
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+)
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+)
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+)
+)
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+)
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+)
+)
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+)
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+)
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+)
+)
+)
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+)
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+)
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+)
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+)
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+)
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+)
+)
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+)
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+)
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+"34750,56000"
+"51000,56000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"34750,58000"
+"51000,58000"
+]
+)
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+)
+)
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+)
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+)
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+"34750,59000"
+"51000,59000"
+]
+)
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+)
+)
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+)
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+)
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+"34750,60000"
+"51000,60000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"34750,61000"
+"51000,61000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+pts [
+"34750,62000"
+"51000,62000"
+]
+)
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+)
+)
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+)
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+)
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+"34750,63000"
+"51000,63000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"34750,64000"
+"51000,64000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"34750,65000"
+"51000,65000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"34750,66000"
+"51000,66000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"34750,67000"
+"51000,67000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"34750,68000"
+"51000,68000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+pts [
+"34750,69000"
+"51000,69000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+pts [
+"34750,70000"
+"51000,70000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"34750,71000"
+"51000,71000"
+]
+)
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+)
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+)
+)
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+)
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+)
+xt "34750,72000,51000,72000"
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+"34750,72000"
+"51000,72000"
+]
+)
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+)
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+st "dwrite_enable"
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+)
+)
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+)
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+)
+xt "34750,73000,51000,73000"
+pts [
+"34750,73000"
+"51000,73000"
+]
+)
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+)
+xt "36000,72000,40700,73000"
+st "sclk_enable"
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+)
+)
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+)
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+)
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+pts [
+"34750,74000"
+"51000,74000"
+]
+)
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+)
+xt "36000,73000,41000,74000"
+st "srclk_enable"
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+tm "WireNameMgr"
+)
+)
+on &78
+)
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+)
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+pts [
+"34750,75000"
+"51000,75000"
+]
+)
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+)
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+st "ps_direction"
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+)
+)
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+)
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+)
+xt "34750,76000,51000,76000"
+pts [
+"34750,76000"
+"51000,76000"
+]
+)
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+)
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+st "ps_do_phase_shift"
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+tm "WireNameMgr"
+)
+)
+on &80
+)
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+)
+xt "34750,77000,51000,77000"
+pts [
+"34750,77000"
+"51000,77000"
+]
+)
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+va (VaSet
+)
+xt "36000,76000,39300,77000"
+st "ps_reset"
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+tm "WireNameMgr"
+)
+)
+on &81
+)
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+va (VaSet
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+)
+xt "34750,78000,51000,78000"
+pts [
+"34750,78000"
+"51000,78000"
+]
+)
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+f (Text
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+va (VaSet
+)
+xt "36000,77000,41500,78000"
+st "socks_waiting"
+blo "36000,77800"
+tm "WireNameMgr"
+)
+)
+on &82
+)
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+va (VaSet
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+)
+xt "34750,79000,51000,79000"
+pts [
+"34750,79000"
+"51000,79000"
+]
+)
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+stg "STSignalDisplayStrategy"
+f (Text
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+va (VaSet
+)
+xt "36000,78000,42500,79000"
+st "socks_connected"
+blo "36000,78800"
+tm "WireNameMgr"
+)
+)
+on &83
+)
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+)
+xt "-19000,47000,-750,47000"
+pts [
+"-19000,47000"
+"-750,47000"
+]
+)
+end &5
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+sf 1
+si 0
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+stg "STSignalDisplayStrategy"
+f (Text
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+va (VaSet
+)
+xt "-18000,46000,-9500,47000"
+st "data_generator_idle_i"
+blo "-18000,46800"
+tm "WireNameMgr"
+)
+)
+on &84
+)
+*154 (Wire
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+va (VaSet
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+)
+xt "-19000,48000,-750,48000"
+pts [
+"-19000,48000"
+"-750,48000"
+]
+)
+end &6
+sat 16
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+sf 1
+si 0
+tg (WTG
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+)
+xt "-18000,47000,-16700,48000"
+st "clk"
+blo "-18000,47800"
+tm "WireNameMgr"
+)
+)
+on &85
+)
+*155 (Wire
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+shape (OrthoPolyLine
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+va (VaSet
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+)
+xt "-19000,49000,-750,49000"
+pts [
+"-19000,49000"
+"-750,49000"
+]
+)
+end &13
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+sf 1
+si 0
+tg (WTG
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+stg "STSignalDisplayStrategy"
+f (Text
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+va (VaSet
+)
+xt "-18000,48000,-16800,49000"
+st "int"
+blo "-18000,48800"
+tm "WireNameMgr"
+)
+)
+on &86
+)
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+shape (OrthoPolyLine
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+lineWidth 2
+)
+xt "-19000,50000,-750,50000"
+pts [
+"-19000,50000"
+"-750,50000"
+]
+)
+end &14
+sat 16
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+sf 1
+si 0
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+stg "STSignalDisplayStrategy"
+f (Text
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+va (VaSet
+)
+xt "-18000,49000,-10100,50000"
+st "write_length : (16:0)"
+blo "-18000,49800"
+tm "WireNameMgr"
+)
+)
+on &87
+)
+*157 (Wire
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+shape (OrthoPolyLine
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+va (VaSet
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+lineWidth 2
+)
+xt "-19000,51000,-750,51000"
+pts [
+"-19000,51000"
+"-750,51000"
+]
+)
+end &15
+sat 16
+eat 32
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+sf 1
+si 0
+tg (WTG
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+stg "STSignalDisplayStrategy"
+f (Text
+uid 524,0
+va (VaSet
+)
+xt "-18000,50000,-9100,51000"
+st "ram_start_addr : (13:0)"
+blo "-18000,50800"
+tm "WireNameMgr"
+)
+)
+on &88
+)
+*158 (Wire
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+shape (OrthoPolyLine
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+va (VaSet
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+lineWidth 2
+)
+xt "-19000,52000,-750,52000"
+pts [
+"-19000,52000"
+"-750,52000"
+]
+)
+end &16
+sat 16
+eat 32
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+st 0
+sf 1
+si 0
+tg (WTG
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+stg "STSignalDisplayStrategy"
+f (Text
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+va (VaSet
+)
+xt "-18000,51000,-11500,52000"
+st "ram_data : (15:0)"
+blo "-18000,51800"
+tm "WireNameMgr"
+)
+)
+on &89
+)
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+shape (OrthoPolyLine
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+va (VaSet
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+)
+xt "-19000,53000,-750,53000"
+pts [
+"-19000,53000"
+"-750,53000"
+]
+)
+end &18
+sat 16
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+sf 1
+si 0
+tg (WTG
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+stg "STSignalDisplayStrategy"
+f (Text
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+va (VaSet
+)
+xt "-18000,52000,-13900,53000"
+st "data_valid"
+blo "-18000,52800"
+tm "WireNameMgr"
+)
+)
+on &90
+)
+*160 (Wire
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+shape (OrthoPolyLine
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+va (VaSet
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+)
+xt "-19000,54000,-750,54000"
+pts [
+"-19000,54000"
+"-750,54000"
+]
+)
+end &21
+sat 16
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+sf 1
+si 0
+tg (WTG
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+stg "STSignalDisplayStrategy"
+f (Text
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+va (VaSet
+)
+xt "-18000,53000,-11200,54000"
+st "write_header_flag"
+blo "-18000,53800"
+tm "WireNameMgr"
+)
+)
+on &91
+)
+*161 (Wire
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+shape (OrthoPolyLine
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+va (VaSet
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+)
+xt "-19000,55000,-750,55000"
+pts [
+"-19000,55000"
+"-750,55000"
+]
+)
+end &22
+sat 16
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+sf 1
+si 0
+tg (WTG
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+stg "STSignalDisplayStrategy"
+f (Text
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+va (VaSet
+)
+xt "-18000,54000,-12300,55000"
+st "write_end_flag"
+blo "-18000,54800"
+tm "WireNameMgr"
+)
+)
+on &92
+)
+*162 (Wire
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+shape (OrthoPolyLine
+uid 560,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "-19000,56000,-750,56000"
+pts [
+"-19000,56000"
+"-750,56000"
+]
+)
+end &23
+sat 16
+eat 32
+sty 1
+st 0
+sf 1
+si 0
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 564,0
+va (VaSet
+)
+xt "-18000,55000,-10200,56000"
+st "fifo_channels : (3:0)"
+blo "-18000,55800"
+tm "WireNameMgr"
+)
+)
+on &93
+)
+*163 (Wire
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+shape (OrthoPolyLine
+uid 568,0
+va (VaSet
+vasetType 3
+)
+xt "-19000,57000,-750,57000"
+pts [
+"-19000,57000"
+"-750,57000"
+]
+)
+end &28
+sat 16
+eat 32
+st 0
+sf 1
+si 0
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 572,0
+va (VaSet
+)
+xt "-18000,56000,-5800,57000"
+st "memory_manager_config_valid_i"
+blo "-18000,56800"
+tm "WireNameMgr"
+)
+)
+on &94
+)
+*164 (Wire
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+shape (OrthoPolyLine
+uid 576,0
+va (VaSet
+vasetType 3
+)
+xt "-19000,58000,-750,58000"
+pts [
+"-19000,58000"
+"-750,58000"
+]
+)
+end &30
+sat 16
+eat 32
+st 0
+sf 1
+si 0
+tg (WTG
+uid 579,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 580,0
+va (VaSet
+)
+xt "-18000,57000,-7500,58000"
+st "spi_interface_config_valid_i"
+blo "-18000,57800"
+tm "WireNameMgr"
+)
+)
+on &95
+)
+*165 (Wire
+uid 583,0
+shape (OrthoPolyLine
+uid 584,0
+va (VaSet
+vasetType 3
+)
+xt "-19000,59000,-750,59000"
+pts [
+"-19000,59000"
+"-750,59000"
+]
+)
+end &35
+sat 16
+eat 32
+st 0
+sf 1
+si 0
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 588,0
+va (VaSet
+)
+xt "-18000,58000,-11800,59000"
+st "data_ram_empty"
+blo "-18000,58800"
+tm "WireNameMgr"
+)
+)
+on &96
+)
+*166 (Wire
+uid 591,0
+shape (OrthoPolyLine
+uid 592,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "-19000,60000,-750,60000"
+pts [
+"-19000,60000"
+"-750,60000"
+]
+)
+end &36
+sat 16
+eat 32
+sty 1
+st 0
+sf 1
+si 0
+tg (WTG
+uid 595,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 596,0
+va (VaSet
+)
+xt "-18000,59000,-10500,60000"
+st "MAC_jumper : (1:0)"
+blo "-18000,59800"
+tm "WireNameMgr"
+)
+)
+on &97
+)
+*167 (Wire
+uid 599,0
+shape (OrthoPolyLine
+uid 600,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "-19000,61000,-750,61000"
+pts [
+"-19000,61000"
+"-750,61000"
+]
+)
+end &37
+sat 16
+eat 32
+sty 1
+st 0
+sf 1
+si 0
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 604,0
+va (VaSet
+)
+xt "-18000,60000,-12200,61000"
+st "BoardID : (3:0)"
+blo "-18000,60800"
+tm "WireNameMgr"
+)
+)
+on &98
+)
+*168 (Wire
+uid 607,0
+shape (OrthoPolyLine
+uid 608,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "-19000,62000,-750,62000"
+pts [
+"-19000,62000"
+"-750,62000"
+]
+)
+end &38
+sat 16
+eat 32
+sty 1
+st 0
+sf 1
+si 0
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 612,0
+va (VaSet
+)
+xt "-18000,61000,-12300,62000"
+st "CrateID : (1:0)"
+blo "-18000,61800"
+tm "WireNameMgr"
+)
+)
+on &99
+)
+*169 (Wire
+uid 615,0
+shape (OrthoPolyLine
+uid 616,0
+va (VaSet
+vasetType 3
+)
+xt "-19000,63000,-750,63000"
+pts [
+"-19000,63000"
+"-750,63000"
+]
+)
+end &47
+sat 16
+eat 32
+st 0
+sf 1
+si 0
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 620,0
+va (VaSet
+)
+xt "-18000,62000,-14600,63000"
+st "ps_ready"
+blo "-18000,62800"
+tm "WireNameMgr"
+)
+)
+on &100
+)
+*170 (Wire
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+shape (OrthoPolyLine
+uid 640,0
+va (VaSet
+vasetType 3
+)
+xt "108000,58000,125000,58000"
+pts [
+"108000,58000"
+"125000,58000"
+]
+)
+start &101
+sat 1
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 646,0
+va (VaSet
+)
+xt "109000,57000,114600,58000"
+st "data_valid_ack"
+blo "109000,57800"
+tm "WireNameMgr"
+)
+)
+on &63
+)
+*171 (Wire
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+shape (OrthoPolyLine
+uid 648,0
+va (VaSet
+vasetType 3
+)
+xt "108000,50000,125000,50000"
+pts [
+"108000,50000"
+"125000,50000"
+]
+)
+start &101
+sat 1
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 654,0
+va (VaSet
+)
+xt "109000,49000,112600,50000"
+st "wiz_reset"
+blo "109000,49800"
+tm "WireNameMgr"
+)
+)
+on &56
+)
+*172 (Wire
+uid 655,0
+shape (OrthoPolyLine
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+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "68000,29000,93250,33000"
+pts [
+"68000,33000"
+"93250,29000"
+]
+)
+end &114
+es 0
+sat 16
+eat 32
+sty 1
+st 0
+sf 1
+si 0
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 662,0
+va (VaSet
+)
+xt "69000,32000,73800,33000"
+st "data : (15:0)"
+blo "69000,32800"
+tm "WireNameMgr"
+)
+)
+on &58
+)
+*173 (Wire
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+shape (OrthoPolyLine
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+va (VaSet
+vasetType 3
+)
+xt "108000,59000,125000,59000"
+pts [
+"108000,59000"
+"125000,59000"
+]
+)
+start &101
+sat 1
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+st 0
+sf 1
+si 0
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 670,0
+va (VaSet
+)
+xt "109000,58000,110900,59000"
+st "busy"
+blo "109000,58800"
+tm "WireNameMgr"
+)
+)
+on &64
+)
+*174 (Wire
+uid 671,0
+shape (OrthoPolyLine
+uid 672,0
+va (VaSet
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+)
+xt "108000,63000,125000,63000"
+pts [
+"108000,63000"
+"125000,63000"
+]
+)
+start &101
+sat 1
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 677,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 678,0
+va (VaSet
+)
+xt "109000,62000,121400,63000"
+st "memory_manager_config_start_o"
+blo "109000,62800"
+tm "WireNameMgr"
+)
+)
+on &68
+)
+*175 (Wire
+uid 679,0
+shape (OrthoPolyLine
+uid 680,0
+va (VaSet
+vasetType 3
+)
+xt "108000,47000,125000,47000"
+pts [
+"108000,47000"
+"125000,47000"
+]
+)
+start &101
+sat 1
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 686,0
+va (VaSet
+)
+xt "109000,46000,118100,47000"
+st "debug_data_ram_empty"
+blo "109000,46800"
+tm "WireNameMgr"
+)
+)
+on &54
+)
+*176 (Wire
+uid 687,0
+shape (OrthoPolyLine
+uid 688,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "108000,46000,125000,46000"
+pts [
+"108000,46000"
+"125000,46000"
+]
+)
+start &101
+sat 1
+eat 16
+sty 1
+st 0
+sf 1
+si 0
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 694,0
+va (VaSet
+)
+xt "109000,45000,113600,46000"
+st "state : (7:0)"
+blo "109000,45800"
+tm "WireNameMgr"
+)
+)
+on &53
+)
+*177 (Wire
+uid 695,0
+shape (OrthoPolyLine
+uid 696,0
+va (VaSet
+vasetType 3
+)
+xt "108000,61000,125000,61000"
+pts [
+"108000,61000"
+"125000,61000"
+]
+)
+start &101
+sat 1
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 701,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 702,0
+va (VaSet
+)
+xt "109000,60000,115600,61000"
+st "c_trigger_enable"
+blo "109000,60800"
+tm "WireNameMgr"
+)
+)
+on &66
+)
+*178 (Wire
+uid 711,0
+shape (OrthoPolyLine
+uid 712,0
+va (VaSet
+vasetType 3
+)
+xt "108000,48000,125000,48000"
+pts [
+"108000,48000"
+"125000,48000"
+]
+)
+start &101
+sat 1
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 717,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 718,0
+va (VaSet
+)
+xt "109000,47000,115600,48000"
+st "debug_data_valid"
+blo "109000,47800"
+tm "WireNameMgr"
+)
+)
+on &55
+)
+*179 (Wire
+uid 719,0
+shape (OrthoPolyLine
+uid 720,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "108000,57000,125000,57000"
+pts [
+"108000,57000"
+"125000,57000"
+]
+)
+start &101
+sat 1
+eat 16
+sty 1
+st 0
+sf 1
+si 0
+tg (WTG
+uid 725,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 726,0
+va (VaSet
+)
+xt "110000,56000,116600,57000"
+st "ram_addr : (13:0)"
+blo "110000,56800"
+tm "WireNameMgr"
+)
+)
+on &62
+)
+*180 (Wire
+uid 727,0
+shape (OrthoPolyLine
+uid 728,0
+va (VaSet
+vasetType 3
+)
+xt "108000,60000,125000,60000"
+pts [
+"108000,60000"
+"125000,60000"
+]
+)
+start &101
+sat 1
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 733,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 734,0
+va (VaSet
+)
+xt "109000,59000,112600,60000"
+st "s_trigger"
+blo "109000,59800"
+tm "WireNameMgr"
+)
+)
+on &65
+)
+*181 (Wire
+uid 735,0
+shape (OrthoPolyLine
+uid 736,0
+va (VaSet
+vasetType 3
+)
+xt "71000,33000,93250,34000"
+pts [
+"71000,34000"
+"93250,33000"
+]
+)
+end &116
+sat 16
+eat 32
+st 0
+sf 1
+si 0
+tg (WTG
+uid 741,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 742,0
+va (VaSet
+)
+xt "72000,33000,73200,34000"
+st "wr"
+blo "72000,33800"
+tm "WireNameMgr"
+)
+)
+on &60
+)
+*182 (Wire
+uid 743,0
+shape (OrthoPolyLine
+uid 744,0
+va (VaSet
+vasetType 3
+)
+xt "63000,32000,93250,35000"
+pts [
+"63000,35000"
+"93250,32000"
+]
+)
+end &115
+es 0
+sat 16
+eat 32
+st 0
+sf 1
+si 0
+tg (WTG
+uid 749,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 750,0
+va (VaSet
+)
+xt "64000,34000,65100,35000"
+st "rd"
+blo "64000,34800"
+tm "WireNameMgr"
+)
+)
+on &61
+)
+*183 (Wire
+uid 751,0
+shape (OrthoPolyLine
+uid 752,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "70000,28000,93250,30000"
+pts [
+"70000,30000"
+"93250,28000"
+]
+)
+end &113
+es 0
+sat 16
+eat 32
+sty 1
+st 0
+sf 1
+si 0
+tg (WTG
+uid 757,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 758,0
+va (VaSet
+)
+xt "71000,29000,75500,30000"
+st "addr : (9:0)"
+blo "71000,29800"
+tm "WireNameMgr"
+)
+)
+on &57
+)
+*184 (Wire
+uid 759,0
+shape (OrthoPolyLine
+uid 760,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "108000,67000,125000,67000"
+pts [
+"108000,67000"
+"125000,67000"
+]
+)
+start &101
+sat 1
+eat 16
+sty 1
+st 0
+sf 1
+si 0
+tg (WTG
+uid 765,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 766,0
+va (VaSet
+)
+xt "109000,66000,116000,67000"
+st "runnumber : (31:0)"
+blo "109000,66800"
+tm "WireNameMgr"
+)
+)
+on &72
+)
+*185 (Wire
+uid 767,0
+shape (OrthoPolyLine
+uid 768,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "55000,49000,74000,49000"
+pts [
+"55000,49000"
+"74000,49000"
+]
+)
+end &101
+sat 16
+eat 2
+sty 1
+st 0
+sf 1
+si 0
+tg (WTG
+uid 773,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 774,0
+va (VaSet
+)
+xt "56000,48000,63900,49000"
+st "write_length : (16:0)"
+blo "56000,48800"
+tm "WireNameMgr"
+)
+)
+on &87
+)
+*186 (Wire
+uid 775,0
+shape (OrthoPolyLine
+uid 776,0
+va (VaSet
+vasetType 3
+)
+xt "108000,70000,125000,70000"
+pts [
+"108000,70000"
+"125000,70000"
+]
+)
+start &101
+sat 1
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 781,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 782,0
+va (VaSet
+)
+xt "109000,69000,112000,70000"
+st "denable"
+blo "109000,69800"
+tm "WireNameMgr"
+)
+)
+on &75
+)
+*187 (Wire
+uid 783,0
+shape (OrthoPolyLine
+uid 784,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "55000,50000,74000,50000"
+pts [
+"55000,50000"
+"74000,50000"
+]
+)
+end &101
+sat 16
+eat 2
+sty 1
+st 0
+sf 1
+si 0
+tg (WTG
+uid 789,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 790,0
+va (VaSet
+)
+xt "57000,49000,65900,50000"
+st "ram_start_addr : (13:0)"
+blo "57000,49800"
+tm "WireNameMgr"
+)
+)
+on &88
+)
+*188 (Wire
+uid 791,0
+shape (OrthoPolyLine
+uid 792,0
+va (VaSet
+vasetType 3
+)
+xt "108000,71000,125000,71000"
+pts [
+"108000,71000"
+"125000,71000"
+]
+)
+start &101
+sat 1
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 797,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 798,0
+va (VaSet
+)
+xt "109000,70000,114400,71000"
+st "dwrite_enable"
+blo "109000,70800"
+tm "WireNameMgr"
+)
+)
+on &76
+)
+*189 (Wire
+uid 799,0
+shape (OrthoPolyLine
+uid 800,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "55000,51000,74000,51000"
+pts [
+"55000,51000"
+"74000,51000"
+]
+)
+end &101
+sat 16
+eat 2
+sty 1
+st 0
+sf 1
+si 0
+tg (WTG
+uid 805,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 806,0
+va (VaSet
+)
+xt "56000,50000,62500,51000"
+st "ram_data : (15:0)"
+blo "56000,50800"
+tm "WireNameMgr"
+)
+)
+on &89
+)
+*190 (Wire
+uid 807,0
+shape (OrthoPolyLine
+uid 808,0
+va (VaSet
+vasetType 3
+)
+xt "108000,73000,125000,73000"
+pts [
+"108000,73000"
+"125000,73000"
+]
+)
+start &101
+sat 1
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 813,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 814,0
+va (VaSet
+)
+xt "109000,72000,114000,73000"
+st "srclk_enable"
+blo "109000,72800"
+tm "WireNameMgr"
+)
+)
+on &78
+)
+*191 (Wire
+uid 815,0
+shape (OrthoPolyLine
+uid 816,0
+va (VaSet
+vasetType 3
+)
+xt "108000,68000,125000,68000"
+pts [
+"108000,68000"
+"125000,68000"
+]
+)
+start &101
+sat 1
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 821,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 822,0
+va (VaSet
+)
+xt "109000,67000,115300,68000"
+st "reset_trigger_id"
+blo "109000,67800"
+tm "WireNameMgr"
+)
+)
+on &73
+)
+*192 (Wire
+uid 823,0
+shape (OrthoPolyLine
+uid 824,0
+va (VaSet
+vasetType 3
+)
+xt "108000,74000,125000,74000"
+pts [
+"108000,74000"
+"125000,74000"
+]
+)
+start &101
+sat 1
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 829,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 830,0
+va (VaSet
+)
+xt "109000,73000,113900,74000"
+st "ps_direction"
+blo "109000,73800"
+tm "WireNameMgr"
+)
+)
+on &79
+)
+*193 (Wire
+uid 831,0
+shape (OrthoPolyLine
+uid 832,0
+va (VaSet
+vasetType 3
+)
+xt "108000,65000,125000,65000"
+pts [
+"108000,65000"
+"125000,65000"
+]
+)
+start &101
+sat 1
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
+uid 837,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 838,0
+va (VaSet
+)
+xt "109000,64000,113700,65000"
+st "dac_setting"
+blo "109000,64800"
+tm "WireNameMgr"
+)
+)
+on &70
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Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/w5300_modul2_tb/symbol.sb
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/w5300_modul2_tb/symbol.sb	(revision 10914)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/w5300_modul2_tb/symbol.sb	(revision 10914)
@@ -0,0 +1,1235 @@
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Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/w5300_modul2_tb/symbol.sb.bak
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/w5300_modul2_tb/symbol.sb.bak	(revision 10914)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/w5300_modul2_tb/symbol.sb.bak	(revision 10914)
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Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/w5300_modul2_tester/interface
===================================================================
--- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/w5300_modul2_tester/interface	(revision 10914)
+++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_TB_lib/hds/w5300_modul2_tester/interface	(revision 10914)
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+)
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+)
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+)
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+)
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+)
+*119 (TypeColHdr
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+)
+*120 (InitColHdr
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+)
+*121 (PragmaColHdr
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+)
+*122 (EolColHdr
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+)
+]
+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
+(vvPair
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+)
+(vvPair
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+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tester\\interface.info"
+)
+(vvPair
+variable "SideDataUserDir"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tester\\interface.user"
+)
+(vvPair
+variable "SourceDir"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds"
+)
+(vvPair
+variable "appl"
+value "HDL Designer"
+)
+(vvPair
+variable "arch_name"
+value "interface"
+)
+(vvPair
+variable "config"
+value "%(unit)_%(view)_config"
+)
+(vvPair
+variable "d"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tester"
+)
+(vvPair
+variable "d_logical"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tester"
+)
+(vvPair
+variable "date"
+value "01.06.2011"
+)
+(vvPair
+variable "day"
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+)
+(vvPair
+variable "day_long"
+value "Mittwoch"
+)
+(vvPair
+variable "dd"
+value "01"
+)
+(vvPair
+variable "entity_name"
+value "w5300_modul2_tester"
+)
+(vvPair
+variable "ext"
+value "<TBD>"
+)
+(vvPair
+variable "f"
+value "interface"
+)
+(vvPair
+variable "f_logical"
+value "interface"
+)
+(vvPair
+variable "f_noext"
+value "interface"
+)
+(vvPair
+variable "group"
+value "UNKNOWN"
+)
+(vvPair
+variable "host"
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+)
+(vvPair
+variable "language"
+value "VHDL"
+)
+(vvPair
+variable "library"
+value "FACT_FAD_TB_lib"
+)
+(vvPair
+variable "library_downstream_HdsLintPlugin"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/designcheck"
+)
+(vvPair
+variable "library_downstream_ISEPARInvoke"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
+)
+(vvPair
+variable "library_downstream_ImpactInvoke"
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+)
+(vvPair
+variable "library_downstream_ModelSimCompiler"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/work"
+)
+(vvPair
+variable "library_downstream_XSTDataPrep"
+value "$HDS_PROJECT_DIR/FACT_FAD_TB_lib/ise"
+)
+(vvPair
+variable "mm"
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+)
+(vvPair
+variable "module_name"
+value "w5300_modul2_tester"
+)
+(vvPair
+variable "month"
+value "Jun"
+)
+(vvPair
+variable "month_long"
+value "Juni"
+)
+(vvPair
+variable "p"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tester\\interface"
+)
+(vvPair
+variable "p_logical"
+value "C:\\fact.isdc.unige.ch_svn_firmware\\FAD\\FACT_FAD_20MHz_VAR_PS\\FACT_FAD_TB_lib\\hds\\w5300_modul2_tester\\interface"
+)
+(vvPair
+variable "package_name"
+value "<Undefined Variable>"
+)
+(vvPair
+variable "project_name"
+value "FACT_FAD"
+)
+(vvPair
+variable "series"
+value "HDL Designer Series"
+)
+(vvPair
+variable "task_DesignCompilerPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_LeonardoPath"
+value "<TBD>"
+)
+(vvPair
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+value "C:\\modeltech_6.6a\\win32"
+)
+(vvPair
+variable "task_NC-SimPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_PrecisionRTLPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_QuestaSimPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_VCSPath"
+value "<TBD>"
+)
+(vvPair
+variable "this_ext"
+value "<TBD>"
+)
+(vvPair
+variable "this_file"
+value "interface"
+)
+(vvPair
+variable "this_file_logical"
+value "interface"
+)
+(vvPair
+variable "time"
+value "09:26:48"
+)
+(vvPair
+variable "unit"
+value "w5300_modul2_tester"
+)
+(vvPair
+variable "user"
+value "dneise"
+)
+(vvPair
+variable "version"
+value "2009.2 (Build 10)"
+)
+(vvPair
+variable "view"
+value "interface"
+)
+(vvPair
+variable "year"
+value "2011"
+)
+(vvPair
+variable "yy"
+value "11"
+)
+]
+)
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+)
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+uid 2383,0
+va (VaSet
+font "Courier New,8,0"
+)
+)
+thePort (LogicalPort
+lang 10
+m 1
+decl (Decl
+n "fifo_channels"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 34
+suid 310,0
+)
+)
+)
+*152 (CptPort
+uid 2384,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 2385,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "14250,19625,15000,20375"
+)
+tg (CPTG
+uid 2386,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 2387,0
+va (VaSet
+)
+xt "16000,19500,21300,20500"
+st "MAC_jumper"
+blo "16000,20300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 2388,0
+va (VaSet
+font "Courier New,8,0"
+)
+)
+thePort (LogicalPort
+lang 10
+m 1
+decl (Decl
+n "MAC_jumper"
+t "std_logic_vector"
+b "(1 DOWNTO 0)"
+o 30
+suid 311,0
+)
+)
+)
+*153 (CptPort
+uid 2389,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 2390,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "49000,23625,49750,24375"
+)
+tg (CPTG
+uid 2391,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 2392,0
+va (VaSet
+)
+xt "35600,23500,48000,24500"
+st "memory_manager_config_start_o"
+ju 2
+blo "48000,24300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 2393,0
+va (VaSet
+font "Courier New,8,0"
+)
+)
+thePort (LogicalPort
+lang 10
+decl (Decl
+n "memory_manager_config_start_o"
+t "std_logic"
+o 11
+suid 312,0
+)
+)
+)
+*154 (CptPort
+uid 2394,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 2395,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "14250,16625,15000,17375"
+)
+tg (CPTG
+uid 2396,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 2397,0
+va (VaSet
+)
+xt "16000,16500,28200,17500"
+st "memory_manager_config_valid_i"
+blo "16000,17300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 2398,0
+va (VaSet
+font "Courier New,8,0"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "memory_manager_config_valid_i"
+t "std_logic"
+o 35
+suid 313,0
+)
+)
+)
+*155 (CptPort
+uid 2399,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 2400,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "49000,34625,49750,35375"
+)
+tg (CPTG
+uid 2401,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 2402,0
+va (VaSet
+)
+xt "43100,34500,48000,35500"
+st "ps_direction"
+ju 2
+blo "48000,35300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 2403,0
+va (VaSet
+font "Courier New,8,0"
+)
+)
+thePort (LogicalPort
+lang 10
+decl (Decl
+n "ps_direction"
+t "std_logic"
+o 12
+suid 314,0
+)
+)
+)
+*156 (CptPort
+uid 2404,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 2405,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "49000,35625,49750,36375"
+)
+tg (CPTG
+uid 2406,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 2407,0
+va (VaSet
+)
+xt "41000,35500,48000,36500"
+st "ps_do_phase_shift"
+ju 2
+blo "48000,36300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 2408,0
+va (VaSet
+font "Courier New,8,0"
+)
+)
+thePort (LogicalPort
+lang 10
+decl (Decl
+n "ps_do_phase_shift"
+t "std_logic"
+o 13
+suid 315,0
+)
+)
+)
+*157 (CptPort
+uid 2409,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 2410,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "14250,22625,15000,23375"
+)
+tg (CPTG
+uid 2411,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 2412,0
+va (VaSet
+)
+xt "16000,22500,19400,23500"
+st "ps_ready"
+blo "16000,23300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 2413,0
+va (VaSet
+font "Courier New,8,0"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "ps_ready"
+t "std_logic"
+o 36
+suid 316,0
+)
+)
+)
+*158 (CptPort
+uid 2414,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 2415,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "49000,36625,49750,37375"
+)
+tg (CPTG
+uid 2416,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 2417,0
+va (VaSet
+)
+xt "44700,36500,48000,37500"
+st "ps_reset"
+ju 2
+blo "48000,37300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 2418,0
+va (VaSet
+font "Courier New,8,0"
+)
+)
+thePort (LogicalPort
+lang 10
+decl (Decl
+n "ps_reset"
+t "std_logic"
+o 14
+suid 317,0
+)
+)
+)
+*159 (CptPort
+uid 2419,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 2420,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "49000,17625,49750,18375"
+)
+tg (CPTG
+uid 2421,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 2422,0
+va (VaSet
+)
+xt "44400,17500,48000,18500"
+st "ram_addr"
+ju 2
+blo "48000,18300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 2423,0
+va (VaSet
+font "Courier New,8,0"
+)
+)
+thePort (LogicalPort
+lang 10
+decl (Decl
+n "ram_addr"
+t "std_logic_vector"
+b "(13 DOWNTO 0)"
+o 15
+suid 318,0
+)
+)
+)
+*160 (CptPort
+uid 2424,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 2425,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "14250,11625,15000,12375"
+)
+tg (CPTG
+uid 2426,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 2427,0
+va (VaSet
+)
+xt "16000,11500,19500,12500"
+st "ram_data"
+blo "16000,12300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 2428,0
+va (VaSet
+font "Courier New,8,0"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "ram_data"
+t "std_logic_vector"
+b "(15 DOWNTO 0)"
+o 37
+suid 319,0
+)
+)
+)
+*161 (CptPort
+uid 2429,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 2430,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "14250,10625,15000,11375"
+)
+tg (CPTG
+uid 2431,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 2432,0
+va (VaSet
+)
+xt "16000,10500,21900,11500"
+st "ram_start_addr"
+blo "16000,11300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 2433,0
+va (VaSet
+font "Courier New,8,0"
+)
+)
+thePort (LogicalPort
+lang 10
+m 1
+decl (Decl
+n "ram_start_addr"
+t "std_logic_vector"
+b "(13 DOWNTO 0)"
+o 38
+suid 320,0
+)
+)
+)
+*162 (CptPort
+uid 2434,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 2435,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "49000,28625,49750,29375"
+)
+tg (CPTG
+uid 2436,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 2437,0
+va (VaSet
+)
+xt "41700,28500,48000,29500"
+st "reset_trigger_id"
+ju 2
+blo "48000,29300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 2438,0
+va (VaSet
+font "Courier New,8,0"
+)
+)
+thePort (LogicalPort
+lang 10
+decl (Decl
+n "reset_trigger_id"
+t "std_logic"
+o 16
+suid 321,0
+)
+)
+)
+*163 (CptPort
+uid 2439,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 2440,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "49000,26625,49750,27375"
+)
+tg (CPTG
+uid 2441,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 2442,0
+va (VaSet
+)
+xt "43600,26500,48000,27500"
+st "roi_setting"
+ju 2
+blo "48000,27300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 2443,0
+va (VaSet
+font "Courier New,8,0"
+)
+)
+thePort (LogicalPort
+lang 10
+decl (Decl
+n "roi_setting"
+t "roi_array_type"
+o 17
+suid 322,0
+)
+)
+)
+*164 (CptPort
+uid 2444,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 2445,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "49000,27625,49750,28375"
+)
+tg (CPTG
+uid 2446,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 2447,0
+va (VaSet
+)
+xt "44000,27500,48000,28500"
+st "runnumber"
+ju 2
+blo "48000,28300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 2448,0
+va (VaSet
+font "Courier New,8,0"
+)
+)
+thePort (LogicalPort
+lang 10
+decl (Decl
+n "runnumber"
+t "std_logic_vector"
+b "(31 DOWNTO 0)"
+o 18
+suid 323,0
+)
+)
+)
+*165 (CptPort
+uid 2449,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 2450,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "49000,20625,49750,21375"
+)
+tg (CPTG
+uid 2451,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 2452,0
+va (VaSet
+)
+xt "44400,20500,48000,21500"
+st "s_trigger"
+ju 2
+blo "48000,21300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 2453,0
+va (VaSet
+font "Courier New,8,0"
+)
+)
+thePort (LogicalPort
+lang 10
+decl (Decl
+n "s_trigger"
+t "std_logic"
+o 19
+suid 324,0
+)
+)
+)
+*166 (CptPort
+uid 2454,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 2455,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "49000,32625,49750,33375"
+)
+tg (CPTG
+uid 2456,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 2457,0
+va (VaSet
+)
+xt "43300,32500,48000,33500"
+st "sclk_enable"
+ju 2
+blo "48000,33300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 2458,0
+va (VaSet
+font "Courier New,8,0"
+)
+)
+thePort (LogicalPort
+lang 10
+decl (Decl
+n "sclk_enable"
+t "std_logic"
+o 20
+suid 325,0
+)
+)
+)
+*167 (CptPort
+uid 2459,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 2460,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "49000,38625,49750,39375"
+)
+tg (CPTG
+uid 2461,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 2462,0
+va (VaSet
+)
+xt "41500,38500,48000,39500"
+st "socks_connected"
+ju 2
+blo "48000,39300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 2463,0
+va (VaSet
+font "Courier New,8,0"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "socks_connected"
+t "std_logic"
+o 21
+suid 326,0
+)
+)
+)
+*168 (CptPort
+uid 2464,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 2465,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "49000,37625,49750,38375"
+)
+tg (CPTG
+uid 2466,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 2467,0
+va (VaSet
+)
+xt "42500,37500,48000,38500"
+st "socks_waiting"
+ju 2
+blo "48000,38300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 2468,0
+va (VaSet
+font "Courier New,8,0"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "socks_waiting"
+t "std_logic"
+o 22
+suid 327,0
+)
+)
+)
+*169 (CptPort
+uid 2469,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 2470,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "49000,24625,49750,25375"
+)
+tg (CPTG
+uid 2471,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 2472,0
+va (VaSet
+)
+xt "37300,24500,48000,25500"
+st "spi_interface_config_start_o"
+ju 2
+blo "48000,25300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 2473,0
+va (VaSet
+font "Courier New,8,0"
+)
+)
+thePort (LogicalPort
+lang 10
+decl (Decl
+n "spi_interface_config_start_o"
+t "std_logic"
+o 23
+suid 328,0
+)
+)
+)
+*170 (CptPort
+uid 2474,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 2475,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "14250,17625,15000,18375"
+)
+tg (CPTG
+uid 2476,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 2477,0
+va (VaSet
+)
+xt "16000,17500,26500,18500"
+st "spi_interface_config_valid_i"
+blo "16000,18300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 2478,0
+va (VaSet
+font "Courier New,8,0"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "spi_interface_config_valid_i"
+t "std_logic"
+o 39
+suid 329,0
+)
+)
+)
+*171 (CptPort
+uid 2479,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 2480,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "49000,33625,49750,34375"
+)
+tg (CPTG
+uid 2481,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 2482,0
+va (VaSet
+)
+xt "43000,33500,48000,34500"
+st "srclk_enable"
+ju 2
+blo "48000,34300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 2483,0
+va (VaSet
+font "Courier New,8,0"
+)
+)
+thePort (LogicalPort
+lang 10
+decl (Decl
+n "srclk_enable"
+t "std_logic"
+o 24
+suid 330,0
+)
+)
+)
+*172 (CptPort
+uid 2484,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 2485,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "49000,6625,49750,7375"
+)
+tg (CPTG
+uid 2486,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 2487,0
+va (VaSet
+)
+xt "46000,6500,48000,7500"
+st "state"
+ju 2
+blo "48000,7300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 2488,0
+va (VaSet
+font "Courier New,8,0"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "state"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+o 25
+suid 331,0
+)
+)
+)
+*173 (CptPort
+uid 2489,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 2490,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "49000,29625,49750,30375"
+)
+tg (CPTG
+uid 2491,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 2492,0
+va (VaSet
+)
+xt "42200,29500,48000,30500"
+st "trigger_enable"
+ju 2
+blo "48000,30300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 2493,0
+va (VaSet
+font "Courier New,8,0"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "trigger_enable"
+t "std_logic"
+o 26
+suid 332,0
+)
+)
+)
+*174 (CptPort
+uid 2494,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 2495,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "49000,10625,49750,11375"
+)
+tg (CPTG
+uid 2496,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 2497,0
+va (VaSet
+)
+xt "44400,10500,48000,11500"
+st "wiz_reset"
+ju 2
+blo "48000,11300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 2498,0
+va (VaSet
+font "Courier New,8,0"
+)
+)
+thePort (LogicalPort
+lang 10
+decl (Decl
+n "wiz_reset"
+t "std_logic"
+o 27
+suid 333,0
+)
+)
+)
+*175 (CptPort
+uid 2499,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 2500,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "14250,14625,15000,15375"
+)
+tg (CPTG
+uid 2501,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 2502,0
+va (VaSet
+)
+xt "16000,14500,21700,15500"
+st "write_end_flag"
+blo "16000,15300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 2503,0
+va (VaSet
+font "Courier New,8,0"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "write_end_flag"
+t "std_logic"
+o 40
+suid 334,0
+)
+)
+)
+*176 (CptPort
+uid 2504,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 2505,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "14250,13625,15000,14375"
+)
+tg (CPTG
+uid 2506,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 2507,0
+va (VaSet
+)
+xt "16000,13500,22800,14500"
+st "write_header_flag"
+blo "16000,14300"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 2508,0
+va (VaSet
+font "Courier New,8,0"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "write_header_flag"
+t "std_logic"
+o 41
+suid 335,0
+)
+)
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