Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd (revision 10956) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd (revision 10957) @@ -389,5 +389,5 @@ when WRITE_CHANNEL_ID => -- write DRS and Channel IDs state_sig <= X"1B"; - data_out <= conv_std_logic_vector(3,12) & conv_std_logic_vector(channel_id,4) & + data_out <= conv_std_logic_vector(3,12) & conv_std_logic_vector(channel_id,4) & conv_std_logic_vector(2,12) & conv_std_logic_vector(channel_id,4) & conv_std_logic_vector(1,12) & conv_std_logic_vector(channel_id,4) & Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf (revision 10956) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf (revision 10957) @@ -83,8 +83,8 @@ #NET W_BRDY<0> LOC = AB26 | IOSTANDARD=LVCMOS33; #ok # Testpoint near W5300 -#NET W_T<3> LOC = R19 | IOSTANDARD=LVCMOS33; #ok -#NET W_T<2> LOC = N21 | IOSTANDARD=LVCMOS33; #ok -#NET W_T<1> LOC = M21 | IOSTANDARD=LVCMOS33; #ok -#NET W_T<0> LOC = K21 | IOSTANDARD=LVCMOS33; #ok +NET W_T<3> LOC = R19 | IOSTANDARD=LVCMOS33; #ok +NET W_T<2> LOC = N21 | IOSTANDARD=LVCMOS33; #ok +NET W_T<1> LOC = M21 | IOSTANDARD=LVCMOS33; #ok +NET W_T<0> LOC = K21 | IOSTANDARD=LVCMOS33; #ok # Platform Flash - serial connection Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd (revision 10956) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd (revision 10957) @@ -2,8 +2,8 @@ -- -- Created: --- by - dneise.UNKNOWN (E5B-LABOR6) --- at - 14:33:27 03.06.2011 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- by - daqct3.UNKNOWN (IHP110) +-- at - 16:56:38 09.06.2011 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) -- LIBRARY ieee; @@ -30,18 +30,18 @@ W_INT : IN std_logic; X_50M : IN STD_LOGIC; - A0_T : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); - A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + A0_T : OUT std_logic_vector (7 DOWNTO 0) := (others => '0'); + A1_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); AMBER_LED : OUT std_logic; A_CLK : OUT std_logic_vector (3 DOWNTO 0); DAC_CS : OUT std_logic; - DENABLE : OUT std_logic := '0'; - DSRCLK : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); - DWRITE : OUT std_logic := '0'; - D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); - D_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); - D_T2 : OUT std_logic_vector (1 DOWNTO 0) := (others => '0'); + DENABLE : OUT std_logic := '0'; + DSRCLK : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); + DWRITE : OUT std_logic := '0'; + D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0'); + D_T : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0'); + D_T2 : OUT std_logic_vector (1 DOWNTO 0) := (others => '0'); EE_CS : OUT std_logic; GREEN_LED : OUT std_logic; - MOSI : OUT std_logic := '0'; + MOSI : OUT std_logic := '0'; OE_ADC : OUT STD_LOGIC; RED_LED : OUT std_logic; @@ -52,14 +52,15 @@ RS485_E_DO : OUT std_logic; RS485_E_RE : OUT std_logic; - RSRLOAD : OUT std_logic := '0'; - SRIN : OUT std_logic := '0'; + RSRLOAD : OUT std_logic := '0'; + SRIN : OUT std_logic := '0'; S_CLK : OUT std_logic; TCS : OUT std_logic_vector (3 DOWNTO 0); - TRG_V : OUT std_logic := '0'; + TRG_V : OUT std_logic := '0'; W_A : OUT std_logic_vector (9 DOWNTO 0); - W_CS : OUT std_logic := '1'; - W_RD : OUT std_logic := '1'; - W_RES : OUT std_logic := '1'; - W_WR : OUT std_logic := '1'; + W_CS : OUT std_logic := '1'; + W_RD : OUT std_logic := '1'; + W_RES : OUT std_logic := '1'; + W_T : OUT std_logic_vector ( 3 DOWNTO 0 ) := (others => '0'); + W_WR : OUT std_logic := '1'; MISO : INOUT std_logic; W_D : INOUT std_logic_vector (15 DOWNTO 0) @@ -74,8 +75,8 @@ -- -- Created: --- by - dneise.UNKNOWN (E5B-LABOR6) --- at - 14:33:27 03.06.2011 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- by - daqct3.UNKNOWN (IHP110) +-- at - 16:56:38 09.06.2011 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) -- LIBRARY ieee; @@ -106,10 +107,17 @@ SIGNAL counter_result : std_logic_vector(11 DOWNTO 0) := (others => '0'); SIGNAL crate_id : std_logic_vector(1 DOWNTO 0); + SIGNAL dac_cs1 : std_logic; SIGNAL debug_data_ram_empty : std_logic; SIGNAL debug_data_valid : std_logic; SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0'); SIGNAL mem_manager_state : std_logic_vector(3 DOWNTO 0); -- state is encoded here ... useful for debugging. + SIGNAL mosi1 : std_logic; + SIGNAL sclk : std_logic; + SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0); SIGNAL socket_tx_free_out : std_logic_vector(16 DOWNTO 0); -- 17bit value .. that's true SIGNAL w5300_state : std_logic_vector(7 DOWNTO 0); -- state is encoded here ... useful for debugging. + + -- Implicit buffer signal declarations + SIGNAL TRG_V_internal : std_logic; @@ -209,18 +217,33 @@ --D_T <= (others => '0'); D_T <= w5300_state; - D_T2(0) <= debug_data_valid; - --D_T2(1) <= debug_data_ram_empty; - D_T2(1) <= socket_tx_free_out(16); + --D_T2(0) <= debug_data_valid; + D_T2(0) <= debug_data_ram_empty; + --D_T2(1) <= socket_tx_free_out(16); + + D_T2(1) <= TRG_V_internal; --D_T2 <= ( others => '0' ); + A0_T <= (others => '0'); + A1_T <= (others => '1'); --A0_T <= DG_state; - --A1_T(3 downto 0) <= mem_manager_state; + W_T(3 downto 0) <= mem_manager_state; --A1_T(7 downto 4) <= "1100"; - A0_T <= socket_tx_free_out(7 downto 0); - A1_T <= socket_tx_free_out(15 downto 8); + --A0_T <= socket_tx_free_out(7 downto 0); + --A0_T <= spi_debug_16bit(7 downto 0); + --A1_T <= spi_debug_16bit(15 downto 8); + --A1_T <= socket_tx_free_out(15 downto 8); + + -- check SPI interfac + --A1_T(7) <= sclk; + --A1_T(6) <= MISO; + --A1_T(5) <= mosi1; + + --A1_T(4) <= dac_cs1; + --A1_T( 3 downto 0) <= sensor_cs; + --D_T(3 downto 0) <= counter_result ( 11 downto 8); @@ -242,4 +265,16 @@ EE_CS <= '1'; + + -- ModuleWare code(v1.9) for instance 'I0' of 'assignment' + DAC_CS <= dac_cs1; + + -- ModuleWare code(v1.9) for instance 'I1' of 'assignment' + TCS <= sensor_cs; + + -- ModuleWare code(v1.9) for instance 'I2' of 'assignment' + S_CLK <= sclk; + + -- ModuleWare code(v1.9) for instance 'I3' of 'assignment' + MOSI <= mosi1; -- Instance port mappings. @@ -279,5 +314,5 @@ amber => AMBER_LED, counter_result => counter_result, - dac_cs => DAC_CS, + dac_cs => dac_cs1, debug_data_ram_empty => debug_data_ram_empty, debug_data_valid => debug_data_valid, @@ -288,10 +323,10 @@ led => led, mem_manager_state => mem_manager_state, - mosi => MOSI, + mosi => mosi1, red => GREEN_LED, - sclk => S_CLK, - sensor_cs => TCS, + sclk => sclk, + sensor_cs => sensor_cs, socket_tx_free_out => socket_tx_free_out, - trigger_veto => TRG_V, + trigger_veto => TRG_V_internal, w5300_state => w5300_state, wiz_addr => W_A, @@ -304,3 +339,6 @@ ); + -- Implicit buffered output assignments + TRG_V <= TRG_V_internal; + END struct; Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd (revision 10956) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd (revision 10957) @@ -195,5 +195,5 @@ -- for W5300 modul2 constant W5300_RAM_ADDR_WIDTH : integer := 17; -constant TX_FIFO_MAX_FREE : std_logic_vector(16 downto 0) := conv_std_logic_vector(15360 ,16); +constant TX_FIFO_MAX_FREE : std_logic_vector(16 downto 0) := conv_std_logic_vector(15360 ,17); -- not needed Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd (revision 10956) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd (revision 10957) @@ -2,8 +2,8 @@ -- -- Created: --- by - dneise.UNKNOWN (E5B-LABOR6) --- at - 14:33:25 03.06.2011 +-- by - daqct3.UNKNOWN (IHP110) +-- at - 16:56:36 09.06.2011 -- --- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) -- LIBRARY ieee; @@ -82,8 +82,8 @@ -- -- Created: --- by - dneise.UNKNOWN (E5B-LABOR6) --- at - 14:33:26 03.06.2011 +-- by - daqct3.UNKNOWN (IHP110) +-- at - 16:56:37 09.06.2011 -- --- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) -- library ieee; @@ -100,4 +100,6 @@ USE IEEE.std_logic_signed.all; USE fact_fad_lib.fad_rs485_constants.all; +LIBRARY hds_package_library; +USE hds_package_library.random_generators.all; LIBRARY FACT_FAD_lib; @@ -144,4 +146,5 @@ SIGNAL dout3 : STD_LOGIC; SIGNAL dout4 : STD_LOGIC; + SIGNAL dout5 : std_logic; SIGNAL drs_clk_en : std_logic := '0'; SIGNAL drs_read_s_cell : std_logic := '0'; @@ -199,4 +202,5 @@ SIGNAL trigger_or_s_trigger : std_logic; SIGNAL trigger_out : std_logic; + SIGNAL trigger_veto1 : std_logic := '1'; SIGNAL wiz_number_of_channels : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0'); @@ -626,4 +630,7 @@ din1 <= NOT(alarm_refclk_too_low_internal); + -- ModuleWare code(v1.9) for instance 'inverter_2' of 'inv' + dout5 <= NOT(ram_write_ea); + -- ModuleWare code(v1.9) for instance 'U_2' of 'or' dout4 <= dout OR I_really_want_dwrite; @@ -631,4 +638,7 @@ -- ModuleWare code(v1.9) for instance 'or_1' of 'or' s_trigger_or_cont_trigger <= s_trigger OR cont_trigger; + + -- ModuleWare code(v1.9) for instance 'or_2' of 'or' + trigger_veto <= trigger_veto1 OR dout5; -- ModuleWare code(v1.9) for instance 'or_5' of 'or' @@ -780,5 +790,5 @@ drs_s_cell_array => drs_s_cell_array, drs_readout_started => drs_readout_started, - trigger_veto => trigger_veto + trigger_veto => trigger_veto1 ); dna_gen_instance : dna_gen Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_2.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_2.vhd (revision 10956) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/memory_manager_2.vhd (revision 10957) @@ -360,4 +360,5 @@ wiz_write_header <= '0'; end if; + if (package_index = (number_of_packages - 1)) then -- last package -> write end-flag Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_controller_beha.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_controller_beha.vhd (revision 10956) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_controller_beha.vhd (revision 10957) @@ -18,13 +18,17 @@ miso : INOUT std_logic := 'Z'; mosi : OUT std_logic := '0'; + dac_cs : OUT std_logic := '1'; + sensor_cs : OUT std_logic_vector (3 DOWNTO 0) := (others => '1'); + dac_id : IN std_logic_vector (2 DOWNTO 0); sensor_id : IN std_logic_vector (1 downto 0); data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); - dac_cs : OUT std_logic := '1'; - sensor_cs : OUT std_logic_vector (3 DOWNTO 0) := (others => '1'); + measured_temp_data : out std_logic_vector (15 DOWNTO 0) := (others => '0'); + dac_start : IN std_logic; dac_ready : OUT std_logic := '0'; sensor_start : IN std_logic; - sensor_valid : OUT std_logic := '0' + sensor_valid : OUT std_logic := '0'; + spi_channel_ready : OUT std_logic := '1' ); END spi_controller ; @@ -58,8 +62,11 @@ case spi_state is when SPI_IDLE => + spi_channel_ready <= '1'; if (dac_start_sr(1) = '1') then + spi_channel_ready <= '0'; dac_ready <= '0'; spi_state <= SPI_LOAD_COMMAND; elsif (sensor_start_sr(1) = '1') then + spi_channel_ready <= '0'; sensor_valid <= '0'; spi_state <= SPI_LOAD_COMMAND; @@ -68,6 +75,10 @@ when SPI_LOAD_COMMAND => spi_cycle_cnt <= 0; + spi_channel_ready <= '0'; + if (sensor_start_sr(1) = '1') then - shift_reg <= X"C1" & X"0000"; -- command: Temperature register read + + --shift_reg <= X"C1" & X"0000"; -- command: Temperature register read + shift_reg <= X"C1" & "ZZZZZZZZZZZZZZZZ"; -- command: Temperature register read spi_state <= SPI_GET_TEMP; elsif (dac_start_sr(1) = '1') then @@ -78,5 +89,5 @@ -- start temperature sensor read when SPI_GET_TEMP => - if (spi_cycle_cnt < 24) then -- must be on more cause MAX6662 provides data on falling edge + if (spi_cycle_cnt < 24) then -- must be one more cause MAX6662 provides data on falling edge sensor_cs(conv_integer(sensor_id)) <= '0'; sensor_valid <= '0'; @@ -87,9 +98,10 @@ end if; else - data <= data_reg; + data <= data_reg; + measured_temp_data <= data_reg; sensor_valid <= '1'; spi_state <= SPI_IDLE; end if; - + -- start loading DACs when SPI_LOAD_DAC => Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_distributor_beha.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_distributor_beha.vhd (revision 10956) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_distributor_beha.vhd (revision 10957) @@ -26,19 +26,27 @@ PORT( - clk : IN std_logic; -- 50MHz + clk : IN std_logic; + + -- interface nach aussen config_start : IN std_logic; config_ready : OUT std_logic := '1'; + + dac_array : IN dac_array_type; + current_dac_array : OUT dac_array_type := ( others => 0); + sensor_array : OUT sensor_array_type; sensor_valid : OUT std_logic := '0'; - dac_array : IN dac_array_type; - current_dac_array : OUT dac_array_type := ( others => 0); - sensor_array : OUT sensor_array_type; + + + sensor_read_start : OUT std_logic := '0'; + sensor_read_valid : IN std_logic; dac_config_start : OUT std_logic := '0'; dac_config_ready : IN std_logic; - sclk_enable_override : OUT std_logic := '0'; - sensor_read_start : OUT std_logic := '0'; - sensor_read_valid : IN std_logic; + spi_channel_ready : IN std_logic; + + sclk_enable_override : OUT std_logic := '0'; dac_id : OUT std_logic_vector(2 downto 0) := (others => '0'); sensor_id : OUT std_logic_vector(1 downto 0) := (others => '0'); - data : INOUT std_logic_vector(15 downto 0) := (others => 'Z') + data : INOUT std_logic_vector(15 downto 0) := (others => 'Z'); + measured_temp_data : IN std_logic_vector(15 downto 0) ); END ENTITY spi_distributor; @@ -46,5 +54,11 @@ ARCHITECTURE beha OF spi_distributor IS - type TYPE_SPI_DISTRIBUTION_STATE is (INIT, IDLE, READ_SENSOR, CONFIG_DAC); + type TYPE_SPI_DISTRIBUTION_STATE is (INIT, IDLE, + PRE_READ_SENSOR, + SENSOR_READ_START_ACK, + READ_SENSOR, + PRE_CONFIG_DAC, + DAC_CONFIG_START_ACK, + CONFIG_DAC); signal spi_distr_state : TYPE_SPI_DISTRIBUTION_STATE := INIT; @@ -61,4 +75,9 @@ signal config_start_sr : std_logic_vector (1 downto 0) := "00"; + + signal sensor_read_valid_sr : std_logic_vector (1 downto 0) := "00"; + signal dac_config_ready_sr : std_logic_vector (1 downto 0) := "00"; + signal spi_channel_ready_sr : std_logic_vector (1 downto 0) := "00"; + BEGIN sclk_enable_override <= sclk_enable_override_sig; @@ -69,4 +88,7 @@ if rising_edge(clk) then + sensor_read_valid_sr <= sensor_read_valid_sr(0) & sensor_read_valid; + dac_config_ready_sr <= dac_config_ready_sr(0) & dac_config_ready; + spi_channel_ready_sr <= spi_channel_ready_sr(0) & spi_channel_ready; -- synch in config_start_sr <= config_start_sr(0) & config_start; @@ -77,5 +99,6 @@ data <= (others => 'Z'); int_sensor_valid <= '0'; - spi_distr_state <= READ_SENSOR; + spi_distr_state <= PRE_READ_SENSOR; + when IDLE => sclk_enable_override_sig <= '0'; @@ -87,49 +110,75 @@ -- start DAC configuration if (config_start_sr(1) = '1' AND int_sensor_valid = '1') then - config_ready <= '0'; + internal_dac_array <= dac_array; + spi_distr_state <= PRE_CONFIG_DAC; + -- start temperature sensor reading + elsif (dac_config_ready <= '1' AND int_sensor_read_start = '1' ) then + spi_distr_state <= PRE_READ_SENSOR; + end if; + + when PRE_READ_SENSOR => + + int_sensor_valid <= '0'; + sensor_read_start <= '1'; + sensor_id <= conv_std_logic_vector(sensor_id_cnt, sensor_id'length); + spi_distr_state <= SENSOR_READ_START_ACK; + + when SENSOR_READ_START_ACK => + if (spi_channel_ready_sr(1) = '0') then + sensor_read_start <= '0'; + spi_distr_state <= READ_SENSOR; + end if; + + when PRE_CONFIG_DAC => + config_ready <= '0'; sclk_enable_override_sig <= '1'; dac_config_start <= '1'; dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length); - data <= conv_std_logic_vector(dac_array(dac_id_cnt),data'length); - internal_dac_array <= dac_array; - spi_distr_state <= CONFIG_DAC; - -- start temperature sensor reading - elsif (dac_config_ready <= '1' AND int_sensor_read_start = '1') then - int_sensor_valid <= '0'; - sensor_read_start <= '1'; - sensor_id <= conv_std_logic_vector(sensor_id_cnt, sensor_id'length); - spi_distr_state <= READ_SENSOR; - end if; - + data <= conv_std_logic_vector(internal_dac_array(dac_id_cnt),data'length); + spi_distr_state <= DAC_CONFIG_START_ACK; + + + when DAC_CONFIG_START_ACK => + dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length); + data <= conv_std_logic_vector(internal_dac_array(dac_id_cnt),data'length); + + if (spi_channel_ready_sr(1) = '0') then + dac_config_start <= '0'; + spi_distr_state <= CONFIG_DAC; + end if; + -- sensor reading when READ_SENSOR => - sensor_read_start <= '1'; - sensor_id <= conv_std_logic_vector(sensor_id_cnt, sensor_id'length); - if (sensor_read_valid = '1') then - int_sensor_array(sensor_id_cnt) <= conv_integer(data); - sensor_read_start <= '0'; - if (sensor_id_cnt < 3) then - sensor_id_cnt <= sensor_id_cnt + 1; - sensor_read_start <= '1'; - spi_distr_state <= READ_SENSOR; - else - sensor_id_cnt <= 0; - sensor_valid <= '0'; - int_sensor_valid <= '1'; - spi_distr_state <= IDLE; - end if; - end if; - + + if (sensor_read_valid_sr(1) = '1') then + int_sensor_array(sensor_id_cnt) <= conv_integer(measured_temp_data); + --sensor_read_start <= '0'; + if (sensor_id_cnt < 3) then + sensor_id_cnt <= sensor_id_cnt + 1; + --sensor_read_start <= '1'; + spi_distr_state <= PRE_READ_SENSOR; + else + sensor_id_cnt <= 0; + sensor_valid <= '0'; + int_sensor_valid <= '1'; + spi_distr_state <= IDLE; + end if; + end if; + + + + -- DAC configuration when CONFIG_DAC => - dac_config_start <= '1'; - dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length); - data <= conv_std_logic_vector(internal_dac_array(dac_id_cnt),data'length); - if (dac_config_ready = '1') then - dac_config_start <= '0'; + --dac_config_start <= '1'; + --dac_id <= conv_std_logic_vector(dac_id_cnt, dac_id'length); + --data <= conv_std_logic_vector(internal_dac_array(dac_id_cnt),data'length); + --if (dac_config_ready = '1') then + if (spi_channel_ready_sr(1) = '1') then + --dac_config_start <= '0'; if (dac_id_cnt < 7) then dac_id_cnt <= dac_id_cnt + 1; - dac_config_start <= '1'; - spi_distr_state <= CONFIG_DAC; + --dac_config_start <= '1'; + spi_distr_state <= PRE_CONFIG_DAC; else dac_id_cnt <= 0; Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_interface_struct.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_interface_struct.vhd (revision 10956) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/spi_interface_struct.vhd (revision 10957) @@ -2,8 +2,8 @@ -- -- Created: --- by - dneise.UNKNOWN (E5B-LABOR6) --- at - 13:20:48 01.06.2011 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- by - daqct3.UNKNOWN (IHP110) +-- at - 16:56:36 09.06.2011 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) -- LIBRARY ieee; @@ -38,8 +38,8 @@ -- -- Created: --- by - dneise.UNKNOWN (E5B-LABOR6) --- at - 13:20:48 01.06.2011 --- --- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10) +-- by - daqct3.UNKNOWN (IHP110) +-- at - 16:56:36 09.06.2011 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) -- LIBRARY ieee; @@ -59,14 +59,16 @@ -- Internal signal declarations SIGNAL T_sensor_start : std_logic; - SIGNAL clk_2Mhz : std_logic := '0'; + SIGNAL clk_2Mhz : std_logic := '0'; SIGNAL dac_config_ready : std_logic; SIGNAL dac_config_start : std_logic; SIGNAL dac_id : std_logic_vector(2 DOWNTO 0); SIGNAL data : std_logic_vector(15 DOWNTO 0); - SIGNAL sclk_enable_override : std_logic := '0'; - SIGNAL sclk_enable_sig : std_logic := '0'; + SIGNAL measured_temp_data : std_logic_vector(15 DOWNTO 0) := (others => '0'); + SIGNAL sclk_enable_override : std_logic := '0'; + SIGNAL sclk_enable_sig : std_logic := '0'; SIGNAL sensor_id : std_logic_vector(1 DOWNTO 0); SIGNAL sensor_start : std_logic; SIGNAL sensor_valid : std_logic; + SIGNAL spi_channel_ready : std_logic := '1'; -- Implicit buffer signal declarations @@ -86,16 +88,18 @@ COMPONENT spi_controller PORT ( - clk : IN std_logic; - dac_id : IN std_logic_vector (2 DOWNTO 0); - dac_start : IN std_logic; - sensor_id : IN std_logic_vector (1 DOWNTO 0); - sensor_start : IN std_logic; - dac_cs : OUT std_logic := '1'; - dac_ready : OUT std_logic := '0'; - mosi : OUT std_logic := '0'; - sensor_cs : OUT std_logic_vector (3 DOWNTO 0) := (others => '1'); - sensor_valid : OUT std_logic := '0'; - data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); - miso : INOUT std_logic := 'Z' + clk : IN std_logic; + dac_id : IN std_logic_vector (2 DOWNTO 0); + dac_start : IN std_logic; + sensor_id : IN std_logic_vector (1 DOWNTO 0); + sensor_start : IN std_logic; + dac_cs : OUT std_logic := '1'; + dac_ready : OUT std_logic := '0'; + measured_temp_data : OUT std_logic_vector (15 DOWNTO 0) := (others => '0'); + mosi : OUT std_logic := '0'; + sensor_cs : OUT std_logic_vector (3 DOWNTO 0) := (others => '1'); + sensor_valid : OUT std_logic := '0'; + spi_channel_ready : OUT std_logic := '1'; + data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z'); + miso : INOUT std_logic := 'Z' ); END COMPONENT; @@ -109,6 +113,8 @@ dac_array : IN dac_array_type; dac_config_ready : IN std_logic; + measured_temp_data : IN std_logic_vector (15 DOWNTO 0); sensor_read_valid : IN std_logic; - config_ready : OUT std_logic := '0'; + spi_channel_ready : IN std_logic; + config_ready : OUT std_logic := '1'; current_dac_array : OUT dac_array_type := ( others => 0); dac_config_start : OUT std_logic := '0'; @@ -158,16 +164,18 @@ I_spi_controller : spi_controller PORT MAP ( - clk => sclk_internal, - miso => miso, - mosi => mosi, - dac_id => dac_id, - sensor_id => sensor_id, - data => data, - dac_cs => dac_cs, - sensor_cs => sensor_cs, - dac_start => dac_config_start, - dac_ready => dac_config_ready, - sensor_start => sensor_start, - sensor_valid => sensor_valid + clk => sclk_internal, + miso => miso, + mosi => mosi, + dac_cs => dac_cs, + sensor_cs => sensor_cs, + dac_id => dac_id, + sensor_id => sensor_id, + data => data, + measured_temp_data => measured_temp_data, + dac_start => dac_config_start, + dac_ready => dac_config_ready, + sensor_start => sensor_start, + sensor_valid => sensor_valid, + spi_channel_ready => spi_channel_ready ); I_spi_distributor : spi_distributor @@ -179,16 +187,18 @@ config_start => config_start, config_ready => config_ready, - sensor_valid => sensor_ready, dac_array => dac_array, current_dac_array => current_dac_array, sensor_array => sensor_array, + sensor_valid => sensor_ready, + sensor_read_start => sensor_start, + sensor_read_valid => sensor_valid, dac_config_start => dac_config_start, dac_config_ready => dac_config_ready, + spi_channel_ready => spi_channel_ready, sclk_enable_override => sclk_enable_override, - sensor_read_start => sensor_start, - sensor_read_valid => sensor_valid, dac_id => dac_id, sensor_id => sensor_id, - data => data + data => data, + measured_temp_data => measured_temp_data ); Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd (revision 10956) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd (revision 10957) @@ -124,5 +124,5 @@ WORKAROUND_CHECK_FIFO_SPACE_01, WORKAROUND_CHECK_FIFO_SPACE_02, WORKAROUND_CHECK_FIFO_SPACE_03, WORKAROUND_CHECK_FIFO_SPACE_04, WR_05a, WR_05b, WR_06, WR_07, - WR_ACK, WR_WAIT_FOR_ACK, + WR_ACK, WR_WAIT_FOR_ACK, WAIT_FOR_DATA_VALID_HIGH_AGAIN, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2, WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3 @@ -196,8 +196,8 @@ signal local_fifo_channels : std_logic_vector (3 downto 0); -signal wait_100ns_sig : std_logic_vector (2 downto 0) := "000"; - -signal config_addr : integer range 0 to 44; -type config_data_type is array (0 to 46) of std_logic_vector(15 downto 0); +signal wait_100ns_sig : std_logic_vector (5 downto 0) := "000000"; + +signal config_addr : integer range 0 to 47; +type config_data_type is array (0 to 47) of std_logic_vector(15 downto 0); signal config_setting : config_data_type := ( -- X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", X"000A", --<<-- ROIs = 10 TESTING ONLY @@ -213,5 +213,6 @@ X"61A8", X"0000", X"0000", X"0000", X"7080", X"7080", X"7080", X"7080", --<<-- DACs X"0000", - X"0000", X"0000" -- MSword // LSword + X"0000", X"0000", -- MSword // LSword + X"0000" -- this is a dummy address; this address is used only, if the user sent an invalid address within a WRITE command ); @@ -303,5 +304,5 @@ -- output config settings as DAC and ROI arrays. state <= state_sig; -debug_data_ram_empty <= int_flag; + debug_data_valid <= interrupt_ignore; --debug_data_ram_empty <= data_ram_empty_sr(1); @@ -315,5 +316,5 @@ c_trigger_mult <= config_setting(44); -runnumber <= config_setting(45) & config_setting(46); + trigger_enable <= trigger_enable_sig; @@ -740,6 +741,6 @@ state_sig <= X"15"; wait_100ns_sig <= wait_100ns_sig + 1; - if (wait_100ns_sig = "100") then - wait_100ns_sig <= "000"; + if (wait_100ns_sig = "110010") then + wait_100ns_sig <= "000000"; state_init <= WAIT_UNTIL_DG_IDLE; end if; @@ -749,5 +750,5 @@ if (data_generator_idle_sr = "111") then --state_init <= CONFIG_MEMORY_MANAGER; - state_init <= MAIN; + state_init <= CONFIG_MEMORY_MANAGER; end if; @@ -774,4 +775,5 @@ if (memory_manager_config_valid_i_sr(1) = '1') then --state_init <= CONFIG_DATA_GENERATOR; + trigger_enable_sig <= trigger_enable_storage_sig; state_init <= MAIN; end if; @@ -821,5 +823,5 @@ if (update_of_rois = '1') then update_of_rois <= '0'; - state_init <= CONFIG_MEMORY_MANAGER; + state_init <= CONFIG; -- if (trigger_enable_sig = '1') then -- trigger_enable_storage_sig <= trigger_enable_sig; @@ -876,4 +878,5 @@ end if; when MAIN3 => + debug_data_ram_empty <= local_write_end_flag; state_sig <= X"23"; -- needed for the check: if there is enough space in W5300 FIFO @@ -1009,6 +1012,11 @@ when CMD_WRITE => - config_addr <= conv_integer(data_read (7 downto 0)); - state_read_data <= READ_COMMAND_DATA_SECTION; + if ( (conv_integer(data_read (7 downto 0)) >= 0) and (conv_integer(data_read (7 downto 0)) <= 46) ) then + config_addr <= conv_integer(data_read (7 downto 0)); + state_read_data <= READ_COMMAND_DATA_SECTION; + else + config_addr <= 47; + state_read_data <= READ_COMMAND_DATA_SECTION; + end if; when CMD_EXECUTE => @@ -1057,4 +1065,5 @@ update_of_rois <= '1'; update_of_lessimportant <= '1'; + runnumber <= config_setting(45) & config_setting(46); state_read_data <= RD_5; @@ -1299,5 +1308,5 @@ number_of_bytes_written_to_fifo <= number_of_words_written_to_fifo(15 downto 0) & '0'; state_init <= WRITE_DATA; - state_write <= WORKAROUND_CHECK_FIFO_SPACE_01; + state_write <= WR_05; @@ -1347,15 +1356,35 @@ state_init <= WRITE_REG; state_write <= WR_ACK; - when WR_ACK => + when WR_ACK => -- handshake with MM data_valid_ack <= '1'; state_write <= WR_WAIT_FOR_ACK; - when WR_WAIT_FOR_ACK => + when WR_WAIT_FOR_ACK => -- handshake ACK with MM state_write <= WR_WAIT_FOR_ACK; if (data_valid_sr(1) = '0') then data_valid_ack <= '0'; - state_init <= next_state_tmp; + + if (local_write_end_flag = '1') then + -- the last package was just written, and we can go back to the main state + state_init <= MAIN; + state_write <= WR_START; + else + -- we just wrote, a part of an event and should not go back to main, in order to avoid + -- intermediate reconfiguration of the MM, in case an 'EXECUTE' command just arrived. + -- but neither we should not go back to MAIN2, because data_valid is still low, as part of the MM-handshake. + -- so we have to wait, until data_valid goes back high. + -- if it never goes high, this can be a deadlock again, but it MUST go high, + -- because we did not send away the entire event, yet. + state_init <= WRITE_DATA; + state_write <= WAIT_FOR_DATA_VALID_HIGH_AGAIN; + end if; + + + end if; + + when WAIT_FOR_DATA_VALID_HIGH_AGAIN => + if (data_valid_sr(1) = '1') then + state_init <= MAIN2; state_write <= WR_START; end if; - when others =>