Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd (revision 11121) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd (revision 11122) @@ -3,5 +3,5 @@ -- Created: -- by - daqct3.UNKNOWN (IHP110) --- at - 16:56:38 09.06.2011 +-- at - 21:52:14 22.06.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) @@ -76,5 +76,5 @@ -- Created: -- by - daqct3.UNKNOWN (IHP110) --- at - 16:56:38 09.06.2011 +-- at - 21:52:15 22.06.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) @@ -116,4 +116,5 @@ SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0); SIGNAL socket_tx_free_out : std_logic_vector(16 DOWNTO 0); -- 17bit value .. that's true + SIGNAL trigger_veto : std_logic := '1'; SIGNAL w5300_state : std_logic_vector(7 DOWNTO 0); -- state is encoded here ... useful for debugging. @@ -278,4 +279,7 @@ MOSI <= mosi1; + -- ModuleWare code(v1.9) for instance 'I4' of 'assignment' + TRG_V_internal <= trigger_veto; + -- Instance port mappings. I_board_main : FAD_main @@ -320,13 +324,13 @@ drs_channel_id => D_A, drs_dwrite => DWRITE, - green => RED_LED, + green => GREEN_LED, led => led, mem_manager_state => mem_manager_state, mosi => mosi1, - red => GREEN_LED, + red => RED_LED, sclk => sclk, sensor_cs => sensor_cs, socket_tx_free_out => socket_tx_free_out, - trigger_veto => TRG_V_internal, + trigger_veto => trigger_veto, w5300_state => w5300_state, wiz_addr => W_A, Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd (revision 11121) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd (revision 11122) @@ -57,5 +57,5 @@ --constant SUBVERSION_NUMBER : std_logic_vector (15 downto 0) := conv_std_logic_vector(str_to_int(SUBVERSION_STRING),16); constant PACKAGE_VERSION : std_logic_vector(7 downto 0) := X"02"; - constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"00"; + constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"02"; constant PACKAGE_HEADER_LENGTH : integer := 36; constant PACKAGE_HEADER_ZEROS : integer := 0; @@ -105,4 +105,7 @@ -- End W5300 registers +-- START W5300 Socket State Codes + constant SOCKET_CLOSED : std_logic_vector (7 downto 0) := X"00"; + -- constant W5300_TX_FIFO_SIZE_8B : integer := 15360; -- Socket TX FIFO-Size in Bytes Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd (revision 11121) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd (revision 11122) @@ -3,5 +3,5 @@ -- Created: -- by - daqct3.UNKNOWN (IHP110) --- at - 16:56:36 09.06.2011 +-- at - 21:52:13 22.06.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) @@ -83,5 +83,5 @@ -- Created: -- by - daqct3.UNKNOWN (IHP110) --- at - 16:56:37 09.06.2011 +-- at - 21:52:14 22.06.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) @@ -147,4 +147,5 @@ SIGNAL dout4 : STD_LOGIC; SIGNAL dout5 : std_logic; + SIGNAL dout6 : std_logic; SIGNAL drs_clk_en : std_logic := '0'; SIGNAL drs_read_s_cell : std_logic := '0'; @@ -184,5 +185,4 @@ SIGNAL runnumber : std_logic_vector(31 DOWNTO 0); SIGNAL s_trigger : std_logic; - SIGNAL s_trigger_or_cont_trigger : std_logic; SIGNAL sclk_enable : std_logic; SIGNAL sensor_array : sensor_array_type; @@ -198,4 +198,5 @@ SIGNAL start_srin_write_8b : std_logic; SIGNAL time : std_logic_vector(31 DOWNTO 0); + SIGNAL trig_veto : std_logic; SIGNAL trigger_enable : std_logic; SIGNAL trigger_id : std_logic_vector(31 DOWNTO 0); @@ -205,4 +206,5 @@ SIGNAL wiz_number_of_channels : std_logic_vector(3 DOWNTO 0) := (others => '0'); SIGNAL wiz_ram_start_addr : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0'); + SIGNAL wiz_reset_sig : std_logic := '1'; SIGNAL wiz_write_ea : std_logic := '0'; SIGNAL wiz_write_end : std_logic := '0'; @@ -408,4 +410,6 @@ socks_waiting : IN std_logic; trigger : IN std_logic; + trigger_veto : IN std_logic; + w5300_reset : IN std_logic; additional_flasher_out : OUT std_logic; amber : OUT std_logic; @@ -612,6 +616,5 @@ -- ModuleWare code(v1.9) for instance 'and_4' of 'and' - enabled_trigger_or_s_trigger <= trigger_or_s_trigger - AND trigger_enable; + dout6 <= trigger_or_s_trigger AND trigger_enable; -- ModuleWare code(v1.9) for instance 'and_5' of 'and' @@ -621,4 +624,10 @@ denable <= denable_sig; + -- ModuleWare code(v1.9) for instance 'U_7' of 'assignment' + trigger_veto <= trig_veto; + + -- ModuleWare code(v1.9) for instance 'U_8' of 'assignment' + wiz_reset <= wiz_reset_sig; + -- ModuleWare code(v1.9) for instance 'U_6' of 'gnd' software_trigger_in <= '0'; @@ -636,12 +645,12 @@ dout4 <= dout OR I_really_want_dwrite; - -- ModuleWare code(v1.9) for instance 'or_1' of 'or' - s_trigger_or_cont_trigger <= s_trigger OR cont_trigger; - -- ModuleWare code(v1.9) for instance 'or_2' of 'or' - trigger_veto <= trigger_veto1 OR dout5; + trig_veto <= trigger_veto1 OR dout5; -- ModuleWare code(v1.9) for instance 'or_5' of 'or' - trigger_or_s_trigger <= s_trigger_or_cont_trigger OR trigger; + trigger_or_s_trigger <= cont_trigger OR trigger; + + -- ModuleWare code(v1.9) for instance 'or_6' of 'or' + enabled_trigger_or_s_trigger <= s_trigger OR dout6; -- ModuleWare code(v1.9) for instance 'U_0' of 'split' @@ -664,5 +673,5 @@ -- Instance port mappings. - U_7 : FAD_rs485_receiver + Inst_rs485_receiver : FAD_rs485_receiver GENERIC MAP ( RX_BYTES => RS485_MESSAGE_LEN_BYTES, -- no. of bytes to receive @@ -829,4 +838,6 @@ additional_flasher_out => OPEN, trigger => drs_readout_started, + w5300_reset => wiz_reset_sig, + trigger_veto => trig_veto, refclk_too_high => alarm_refclk_too_high_internal, refclk_too_low => alarm_refclk_too_low_internal, @@ -917,5 +928,5 @@ socket_tx_free_out => socket_tx_free_out, clk => CLK_50_internal, - wiz_reset => wiz_reset, + wiz_reset => wiz_reset_sig, addr => wiz_addr, data => wiz_data, Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/led_controller_bahavior.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/led_controller_bahavior.vhd (revision 11121) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/led_controller_bahavior.vhd (revision 11122) @@ -36,4 +36,7 @@ -- status INs trigger : IN std_logic; -- when trigger is received green should toggle + + w5300_reset : in std_logic; + trigger_veto : in std_logic; refclk_too_high : in std_logic; @@ -71,6 +74,11 @@ -- since leds have inverted logic, the outs are inverted at this point. green <= not green_loc; - amber <= not amber_loc; - red <= not red_loc; + + --amber <= not amber_loc; + amber <= w5300_reset; + + --red <= not red_loc; + red <= trigger_veto; + additional_flasher_out <= flasher; @@ -91,5 +99,5 @@ when INIT => - amber_loc <= '0'; + green_loc <= '0'; if (socks_waiting = '1') then next_state <= WAITING; @@ -99,5 +107,5 @@ when WAITING => - amber_loc <= flasher; + green_loc <= flasher; if (socks_connected = '1') then next_state <= CONNECTED; @@ -107,5 +115,5 @@ when CONNECTED => - amber_loc <= '1'; + green_loc <= '1'; if (socks_connected = '0') then next_state <= INIT; @@ -117,9 +125,9 @@ - -- if trigger is received green_loc toggles + -- if trigger is received red_loc toggles trigger_proc : process (trigger) begin if Rising_edge(trigger) then - green_loc <= not green_loc; + red_loc <= not red_loc; end if; end process trigger_proc; @@ -178,8 +186,8 @@ if (heartbeat_counter = 0) then - red_loc <= '1'; + amber_loc <= '1'; end if; if (heartbeat_counter = on_time) then - red_loc <= '0'; + amber_loc <= '0'; end if; end if; Index: /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd =================================================================== --- /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd (revision 11121) +++ /firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd (revision 11122) @@ -109,5 +109,5 @@ SI, SI1, SI1b, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, - CONFIG, WAIT_100NS, WAIT_UNTIL_DG_IDLE, WAIT_FOR_DATA_RAM_EMPTY, -- <-- this is THE deadlock state + CONFIG, WAIT_100NS, WAIT_UNTIL_DG_IDLE, CONFIG_MEMORY_MANAGER, WAIT_FOR_CONFIG_MEMORY_MANAGER, CONFIG_DATA_GENERATOR, WAIT_FOR_CONFIG_DATA_GENERATOR, @@ -123,5 +123,7 @@ WR_05, WR_05_PREPARE_LENGTH_INFO, WR_05_POSTPREPARE_LENGTH_INFO, WORKAROUND_CHECK_FIFO_SPACE_01, WORKAROUND_CHECK_FIFO_SPACE_02, WORKAROUND_CHECK_FIFO_SPACE_03, WORKAROUND_CHECK_FIFO_SPACE_04, - WR_05a, WR_05b, WR_06, WR_07, + WR_05a, WR_05b, WR_06, + WAIT_BEFORE_SEND, -- new state for serializing the 'send' + WR_07, WR_ACK, WR_WAIT_FOR_ACK, WAIT_FOR_DATA_VALID_HIGH_AGAIN, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2, @@ -129,5 +131,9 @@ ); type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04); -type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06); +type state_interrupt_2_type is ( + IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, + IR2_CHECK_SOCKET_STATE, IR2_WAIT_FOR_SOCKETS_IN_CLOSED_STATE, + IR2_06); + type state_read_data_type is ( RD_1, @@ -152,4 +158,5 @@ signal state_init, next_state , next_state_tmp : state_init_type := RESET; +signal state_after_config : state_init_type := MAIN; signal count : std_logic_vector (2 downto 0) := "000"; signal state_write : state_write_type := WR_START; @@ -226,4 +233,11 @@ signal bid : std_logic_vector (3 downto 0); signal cid : std_logic_vector (1 downto 0); + +-- for 'send'-serialization +signal FADid : integer range 0 to 39 := 0; -- 39 = number of FADs in camera minus 1 +constant MICROSEC_TO_WAIT_BEFORE_SEND : integer := 25; +signal wait_before_send_counter : integer range 0 to 50*39*MICROSEC_TO_WAIT_BEFORE_SEND := 0; +signal wait_before_send_counter_goal : integer range 0 to 50*39*MICROSEC_TO_WAIT_BEFORE_SEND := 0; + -- these are just used as local variables, to make reading easier. signal mac_loc : mac_type; @@ -268,4 +282,13 @@ signal number_of_words_written_to_fifo : std_logic_vector(15 downto 0) := (others => '0'); signal number_of_bytes_written_to_fifo : std_logic_vector(16 downto 0) := (others => '0'); + + + +signal wait_for_sockets_closed_counter_overflow : std_logic := '0'; +signal wait_for_sockets_closed_counter_enable : std_logic := '0'; +signal wfscc_1 : integer range 0 to 50000 := 0; +signal wfscc_2 : integer range 0 to 2000 := 0; + + COMPONENT mod7 @@ -391,5 +414,5 @@ socket_cnt <= socket_cnt + 1; if (socket_cnt = 7) then - state_interrupt_2 <= IR2_06; + state_interrupt_2 <= IR2_05; else state_interrupt_2 <= IR2_02; -- go on with loop @@ -418,14 +441,47 @@ state_sig <= X"F7"; par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; - par_data <= X"0010"; -- CLOSE + --par_data <= X"0010"; -- CLOSE + par_data <= X"0008"; -- DISCON state_init <= WRITE_REG; next_state <= INTERRUPT; socket_cnt <= socket_cnt + 1; if (socket_cnt = 7) then - state_interrupt_2 <= IR2_06; + socket_cnt <= "000"; + state_interrupt_2 <= IR2_06; else state_interrupt_2 <= IR2_01; end if; + when IR2_CHECK_SOCKET_STATE => + wait_for_sockets_closed_counter_enable <= '1'; + + par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC; -- READ Socket Status Register + state_init <= READ_REG; + next_state <= INTERRUPT; + state_interrupt_2 <= IR2_WAIT_FOR_SOCKETS_IN_CLOSED_STATE; + + when IR2_WAIT_FOR_SOCKETS_IN_CLOSED_STATE => + if ( wait_for_sockets_closed_counter_overflow = '1') then + wait_for_sockets_closed_counter_enable <= '0'; + socket_cnt <= "000"; + state_interrupt_2 <= IR2_06; + else + if ( data_read(7 downto 0) = SOCKET_CLOSED ) then + if ( socket_cnt = 7 ) then + socket_cnt <= "000"; + state_interrupt_2 <= IR2_06; + else + socket_cnt <= socket_cnt + 1; + state_interrupt_2 <= IR2_CHECK_SOCKET_STATE; + end if; + else + state_interrupt_2 <= IR2_CHECK_SOCKET_STATE; + end if; + end if; + + + + + -- we go on and reset, the W5300 and this entire state machine. when IR2_06 => @@ -465,5 +521,12 @@ cs <= '1'; state_write <= WR_START; - state_init <= INIT; + --state_init <= INIT; + + -- I do this early configuration here, in order to get rid of all events in RAM. + -- in order to end up, with disabled trigger lines, I set trigger enable to 0. + -- So busy should vanish, once we are here. + trigger_enable_sig <= '0'; + state_init <= CONFIG; + state_after_config <= INIT; end if; @@ -483,6 +546,9 @@ when LOCATE => - state_sig <= X"03"; + state_sig <= X"03"; state_init <= IM; + + -- calculate FADid for 'send'-ing serialization + FADid <= conv_integer(cid)*10+conv_integer(bid); if (FAD_in_cam = '1') then @@ -749,17 +815,7 @@ state_sig <= X"16"; if (data_generator_idle_sr = "111") then - --state_init <= CONFIG_MEMORY_MANAGER; state_init <= CONFIG_MEMORY_MANAGER; end if; - - - - - when WAIT_FOR_DATA_RAM_EMPTY => -- GUARANTIED DEAD LOCK HERE, because RAM will never empty, when staying in this state. - state_sig <= X"17"; - if (data_ram_empty_sr(1) = '1') then - state_init <= CONFIG_MEMORY_MANAGER; - end if; when CONFIG_MEMORY_MANAGER => @@ -776,20 +832,7 @@ --state_init <= CONFIG_DATA_GENERATOR; trigger_enable_sig <= trigger_enable_storage_sig; - state_init <= MAIN; + state_init <= state_after_config; + --state_init <= MAIN; end if; - --- when CONFIG_DATA_GENERATOR => --- state_sig <= X"1A"; --- data_generator_config_start_o <= '1'; --- if (data_generator_config_valid_i_sr = "00") then --- state_init <= WAIT_FOR_CONFIG_DATA_GENERATOR; --- end if; --- when WAIT_FOR_CONFIG_DATA_GENERATOR => --- state_sig <= X"1B"; --- data_generator_config_start_o <= '0'; --- if (data_generator_config_valid_i_sr ="11") then --- trigger_enable_sig <= trigger_enable_storage_sig; --restore value of this signal to the value it had before CONFIG --- state_init <= MAIN; --- end if; @@ -823,4 +866,6 @@ if (update_of_rois = '1') then update_of_rois <= '0'; + + state_after_config <= MAIN; --this needs to be set to main, in order to return here, after configuration state_init <= CONFIG; -- if (trigger_enable_sig = '1') then @@ -1330,8 +1375,4 @@ - - - - when WR_05 => ram_access <= '0'; @@ -1347,6 +1388,21 @@ --par_data <= number_of_bytes_written_to_fifo(15 downto 0); + -- prepare this value here, so I have it in the next state. + wait_before_send_counter_goal <= FADid*50*MICROSEC_TO_WAIT_BEFORE_SEND; + state_init <= WRITE_REG; state_write <= WR_07; + + when WAIT_BEFORE_SEND => + state_init <= WRITE_DATA; + state_write <= WAIT_BEFORE_SEND; + + if (wait_before_send_counter = wait_before_send_counter_goal) then + wait_before_send_counter <= 0; + state_write <= WR_07; + else + wait_before_send_counter <= wait_before_send_counter + 1; + end if; + when WR_07 => number_of_words_written_to_fifo <= (others => '0'); @@ -1458,4 +1514,38 @@ end process w5300_proc; + + + + --signal wait_for_sockets_closed_counter_overflow : std_logic := '0'; + --signal wait_for_sockets_closed_counter_enable : std_logic := '0'; + --signal wfscc_1 : integer range 0 to 50000 := 0; + --signal wfscc_2 : integer range 0 to 2000 := 0; + counter_before_reset_proc : process (clk) + begin + if rising_edge (clk) then + if (wait_for_sockets_closed_counter_enable = '1') then + wait_for_sockets_closed_counter_overflow <= '0'; + if (wfscc_1 = 50000) then + if (wfscc_2 = 2000) then + wait_for_sockets_closed_counter_overflow <= '1'; + wfscc_2 <= 2000; + wfscc_1 <= 50000; + else + wfscc_2 <= wfscc_2 + 1; + wfscc_1 <= 0; + end if; + else + wfscc_1 <= wfscc_1 + 1; + end if; + else + wfscc_1 <= 0; + wfscc_2 <= 0; + wait_for_sockets_closed_counter_overflow <= '0'; + end if; + + end if; + end process counter_before_reset_proc; + + end Behavioral;