Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd (revision 11122) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/data_generator.vhd (revision 11155) @@ -51,4 +51,9 @@ dwrite_enable_in : in std_logic; denable_enable_in : in std_logic; + busy_enable_in : in std_logic; + trigger_enable_in : in std_logic; + cont_trigger_en_in : in std_logic; + socket_send_mode_in : in std_logic; + -- EVT HEADER - part 2 --> FTM trigger informaton, comes in late ... @@ -275,5 +280,9 @@ DCM_ready_status & -- 1 bit SPI_SCLK_enable_status &-- 1 bit - conv_std_logic_vector(0,5) & + busy_enable_in & + trigger_enable_in & + cont_trigger_en_in & + socket_send_mode_in& + conv_std_logic_vector(0,1) & PACKAGE_VERSION & PACKAGE_SUB_VERSION & package_length_sig & @@ -450,8 +459,82 @@ state_sig <= X"20"; if (data_cntr < roi_max_int (channel_id)) then - data_out <= adc_data_array(3)(7 downto 0) & "000" & adc_otr(3) & adc_data_array(3)(11 downto 8) & - adc_data_array(2)(7 downto 0) & "000" & adc_otr(2) & adc_data_array(2)(11 downto 8) & - adc_data_array(1)(7 downto 0) & "000" & adc_otr(1) & adc_data_array(1)(11 downto 8) & - adc_data_array(0)(7 downto 0) & "000" & adc_otr(0) & adc_data_array(0)(11 downto 8) ; + data_out <= + --DRS chip 3 LOW BYTE + (adc_otr(3) xor adc_data_array(3)(7)) & + (adc_otr(3) xor adc_data_array(3)(6)) & + (adc_otr(3) xor adc_data_array(3)(5)) & + (adc_otr(3) xor adc_data_array(3)(4)) & + (adc_otr(3) xor adc_data_array(3)(3)) & + (adc_otr(3) xor adc_data_array(3)(2)) & + (adc_otr(3) xor adc_data_array(3)(1)) & + (adc_otr(3) xor adc_data_array(3)(0)) & + --DRS chip 3 HIGH BYTE + adc_data_array(3)(11) & + adc_data_array(3)(11) & + adc_data_array(3)(11) & + adc_data_array(3)(11) & + (adc_otr(3) xor adc_data_array(3)(11)) & + (adc_otr(3) xor adc_data_array(3)(10)) & + (adc_otr(3) xor adc_data_array(3)(9)) & + (adc_otr(3) xor adc_data_array(3)(8)) & + --DRS chip 2 LOW BYTE + (adc_otr(2) xor adc_data_array(2)(7)) & + (adc_otr(2) xor adc_data_array(2)(6)) & + (adc_otr(2) xor adc_data_array(2)(5)) & + (adc_otr(2) xor adc_data_array(2)(4)) & + (adc_otr(2) xor adc_data_array(2)(3)) & + (adc_otr(2) xor adc_data_array(2)(2)) & + (adc_otr(2) xor adc_data_array(2)(1)) & + (adc_otr(2) xor adc_data_array(2)(0)) & + --DRS chip 2 HIGH BYTE + adc_data_array(2)(11) & + adc_data_array(2)(11) & + adc_data_array(2)(11) & + adc_data_array(2)(11) & + (adc_otr(2) xor adc_data_array(2)(11)) & + (adc_otr(2) xor adc_data_array(2)(10)) & + (adc_otr(2) xor adc_data_array(2)(9)) & + (adc_otr(2) xor adc_data_array(2)(8)) & + --DRS chip 1 LOW BYTE + (adc_otr(1) xor adc_data_array(1)(7)) & + (adc_otr(1) xor adc_data_array(1)(6)) & + (adc_otr(1) xor adc_data_array(1)(5)) & + (adc_otr(1) xor adc_data_array(1)(4)) & + (adc_otr(1) xor adc_data_array(1)(3)) & + (adc_otr(1) xor adc_data_array(1)(2)) & + (adc_otr(1) xor adc_data_array(1)(1)) & + (adc_otr(1) xor adc_data_array(1)(0)) & + --DRS chip 1 HIGH BYTE + adc_data_array(1)(11) & + adc_data_array(1)(11) & + adc_data_array(1)(11) & + adc_data_array(1)(11) & + (adc_otr(1) xor adc_data_array(1)(11)) & + (adc_otr(1) xor adc_data_array(1)(10)) & + (adc_otr(1) xor adc_data_array(1)(9)) & + (adc_otr(1) xor adc_data_array(1)(8)) & + --DRS chip 0 LOW BYTE + (adc_otr(0) xor adc_data_array(0)(7)) & + (adc_otr(0) xor adc_data_array(0)(6)) & + (adc_otr(0) xor adc_data_array(0)(5)) & + (adc_otr(0) xor adc_data_array(0)(4)) & + (adc_otr(0) xor adc_data_array(0)(3)) & + (adc_otr(0) xor adc_data_array(0)(2)) & + (adc_otr(0) xor adc_data_array(0)(1)) & + (adc_otr(0) xor adc_data_array(0)(0)) & + --DRS chip 0 HIGH BYTE + adc_data_array(0)(11) & + adc_data_array(0)(11) & + adc_data_array(0)(11) & + adc_data_array(0)(11) & + (adc_otr(0) xor adc_data_array(0)(11)) & + (adc_otr(0) xor adc_data_array(0)(10)) & + (adc_otr(0) xor adc_data_array(0)(9)) & + (adc_otr(0) xor adc_data_array(0)(8)) ; + + --adc_data_array(3)(7 downto 0) & "000" & adc_otr(3) & adc_data_array(3)(11 downto 8) & + --adc_data_array(2)(7 downto 0) & "000" & adc_otr(2) & adc_data_array(2)(11 downto 8) & + --adc_data_array(1)(7 downto 0) & "000" & adc_otr(1) & adc_data_array(1)(11 downto 8) & + --adc_data_array(0)(7 downto 0) & "000" & adc_otr(0) & adc_data_array(0)(11 downto 8) ; addr_cntr <= addr_cntr + 1; Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf (revision 11122) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board.ucf (revision 11155) @@ -255,6 +255,6 @@ # LEDs ####################################################### -NET AMBER_LED LOC = T4 | IOSTANDARD=LVCMOS25 | DRIVE = 2; #schematic: LED_3 D3 AMBER -NET GREEN_LED LOC = C23 | IOSTANDARD=LVCMOS33 | DRIVE = 2; #schematic: LED_0 D1 GREEN +NET AMBER_LED LOC = C23 | IOSTANDARD=LVCMOS33 | DRIVE = 2; +NET GREEN_LED LOC = T4 | IOSTANDARD=LVCMOS25 | DRIVE = 2; NET RED_LED LOC = AD20 | IOSTANDARD=LVCMOS33 | DRIVE = 2;#schematic: LED_2 D2 RED Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd (revision 11122) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_board_struct.vhd (revision 11155) @@ -3,5 +3,5 @@ -- Created: -- by - daqct3.UNKNOWN (IHP110) --- at - 21:52:14 22.06.2011 +-- at - 13:24:39 23.06.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) @@ -76,5 +76,5 @@ -- Created: -- by - daqct3.UNKNOWN (IHP110) --- at - 21:52:15 22.06.2011 +-- at - 13:24:39 23.06.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd (revision 11122) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_definitions.vhd (revision 11155) @@ -57,5 +57,5 @@ --constant SUBVERSION_NUMBER : std_logic_vector (15 downto 0) := conv_std_logic_vector(str_to_int(SUBVERSION_STRING),16); constant PACKAGE_VERSION : std_logic_vector(7 downto 0) := X"02"; - constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"02"; + constant PACKAGE_SUB_VERSION : std_logic_vector(7 downto 0) := X"05"; constant PACKAGE_HEADER_LENGTH : integer := 36; constant PACKAGE_HEADER_ZEROS : integer := 0; @@ -174,4 +174,8 @@ constant CMD_TRIGGER_S : std_logic_vector := X"20"; +constant CMD_BUSY_ON : std_logic_vector := X"24"; +constant CMD_BUSY_OFF : std_logic_vector := X"25"; + + Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd (revision 11122) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/fad_main_struct.vhd (revision 11155) @@ -3,5 +3,5 @@ -- Created: -- by - daqct3.UNKNOWN (IHP110) --- at - 21:52:13 22.06.2011 +-- at - 13:24:37 23.06.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) @@ -83,5 +83,5 @@ -- Created: -- by - daqct3.UNKNOWN (IHP110) --- at - 21:52:14 22.06.2011 +-- at - 13:24:38 23.06.2011 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12) @@ -126,4 +126,5 @@ SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0); SIGNAL addr_out : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0); + SIGNAL busy_enable : std_logic := '1'; SIGNAL c_trigger_enable : std_logic := '0'; SIGNAL c_trigger_mult : std_logic_vector(15 DOWNTO 0); @@ -148,4 +149,5 @@ SIGNAL dout5 : std_logic; SIGNAL dout6 : std_logic; + SIGNAL dout7 : std_logic; SIGNAL drs_clk_en : std_logic := '0'; SIGNAL drs_read_s_cell : std_logic := '0'; @@ -325,4 +327,5 @@ dwrite_enable_in : IN std_logic ; denable_enable_in : IN std_logic ; + busy_enable_in : IN std_logic ; -- EVT HEADER - part 2 --> FTM trigger informaton, comes in late ... -- during EVT header wrinting, this field is left out ... and only written into event header, @@ -557,4 +560,5 @@ sclk_enable : OUT std_logic := '1'; -- default DWRITE HIGH. srclk_enable : OUT std_logic := '1'; -- default SRCLK on. + busy_enable : OUT std_logic := '1'; ------------------------------------------------------------------------------ @@ -621,4 +625,7 @@ drs_dwrite <= dwrite_trigger_manager AND dwrite_global_enable; + -- ModuleWare code(v1.9) for instance 'and_6' of 'and' + trig_veto <= busy_enable AND dout7; + -- ModuleWare code(v1.9) for instance 'U_5' of 'assignment' denable <= denable_sig; @@ -646,5 +653,5 @@ -- ModuleWare code(v1.9) for instance 'or_2' of 'or' - trig_veto <= trigger_veto1 OR dout5; + dout7 <= trigger_veto1 OR dout5; -- ModuleWare code(v1.9) for instance 'or_5' of 'or' @@ -764,4 +771,5 @@ dwrite_enable_in => dwrite_enable_w5300, denable_enable_in => denable_sig, + busy_enable_in => busy_enable, FTM_RS485_ready => FTM_RS485_ready, FTM_trigger_info => rs465_data, @@ -966,4 +974,5 @@ sclk_enable => sclk_enable, srclk_enable => srclk_enable, + busy_enable => busy_enable, ps_direction => ps_direction, ps_do_phase_shift => ps_do_phase_shift, Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/led_controller_bahavior.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/led_controller_bahavior.vhd (revision 11122) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/led_controller_bahavior.vhd (revision 11155) @@ -79,5 +79,5 @@ --red <= not red_loc; - red <= trigger_veto; + red <= not trigger_veto; additional_flasher_out <= flasher; Index: firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd =================================================================== --- firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd (revision 11122) +++ firmware/FAD/FACT_FAD_20MHz_VAR_PS/FACT_FAD_lib/hdl/w5300_modul.vhd (revision 11155) @@ -79,4 +79,6 @@ sclk_enable : out std_logic := '1'; -- default DWRITE HIGH. srclk_enable : out std_logic := '1'; -- default SRCLK on. + busy_enable : out std_logic := '1'; + socket_send_mode_out : out std_logic; ------------------------------------------------------------------------------ @@ -343,4 +345,5 @@ trigger_enable <= trigger_enable_sig; +socket_send_mode_out <= socket_send_mode; w5300_proc : process (clk) @@ -439,5 +442,5 @@ -- if this was not Socket 7 ... if it was Socket 7, we're done anyway. when IR2_05 => - state_sig <= X"F7"; + state_sig <= X"F7"; par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC; --par_data <= X"0010"; -- CLOSE @@ -448,5 +451,6 @@ if (socket_cnt = 7) then socket_cnt <= "000"; - state_interrupt_2 <= IR2_06; + --state_interrupt_2 <= IR2_06; + state_interrupt_2 <= IR2_CHECK_SOCKET_STATE; else state_interrupt_2 <= IR2_01;