Index: firmware/FTM/Clock_cond_interface/Clock_cond_interface_tb.vhd =================================================================== --- firmware/FTM/Clock_cond_interface/Clock_cond_interface_tb.vhd (revision 11485) +++ firmware/FTM/Clock_cond_interface/Clock_cond_interface_tb.vhd (revision 11513) @@ -76,5 +76,5 @@ - signal cc_R0 : std_logic_vector(31 downto 0) := x"00010100"; + signal cc_R0 : std_logic_vector(31 downto 0) := x"00038000"; signal cc_R1 : std_logic_vector(31 downto 0) := x"00010101"; signal cc_R8 : std_logic_vector(31 downto 0) := x"10000908"; @@ -83,7 +83,7 @@ signal cc_R13 : std_logic_vector(31 downto 0) := x"020A000D"; signal cc_R14 : std_logic_vector(31 downto 0) := x"0830280E"; - signal cc_R15 : std_logic_vector(31 downto 0) := x"2000960F"; + signal cc_R15 : std_logic_vector(31 downto 0) := x"1400FA0F"; - + signal start_config : std_logic := '0'; signal timemarker_select : std_logic := '0'; Index: firmware/FTM/Lightpulser_interface/Basic_Version/FM_pulse_generator_Basic.vhd =================================================================== --- firmware/FTM/Lightpulser_interface/Basic_Version/FM_pulse_generator_Basic.vhd (revision 11485) +++ firmware/FTM/Lightpulser_interface/Basic_Version/FM_pulse_generator_Basic.vhd (revision 11513) @@ -15,4 +15,9 @@ -- by Patrick Vogler, Quirin Weitzel -- -> clean up +-- +-- modified: July 20 2011 +-- by Patrick Vogler +-- reduce LED current to reduce total light yield +-- @@ -29,10 +34,10 @@ ENTITY FM_pulse_generator_Basic IS GENERIC( - pulse_length : integer := FLD_PULSE_LENGTH_BASIC -- 60ns + pulse_length : integer := FLD_PULSE_LENGTH_FM -- 60ns ); PORT( clk : in std_logic; - pulse_freq : in std_logic_vector (5 downto 0); - FM_out : out std_logic := '0' + pulse_freq : in std_logic_vector (6 downto 0); + FM_out : out std_logic := '0' ); END FM_pulse_generator_Basic; @@ -44,5 +49,5 @@ clk_div: process (clk) variable Z : integer range - FLD_MIN_FREQ_DIV_BASIC to FLD_FD_MAX_RANGE_BASIC; - variable Y : integer range 0 to FLD_PULSE_LENGTH_BASIC; + variable Y : integer range 0 to FLD_PULSE_LENGTH_FM; variable X : integer range 0 to FLD_FD_MULT_BASIC ; @@ -50,5 +55,5 @@ if rising_edge(clk) then - if (X < FLD_FD_MULT_BASIC) then + if (X < FLD_FD_MULT_BASIC - 1) then X := X+1; else @@ -57,5 +62,5 @@ Z := Z + 1; else - Z := - FLD_MIN_FREQ_DIV_BASIC; + Z := - FLD_MIN_FREQ_DIV_BASIC + 1; Y := 0; end if; Index: firmware/FTM/Lightpulser_interface/Basic_Version/Lightpulser_interface_Basic.vhd =================================================================== --- firmware/FTM/Lightpulser_interface/Basic_Version/Lightpulser_interface_Basic.vhd (revision 11485) +++ firmware/FTM/Lightpulser_interface/Basic_Version/Lightpulser_interface_Basic.vhd (revision 11513) @@ -31,4 +31,8 @@ -- by Patrick Vogler, Quirin Weitzel -- -> clean up +-- +-- modified: July 20 2011 +-- by Patrick Vogler +-- reduce minimal LED light output and increase dynamic range -- ---------------------------------------------------------------------------------- @@ -111,5 +115,5 @@ port( clk : in std_logic; -- 50 MHz - pulse_freq : in std_logic_vector (5 downto 0); + pulse_freq : in std_logic_vector (6 downto 0); FM_out : out std_logic := '0' ); @@ -198,5 +202,5 @@ port map( clk => clk_50, - pulse_freq => LP1_ampl_sig(5 downto 0), + pulse_freq => LP1_ampl_sig(6 downto 0), FM_out => PWM_sig_1 ); @@ -206,5 +210,5 @@ port map( clk => clk_50, - pulse_freq => LP2_ampl_sig(5 downto 0), + pulse_freq => LP2_ampl_sig(6 downto 0), FM_out => PWM_sig_2 ); Index: firmware/FTM/Lightpulser_interface/Basic_Version/Lightpulser_interface_Basic_tb.vhd =================================================================== --- firmware/FTM/Lightpulser_interface/Basic_Version/Lightpulser_interface_Basic_tb.vhd (revision 11513) +++ firmware/FTM/Lightpulser_interface/Basic_Version/Lightpulser_interface_Basic_tb.vhd (revision 11513) @@ -0,0 +1,223 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 10:12:21 07/21/2011 +-- Design Name: +-- Module Name: /home/pavogler/ISDC_repos/firmware/FTM/Lightpulser_interface/Basic_Version//Lightpulser_interface_Basic_tb.vhd +-- Project Name: Lightpulser_Basic +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: Lightpulser_interface_Basic +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE ieee.numeric_std.ALL; + +ENTITY Lightpulser_interface_Basic_tb IS +END Lightpulser_interface_Basic_tb; + +ARCHITECTURE behavior OF Lightpulser_interface_Basic_tb IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT Lightpulser_interface_Basic + PORT( + clk_50 : IN std_logic; + Cal_0_p : OUT std_logic; + Cal_0_n : OUT std_logic; + Cal_1_p : OUT std_logic; + Cal_1_n : OUT std_logic; + Cal_2_p : OUT std_logic; + Cal_2_n : OUT std_logic; + Cal_3_p : OUT std_logic; + Cal_3_n : OUT std_logic; + Cal_4_p : OUT std_logic; + Cal_4_n : OUT std_logic; + Cal_5_p : OUT std_logic; + Cal_5_n : OUT std_logic; + Cal_6_p : OUT std_logic; + Cal_6_n : OUT std_logic; + Cal_7_p : OUT std_logic; + Cal_7_n : OUT std_logic; + LP1_ampl : IN std_logic_vector(15 downto 0); + LP2_ampl : IN std_logic_vector(15 downto 0); + LP1_pulse : IN std_logic; + LP2_pulse : IN std_logic; + start_config : IN std_logic; + config_started : OUT std_logic; + config_done : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal clk_50 : std_logic := '0'; + signal LP1_ampl : std_logic_vector(15 downto 0) := (others => '0'); + signal LP2_ampl : std_logic_vector(15 downto 0) := (others => '0'); + signal LP1_pulse : std_logic := '0'; + signal LP2_pulse : std_logic := '0'; + signal start_config : std_logic := '0'; + + --Outputs + signal Cal_0_p : std_logic; + signal Cal_0_n : std_logic; + signal Cal_1_p : std_logic; + signal Cal_1_n : std_logic; + signal Cal_2_p : std_logic; + signal Cal_2_n : std_logic; + signal Cal_3_p : std_logic; + signal Cal_3_n : std_logic; + signal Cal_4_p : std_logic; + signal Cal_4_n : std_logic; + signal Cal_5_p : std_logic; + signal Cal_5_n : std_logic; + signal Cal_6_p : std_logic; + signal Cal_6_n : std_logic; + signal Cal_7_p : std_logic; + signal Cal_7_n : std_logic; + signal config_started : std_logic; + signal config_done : std_logic; + + -- Clock period definitions + constant clk_50_period : time := 20 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: Lightpulser_interface_Basic PORT MAP ( + clk_50 => clk_50, + Cal_0_p => Cal_0_p, + Cal_0_n => Cal_0_n, + Cal_1_p => Cal_1_p, + Cal_1_n => Cal_1_n, + Cal_2_p => Cal_2_p, + Cal_2_n => Cal_2_n, + Cal_3_p => Cal_3_p, + Cal_3_n => Cal_3_n, + Cal_4_p => Cal_4_p, + Cal_4_n => Cal_4_n, + Cal_5_p => Cal_5_p, + Cal_5_n => Cal_5_n, + Cal_6_p => Cal_6_p, + Cal_6_n => Cal_6_n, + Cal_7_p => Cal_7_p, + Cal_7_n => Cal_7_n, + LP1_ampl => LP1_ampl, + LP2_ampl => LP2_ampl, + LP1_pulse => LP1_pulse, + LP2_pulse => LP2_pulse, + start_config => start_config, + config_started => config_started, + config_done => config_done + ); + + -- Clock process definitions + clk_50_process :process + begin + clk_50 <= '0'; + wait for clk_50_period/2; + clk_50 <= '1'; + wait for clk_50_period/2; + end process; + + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100 ms. + -- wait for 100 ms; + + wait for clk_50_period*10; + + -- insert stimulus here + + + + -- init input signals + start_config <= '0'; + LP1_pulse <= '0'; + LP2_pulse <= '0'; + + + + -- latch settings + LP1_ampl <= "1000000000001000"; + LP2_ampl <= "0100000000010000"; + + + wait for clk_50_period*5; + start_config <= '1'; + wait for clk_50_period*1; + start_config <= '0'; + + + wait for clk_50_period*5; + + + -- trigger lightpulses + + -- LP1: mirror dish + LP1_pulse <= '1'; + wait for clk_50_period*5; + LP1_pulse <= '0'; + + -- LP2: shutter + LP2_pulse <= '1'; + wait for clk_50_period*5; + LP2_pulse <= '0'; + + + + + + -- second cyclus + wait for clk_50_period*10; + + + -- latch settings + LP1_ampl <= "1100000001111111"; + LP2_ampl <= "0000000000000000"; + + wait for clk_50_period*5; + start_config <= '1'; + wait for clk_50_period*1; + start_config <= '0'; + + + wait for clk_50_period*5; + + -- trigger lightpulses + + -- LP1: mirror dish + LP1_pulse <= '1'; + wait for clk_50_period*2; + LP1_pulse <= '0'; + + -- LP2: shutter + LP2_pulse <= '1'; + wait for clk_50_period*2; + LP2_pulse <= '0'; + + + wait; + end process; + +END; Index: firmware/FTM/Lightpulser_interface/Basic_Version/single_LP_Basic.vhd =================================================================== --- firmware/FTM/Lightpulser_interface/Basic_Version/single_LP_Basic.vhd (revision 11485) +++ firmware/FTM/Lightpulser_interface/Basic_Version/single_LP_Basic.vhd (revision 11513) @@ -32,4 +32,10 @@ -- by Patrick Vogler, Quirin Weitzel -- -> clean up +-- +-- +-- modified: July 20 2011 +-- by Patrick Vogler +-- reduce minimal LED light output and increase dynamic range +-- ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- @@ -77,5 +83,5 @@ single_LP_Basic_proc: process (clk_50) -variable Y : integer range 0 to FLD_PULSE_LENGTH_BASIC; +variable Y : integer range 0 to FLD_PULSE_LENGTH_Pulse; begin @@ -89,5 +95,5 @@ if (Pulse_Flag = '1') then - if (Y < FLD_PULSE_LENGTH_BASIC) then + if (Y < FLD_PULSE_LENGTH_Pulse) then Y := Y + 1; LP_Pulse_out <= '1'; Index: firmware/FTM/ftm_definitions.vhd =================================================================== --- firmware/FTM/ftm_definitions.vhd (revision 11485) +++ firmware/FTM/ftm_definitions.vhd (revision 11513) @@ -60,4 +60,6 @@ -- -- kw 10.06.: added CMD_CONFIG_FTU +-- +-- pv 21.07.: new lightpulser firmware to reduce LED current and light output -- ---------------------------------------------------------------------------------- @@ -423,8 +425,9 @@ -- Lightpulser Basic Version -- -------------------------------------------------------------------------------------- - constant FLD_PULSE_LENGTH_BASIC : integer := 3; -- 60ns pulse @ 50MHz - constant FLD_MIN_FREQ_DIV_BASIC : integer := 25; - constant FLD_FD_MULT_BASIC : integer := 10; - constant FLD_FD_MAX_RANGE_BASIC : integer := 64; + constant FLD_PULSE_LENGTH_Pulse : integer := 2; -- 40ns pulse @ 50MHz, instead of 3: 60ns pulse @ 50MHz + constant FLD_PULSE_LENGTH_FM : integer := 3; -- 60ns pulse @ 50MHz + constant FLD_MIN_FREQ_DIV_BASIC : integer := 8; -- before 25 + constant FLD_FD_MULT_BASIC : integer := 8; -- before 10 + constant FLD_FD_MAX_RANGE_BASIC : integer := 128;-- before 64 -- Timing counter