Index: firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd =================================================================== --- firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd (revision 11541) +++ firmware/FTM/Clock_cond_interface/Clock_cond_interface.vhd (revision 11648) @@ -21,4 +21,5 @@ -- March 23 2011 by Patrick Vogler -- May 03 2011 by Patrick Vogler and Quirin Weitzel +-- July 19 2011 by Patrick Vogler ---------------------------------------------------------------------------------- @@ -76,14 +77,15 @@ -- FPGA intern control signals ------------------------------------------------------------------------------- - start_config : in STD_LOGIC; -- load new configuration into the clock + start_config : in STD_LOGIC; -- load new configuration into the clock -- conditioner - config_started : out STD_LOGIC; -- indicates that the new configuration + config_started : out STD_LOGIC; -- indicates that the new configuration -- is currently loaded into the clock conditioner - config_done : out STD_LOGIC; -- indicates that the configuration has - -- been loaded and the clock conditioners - -- PLL is locked - + config_done : out STD_LOGIC; -- indicates that the configuration has + -- been loaded + + -- locked : out STD_LOGIC; -- PLL in the Clock Conditioner locked + timemarker_select: in STD_LOGIC -- selects time marker source -- @@ -96,4 +98,5 @@ ); end Clock_cond_interface; + @@ -118,24 +121,29 @@ signal config_ready_sig : STD_LOGIC; signal config_started_sig : STD_LOGIC; - - signal clk_cond_array_sig : clk_cond_array_type; - - signal cc_R0_sig : std_logic_vector (31 downto 0); - signal cc_R1_sig : std_logic_vector (31 downto 0); - - signal cc_R2_sig : std_logic_vector (31 downto 0); - signal cc_R3_sig : std_logic_vector (31 downto 0); - signal cc_R4_sig : std_logic_vector (31 downto 0); - signal cc_R5_sig : std_logic_vector (31 downto 0); - signal cc_R6_sig : std_logic_vector (31 downto 0); - signal cc_R7_sig : std_logic_vector (31 downto 0); - - signal cc_R8_sig : std_logic_vector (31 downto 0); - signal cc_R9_sig : std_logic_vector (31 downto 0); - signal cc_R11_sig : std_logic_vector (31 downto 0); - signal cc_R13_sig : std_logic_vector (31 downto 0); - signal cc_R14_sig : std_logic_vector (31 downto 0); - signal cc_R15_sig : std_logic_vector (31 downto 0); - + + + signal clk_cond_array_sig : clk_cond_array_type; + + +-- signal cc_R0_sig : std_logic_vector (31 downto 0); +-- signal cc_R1_sig : std_logic_vector (31 downto 0); + +-- signal cc_R2_sig : std_logic_vector (31 downto 0); +-- signal cc_R3_sig : std_logic_vector (31 downto 0); +-- signal cc_R4_sig : std_logic_vector (31 downto 0); +-- signal cc_R5_sig : std_logic_vector (31 downto 0); +-- signal cc_R6_sig : std_logic_vector (31 downto 0); +-- signal cc_R7_sig : std_logic_vector (31 downto 0); + +-- signal cc_R8_sig : std_logic_vector (31 downto 0); +-- signal cc_R9_sig : std_logic_vector (31 downto 0); +-- signal cc_R11_sig : std_logic_vector (31 downto 0); +-- signal cc_R13_sig : std_logic_vector (31 downto 0); +-- signal cc_R14_sig : std_logic_vector (31 downto 0); +-- signal cc_R15_sig : std_logic_vector (31 downto 0); + + + + signal timemarker_select_sig : std_logic := '0'; @@ -166,12 +174,18 @@ end process sync_ld_proc; - --config_done <= config_ready_sig; -- indicates that the configuration - -- has been loaded - - --config_done <= (config_ready_sig AND LD_Clk_Cond); -- indicates that the configuration - -- has been loaded and - -- the PLL has locked - - config_done <= config_ready_sig and (load_detect_sr(1) and load_detect_sr(0)); + -- config_done <= config_ready_sig; -- indicates that the configuration + -- has been loaded + + -- config_done <= (config_ready_sig AND LD_Clk_Cond); -- indicates that the configuration + -- has been loaded and + -- the PLL has locked + + config_done <= config_ready_sig and (load_detect_sr(1) and load_detect_sr(0)); + +-- config_done <= config_ready_sig; +-- locked <= load_detect_sr(1) and load_detect_sr(0); + + + TIM_Sel <= timemarker_select_sig; @@ -201,37 +215,71 @@ config_started <= config_started_sig; - cc_R0_sig <= cc_R0; - cc_R1_sig <= cc_R1; - cc_R2_sig <= cc_R2_const; - cc_R3_sig <= cc_R3_const; - cc_R4_sig <= cc_R4_const; - cc_R5_sig <= cc_R5_const; - cc_R6_sig <= cc_R6_const; - cc_R7_sig <= cc_R7_const; - cc_R8_sig <= cc_R8; - cc_R9_sig <= cc_R9; - cc_R11_sig <= cc_R11; - cc_R13_sig <= cc_R13; - cc_R14_sig <= cc_R14; - cc_R15_sig <= cc_R15; - + +-- ----------------------------------------------------------------------------- + +-- cc_R0_sig <= cc_R0; +-- cc_R1_sig <= cc_R1; + +-- cc_R2_sig <= cc_R2_const; +-- cc_R3_sig <= cc_R3_const; +-- cc_R4_sig <= cc_R4_const; +-- cc_R5_sig <= cc_R5_const; +-- cc_R6_sig <= cc_R6_const; +-- cc_R7_sig <= cc_R7_const; + +-- cc_R8_sig <= cc_R8; +-- cc_R9_sig <= cc_R9; +-- cc_R11_sig <= cc_R11; +-- cc_R13_sig <= cc_R13; +-- cc_R14_sig <= cc_R14; +-- cc_R15_sig <= cc_R15; + + + + + + + +-- clk_cond_array_sig(0) <= LMK03000_Reset; -- reset LKM03000 by setting +-- -- bit 31 of register 0 +-- clk_cond_array_sig(1) <= cc_R0_sig; +-- clk_cond_array_sig(2) <= cc_R1_sig; + +-- clk_cond_array_sig(3) <= cc_R2_sig; -- unused channels +-- clk_cond_array_sig(4) <= cc_R3_sig; +-- clk_cond_array_sig(5) <= cc_R4_sig; +-- clk_cond_array_sig(6) <= cc_R5_sig; +-- clk_cond_array_sig(7) <= cc_R6_sig; +-- clk_cond_array_sig(8) <= cc_R7_sig; -- unused channels + +-- clk_cond_array_sig(9) <= cc_R8_sig; +-- clk_cond_array_sig(10) <= cc_R9_sig; +-- clk_cond_array_sig(11) <= cc_R11_sig; +-- clk_cond_array_sig(12) <= cc_R13_sig; +-- clk_cond_array_sig(13) <= cc_R14_sig; +-- clk_cond_array_sig(14) <= cc_R15_sig; + +-- ----------------------------------------------------------------------------- + + clk_cond_array_sig(0) <= LMK03000_Reset; -- reset LKM03000 by setting -- bit 31 of register 0 - clk_cond_array_sig(1) <= cc_R0_sig; - clk_cond_array_sig(2) <= cc_R1_sig; - - clk_cond_array_sig(3) <= cc_R2_sig; -- unused channels - clk_cond_array_sig(4) <= cc_R3_sig; - clk_cond_array_sig(5) <= cc_R4_sig; - clk_cond_array_sig(6) <= cc_R5_sig; - clk_cond_array_sig(7) <= cc_R6_sig; - clk_cond_array_sig(8) <= cc_R7_sig; - - clk_cond_array_sig(9) <= cc_R8_sig; - clk_cond_array_sig(10) <= cc_R9_sig; - clk_cond_array_sig(11) <= cc_R11_sig; - clk_cond_array_sig(12) <= cc_R13_sig; - clk_cond_array_sig(13) <= cc_R14_sig; - clk_cond_array_sig(14) <= cc_R15_sig; + clk_cond_array_sig(1) <= cc_R0; + clk_cond_array_sig(2) <= cc_R1; + + clk_cond_array_sig(3) <= cc_R2_const; -- unused channels + clk_cond_array_sig(4) <= cc_R3_const; + clk_cond_array_sig(5) <= cc_R4_const; + clk_cond_array_sig(6) <= cc_R5_const; + clk_cond_array_sig(7) <= cc_R6_const; + clk_cond_array_sig(8) <= cc_R7_const; -- unused channels + + clk_cond_array_sig(9) <= cc_R8; + clk_cond_array_sig(10) <= cc_R9; + clk_cond_array_sig(11) <= cc_R11; + clk_cond_array_sig(12) <= cc_R13; + clk_cond_array_sig(13) <= cc_R14; + clk_cond_array_sig(14) <= cc_R15; + end Behavioral; Index: firmware/FTM/Clock_cond_interface/Clock_cond_interface_tb.vhd =================================================================== --- firmware/FTM/Clock_cond_interface/Clock_cond_interface_tb.vhd (revision 11541) +++ firmware/FTM/Clock_cond_interface/Clock_cond_interface_tb.vhd (revision 11648) @@ -53,4 +53,5 @@ LD_Clk_Cond : IN std_logic; TIM_Sel : OUT std_logic; + -- locked : out STD_LOGIC; -- PLL in the Clock Conditioner locked cc_R0 : IN std_logic_vector(31 downto 0); cc_R1 : IN std_logic_vector(31 downto 0); @@ -83,5 +84,5 @@ signal cc_R13 : std_logic_vector(31 downto 0) := x"020A000D"; signal cc_R14 : std_logic_vector(31 downto 0) := x"0830280E"; - signal cc_R15 : std_logic_vector(31 downto 0) := x"1400FA0F"; + signal cc_R15 : std_logic_vector(31 downto 0) := x"1400FA0F"; @@ -101,5 +102,5 @@ signal config_started : std_logic; signal config_done : std_logic; - + -- signal locked : STD_LOGIC; -- PLL in the Clock Conditioner locked @@ -121,4 +122,5 @@ LD_Clk_Cond => LD_Clk_Cond, TIM_Sel => TIM_Sel, + -- locked => locked, cc_R0 => cc_R0, cc_R1 => cc_R1, @@ -147,12 +149,5 @@ end process; --- CLK_Clk_Cond_process :process --- begin --- CLK_Clk_Cond <= '0'; --- wait for CLK_Clk_Cond_period/2; --- CLK_Clk_Cond <= '1'; --- wait for CLK_Clk_Cond_period/2; --- end process; - + @@ -174,7 +169,41 @@ start_config <= '0'; - wait for 180 us; + wait for 300 us; LD_Clk_Cond <= '1'; + + wait for 300 us; + LD_Clk_Cond <= '0'; + start_config <= '1'; + wait for clk_period*100; + start_config <= '0'; + wait for 300 us; + LD_Clk_Cond <= '1'; + + + + + + -- programm new settings + + cc_R0 <= x"00038027"; + cc_R1 <= x"00010101"; + cc_R8 <= x"10000963"; + cc_R9 <= x"A0032A09"; + cc_R11 <= x"0082000B"; + cc_R13 <= x"020A000D"; + cc_R14 <= x"0830280E"; + cc_R15 <= x"1400FA0F"; + + wait for 300 us; + LD_Clk_Cond <= '0'; + start_config <= '1'; + wait for clk_period*100; + start_config <= '0'; + wait for 300 us; + LD_Clk_Cond <= '1'; + + + wait; end process; Index: firmware/FTM/Clock_cond_interface/microwire_controller.vhd =================================================================== --- firmware/FTM/Clock_cond_interface/microwire_controller.vhd (revision 11541) +++ firmware/FTM/Clock_cond_interface/microwire_controller.vhd (revision 11648) @@ -18,4 +18,7 @@ -- modified to be used as a Microwire interface to control the clock -- conditioner LMK03000 on the FTM board +-- +-- modified July 19 2011 by Patrick Vogler +-- ------------------------------------------------------------------------------- @@ -40,4 +43,5 @@ clk_cond_array : IN clk_cond_array_type; -- data to be loaded -- into the clock conditioner + config_start : IN std_logic; config_ready : OUT std_logic := '0'; @@ -54,5 +58,9 @@ signal bit_count : integer range 0 to LMK03000_REGISTER_WIDTH := 0; signal shift_reg : std_logic_vector (LMK03000_REGISTER_WIDTH - 1 downto 0) := (others => '0'); - + + signal clk_cond_array_update : clk_cond_array_type := (others => (others => '0')); + + + @@ -80,24 +88,36 @@ end if; + +------------------------------------------------------------------------------- +-- send new data only when settings changed when LOAD_SHIFT_REG => - bit_count <= 0; - config_started <= '1'; - shift_reg <= clk_cond_array(register_count) (LMK03000_REGISTER_WIDTH - 1 downto 0); - register_count <= register_count + 1; --- le_uwire <= '0'; - uwire_state <= SHIFT; - + + if (clk_cond_array_update = clk_cond_array) then -- compare old and new settings + config_started <= '1'; + uwire_state <= IDLE; -- do nothing if settings didn't change + + else -- program new (changed !!) settings to clock conditioner + bit_count <= 0; + config_started <= '1'; + shift_reg <= clk_cond_array(register_count) (LMK03000_REGISTER_WIDTH - 1 downto 0); + register_count <= register_count + 1; + uwire_state <= SHIFT; + + end if; +------------------------------------------------------------------------------- + when SHIFT => - data_uwire <= shift_reg(LMK03000_REGISTER_WIDTH - 1); - le_uwire <= '0'; + data_uwire <= shift_reg(LMK03000_REGISTER_WIDTH - 1); + le_uwire <= '0'; shift_reg <= shift_reg(LMK03000_REGISTER_WIDTH - 2 downto 0) & shift_reg(LMK03000_REGISTER_WIDTH - 1); bit_count <= bit_count + 1; if ((bit_count = LMK03000_REGISTER_WIDTH)AND(register_count = LMK03000_REGISTER_COUNT)) then - le_uwire <= '1'; + le_uwire <= '1'; + clk_cond_array_update <= clk_cond_array; -- get a copy of the date for comparison lateron uwire_state <= IDLE; elsif ((bit_count =LMK03000_REGISTER_WIDTH )AND(NOT(register_count = LMK03000_REGISTER_COUNT))) then - le_uwire <= '1'; + le_uwire <= '1'; uwire_state <= LOAD_SHIFT_REG; else