--
-- VHDL Architecture FACT_FAD_TB_lib.mod7_tester.beha
--
-- Created:
--          by - dneise.UNKNOWN (E5B-LABOR6)
--          at - 13:27:06 16.02.2011
--
-- using Mentor Graphics HDL Designer(TM) 2009.2 (Build 10)
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY mod7_tester IS
   PORT( 
      remainder : IN     std_logic_vector (2 DOWNTO 0);
      started   : IN     std_logic;
      valid     : IN     std_logic;
     
      number    : OUT    std_logic_vector (31 DOWNTO 0);
      start     : OUT    std_logic
   );

-- Declarations

END mod7_tester ;

--
ARCHITECTURE beha OF mod7_tester IS
BEGIN
	process 
		begin
	start <= '0';
	number <= conv_std_logic_vector(100523,32);
	wait for 45 ns;
	start <= '1';
	wait for 50 ns;
	start <= '0';
	wait for 310 ns;
	number <= conv_std_logic_vector(106523,32);
	start <= '1';
	wait for 50 ns;
	start <= '0';
	wait;
end process;
END ARCHITECTURE beha;

