-- VHDL Entity FACT_FAD_TB_lib.clock_generator_var_ps_tb.symbol
--
-- Created:
--          by - dneise.UNKNOWN (E5B-LABOR6)
--          at - 13:41:56 12.02.2011
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
--


ENTITY clock_generator_var_ps_tb IS
-- Declarations

END clock_generator_var_ps_tb ;

--
-- VHDL Architecture FACT_FAD_TB_lib.clock_generator_var_ps_tb.struct
--
-- Created:
--          by - dneise.UNKNOWN (E5B-LABOR6)
--          at - 13:41:56 12.02.2011
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.all;

LIBRARY FACT_FAD_lib;
LIBRARY FACT_FAD_TB_lib;

ARCHITECTURE struct OF clock_generator_var_ps_tb IS

   -- Architecture declarations

   -- Internal signal declarations
   SIGNAL CLK       : std_logic;
   SIGNAL CLK_25    : std_logic;
   SIGNAL CLK_25_PS : std_logic;
   SIGNAL CLK_50    : std_logic;
   SIGNAL RST_IN    : std_logic;
   SIGNAL direction : std_logic;
   SIGNAL do_shift  : std_logic;
   SIGNAL offset    : std_logic_vector(7 DOWNTO 0);


   -- Component Declarations
   COMPONENT clock_generator_var_ps
   PORT (
      CLK       : IN     std_logic ;
      RST_IN    : IN     std_logic ;
      direction : IN     std_logic ;
      do_shift  : IN     std_logic ;
      CLK_25    : OUT    std_logic ;
      CLK_25_PS : OUT    std_logic ;
      CLK_50    : OUT    std_logic ;
      offset    : OUT    std_logic_vector (7 DOWNTO 0) := (OTHERS => '0')
   );
   END COMPONENT;
   COMPONENT clock_generator
   GENERIC (
      clock_period : time := 20 ns;
      reset_time   : time := 50 ns
   );
   PORT (
      clk : OUT    std_logic  := '0';
      rst : OUT    std_logic  := '0'
   );
   END COMPONENT;
   COMPONENT clock_generator_var_ps_tester
   PORT (
      CLK_25    : IN     std_logic ;
      CLK_25_PS : IN     std_logic ;
      CLK_50    : IN     std_logic ;
      offset    : IN     std_logic_vector (7 DOWNTO 0);
      RST_IN    : OUT    std_logic ;
      direction : OUT    std_logic ;
      do_shift  : OUT    std_logic 
   );
   END COMPONENT;

   -- Optional embedded configurations
   -- pragma synthesis_off
   FOR ALL : clock_generator USE ENTITY FACT_FAD_TB_lib.clock_generator;
   FOR ALL : clock_generator_var_ps USE ENTITY FACT_FAD_lib.clock_generator_var_ps;
   FOR ALL : clock_generator_var_ps_tester USE ENTITY FACT_FAD_TB_lib.clock_generator_var_ps_tester;
   -- pragma synthesis_on


BEGIN

   -- Instance port mappings.
   U_0 : clock_generator_var_ps
      PORT MAP (
         CLK       => CLK,
         RST_IN    => RST_IN,
         direction => direction,
         do_shift  => do_shift,
         CLK_25    => CLK_25,
         CLK_25_PS => CLK_25_PS,
         CLK_50    => CLK_50,
         offset    => offset
      );
   --   synthesis translate_off
   U_2 : clock_generator
      GENERIC MAP (
         clock_period => 20 ns,
         reset_time   => 50 ns
      )
      PORT MAP (
         clk => CLK,
         rst => OPEN
      );
   U_1 : clock_generator_var_ps_tester
      PORT MAP (
         CLK_25    => CLK_25,
         CLK_25_PS => CLK_25_PS,
         CLK_50    => CLK_50,
         offset    => offset,
         RST_IN    => RST_IN,
         direction => direction,
         do_shift  => do_shift
      );

END struct;
