--
-- VHDL Architecture FACT_FAD_TB_lib.clock_generator_var_ps_tester.beha
--
-- Created:
--          by - dneise.UNKNOWN (E5B-LABOR6)
--          at - 13:23:57 12.02.2011
--
-- using Mentor Graphics HDL Designer(TM) 2009.2 (Build 10)
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.all;

ENTITY clock_generator_var_ps_tester IS
   PORT( 
      CLK_25    : IN     std_logic;
      CLK_25_PS : IN     std_logic;
      CLK_50    : IN     std_logic;
      offset    : IN     std_logic_vector (7 DOWNTO 0);
      RST_IN    : OUT    std_logic;
      direction : OUT    std_logic;
      do_shift  : OUT    std_logic
   );

-- Declarations

END clock_generator_var_ps_tester ;

--
ARCHITECTURE beha OF clock_generator_var_ps_tester IS
BEGIN
	
process
	begin
		direction <= '1';
		do_shift <= '0';
		RST_IN <= '0';
		
wait for 1000 ns;
	do_shift <= '1';			
wait for 300 ns;
	do_shift <= '0';

wait for 200 ns;
	do_shift <= '1';			
wait for 100 ns;
	do_shift <= '0';

wait for 200 ns;
	do_shift <= '1';			
wait for 100 ns;
	do_shift <= '0';

wait for 200 ns;
	do_shift <= '1';			
wait for 100 ns;
	do_shift <= '0';

wait for 200 ns;
	do_shift <= '1';			
wait for 100 ns;
	do_shift <= '0';

wait for 200 ns;
	do_shift <= '1';			
wait for 100 ns;
	do_shift <= '0';

wait for 200 ns;
	do_shift <= '1';			
wait for 100 ns;
	do_shift <= '0';

RST_IN <= '1';
wait for 100 ns;
RST_IN <= '0';
wait ;
		
	end process;

END ARCHITECTURE beha;

