--
-- VHDL Architecture FACT_FAD_TB_lib.w5300_modul2_tester.beha
--
-- Created:
--          by - dneise.UNKNOWN (E5B-LABOR6)
--          at - 14:18:31 31.05.2011
--
-- using Mentor Graphics HDL Designer(TM) 2009.2 (Build 10)
--
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY FACT_FAD_lib;
USE FACT_FAD_lib.fad_definitions.ALL;

ENTITY w5300_modul2_tester IS
   PORT( 
   		clk                           : IN    std_logic;
   		

      busy                          : IN     std_logic;
      c_trigger_enable              : IN     std_logic;
      c_trigger_mult                : IN     std_logic_vector (15 DOWNTO 0);

      dac_setting                   : IN     dac_array_type;
      data_valid_ack                : IN     std_logic;
      debug_data_ram_empty          : IN     std_logic;
      debug_data_valid              : IN     std_logic;
      denable                       : IN     std_logic;
      dwrite_enable                 : IN     std_logic;

      memory_manager_config_start_o : IN     std_logic;
      ps_direction                  : IN     std_logic;
      ps_do_phase_shift             : IN     std_logic;
      ps_reset                      : IN     std_logic;
      ram_addr                      : IN     std_logic_vector (13 DOWNTO 0);

      reset_trigger_id              : IN     std_logic;
      roi_setting                   : IN     roi_array_type;
      runnumber                     : IN     std_logic_vector (31 DOWNTO 0);
      s_trigger                     : IN     std_logic;
      sclk_enable                   : IN     std_logic;

      socks_connected               : IN     std_logic;
      socks_waiting                 : IN     std_logic;
      spi_interface_config_start_o  : IN     std_logic;
      srclk_enable                  : IN     std_logic;
      state                         : IN     std_logic_vector (7 DOWNTO 0);
      trigger_enable                : IN     std_logic;
      wiz_reset                     : IN     std_logic;

      BoardID                       : OUT    std_logic_vector (3 DOWNTO 0);
      CrateID                       : OUT    std_logic_vector (1 DOWNTO 0);
      MAC_jumper                    : OUT    std_logic_vector (1 DOWNTO 0);
      
      data_generator_idle_i         : OUT    std_logic;
      data_ram_empty                : OUT    std_logic;
      data_valid                    : OUT    std_logic;
      fifo_channels                 : OUT    std_logic_vector (3 DOWNTO 0);

      memory_manager_config_valid_i : OUT    std_logic;
      ps_ready                      : OUT    std_logic;
      ram_data                      : OUT    std_logic_vector (15 DOWNTO 0);
      ram_start_addr                : OUT    std_logic_vector (13 DOWNTO 0);
      spi_interface_config_valid_i  : OUT    std_logic;
      write_end_flag                : OUT    std_logic;
      write_header_flag             : OUT    std_logic;
      write_length                  : OUT    std_logic_vector (16 DOWNTO 0)

   );

-- Declarations

END w5300_modul2_tester ;

--
ARCHITECTURE beha OF w5300_modul2_tester IS
BEGIN
END ARCHITECTURE beha;

