-- VHDL Entity FACT_FAD_TB_lib.REFCLK_counter_tb.symbol
--
-- Created:
--          by - daqct3.UNKNOWN (IHP110)
--          at - 18:11:15 03.03.2011
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--


ENTITY REFCLK_counter_tb IS
   GENERIC( 
      FREQ_UPPER_LIMIT : integer := 3000;
      FREQ_LOWER_LIMIT : integer := 300
   );
-- Declarations

END REFCLK_counter_tb ;

--
-- VHDL Architecture FACT_FAD_TB_lib.REFCLK_counter_tb.struct
--
-- Created:
--          by - daqct3.UNKNOWN (IHP110)
--          at - 18:11:15 03.03.2011
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
LIBRARY FACT_FAD_lib;
USE FACT_FAD_lib.fad_definitions.ALL;
USE ieee.std_logic_unsigned.all;

LIBRARY FACT_FAD_lib;
LIBRARY FACT_FAD_TB_lib;

ARCHITECTURE struct OF REFCLK_counter_tb IS

   -- Architecture declarations

   -- Internal signal declarations
   SIGNAL alarm_refclk_too_high : std_logic;
   SIGNAL alarm_refclk_too_low  : std_logic;
   SIGNAL clk                   : std_logic := '0';
   SIGNAL counter_result        : std_logic_vector(11 DOWNTO 0);
   SIGNAL refclk_in             : std_logic;


   -- Component Declarations
   COMPONENT REFCLK_counter
   PORT (
      clk                   : IN     std_logic;
      refclk_in             : IN     std_logic;
      alarm_refclk_too_high : OUT    std_logic                      := '0';
      alarm_refclk_too_low  : OUT    std_logic                      := '0';
      counter_result        : OUT    std_logic_vector (11 DOWNTO 0) := (others => '0')
   );
   END COMPONENT;
   COMPONENT REFCLK_counter_tester
   PORT (
      alarm_refclk_too_high : IN     std_logic ;
      alarm_refclk_too_low  : IN     std_logic ;
      counter_result        : IN     std_logic_vector (11 DOWNTO 0);
      clk                   : OUT    std_logic ;
      refclk_in             : OUT    std_logic 
   );
   END COMPONENT;

   -- Optional embedded configurations
   -- pragma synthesis_off
   FOR ALL : REFCLK_counter USE ENTITY FACT_FAD_lib.REFCLK_counter;
   FOR ALL : REFCLK_counter_tester USE ENTITY FACT_FAD_TB_lib.REFCLK_counter_tester;
   -- pragma synthesis_on


BEGIN

   -- Instance port mappings.
   U_0 : REFCLK_counter
      PORT MAP (
         clk                   => clk,
         refclk_in             => refclk_in,
         counter_result        => counter_result,
         alarm_refclk_too_high => alarm_refclk_too_high,
         alarm_refclk_too_low  => alarm_refclk_too_low
      );
   U_1 : REFCLK_counter_tester
      PORT MAP (
         alarm_refclk_too_high => alarm_refclk_too_high,
         alarm_refclk_too_low  => alarm_refclk_too_low,
         counter_result        => counter_result,
         clk                   => clk,
         refclk_in             => refclk_in
      );

END struct;
