-- VHDL Entity FACT_FAD_TB_lib.mod7_tb.symbol
--
-- Created:
--          by - dneise.UNKNOWN (E5B-LABOR6)
--          at - 15:45:32 16.02.2011
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
--


ENTITY mod7_tb IS
-- Declarations

END mod7_tb ;

--
-- VHDL Architecture FACT_FAD_TB_lib.mod7_tb.struct
--
-- Created:
--          by - dneise.UNKNOWN (E5B-LABOR6)
--          at - 15:45:32 16.02.2011
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.2 (Build 10)
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

LIBRARY FACT_FAD_lib;
LIBRARY FACT_FAD_TB_lib;

ARCHITECTURE struct OF mod7_tb IS

   -- Architecture declarations

   -- Internal signal declarations
   SIGNAL clk       : std_logic;
   SIGNAL number    : std_logic_vector(31 DOWNTO 0);
   SIGNAL remainder : std_logic_vector(2 DOWNTO 0);
   SIGNAL start     : std_logic;
   SIGNAL started   : std_logic;
   SIGNAL valid     : std_logic;


   -- Component Declarations
   COMPONENT mod7
   PORT (
      clk       : IN     std_logic;
      number    : IN     std_logic_vector (31 DOWNTO 0);
      start     : IN     std_logic;
      remainder : OUT    std_logic_vector (2 DOWNTO 0) := (others => '0');
      started   : OUT    std_logic                     := '0';
      valid     : OUT    std_logic                     := '0'
   );
   END COMPONENT;
   COMPONENT clock_generator
   GENERIC (
      clock_period : time := 20 ns;
      reset_time   : time := 50 ns
   );
   PORT (
      clk : OUT    std_logic  := '0';
      rst : OUT    std_logic  := '0'
   );
   END COMPONENT;
   COMPONENT mod7_tester
   PORT (
      remainder : IN     std_logic_vector (2 DOWNTO 0);
      started   : IN     std_logic ;
      valid     : IN     std_logic ;
      number    : OUT    std_logic_vector (31 DOWNTO 0);
      start     : OUT    std_logic 
   );
   END COMPONENT;

   -- Optional embedded configurations
   -- pragma synthesis_off
   FOR ALL : clock_generator USE ENTITY FACT_FAD_TB_lib.clock_generator;
   FOR ALL : mod7 USE ENTITY FACT_FAD_lib.mod7;
   FOR ALL : mod7_tester USE ENTITY FACT_FAD_TB_lib.mod7_tester;
   -- pragma synthesis_on


BEGIN

   -- Instance port mappings.
   U_0 : mod7
      PORT MAP (
         clk       => clk,
         number    => number,
         start     => start,
         remainder => remainder,
         started   => started,
         valid     => valid
      );
   U_2 : clock_generator
      GENERIC MAP (
         clock_period => 20 ns,
         reset_time   => 50 ns
      )
      PORT MAP (
         clk => clk,
         rst => OPEN
      );
   U_1 : mod7_tester
      PORT MAP (
         remainder => remainder,
         started   => started,
         valid     => valid,
         number    => number,
         start     => start
      );

END struct;
