--
-- VHDL Architecture FACT_FAD_TB_lib.trigger_manager_tester.beha
--
-- Created:
--          by - daqct3.UNKNOWN (IHP110)
--          at - 13:39:39 14.01.2011
--
-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.all;

ENTITY trigger_manager_tester IS
   PORT( 
      drs_readout_ready_ack : IN     std_logic;
--      drs_write             : IN     std_logic;
--      trigger_out           : IN     std_logic;
--      clk                   : OUT    std_logic;
      drs_readout_ready     : OUT    std_logic := '0';
      trigger_in            : OUT    std_logic := '0'
   );

-- Declarations

END trigger_manager_tester ;

--
ARCHITECTURE beha OF trigger_manager_tester IS
BEGIN
  
  main_proc : process
  begin
    wait for 500 ns;
    wait for 5 ns;
    trigger_in <= '1';
    wait for 15 ns;
    wait for 100 ns;
    trigger_in <= '0';
    wait for 110 ns;
    drs_readout_ready <= '1';
    wait until (drs_readout_ready_ack = '1');
    wait for 20 ns;
    drs_readout_ready <= '0';
    wait for 100 ns;
  end process main_proc;
  
  
END ARCHITECTURE beha;

